JP4198079B2 - Photovoltaic device manufacturing method - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000010408 film Substances 0.000 claims description 59
- 239000000758 substrate Substances 0.000 claims description 43
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 38
- 239000004065 semiconductor Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 12
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 11
- 239000010409 thin film Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 5
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 9
- 229910021419 crystalline silicon Inorganic materials 0.000 description 7
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- 239000000843 powder Substances 0.000 description 4
- 229910006404 SnO 2 Inorganic materials 0.000 description 3
- 230000004075 alteration Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010606 normalization Methods 0.000 description 2
- 238000012805 post-processing Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000003917 TEM image Methods 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000011231 conductive filler Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
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Description
本発明は、半導体接合を用いた光起電力装置の製造法に関する。 The present invention relates to a method for manufacturing a photovoltaic device using a semiconductor junction.
近年光起電力素子として、単結晶シリコンや多結晶シリコン等の結晶系シリコンを用いた太陽電池の研究および実用化が盛んに行なわれている。中でも、非晶質シリコンと結晶系シリコンとを組合せることにより構成されたヘテロ接合を有する太陽電池は、その接合を２００℃以下の低温プロセスで形成することができ、かつ、高い変換効率が得られることから、注目を集めている。このような光起電力素子において、光電変換効率を向上させるためには、高い短絡電流（Ｉｓｃ）および開放電圧（Ｖｏｃ）を維持しつつ曲線因子（Ｆ．Ｆ．）を向上させる必要がある。 In recent years, research and practical application of solar cells using crystalline silicon such as single crystal silicon and polycrystalline silicon as photovoltaic elements have been actively conducted. In particular, a solar cell having a heterojunction formed by combining amorphous silicon and crystalline silicon can form the junction by a low-temperature process of 200 ° C. or less, and obtain high conversion efficiency. It attracts attention because it is. In such a photovoltaic device, in order to improve the photoelectric conversion efficiency, it is necessary to improve the fill factor (FF) while maintaining a high short circuit current (Isc) and an open circuit voltage (Voc).
そこで、ｎ型単結晶シリコン基板とｐ型非晶質シリコン膜との間に、実質的に真性な非晶質シリコン膜（ｉ型非晶質シリコン膜）が挿入された所謂ＨＩＴ構造を有する太陽電池が開発されている（例えば、特許文献１参照）。 Therefore, a sun having a so-called HIT structure in which a substantially intrinsic amorphous silicon film (i-type amorphous silicon film) is inserted between an n-type single crystal silicon substrate and a p-type amorphous silicon film. A battery has been developed (see, for example, Patent Document 1).
一方、従来の非晶質半導体と結晶系シリコンとを組合せた光起電力素子の製造においては、結晶系シリコンのみからなる光起電力素子と異なり、結晶系シリコン基板上に接合形成のための非晶質シリコン層や導電性薄膜を形成する必要がある。 On the other hand, in the production of a photovoltaic device combining a conventional amorphous semiconductor and crystalline silicon, unlike a photovoltaic device made only of crystalline silicon, non-forming for forming a junction on a crystalline silicon substrate is performed. It is necessary to form a crystalline silicon layer or a conductive thin film.
ここで、従来、基板上にこれらの膜を形成する際には、プラズマＣＶＤ法、スパッタ法あるいは蒸着法等の製造法を用いるために、非晶質シリコン層や導電性薄膜が基板の表面のみならず側面あるいは裏面に回り込んでしまい、これらを介して素子の短絡が生じ、リーク発生に伴う出力低下が問題となる。 Here, conventionally, when these films are formed on a substrate, an amorphous silicon layer or a conductive thin film is formed only on the surface of the substrate in order to use a manufacturing method such as plasma CVD, sputtering, or vapor deposition. In other words, it wraps around the side surface or the back surface, causing a short circuit of the element through these, resulting in a problem of a decrease in output due to leakage.
上記した問題点を解決するために、一導電型の結晶系半導体基板の表裏面の全面に、前記基板とヘテロ接合を形成する非晶質半導体層および導電性薄膜を形成した後、レーザーにより非晶質半導体層と導電性薄膜を除去して、リーク電流パスを抑制する方法が提案されている（例えば、特許文献２参照）。
上記した特許文献２による方法によれば、レーザーにより非晶質半導体層と導電性薄膜を除去することで、回込みによる光起電力素子の短絡は有効に防止される。しかしながら、非晶質半導体層および導電性薄膜を形成した後に、レーザーで加工した場合には、レーザー加工した端部での非晶質半導体層が変質し、微結晶化され、変質した微結晶ライクの半導体層でのリーク電流が発生し、セル特性が低下するという問題があった。 According to the method according to Patent Document 2 described above, the amorphous semiconductor layer and the conductive thin film are removed by a laser, so that a short circuit of the photovoltaic element due to wraparound is effectively prevented. However, when laser processing is performed after forming an amorphous semiconductor layer and a conductive thin film, the amorphous semiconductor layer at the laser-processed edge is altered, microcrystallized, and altered microcrystal-like. There is a problem that a leak current occurs in the semiconductor layer and cell characteristics deteriorate.
本発明は、上記した従来の問題点に鑑みなされたものにして、非晶質半導体層の変質を無くすると共に、膜の回り込みを無くしてリーク電流がなくセル特性を向上させた光起電力装置を提供することを目的とする。 The present invention has been made in view of the above-described conventional problems, and eliminates the alteration of the amorphous semiconductor layer and eliminates the wraparound of the film, thereby eliminating the leakage current and improving the cell characteristics. The purpose is to provide.
本発明は、一導電型の結晶系半導体基板の表面上に、他導電型の非晶質半導体層と導電性薄膜とからなる積層体を備え、前記基板の裏面上に少なくとも裏面電極膜が設けられた光起電力装置の製造法であって、前記基板の表裏面に設けられる膜の膜厚の総和の内、総和の大きい方の大きさより大きな幅、深さを有する溝を前記基板の側面に形成し、その後、他導電型の非晶質半導体層と導電性薄膜とからなる積層体、前記基板の裏面上に少なくとも裏面電極膜を設けることを特徴とする。 The present invention comprises a laminate composed of an amorphous semiconductor layer of another conductivity type and a conductive thin film on the surface of a crystalline semiconductor substrate of one conductivity type, and at least a back electrode film is provided on the back surface of the substrate. A method of manufacturing a photovoltaic device according to claim 1, wherein a groove having a width and a depth larger than the larger sum of the film thicknesses of the films provided on the front and back surfaces of the substrate is formed on the side surface of the substrate. Thereafter, at least a back electrode film is provided on the back surface of the substrate, which is a laminated body including an amorphous semiconductor layer of another conductivity type and a conductive thin film.
前記基板は単結晶シリコン基板からなり、異方性エッチングにより凹凸が形成される共に、レーザー加工により側面部に、幅は１００μｍを超えず、深さは１０μｍ以上１２０μｍ以内の溝を形成するとよい。 The substrate is formed of a single crystal silicon substrate, and irregularities are formed by anisotropic etching, and a groove having a width not exceeding 100 μm and a depth not less than 10 μm and not more than 120 μm is preferably formed on the side surface by laser processing.
以上説明したように、本発明によれば、基板側面に予め溝をつけることによって、表裏の導電膜が基板側面で確実に分離され、電気的に接続されるような大きなリーク電流パスの発生を抑制でき、太陽電池特性が向上する。 As described above, according to the present invention, by forming a groove on the side surface of the substrate in advance, it is possible to generate a large leakage current path so that the conductive films on the front and back sides are reliably separated on the side surface of the substrate and are electrically connected. It can suppress and a solar cell characteristic improves.
以下、本発明の実施形態につき、図面を参照して説明する。図１は、本発明の実施の形態による光起電力装置の断面図、図２は、本発明の実施の形態による光起電力装置の要部拡大断面図である。 Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a photovoltaic device according to an embodiment of the present invention, and FIG. 2 is an enlarged cross-sectional view of a main part of the photovoltaic device according to the embodiment of the present invention.
約１Ω・ｃｍの抵抗率と約３００μｍの厚みとを有するとともに、（１００）面を有するｎ型単結晶シリコンウェハを用意し、このシリコンウェハをアルカリ溶液、この実施形態では、水酸化ナトリウム溶液（ＮａＯＨ）を用いた異方性エッチングにより約１０μｍの凹凸状のピラミッド構造を形成する。凹凸を形成したシリコンウェハの厚みは２４０μｍである。 An n-type single crystal silicon wafer having a resistivity of about 1 Ω · cm and a thickness of about 300 μm and having a (100) plane is prepared. This silicon wafer is prepared as an alkaline solution, in this embodiment, a sodium hydroxide solution ( An uneven pyramid structure of about 10 μm is formed by anisotropic etching using (NaOH). The thickness of the silicon wafer on which the irregularities are formed is 240 μm.
このピラミッド状の凹凸を設けたｎ型単結晶シリコン基板１の側面には、ＹＡＧレーザーを用いて所望の幅、深さを有する溝１１を側面周囲に形成する。この幅、深さは、後工程で表裏に形成される膜厚の総合計の内、どちらか大きい方より大きな幅及び深い深さの矩形状の溝１１を形成する。これは後から形成する膜の回り込みを防止するために、溝部１１に形成した膜が回り込んで、表裏の膜が繋がらないようにするためである。
On the side surface of the n-type single crystal silicon substrate 1 provided with the pyramidal irregularities, a
この実施形態では、後述するように、非晶質シリコン膜がそれぞれ１０ｎｍ程度、透明導電膜が１００ｎｍ程度であるから、１２０ｎｍを超える大きさの幅、並びに深さの溝１１を形成すればよい。レーザーを用いた加工の場合、幅は２０μｍを越える大きさの加工になるので、上記の条件は満足する。また、深さも２μｍ程度は加工されるので、上記の条件は満足する。溝１１の幅及び深さは、あまりに大きくすると強度的な問題もある。２４０μｍの厚さの基板１の場合、幅は１００μｍを越えず、また深さは１２０μｍを越えない方が良い。
In this embodiment, as will be described later, since the amorphous silicon film is about 10 nm and the transparent conductive film is about 100 nm, the
溝１１を形成した基板１を通常の手法に従い洗浄して不純物を除去し、公知のＲＦプラズマＣＶＤ（１３．５６ＭＨｚ）を用いてｎ型単結晶シリコン基板１の上面上には、約１０ｎｍの厚みを有する実質的に真性のｉ型非晶質シリコン膜２、ｉ型非晶質シリコン（ａ−Ｓｉ）膜２上には、約１０ｎｍの厚みを有するｐ型非晶質シリコン（ａ−Ｓｉ）膜３が形成される。この膜の形成条件については、表１に示す。
The substrate 1 in which the
また、ｐ型非晶質シリコン（ａ−Ｓｉ）膜３上には、約１００ｎｍの厚みを有する透明導電膜としてのスパッタ法によりＩＴＯ膜４が形成されている。このＩＴＯ膜４は、ＳｎＯ2を添加したＩｎ2Ｏ3によって形成されている。 An ITO film 4 is formed on the p-type amorphous silicon (a-Si) film 3 by sputtering as a transparent conductive film having a thickness of about 100 nm. The ITO film 4 is made of In 2 O 3 to which SnO 2 is added.
このＩＴＯ膜４は、次のようにスパッタ法により形成される。ＳｎＯ2粉末を５ｗｔ％として、Ｉｎ2Ｏ3粉末との焼結体をターゲットとし、カソードに設置する。他にＳｉ、Ｇｅ、Ｔｉの少なくとも１つをドーパントとして用いても良い。これらの化合物粉末を適量、酸化インジウム粉末に混ぜて焼結し、ターゲットを作成すればよい。ＳｎＯ2の量を変えることで、ＩＴＯ膜中のＳｎ量を変化させることが可能であるが、なお、ＩＴＯの光の透過率を向上させるために、Ｉｎに対するＳｎの量は１から１０ａｔ％が好ましく、更に、２から７ａｔ％が好ましい。ターゲットの焼結密度は９０％以上が好ましい。 The ITO film 4 is formed by sputtering as follows. The SnO 2 powder is set to 5 wt%, and a sintered body with In 2 O 3 powder is used as a target and is set on the cathode. In addition, at least one of Si, Ge, and Ti may be used as a dopant. An appropriate amount of these compound powders may be mixed with indium oxide powder and sintered to prepare a target. It is possible to change the amount of Sn in the ITO film by changing the amount of SnO 2. However, in order to improve the light transmittance of ITO, the amount of Sn with respect to In is 1 to 10 at%. Furthermore, 2 to 7 at% is preferable. The sintered density of the target is preferably 90% or more.
成膜時のプラズマダメージ抑制のために、カソード表面に３００〜３０００ガウス（Ｇａｕｓｓ）の強磁場をマグネットより印加できる装置を使用し、素子をカソードと平行に対向配置してから、チャンバーを真空排気する。加熱ヒータにより、基板温度を室温から２００℃になるまで加熱する。また、ＡｒとＯ2の混合ガスを流して圧力を０．４〜１．３Ｐａに保ち、カソードにＤＣ電力を０．５〜２ｋＷ投入して放電を開始する。基板をカソードに対して静止した状態で成膜速度は約１０〜８０ｎｍ／分となった。 In order to suppress plasma damage during film formation, use a device that can apply a strong magnetic field of 300 to 3000 Gauss from the magnet to the cathode surface, place the element facing the cathode in parallel, and then evacuate the chamber To do. The substrate temperature is heated from room temperature to 200 ° C. with a heater. Further, a mixed gas of Ar and O 2 is flowed to keep the pressure at 0.4 to 1.3 Pa, and DC power is applied to the cathode at 0.5 to 2 kW to start discharging. The deposition rate was about 10 to 80 nm / min with the substrate stationary relative to the cathode.
このような条件により、ＩＴＯ膜４を１００ｎｍの厚さで形成することで、溝１１により、ＩＴＯ膜４は確実に分離されている。
By forming the ITO film 4 with a thickness of 100 nm under such conditions, the ITO film 4 is reliably separated by the
更に、このＩＴＯ膜４の上面上の所定領域には、櫛型集電極（ペースト電極）５が形成されている。この櫛型電極５は、銀（Ａｇ）からなる導電性フィラーと熱硬化性樹脂とによって構成され、印刷によりフィンガー部とバスバー部とからなる所定のパターンに形成される。 Further, a comb-shaped collector electrode (paste electrode) 5 is formed in a predetermined region on the upper surface of the ITO film 4. The comb-shaped electrode 5 is composed of a conductive filler made of silver (Ag) and a thermosetting resin, and is formed in a predetermined pattern made up of finger portions and bus bar portions by printing.
また、ｎ型単結晶シリコン基板１の下面上には、公知のＲＦプラズマＣＶＤ（１３．５６ＭＨｚ）を用いて約１０ｎｍの厚みを有する実質的に真性のｉ型非晶質シリコン（ａ−Ｓｉ）膜６、ｉ型非晶質シリコン（ａ−Ｓｉ）膜６上には、１０ｎｍの厚みを有するｎ型非晶質シリコン（ａ−Ｓｉ）膜７が形成される。このようにｎ型単結晶シリコン基板１の下面上に、ｉ型非晶質シリコン（ａ−Ｓｉ）膜６およびｎ型非晶質シリコン（ａ−Ｓｉ）膜７が順番に形成されることにより、いわゆるＢＳＦ（Ｂａｃｋ Ｓｕｒｆａｃｅ Ｆｉｅｌｄ）構造が形成されている。 Further, a substantially intrinsic i-type amorphous silicon (a-Si) having a thickness of about 10 nm is formed on the lower surface of the n-type single crystal silicon substrate 1 using a known RF plasma CVD (13.56 MHz). An n-type amorphous silicon (a-Si) film 7 having a thickness of 10 nm is formed on the film 6 and the i-type amorphous silicon (a-Si) film 6. As described above, the i-type amorphous silicon (a-Si) film 6 and the n-type amorphous silicon (a-Si) film 7 are sequentially formed on the lower surface of the n-type single crystal silicon substrate 1. A so-called BSF (Back Surface Field) structure is formed.
また、ｎ型非晶質シリコン（ａ−Ｓｉ）膜７上には、１００ｎｍの厚みを有する上記表面側と同じ形成方法でＩＴＯ膜８が形成される。ＩＴＯ膜８上の所定領域には、櫛型集電極（ペースト電極）９が形成されている。 On the n-type amorphous silicon (a-Si) film 7, an ITO film 8 having a thickness of 100 nm is formed by the same formation method as that for the surface side. A comb-shaped collector electrode (paste electrode) 9 is formed in a predetermined region on the ITO film 8.
表１にＲＦプラズマＣＶＤ法による代表的な太陽電池作成時の非晶質シリコン（ａ−Ｓｉ）の形成条件を示す。 Table 1 shows the formation conditions of amorphous silicon (a-Si) at the time of producing a typical solar cell by the RF plasma CVD method.
表２に、マスクにより端面にａ−Ｓｉ膜、ＩＴＯ膜の非成膜領域を形成した従来構造、有効面積拡大のためにマスクを用いず基板端面までａ−Ｓｉ膜、ＩＴＯ膜を形成した全面形成構造、更に本発明の実施形態である基板１の側面の中央部に、幅４０μｍ、深さ４０μｍの溝を形成した太陽電池セルをそれぞれ形成し、各特性を比較した。成膜条件等は上記した方法で全て同じにした。 Table 2 shows a conventional structure in which a non-deposition region of an a-Si film and an ITO film is formed on the end face using a mask, and an entire surface on which the a-Si film and the ITO film are formed up to the end face of the substrate without using a mask for expanding the effective area. Solar cells each having a groove having a width of 40 μm and a depth of 40 μm were formed in the central portion of the side surface of the formation structure and the substrate 1 according to an embodiment of the present invention, and the characteristics were compared. The film forming conditions and the like were all made the same by the method described above.
表２から明らかなように、全面形成構造は従来構造に比べて有効面積拡大により、電流は増加するが、端面でのａ−Ｓｉ膜、ＩＴＯ膜の回り込みによるリーク電流パス、特にａ−Ｓｉ膜に比べて電気抵抗の小さいＩＴＯ膜によるリーク電流により、Ｆ．Ｆ．が大幅に低下し、出力はむしろ低下した。一方、本発明の実施形態は、端面の溝１１により、ＩＴＯ膜は完全に分離され、リーク電流パスの発生が抑制されて高いＦ．Ｆ．と高い電流が両立できた。
As can be seen from Table 2, although the current increases in the entire surface formation structure as the effective area is increased compared to the conventional structure, the a-Si film at the end face, the leakage current path due to the wraparound of the ITO film, particularly the a-Si film The leakage current due to the ITO film having a lower electrical resistance than F. However, the output was rather lowered. On the other hand, according to the embodiment of the present invention, the ITO film is completely separated by the
表３は、基板１の側面（厚み２４０μｍ）の中央に、溝１１の幅４０μｍ一定とし、深さを２〜１２０μｍに変化させた場合の、規格化Ｆ．Ｆ．の変化である。規格化は、表１の全面形成の値により行った。
表３より、２μｍの深さから規格化Ｆ．Ｆは改善しているが、５μｍまでは改善効果が小さい。これは基板として、アルカリエッチングにより基板表面に凹凸を設けたものを用いているため、基板側面にも大きさ１０μｍ程度の基板表面と同じ凹凸が形成されている。このため凹凸よりも浅い溝の形成は、制御性が十分でないために、本発明の効果を十分に引き出せていないためと考えられる。しかし、深さが１０μｍよりも深い場合は、効果が明確となり、本発明で意図したＩＴＯ膜を介したリークパスの分離に成功した為と考えられる。 From Table 3, the standardized F.D. Although F is improved, the improvement effect is small up to 5 μm. This is because the substrate is provided with irregularities on the substrate surface by alkali etching, and the same irregularities as the substrate surface having a size of about 10 μm are formed on the side surface of the substrate. For this reason, it is considered that the formation of the groove shallower than the concavo-convex is because the controllability is not sufficient and the effect of the present invention cannot be sufficiently obtained. However, when the depth is deeper than 10 μm, the effect becomes clear and it is considered that the leakage path was successfully separated through the ITO film intended in the present invention.
次に、溝１１の深さを１０μｍ一定とし、幅を２０〜１００μｍにて変化させた場合の規格化Ｆ．Ｆ．を表４に示す。規格化は、表１の全面形成の値により行った。表４より、いずれの場合も同レベルの効果が得られた。
Next, the standardized F.D. when the depth of the
続いて、透明導電膜の形成後にレーザーにより、非晶質シリコン膜／透明導電膜を除去することにより、リーク電流パスを抑制する方法で形成した太陽電池セルと本発明よる太陽電池セルとの比較を行った結果を表５に示す。 Subsequently, after the formation of the transparent conductive film, the amorphous silicon film / transparent conductive film is removed by laser to compare the solar battery cell formed by the method for suppressing the leakage current path with the solar battery cell according to the present invention. Table 5 shows the results of the test.
その結果、レーザーで後加工した場合には、基板端面での結晶シリコンのダメージが透過電子顕微鏡写真より明らかとなり、更にレーザー加工した端部でのシリコンの変質（微結晶化）も確認された。この影響で、シリコン基板端面での再結合中心増加、変質した微結晶ライクシリコンでのリーク電流が発生し、Ｆ．Ｆ．等が低下していると考えられる。これに対して、後加工に比べてあらかじめ基板１を加工する本発明では、洗浄工程によるダメージ層の除去が可能であり、ａ−Ｓｉ膜や透明導電膜の変質等の可能性がなく有効であることが分かる。 As a result, when post-processing with a laser, the damage of the crystalline silicon at the end face of the substrate became clear from the transmission electron micrograph, and the alteration (microcrystallization) of the silicon at the end processed with laser was also confirmed. As a result, recombination centers increase at the end face of the silicon substrate, and leakage current occurs in the modified microcrystalline-like silicon. F. Etc. are thought to have declined. On the other hand, in the present invention in which the substrate 1 is processed in advance as compared with post-processing, it is possible to remove the damaged layer by the cleaning process, and there is no possibility of alteration of the a-Si film or the transparent conductive film, which is effective. I understand that there is.
尚、上記した実施形態においては、基板１にＹＡＧレーザーの加工により、溝１１を設けたが、溝１１をホトリソグラフィーとエッチングにより形成することもできる。
In the embodiment described above, the
１ ｎ型単結晶シリコン基板
２ ｉ型非晶質シリコン層
３ ｐ型非晶質シリコン層
４ ＩＴＯ膜
５ 櫛型集電極
６ ｉ型非晶質シリコン層
７ ｎ型非晶質シリコン層
８ ＩＴＯ膜
９ 櫛型集電極
１１ 溝
1 n-type single crystal silicon substrate 2 i-type amorphous silicon layer 3 p-type amorphous silicon layer 4 ITO film 5 comb-shaped collector electrode 6 i-type amorphous silicon layer 7 n-type amorphous silicon layer 8 ITO film 9
Claims (3)
3. The semiconductor device according to claim 1, wherein single crystal silicon is used as the one conductivity type crystalline semiconductor substrate, and a semiconductor layer made of an amorphous or microcrystalline silicon semiconductor is provided at least on a light incident side. Photovoltaic device manufacturing method.
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