JP7237920B2 - Solar cell manufacturing method - Google Patents

Description

The technology disclosed herein belongs to the technical field related to the method of manufacturing a solar cell.

A general solar cell is a double-sided electrode type in which electrodes are arranged on both sides (light-receiving surface and back surface) of a semiconductor substrate. , a back-contact (back electrode) type solar cell in which an electrode is arranged only on the back surface has been developed.

A back-contact solar cell requires a semiconductor layer pattern such as a p-type semiconductor layer and an n-type semiconductor layer to be formed on the back surface with high precision, and the manufacturing method is more complicated than that of a double-sided electrode type solar cell. As a technique for simplifying the manufacturing method, there is a technique for forming a semiconductor layer pattern by a lift-off method, as disclosed in Patent Document 1. That is, the development of a patterning technique for forming a semiconductor layer pattern by removing the lift-off layer and removing the semiconductor layer formed on the lift-off layer is underway.

JP 2013-120863

However, in the method described in Patent Document 1, if the lift-off layer and the semiconductor layer have similar solubility, unintended layers may be removed, and patterning accuracy or productivity may not be improved. There is

The technology disclosed herein has been made in view of the above points, and its purpose is to efficiently manufacture a high-performance back-contact solar cell.

In order to solve the above-mentioned problems, the technology disclosed herein comprises the steps of forming a first semiconductor layer of a first conductivity type on one of two main surfaces facing each other in a semiconductor substrate; stacking a lift-off layer containing oxide as a main component on the first semiconductor layer; selectively removing the first semiconductor layer and the lift-off layer by etching; forming a second semiconductor layer of a second conductivity type on the one main surface including the lift-off layer; and removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer. and in the step of selectively removing the first semiconductor layer and the lift-off layer, when viewed from the one main surface side in the direction perpendicular to the plane of the semiconductor substrate, the etching area of the first semiconductor layer is The first semiconductor layer and the lift-off layer are removed by wet etching using two or more different etchants so that the etching area is equal to or less than the lift-off layer , and the lift-off layer forms the first semiconductor layer. After that, the step of selectively removing the first semiconductor layer and the lift-off layer laminated on the first semiconductor layer without etching the first semiconductor layer is a resist film having a predetermined pattern. A lift-off layer removing step of selectively removing the lift-off layer after being formed on the lift-off layer; and a second step of selectively removing the first semiconductor layer using the resist film used in the lift-off layer removing step. 1 semiconductor layer removing step, and the type of etchant used in the lift-off layer removing step is different from the type of etchant used in the first semiconductor layer removing step.

According to the technique disclosed herein, a high-performance back-contact solar cell can be manufactured efficiently.

1 is a schematic cross-sectional view partially showing a solar cell according to an exemplary embodiment; FIG. FIG. 3 is a plan view showing the back main surface of the crystal substrate that constitutes the solar cell; It is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. It is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. It is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. It is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. It is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. It is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. It is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. It is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. FIG. 8 is a plan view of the state at the end of the process of FIG. 7 viewed from the back main surface side in the direction perpendicular to the plane of the crystal substrate; FIG. 8 is a view equivalent to FIG. 8 showing a modification of the present embodiment; FIG. 9 is a view equivalent to FIG. 9 showing a modification of the present embodiment;

Exemplary embodiments are described with reference to the drawings.

FIG. 1 shows a partial cross-sectional view of a solar cell (cell) according to this embodiment. As shown in FIG. 1, a solar cell 10 according to this embodiment uses a crystalline substrate 11 made of silicon (Si). The crystal substrate 11 has two main surfaces 11S (11SU, 11SB) facing each other. Here, the principal surface on which light is incident is called front principal surface 11SU, and the opposite principal surface is called back principal surface 11SB. For the sake of convenience, the front main surface 11SU is defined as a light-receiving side on the side that more positively receives light than the back main surface 11SB, and a non-light-receiving side on the side that does not positively receive light.

The solar cell 10 according to the present embodiment is a so-called heterojunction crystalline silicon solar cell, and is a back-contact type (back electrode type) solar cell in which an electrode layer is arranged on the back main surface 11SB.

Solar cell 10 includes crystalline substrate 11, intrinsic semiconductor layer 12, conductive semiconductor layer 13 (p-type semiconductor layer 13p, n-type semiconductor layer 13n), low reflection layer 14, and electrode layer 15 (transparent electrode layer 17, metal electrode layer 18).

Hereinafter, for the sake of convenience, members individually corresponding to the p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be added with "p" or "n" at the end of the reference numerals. Also, since the conductivity types are different, such as p-type and n-type, one conductivity type is sometimes referred to as the "first conductivity type" and the other conductivity type as the "second conductivity type".

The crystal substrate 11 may be a semiconductor substrate made of monocrystalline silicon or a semiconductor substrate made of polycrystalline silicon. A single crystal silicon substrate will be described below as an example.

Even if the conductivity type of the crystal substrate 11 is an n-type single crystal silicon substrate into which impurities (for example, phosphorus (P) atoms) that introduce electrons into silicon atoms are introduced, holes are introduced into silicon atoms. A p-type single crystal silicon substrate into which impurities (for example, boron (B)) atoms are introduced may be used. An n-type single crystal substrate, which is said to have a long carrier life, will be described below as an example.

In addition, from the viewpoint of confining the received light, the crystal substrate 11 has a texture structure TX (first texture structure) composed of peaks (convex) and valleys (concave) on the two main surfaces 11S. may have The texture structure TX (uneven surface) is formed, for example, by anisotropic etching that applies the difference between the etching rate of the crystal substrate 11 having a (100) plane orientation and the etching rate having a (111) plane orientation. can be formed.

The thickness of the crystal substrate 11 may be 250 μm or less. The measurement direction when measuring the thickness is perpendicular to the average plane of the crystal substrate 11 (the average plane means the plane of the entire substrate independent of the texture structure TX). Hereinafter, this vertical direction, that is, the direction in which the thickness is measured will be referred to as the perpendicular direction.

The size of unevenness in the texture structure TX can be defined, for example, by the number of vertices. In the present embodiment, the number of vertices is preferably in the range of 50000/mm2 or more and 100000/mm2 or less, and particularly 70000/mm2 or more and 85000/mm2 from the viewpoint of light capturing performance and productivity. mm2 or less is preferable.

If the thickness of the crystal substrate 11 is set to 250 μm or less, the amount of silicon used can be reduced, so it becomes easier to secure the silicon substrate and the cost can be reduced. In addition, the back contact structure in which the holes and electrons generated by photoexcitation in the silicon substrate are recovered only on the back side is preferable from the viewpoint of the free path of each exciton.

On the other hand, if the thickness of the crystal substrate 11 is too small, the mechanical strength will be lowered, and the outside light (sunlight) will not be sufficiently absorbed, resulting in a decrease in the short-circuit current density. Therefore, the thickness of the crystal substrate 11 is preferably 50 μm or more, more preferably 70 μm or more. When the textured structure TX is formed on the main surface of the crystal substrate 11, the thickness of the crystal substrate 11 is represented by the distance between straight lines connecting the apexes of the convexes in the concave-convex structures on the light receiving side and the back side. be done.

The intrinsic semiconductor layers 12 (12U, 12p, 12n) cover both main surfaces 11S (11SU, 11SB) of the crystal substrate 11, thereby suppressing diffusion of impurities into the crystal substrate 11 and performing surface passivation. It should be noted that the term “intrinsic (i-type)” is not limited to a completely intrinsic material containing no conductive impurities, but rather a “weakly conductive material” containing a small amount of n-type or p-type impurities to the extent that the silicon-based layer can function as an intrinsic layer. It also includes layers that are substantially intrinsic of "n-type" or "weakly p-type."

It should be noted that the intrinsic semiconductor layers 12 (12U, 12p, 12n) are not essential, and may be appropriately formed as needed.

Although the material of the intrinsic semiconductor layer 12 is not particularly limited, it may be an amorphous silicon thin film, or a hydrogenated amorphous silicon thin film containing silicon and hydrogen (a-Si:H thin film). good too. The term "amorphous" as used herein means a long-period, non-ordered structure. In other words, not only complete disorder but also short-period order are included.

Although the thickness of the intrinsic semiconductor layer 12 is not particularly limited, it may be 2 nm or more and 20 nm or less. This is because when the thickness is 2 nm or more, the effect as a passivation layer is enhanced, and when the thickness is 20 nm or less, deterioration of conversion characteristics caused by high resistance can be suppressed.

A method for forming the intrinsic semiconductor layer 12 is not particularly limited, but a plasma enhanced chemical vapor deposition (CVD) method is used. According to this method, it is possible to effectively passivate the substrate surface while suppressing the diffusion of impurities into single crystal silicon. Further, with the plasma CVD method, by changing the hydrogen concentration in the intrinsic semiconductor layer 12 in the thickness direction, it is possible to form an energy gap profile effective for recovering carriers.

The conditions for forming a thin film by the plasma CVD method include, for example, a substrate temperature of 100° C. or higher and 300° C. or lower, a pressure of 20 Pa or higher and 2600 Pa or lower, and a high frequency power density of 0.003 W/cm ² or higher and 0.5 W/cm2. cm ² or less.

In the case of the intrinsic semiconductor layer 12, _the raw material gas used for forming the thin film includes silicon-containing gases such as monosilane ( _SiH4 ) and disilane ( _Si2H6 ), or these gases and hydrogen (H2 ₎ . ) may be a mixed gas.

Incidentally, a gas containing a different element such as methane (CH ₄ ), ammonia (NH ₃ ) or monogermane (GeH ₄ ) is added to the above gas to form silicon carbide (SiC) or silicon nitride (SiN _{X )} . ) or a silicon compound such as silicon germanium (SIGe) to change the energy gap of the thin film accordingly.

Conductive semiconductor layer 13 includes p-type semiconductor layer 13p and n-type semiconductor layer 13n. As shown in FIG. 1, p-type semiconductor layer 13p is formed on part of back surface 11SB of crystal substrate 11 with intrinsic semiconductor layer 12p interposed therebetween. N-type semiconductor layer 13n is formed on another portion of the back main surface of crystal substrate 11 with intrinsic semiconductor layer 12n interposed therebetween. In other words, between the p-type semiconductor layer 13p and the crystal substrate 11 and between the n-type semiconductor layer 13n and the crystal substrate 11, the intrinsic semiconductor layer 12 is interposed as an intermediate layer serving as passivation.

Each thickness of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n is not particularly limited, but may be 2 nm or more and 20 nm or less. This is because when the thickness is 2 nm or more, the effect as a passivation layer is enhanced, and when the thickness is 20 nm or less, deterioration of conversion characteristics caused by high resistance can be suppressed.

The p-type semiconductor layer 13p and the n-type semiconductor layer 13n are arranged on the back side of the crystal substrate 11 so that the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are electrically separated through the intrinsic semiconductor layer 12. be. The width of the conductive semiconductor layer 13 may be 50 μm or more and 3000 μm or less, or may be 80 μm or more and 500 μm or less. Unless otherwise specified, the widths of the semiconductor layers 12 and 13 and the widths of the electrode layers 17 and 18 are the lengths of part of each patterned layer. It means the length in the direction perpendicular to the extension direction.

In the solar cell 10 of this embodiment, part of the intrinsic semiconductor layer 12n and part of the n-type semiconductor layer 13n are formed on the p-type semiconductor layer 13p. The portions of the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n formed on the p-type semiconductor layer 13p are configured so that the edges in the width direction are substantially flush.

When photoexcitons (carriers) generated in the crystal substrate 11 are taken out through the conductive semiconductor layer 13, holes have a larger effective mass than electrons. Therefore, from the viewpoint of reducing transport loss, the width of p-type semiconductor layer 13p may be narrower than that of n-type semiconductor layer 13n. For example, the width of the p-type semiconductor layer 13p may be 0.5 to 0.9 times the width of the n-type semiconductor layer 13n, or 0.6 to 0.8 times the width of the n-type semiconductor layer 13n. good too.

The p-type semiconductor layer 13p is a silicon layer to which a p-type dopant (such as boron) is added, and may be formed of amorphous silicon from the viewpoint of suppressing impurity diffusion or suppressing series resistance. On the other hand, the n-type semiconductor layer 13n is a silicon layer to which an n-type dopant (such as phosphorus) is added, and may be formed of an amorphous silicon layer like the p-type semiconductor layer 13p.

Silicon-containing gas such as monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ), or a mixed gas of silicon-based gas and hydrogen (H ₂ ) may be used as the material gas for the conductive semiconductor layer 13 . As the dopant gas, diborane (B ₂ H ₆ ) or the like is used for forming the p-type semiconductor layer 13p, and phosphine (PH ₃ ) or the like is used for forming the n-type semiconductor layer. Further, since the amount of impurities such as boron (B) or phosphorus (P) to be added may be very small, a mixed gas obtained by diluting a dopant gas with a raw material gas may be used.

Further, in order to adjust the energy gap of the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, a different kind of gas such as methane (CH ₄ ), carbon dioxide (CO ₂ ), ammonia (NH ₃ ) or monogermane (GeH ₄ ) is used. p-type semiconductor layer 13p or n-type semiconductor layer 13n may be alloyed by adding a gas containing the element

The low-reflection layer 14 is a layer that suppresses reflection of light received by the solar cell 10 . The material of the low-reflection layer 14 is not particularly limited as long as _it is a light-transmitting material that transmits _light . Titanium ( _TiOx ) can be mentioned. As a method for forming the low-reflection layer 14, for example, a resin material in which nanoparticles of an oxide such as zinc oxide or titanium oxide are dispersed may be applied.

Electrode layer 15 is formed to cover p-type semiconductor layer 13p or n-type semiconductor layer 13n, respectively, and is electrically connected to each conductive semiconductor layer 13 . Thereby, the electrode layer 15 functions as a transport layer that guides carriers generated in the p-type semiconductor layer 13p or the n-type semiconductor layer 13n. The electrode layers 15p and 15n corresponding to the semiconductor layers 13p and 13n are arranged apart from each other, thereby preventing a short circuit between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n.

Moreover, the electrode layer 15 may be formed only of a highly conductive metal. In addition, from the viewpoint of electrical connection with each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, or from the viewpoint of suppressing the diffusion of atoms into both the metal semiconductor layers 13p and 13n, which are electrode materials, the transparent An electrode layer 15 made of a conductive oxide may be provided between the metal electrode layer and the p-type semiconductor layer 13p and between the metal electrode layer and the n-type semiconductor layer 13n.

In this embodiment, the electrode layer 15 made of a transparent conductive oxide is referred to as a transparent electrode layer 17 and the metal electrode layer 15 is referred to as a metal electrode layer 18 . Further, as shown in the plan view of the back main surface 11SB of the crystal substrate 11 shown in FIG. 2, in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n each having a comb-teeth shape, an electrode layer is formed on the back of the comb. are called busbar portions, and the electrode layers formed on the comb tooth portions are sometimes called finger portions.

_{The material} of the transparent electrode layer 17 is not particularly limited. SnO _x ), tungsten oxide (WO _x ), molybdenum oxide (MoO _x ), or the like is added in an amount of 1% by weight or more and 10% by weight or less.

The thickness of the transparent electrode layer 17 may be 20 nm or more and 200 nm or less. Methods for forming a transparent electrode layer suitable for this thickness include, for example, a physical vapor deposition (PVD) method such as a sputtering method, or a metal organic layer using a reaction between an organometallic compound and oxygen or water. Chemical vapor deposition method (MOCVD:Metal-Organic Chemical Vapor Deposition) method etc. are mentioned.

Although the material of the metal electrode layer 18 is not particularly limited, examples thereof include silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), and the like.

The thickness of the metal electrode layer 18 may be 1 μm or more and 80 μm or less. A method of forming the metal electrode layer 18 suitable for this thickness includes a printing method in which a material paste is printed by inkjet printing or screen printing, or a plating method. However, the method is not limited to this, and vapor deposition or sputtering may be employed when a vacuum process is employed.

Moreover, the width of the comb tooth portions in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n may be approximately the same as the width of the metal electrode layer 18 formed on the comb tooth portions. However, the width of the metal electrode layer 18 may be narrower than the width of the comb tooth portion. Moreover, the width of the metal electrode layer 18 may be wider than the width of the comb tooth portion as long as the structure prevents leakage between the metal electrode layers 18 .

In this embodiment, the intrinsic semiconductor layer 12, the conductive semiconductor layer 13, the low-reflection layer 14, and the electrode layer 15 are laminated on the back side main surface 11SB of the crystal substrate 11, and passivation and conduction of each joint surface are performed. A predetermined annealing treatment is performed for the purpose of suppressing generation of defect levels in the semiconductor layer 13 and its interface and crystallizing the transparent conductive oxide in the transparent electrode layer 17 .

An annealing treatment according to the present embodiment includes, for example, an annealing treatment in which the crystal substrate 11 having the above layers formed thereon is placed in an oven heated to 150° C. or higher and 200° C. or lower. In this case, the atmosphere in the oven may be the air, and if hydrogen or nitrogen is used, more effective annealing can be performed. Further, this annealing treatment may be an RTA (Rapid Thermal Annealing) treatment in which the crystal substrate 11 on which each layer is formed is irradiated with infrared rays from an infrared heater.

[Method for manufacturing solar cell]
A method for manufacturing the solar cell 10 according to this embodiment will be described below with reference to FIGS. 3 to 9. FIG.

First, as shown in FIG. 3, the crystal substrate 11 having the texture structure TX on each of the front main surface 11SU and the back main surface 11SB is prepared.

Next, as shown in FIG. 4, on the front main surface 11SU of the crystal substrate 11, for example, an intrinsic semiconductor layer 12U is formed. Subsequently, the low reflection layer 14 is formed on the formed intrinsic semiconductor layer 12U. Silicon nitride (SiN _x ) or silicon oxide (SiO _x ) having a suitable light absorption coefficient and refractive index is used for the low reflection layer 14 from the viewpoint of light confinement.

Next, as shown in FIG. 5, on the back main surface 11SB of the crystal substrate 11, an intrinsic semiconductor layer 12p is formed using i-type amorphous silicon, for example. Subsequently, a p-type semiconductor layer 13p is formed on the formed intrinsic semiconductor layer 12p. As a result, p-type semiconductor layer 13p is formed on back side main surface 11SB, which is one main surface of crystal substrate 11 . As described above, in the present embodiment, the step of forming the p-type semiconductor layer (first semiconductor layer) 13p is performed on one side of the crystal substrate (semiconductor substrate) 11 before forming the p-type semiconductor layer 13p. A step of forming an intrinsic semiconductor layer (first intrinsic semiconductor layer) 12p on the main surface (back side main surface) 11S is included.

After that, a lift-off layer LF is formed on the formed p-type semiconductor layer 13p. In this embodiment, the lift-off layer LF is mainly composed of oxide. Specifically, the lift-off layer LF is mainly composed of an oxide of an element selected from one or more of indium (In), zinc (Zn), tin (SnO), aluminum (Al), and silicon (Si). is configured as The lift-off layer LF does not need to be an oxide (for example, indium oxide (InO _x )) composed of one of the above elements, and may be, for example, an indium-tin composite oxide, an indium-aluminum composite oxide, or an indium-silicon oxide. Ternary type such as composite oxide, zinc-silicon composite oxide, zinc-tin composite oxide, zinc-aluminum composite oxide, aluminum-silicon composite oxide, indium-zinc-tin composite oxide, zinc-tin - A quaternary type such as a silicon composite oxide can be selected.

The lift-off layer LF can be formed by a vacuum process, particularly a CVD method or a sputtering method. In these methods, it is possible to control the film quality such as density by controlling the flow rate ratio and pressure of the raw material gas, the voltage during plasma discharge, etc., without significantly changing the composition. Furthermore, by changing the film forming conditions in the film thickness direction, it is possible to adjust the etching characteristics in the film thickness direction. Also, the structure of the oxide formed by the vacuum process is not particularly limited, but includes, for example, a structure containing physical or chemical voids (defects) inside the layer. When the lift-off layer LF is formed by a vacuum process, growing particles grow so as to pile up almost perpendicularly to the film formation surface. In this case, a large number of grain bodies formed of grown grains may be generated, and voids may be generated between the grain bodies. In the case of the lift-off layer LF containing such voids, the etching solution can easily penetrate into the inside of the layer, which may increase the etching rate. Therefore, the lift-off time, which will be described later, can be shortened.

Next, as shown in FIGS. 6 and 7, on the back main surface 11SB of the crystal substrate 11, the lift-off layer LF and the p-type semiconductor layer 13p are patterned. As a result, a non-formation region NA is generated where the p-type semiconductor layer 13p is not formed. On the other hand, the lift-off layer LF and the p-type semiconductor layer 13p remain in the region of the back main surface 11SB of the crystal substrate 11 that has not been etched.

6 and 7, the area of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p melted by etching (hereinafter referred to as the etching area) is , the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the lift-off layer LF are removed by wet etching using two or more different etchants so that the etched area is equal to or less than the lift-off layer LF. More specifically, the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p have a width equal to or greater than the width of the lift-off layer LF when viewed from the side of the back main surface 11SB in the perpendicular direction of the crystal substrate 11. , the p-type semiconductor layer 13p and the lift-off layer LF are removed.

In the actual process, as shown in FIG. 6, the lift-off layer is selectively removed by wet etching using a first etchant, and then the intrinsic semiconductor layer 12 and the p-type semiconductor layer are removed as shown in FIG. , are selectively removed by wet etching using a second etchant.

Such a patterning step can be realized by photolithography, for example, by forming a resist film (not shown) having a predetermined pattern on the lift-off layer LF and etching the region masked by the formed resist film. . As shown in FIGS. 6 and 7, by patterning each layer of the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p and the lift-off layer LF, a non-formation region NA is formed in a partial region of the back main surface 11SB of the crystal substrate 11. , that is, an exposed region of the back main surface 11SB is generated. Details of the non-formation area NA will be described later.

As the first etchant used in the process shown in FIG. 6, for example, a strong acid etchant such as hydrochloric acid or nitric acid is used. On the other hand, as the second etchant used in the process shown in FIG. 7, for example, a solution obtained by dissolving ozone in hydrofluoric acid (hereinafter referred to as ozone/hydrofluoric acid solution) is used.

Note that the ozone/hydrofluoric acid solution, which is the second etching solution, etches not only the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p, but also the lift-off layer LF. Therefore, in the state after the process shown in FIG. 7, the edges in the width direction of the lift-off layer LF recede compared to the state after the process shown in FIG. As a result, the edge of the lift-off layer LF is recessed from the edge of the p-type semiconductor layer 13p. As a result, as shown in FIG. 11, the widths of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p become equal to or larger than the width of the lift-off layer LF when viewed from the side of the back main surface 11SB in the perpendicular direction of the crystal substrate 11 .

Next, as shown in FIG. 8, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed on the back main surface 11SB of the crystal substrate 11 including the lift-off layer LF, the p-type semiconductor layer 13p and the intrinsic semiconductor layer 12p. Form sequentially. As described above, in the present embodiment, the step of forming the n-type semiconductor layer (second semiconductor layer) 13n includes the step of forming the lift-off layer of the crystal substrate (semiconductor substrate) 11 before forming the n-type semiconductor layer 13n. A step of forming an intrinsic semiconductor layer (second intrinsic semiconductor layer) 12n on one main surface (back side main surface) 11S including the LF and the p-type semiconductor layer is included. As a result, the laminated film of the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n is formed on the non-formation region NA, the surface and side surfaces (end surfaces) of the lift-off layer LF, the lift-off layer LF, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer. It is formed so as to cover the side surfaces (end surfaces) of the layer 12p. Here, since the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed in a state in which the edge of the lift-off layer LF recedes from the edge of the p-type semiconductor layer 13p, as shown in FIG. A portion of the semiconductor layer 12n and a portion of the n-type semiconductor layer 13n are formed directly on the p-type semiconductor layer 13p.

Next, as shown in FIG. 9, an etchant is used to remove the laminated lift-off layer LF, thereby removing the n-type semiconductor layer 13n and the intrinsic semiconductor layer 12n covering the lift-off layer LF from the crystal substrate 11 ( lift off). Here, it is not necessary to dissolve the second intrinsic semiconductor layer and the second conductivity type semiconductor layer covering the lift-off layer LF, and they are separated from the crystal substrate at the same time as the lift-off layer is removed. As the etchant used for this patterning, it is preferable to use a solvent that dissolves the lift-off layer LF but does not dissolve the intrinsic semiconductor layers 12 and the conductive semiconductor layers 13 . For example, when the lift-off layer LF is mainly composed of a metal oxide such as indium oxide (InO _x ) or zinc oxide (ZnO), an acidic liquid such as hydrochloric acid is used, and the lift-off layer LF is made of silicon oxide (SiO _x ) is the main component, hydrofluoric acid is used.

Next, as shown in FIG. 10, a transparent electrode layer is formed on the back main surface 11SB of the crystal substrate 11, that is, on each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by, for example, a sputtering method using a mask. 17 (17p, 17n). The transparent electrode layers 17 (17p, 17n) may be formed in the following manner instead of the sputtering method. For example, a transparent conductive oxide film is formed on the entire back surface 11SB without using a mask, and then a transparent conductive film is formed on the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by photolithography. It may be formed by performing etching to leave a protective oxide film.

After that, a linear metal electrode layer 18 (18p, 18n) is formed on the transparent electrode layer 17 using, for example, a mesh screen (not shown) having openings.

Through the steps described above, the back contact solar cell 10 is formed.

(Summary and effect)
The following can be said from the manufacturing method of the solar cell 10 mentioned above.

First, in the process shown in FIG. 9, when the lift-off layer LF is removed with an etchant, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n deposited on the lift-off layer LF are simultaneously removed from the crystal substrate 11. (So-called lift-off). This process does not require the resist coating process and the development process used in the photolithography method, as compared with the case of using the photolithography method, for example, in the process shown in FIG. Therefore, the n-type semiconductor layer 13n is easily patterned.

Further, the lift-off layer LF is mainly composed of an oxide, and in the process of patterning the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the lift-off layer LF, when viewed from the back side of the crystal substrate 11 in the perpendicular direction, the intrinsic semiconductor The intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p and the lift-off layer 12p, the p-type semiconductor layer 13p and the lift-off layer 12p are etched by wet etching using two or more different etchants so that the etching areas of the layer 12p and the p-type semiconductor layer 13p are equal to or less than the etching area of the lift-off layer LF. Layer LF is removed. In this manner, etching is performed such that the etching area of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p is equal to or less than the etching area of the lift-off layer LF, so that when the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed, , the crystal substrate 11 is prevented from being exposed.

That is, if the etching area of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p is larger than the etching area of the lift-off layer LF when viewed from the back side of the crystal substrate 11 in the perpendicular direction, the intrinsic semiconductor layer 12p and the p-type semiconductor layer 12p A state in which the semiconductor layer 13p recedes from the lift-off layer LF (a side-cut state) is obtained. When the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed in this state, the lift-off layer LF plays a role like a mask, and the side surfaces of the intrinsic semiconductor layer 12n above the non-formation region NA and the intrinsic semiconductor layers 12p and p. A gap is generated between the semiconductor layer 13p and the side surface of the semiconductor layer 13p. Then, when the lift-off layer LF, the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are removed, the crystal substrate 11 is formed between the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p and the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n. The back main surface 11SB is exposed. If the back main surface 11SB of the crystal substrate 11 is exposed, the effective area for collecting holes and electrons is reduced by the amount of the exposed area, which deteriorates the performance of the solar cell.

In contrast, when the lift-off layer LF is mainly composed of oxide as in the present embodiment, the etching characteristics of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p and the etching characteristics of the lift-off layer LF are different. to differ greatly. By using a different etchant for etching the lift-off layer LF and an etchant for etching the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p, the etching area of each layer can be controlled, particularly the intrinsic semiconductor layer. Patterning accuracy in the width direction of 12p and p-type semiconductor layer 13p is improved. As a result, the etching area of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p becomes equal to or less than the etching area of the lift-off layer LF. As a result, the side surfaces of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are flush with the side surfaces of the lift-off layer LF, or the lift-off layer LF seems to recede from the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p. state. If the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed in this state, the intrinsic semiconductor layer 12n is formed so as to be in contact with at least the side surfaces of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p. Exposure of the substrate 11 is suppressed. Therefore, deterioration of the performance of the solar cell is suppressed, and it becomes possible to manufacture a high-performance solar cell.

For these reasons, according to the present embodiment, a high-performance back-contact solar cell can be manufactured efficiently.

As described above, in order to control the etching area of each layer, the etching rate of the first etchant used in the process of FIG.
Etching rate of intrinsic semiconductor layer 12p≦etching rate of p-type semiconductor layer 13p <<etching rate of lift-off layer LF (1)
and the etching rate of the second etchant used in the process shown in FIG. 7 is the following relational expression (2):
Etching rate of intrinsic semiconductor layer 12p≦etching rate of p-type semiconductor layer 13p≦etching rate of lift-off layer LF (2)
is preferably satisfied.

If the first etchant satisfies the relational expression (1), the lift-off layer LF can be dissolved selectively and quickly in the process shown in FIG. Since the second etchant satisfies the relational expression (2), the lift-off layer LF is also dissolved when the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are dissolved in the process shown in FIG. Therefore, the etching area of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p does not become larger than the etching area of the lift-off layer LF, and side cutting of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p is unlikely to occur.

The above relationships (1) and (2) can be satisfied depending on the type of etchant or the concentration of the etchant.

The thickness of the lift-off layer LF is preferably 20 nm or more and 500 nm or less, and more preferably 50 nm or more and 250 nm or less. That is, if the thickness of the lift-off layer LF is too thick, there is concern about insufficient etching in the process of FIG. 6 or a decrease in productivity. Moreover, if the film thickness of the lift-off layer LF is too thick, there is a possibility that the lift-off layer LF will have an inversely tapered undercut due to side etching. When an inversely tapered undercut occurs in the lift-off layer LF, the width of the lift-off layer LF becomes narrower than the surface of the lift-off layer LF toward the p-type semiconductor layer 13p. Therefore, in the state after etching the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p, the edge portions of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are located on the farthest side from the p-type semiconductor layer 13p in the lift-off layer LF. It is in a state of retreating from the edge of the portion. When the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed in this state, the lift-off layer LF serves as a mask as described above, and the side surface of the intrinsic semiconductor layer 12n on the non-formation region NA and the intrinsic semiconductor layer 13n are separated from each other. A gap is generated between the side surfaces of the semiconductor layer 12p and the p-type semiconductor layer 13p, and finally the crystal substrate 11 is exposed. Therefore, the thickness of the lift-off layer LF must be set to a thickness that can prevent the reverse tapered undercut as described above. On the other hand, if the film thickness is too thin, the lift-off layer LF may be completely removed (lifted off) when patterning the lift-off layer LF in the process shown in FIG. Become. Therefore, the film thickness of the lift-off layer LF is particularly preferably 20 nm or more and 500 nm or less.

Further, the crystal substrate 11 has a texture structure TX, and each surface of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n formed on the back surface 11SB of the crystal substrate 11 has the texture structure TX. It is preferable that a texture structure (second texture structure) reflecting the is included.

If the conductive semiconductor layer 13 has the texture structure TX on its surface, the etchant will easily permeate into the semiconductor layer 13 due to the unevenness of the texture structure TX. Therefore, the conductive semiconductor layer 13 is easily removed, that is, easily patterned.

In the present embodiment, the texture structure TX (first texture structure) is provided on both main surfaces 11S of the crystal substrate 11, that is, the front main surface 11SU and the back main surface 11SB, but only one of the main surfaces may be set to That is, when the texture structure TX is provided on the front main surface 11SU, the effect of capturing and confining the received light is enhanced. On the other hand, when the texture structure TX is provided on the back main surface 11SB, the effect of taking in light is improved and the patterning of the conductive semiconductor layer 13 is facilitated. Therefore, the texture structure TX of the crystal substrate 11 may be provided on at least one main surface 11S. Further, in the present embodiment, the texture structures TX on both main surfaces 11S have the same pattern, but this is not restrictive. good too.

The technology disclosed herein is not limited to the above-described embodiments, and substitutions are possible without departing from the scope of the claims.

For example, in the above-described embodiment, in the process shown in FIG. 7, the width of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p when viewed from the back side of the crystal substrate 11 in the direction perpendicular to the plane is greater than the width of the lift-off layer LF. However, the width of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p is substantially the same as the width of the lift-off layer LF (actually Alternatively, patterning (etching) may be performed so that the width of the lift-off layer LF is slightly smaller. That is, when the widths of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are substantially the same as the width of the lift-off layer LF, the edges of the lift-off layer LF and the edges of the p-type semiconductor layer 13p are located at substantially the same positions. do. When the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed in this state, as shown in FIG. It is formed. By removing the lift-off layer LF, the n-type semiconductor layer 13n and the intrinsic semiconductor layer 12n deposited on the lift-off layer LF are removed from the crystal substrate 11. As shown in FIG. 13n is not formed on p-type semiconductor layer 13p, and is separated from p-type semiconductor layer 13p via intrinsic semiconductor layer 12n in the width direction. When the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are formed in this manner, a separation groove is formed at the boundary between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n from the viewpoint of suppressing the occurrence of leakage. is preferably formed.

In the above-described embodiment, the semiconductor layer used in the process shown in FIG. 5 was the p-type semiconductor layer 13p, but it is not limited to this and may be the n-type semiconductor layer 13n. Also, the conductivity type of the crystal substrate 11 is not particularly limited, and may be either p-type or n-type.

The above-described embodiments are merely examples, and the technical scope of the present disclosure should not be construed to be limited. The technical scope of the present disclosure is defined by the claims, and all modifications and changes within the equivalent range of the claims are within the technical scope of the present disclosure.

Hereinafter, the technology according to the present disclosure will be specifically described with reference to examples. However, the technology according to the present disclosure is not limited to these examples. Examples 1 to 3 and Comparative Examples 1 and 2 were produced as follows (see [Table 1]). In the following description, Examples 1 to 3 and Comparative Examples 1 and 2 under the same conditions are not particularly distinguished.

[Crystal substrate]
First, a single crystal silicon substrate having a thickness of 200 μm was adopted as a crystal substrate. Anisotropic etching was performed on both main surfaces of the single crystal silicon substrate. As a result, a pyramidal textured structure was formed on the crystal substrate.

[Intrinsic semiconductor layer]
A crystal substrate was introduced into a CVD apparatus, and an intrinsic semiconductor layer made of silicon (thickness: 8 nm) was formed on both main surfaces of the introduced crystal substrate. The deposition conditions were a substrate temperature of 150° C., a pressure of 120 Pa, a SiH ₄ /H ₂ flow ratio of 3/10, and a power density of 0.011 W/cm ² .

[p-type semiconductor layer (first conductivity type semiconductor layer)]
A crystalline substrate having intrinsic semiconductor layers formed on both main surfaces was introduced into a CVD apparatus, and a p-type hydrogenated amorphous silicon thin film (thickness: 10 nm) was formed on the intrinsic semiconductor layer on the back main surface. The deposition conditions were a substrate temperature of 150° C., a pressure of 60 Pa, a SiH ₄ /B ₂ H ₆ flow ratio of 1/3, and a power density of 0.01 W/cm ₂ . Also, the flow rate of B ₂ H ₆ gas is the flow rate of diluent gas obtained by diluting B ₂ H ₆ with H ₂ to 5000 ppm.

[Lift-off layer]
In Example 1, a lift-off layer containing indium-tin composite oxide as a main component was formed on the p-type hydrogenated amorphous silicon thin film using a magnetron sputtering apparatus so as to have a thickness of 100 nm. . A mixed gas of argon and oxygen was introduced into a chamber of an apparatus using indium oxide containing 20% by weight of tin oxide as a target and the substrate temperature was set to 150° C., and the pressure in the chamber was set to 0.8 Pa. set to be The mixing ratio of argon and oxygen was set so that the oxygen content was 10% by volume, and film deposition was performed using an AC power supply at a power density of 0.4 W/cm ² .

In Example 2, a lift-off layer mainly composed of zinc-tin composite oxide was formed on the p-type hydrogenated amorphous silicon thin film using a magnetron sputtering apparatus so as to have a thickness of 100 nm. . A mixed gas of argon and oxygen was introduced into the chamber of the apparatus using zinc oxide containing 40% by weight of tin oxide as a target and the substrate temperature was set to 150° C., and the pressure in the chamber was set to 0.8 Pa. set to be The mixing ratio of argon and oxygen was set so that the oxygen content was 5% by volume, and film deposition was performed using an AC power supply at a power density of 0.4 W/cm ² .

In Example 3, a CVD apparatus was used to form a lift-off layer containing silicon oxide (SiO _x ) as a main component on the p-type hydrogenated amorphous silicon thin film to a thickness of 150 nm. The deposition conditions were a substrate temperature of 150° C., a pressure of 0.9 kPa, a SiH ₄ /CO ₂ /H ₂ flow ratio of 1/10/750, and a power density of 0.15 W/cm ² .

In Comparative Example 1, a lift-off layer mainly composed of zinc-tin composite oxide was formed on the p-type hydrogenated amorphous silicon thin film so as to have a thickness of 100 nm. A mixed gas of argon and oxygen was introduced into the chamber of the apparatus using zinc oxide containing 40% by weight of tin oxide as a target and the substrate temperature was set to 150° C., and the pressure in the chamber was set to 0.8 Pa. set to be The mixing ratio of argon and oxygen was set so that the oxygen content was 5% by volume, and film deposition was performed using an AC power supply at a power density of 0.4 W/cm ² .

In Comparative Example 2, a lift-off layer containing copper as a main component was formed to a thickness of 200 nm on the p-type hydrogenated amorphous silicon thin film. Using copper as a target, the substrate temperature was set to 150° C., argon was introduced into the chamber of the apparatus, and the pressure in the chamber was set to 0.6 Pa. Film formation was performed using an AC power supply at a power density of 0.4 W/cm ² .

[Patterning of lift-off layer and first conductivity type semiconductor layer]
First, for each of Examples 1 to 3 and Comparative Examples 1 and 2, a photosensitive resist film was formed on the back main surface of the crystal substrate on which the lift-off layer was formed. This was exposed and developed by photolithography to expose regions where the lift-off layer, p-type semiconductor layer and intrinsic semiconductor layer were to be removed.

In Examples 1 and 2, after exposure and development, the exposed areas of the lift-off layer were removed by immersion in 3% by weight hydrochloric acid. After rinsing with pure water, it was immersed in an ozone/hydrofluoric acid solution in which 5.5% by weight of hydrofluoric acid was mixed with 20 ppm of ozone to remove the exposed p-type semiconductor layer and intrinsic semiconductor layer.

In Example 3, after exposure and development, the lift-off layer in the exposed areas was removed by immersion in 5% by weight hydrofluoric acid. After rinsing with pure water, it was immersed in an ozone/hydrofluoric acid solution in which 5.5% by weight of hydrofluoric acid was mixed with 20 ppm of ozone to remove the exposed p-type semiconductor layer and intrinsic semiconductor layer.

In Comparative Example 1, after exposure and development, it was immersed in an ozone/hydrofluoric acid solution in which 5.5% by weight of hydrofluoric acid was mixed with 20 ppm of ozone. The semiconductor layer was removed.

In Comparative Example 2, after exposure and development, the exposed area of the lift-off layer was removed by immersion in a 7% by weight iron (III) chloride aqueous solution. After rinsing with pure water, it was immersed in an ozone/hydrofluoric acid solution in which 5.5% by weight of hydrofluoric acid was mixed with 20 ppm of ozone to remove the exposed p-type semiconductor layer and intrinsic semiconductor layer.

This process is hereinafter referred to as a patterning process.

[n-type semiconductor layer (second conductivity type semiconductor layer)]
After the patterning step, the crystal substrate having the exposed backside main surface washed with hydrofluoric acid having a concentration of 2% by weight is introduced into a CVD apparatus, and an intrinsic semiconductor layer (thickness 8 nm) is formed on the backside main surface for the first time. It was formed under the same film formation conditions as the semiconductor layer. Subsequently, an n-type hydrogenated amorphous silicon thin film (thickness: 10 nm) was formed on the formed intrinsic semiconductor layer. The deposition conditions were a substrate temperature of 150° C., a pressure of 60 Pa, a SiH ₄ /PH ₃ /H ₂ flow rate ratio of 1/2, and a power density of 0.01 W/cm ² . Also, the flow rate of PH ₃ gas is the flow rate of diluent gas obtained by diluting PH ₃ with H ₂ to 5000 ppm.

[Removal of lift-off layer and second conductivity type semiconductor layer]
In Examples 1 and 2, the crystal substrate on which the n-type semiconductor layer was formed was immersed in hydrochloric acid having a concentration of 3% by weight as an etchant to remove the lift-off layer, the n-type semiconductor layer covering the lift-off layer, and the lift-off layer. and the n-type semiconductor layer were collectively removed.

In Example 3, the crystal substrate on which the n-type semiconductor layer was formed was immersed in hydrofluoric acid having a concentration of 5% by weight as an etchant to form a lift-off layer, an n-type semiconductor layer on the lift-off layer, and The intrinsic semiconductor layer between the lift-off layer and the n-type semiconductor layer was collectively removed.

In Comparative Example 1, although details will be described later, this step was not performed because the lift-off layer was excessively etched to the extent that it did not function as a lift-off layer.

In Comparative Example 2, the crystal substrate on which the n-type semiconductor layer was formed was immersed in iron (III) chloride having a concentration of 7% by weight as an etchant to form a lift-off layer, an n-type semiconductor layer on the lift-off layer, and the intrinsic semiconductor layer between the lift-off layer and the n-type semiconductor layer were collectively removed.

This process is hereinafter referred to as a lift-off process.

[Electrode layer, low reflection layer]
Using a magnetron sputtering apparatus, an oxide film (thickness: 100 nm) serving as the base of the transparent electrode layer was formed on the conductive semiconductor layer of the crystal substrate. A silicon nitride layer was formed on the light-receiving surface side of the crystal substrate as a low-reflection layer. As a transparent conductive oxide, indium oxide (ITO) containing tin oxide at a concentration of 10% by weight was used as a target. A mixed gas of argon and oxygen was introduced into the chamber of the apparatus, and the pressure inside the chamber was set to 0.6 Pa. The mixing ratio of argon and oxygen was set to the lowest resistivity (so-called bottom) condition. In addition, film formation was performed using a DC power supply at a power density of 0.4 W/cm ² .

Next, etching was performed by photolithography so as to leave only the transparent conductive oxide film on the conductive semiconductor layer (p-type semiconductor layer and n-type semiconductor layer) to form a transparent electrode layer. The transparent electrode layer formed by this etching prevented conduction between the transparent conductive oxide film on the p-type semiconductor layer and the transparent conductive oxide film on the n-type semiconductor layer.

Further, an undiluted silver paste (Dotite FA-333 manufactured by Fujikura Kasei Co., Ltd.) was screen-printed on the transparent electrode layer and heat-treated in an oven at a temperature of 150° C. for 60 minutes. Thus, a metal electrode layer was formed.

Next, an evaluation method for back-contact solar cells will be described. Refer to [Table 1] for the evaluation results.

[Evaluation of film thickness and etchability]
The film thickness or etching state of the lift-off layer was evaluated using an optical microscope (BX51: manufactured by Olympus Optical Co., Ltd.) and SEM (Field Emission Scanning Electron Microscope S4800: manufactured by Hitachi High-Technologies Corporation). After the patterning process, the p-type semiconductor layer is etched less than the lift-off layer (the p-type semiconductor layer is etched away from the lift-off layer by observing with an optical microscope from the back main surface of the crystal substrate) while being etched according to the designed patterning removal area. When the edge portion did not recede from the edge portion of the lift-off layer), it was rated as "○", and when the lift-off layer was excessively etched and the solar cell characteristics were adversely affected, it was rated as "x".

In the lift-off process, when the lift-off layer was removed, it was evaluated as "◯", and when the lift-off layer remained, it was evaluated as "x". In Comparative Example 2, the lift-off layer was excessively removed in the patterning process, and evaluation after the lift-off process was impossible.

[Evaluation of conversion efficiency]
A solar simulator was used to irradiate standard sunlight of AM (air mass) 1.5 at a light amount of 100 mW/cm ² to measure the conversion efficiency (Eff (%)) of the solar cell. Taking the conversion efficiency (solar cell characteristics) of Example 1 as 1.00, the relative values are shown in [Table 1].

Examples 1 to 3 were good in both pattern accuracy and solar cell characteristics.

By comparing Example 2 and Comparative Example 1, it was found that even when the zinc-tin composite oxide was used as the lift-off layer, the etching in the patterning process was improved by using two types of etchants. That is, the ozone/hydrofluoric acid necessary for etching the semiconductor layer of the first conductivity type (here, the p-type semiconductor layer) and the intrinsic semiconductor layer etches the lift-off layer, and the etchant is used to etch the semiconductor layer of the first conductivity type and the intrinsic semiconductor layer. It takes time to reach the intrinsic semiconductor layer, during which time the lift-off layer is excessively etched. On the other hand, when two types of etchants (here, hydrochloric acid and ozone/hydrofluoric acid) are used, the lift-off layer is first etched with hydrochloric acid, and then the semiconductor layer of the first conductivity type and the intrinsic semiconductor layer are etched with ozone/hydrofluoric acid. can be etched. While removing the semiconductor layer of the first conductivity type and the intrinsic semiconductor layer with ozone/hydrofluoric acid, the lift-off layer is also etched. , the etching time may be short, and the etching amount of the lift-off layer may be very small. Therefore, the etching in the patterning process is improved.

Further, by comparing Examples 1 to 3 and Comparative Example 2, ozone/hydrofluoric acid not only etches the semiconductor layer of the first conductivity type and the intrinsic semiconductor layer, but also slightly etches the lift-off layer. It was found that the side cut of the conductive semiconductor layer and the intrinsic semiconductor layer was suppressed. That is, not a few crystal grain boundaries exist in the lift-off layer of the metal oxide. If the lift-off layer is not etched at all during the etching of the semiconductor layer of the first conductivity type and the intrinsic semiconductor layer, the etchant passes through the grain boundaries of the lift-off layer and the like, and the first conductivity type semiconductor layer and the intrinsic semiconductor layer are etched. may reach On the other hand, the lift-off layer is also slightly etched during the etching of the semiconductor layer of the first conductivity type and the intrinsic semiconductor layer, so that the edges of the semiconductor layer of the first conductivity type and the intrinsic semiconductor layer recede due to the etching. When this is done, the edges of the lift-off layer are also recessed by etching. Therefore, it is possible to prevent the etchant from passing through the grain boundaries of the lift-off layer and etching the first conductivity type semiconductor layer and the intrinsic semiconductor layer located under the lift-off layer.

In summary, compared with the comparative example, the solar cell characteristics of the example were improved by using a lift-off layer containing an oxide as a main component and performing wet etching using two types of etchants. . This is to etch each layer as quickly as possible using two kinds of etchants, and that the lift-off layer is slightly etched by the etchant when etching the semiconductor layer of the first conductivity type and the intrinsic semiconductor layer. Thus, both the patterning process and the lift-off process are performed uniformly and accurately, and thereby the arrangement of the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type or the electrical contact (in series) with the electrode layer is achieved. This is thought to be because resistance rise suppression) is improved.

In particular, when the semiconductor layer of the first conductivity type and the intrinsic semiconductor layer are etched, the lift-off layer is slightly etched with the etchant, thereby suppressing the side cutting of the semiconductor layer of the first conductivity type and the intrinsic semiconductor layer. Therefore, it is considered that sufficient solar cell characteristics can be obtained.

10 solar cell 11 crystal substrate (semiconductor substrate)
12 intrinsic semiconductor layer 13 conductivity type semiconductor layer 13p p-type semiconductor layer [first conductivity type first semiconductor layer/second conductivity type second semiconductor layer]
13n n-type semiconductor layer [second conductivity type first semiconductor layer/first conductivity type second semiconductor layer]
15 electrode layer 17 transparent electrode layer 18 metal electrode layer LF lift-off layer

Claims (6)

forming a first semiconductor layer of a first conductivity type on one of two main surfaces facing each other in a semiconductor substrate;
stacking a lift-off layer containing oxide as a main component on the first semiconductor layer;
selectively removing the first semiconductor layer and the lift-off layer by etching;
forming a second semiconductor layer of a second conductivity type on the one main surface including the first semiconductor layer and the lift-off layer;
removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer;
In the step of selectively removing the first semiconductor layer and the lift-off layer, the etching area of the first semiconductor layer, viewed from the one main surface side in the direction perpendicular to the plane of the semiconductor substrate, is equal to that of the lift-off layer. removing the first semiconductor layer and the lift-off layer by wet etching using two or more different etchants so that the area is equal to or less than the etching area;
The lift-off layer is laminated on the first semiconductor layer without etching the first semiconductor layer after forming the first semiconductor layer,
The step of selectively removing the first semiconductor layer and the lift-off layer includes a lift-off layer removing step of selectively removing the lift-off layer after forming a resist film having a predetermined pattern on the lift-off layer. and a first semiconductor layer removing step of selectively removing the first semiconductor layer using the resist film used in the lift-off layer removing step,
A method for manufacturing a solar cell in which a type of etchant used in the lift-off layer removing step is different from a type of etchant used in the first semiconductor layer removing step. In the method for manufacturing a solar cell according to claim 1 ,
When the etchant used in the lift-off layer removal step is the first etchant and the etchant used in the first semiconductor layer removal step is the second etchant,
The first etchant has the following relational expression (1):
The etching rate of the first semiconductor layer <<etching rate of the lift-off layer is satisfied,
The second etchant satisfies the following relational expression (2):
A method for manufacturing a solar cell that satisfies the etching rate of the first semiconductor layer≦etching rate of the lift-off layer. In the method for manufacturing a solar cell according to claim 1 or 2 ,
The method of manufacturing a solar cell, wherein the lift-off layer is mainly composed of an oxide of an element selected from indium, zinc, tin, aluminum and silicon. In the method for manufacturing a solar cell according to any one of claims 1 to 3 ,
In the method of manufacturing a solar cell, in the step of stacking the lift-off layer, the lift-off layer is formed to have a thickness of 20 nm or more and 500 nm or less. In the method for manufacturing a solar cell according to any one of claims 1 to 4 ,
The semiconductor substrate has a first texture structure on each of the two main surfaces,
The method of manufacturing a solar cell, wherein the first semiconductor layer and the second semiconductor layer formed on the one main surface of the semiconductor substrate include a second texture structure reflecting the first texture structure. In the method for manufacturing a solar cell according to any one of claims 1 to 5 ,
In the step of selectively removing the first semiconductor layer and the lift-off layer, in the step of removing the second semiconductor layer, part of the second semiconductor layer is formed on the first semiconductor layer, A method for manufacturing a solar cell, wherein etching is performed so that an edge portion of the lift-off layer is recessed from an edge portion of the first semiconductor layer.

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