JP7183245B2 - Solar cell manufacturing method - Google Patents

Description

The technology disclosed herein belongs to the technical field related to the method of manufacturing a solar cell.

A general solar cell is a double-sided electrode type in which electrodes are arranged on both sides (light-receiving surface and back surface) of a semiconductor substrate. , a back-contact (back electrode) type solar cell in which an electrode is arranged only on the back surface has been developed.

A back-contact solar cell requires a semiconductor layer pattern such as a p-type semiconductor layer and an n-type semiconductor layer to be formed on the back surface with high precision, and the manufacturing method is more complicated than that of a double-sided electrode type solar cell. As a technique for simplifying the manufacturing method, there is a technique for forming a semiconductor layer pattern by a lift-off method, as disclosed in Patent Document 1. That is, the development of a patterning technique for forming a semiconductor layer pattern by removing the lift-off layer and removing the semiconductor layer formed on the lift-off layer is underway.

JP 2013-120863

However, in the method described in Patent Document 1, if the lift-off layer and the semiconductor layer have similar solubility, even an unintended layer may be removed, and patterning precision and productivity may not be improved. be.

Further, in a back-contact solar cell, a transparent electrode layer made of an oxide may be arranged between a semiconductor layer and a metal electrode layer. There is

The technique disclosed herein has been made in view of such points, and the purpose thereof is to provide a high-performance back-contact solar cell in which the adhesion between the electrode layer and the semiconductor layer is improved. Efficient manufacturing.

In order to solve the above-mentioned problems, the technique disclosed herein comprises the steps of: forming a first conductivity type first semiconductor layer on one of two main surfaces facing each other in a semiconductor substrate; stacking a lift-off layer on a first semiconductor layer; selectively removing the first semiconductor layer and the lift-off layer; forming a second semiconductor layer of a second conductivity type; removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer; forming a transparent electrode layer made of oxide on each of the semiconductor layers; The lift-off layer is removed so that part of the first semiconductor layer is covered with the lift-off layer.

According to the technique disclosed herein, a high-performance back-contact solar cell with improved adhesion between the electrode layer and the semiconductor layer can be efficiently manufactured.

1 is a schematic cross-sectional view partially showing a solar cell according to an exemplary embodiment; FIG. FIG. 3 is a plan view showing the back main surface of the crystal substrate that constitutes the solar cell; It is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. It is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. It is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. It is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. It is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. It is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. It is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. FIG. 10 is an enlarged cross-sectional view of a part of the p-type semiconductor layer at the end of lift-off; FIG. 4 is a partial schematic cross-sectional view showing a lift layer in which crystal grains are mixed; FIG. 4 is a partial schematic cross-sectional view showing a case where the lift-off layer is composed of two layers; 4 is a graph showing the relationship between coverage and solar cell characteristics; 4 is a graph showing the relationship between refractive index and solar cell characteristics;

Exemplary embodiments are described below with reference to the drawings.

FIG. 1 shows a partial cross-sectional view of a solar cell (cell) according to this embodiment. As shown in FIG. 1, a solar cell 10 according to this embodiment uses a crystalline substrate 11 made of silicon (Si). The crystal substrate 11 has two main surfaces 11S (11SU, 11SB) facing each other. Here, the principal surface on which light is incident is called front principal surface 11SU, and the opposite principal surface is called back principal surface 11SB. For the sake of convenience, the front main surface 11SU is defined as a light-receiving side on the side that more positively receives light than the back main surface 11SB, and a non-light-receiving side on the side that does not positively receive light.

The solar cell 10 according to the present embodiment is a so-called heterojunction crystalline silicon solar cell, and is a back-contact type (back electrode type) solar cell in which an electrode layer is arranged on the back main surface 11SB.

Solar cell 10 includes crystalline substrate 11, intrinsic semiconductor layer 12, conductive semiconductor layer 13 (p-type semiconductor layer 13p, n-type semiconductor layer 13n), low reflection layer 14, and electrode layer 15 (transparent electrode layer 17, metal electrode layer 18).

Hereinafter, for the sake of convenience, members individually corresponding to the p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be added with "p" or "n" at the end of the reference numerals. Also, since the conductivity types are different, such as p-type and n-type, one conductivity type is sometimes referred to as the "first conductivity type" and the other conductivity type as the "second conductivity type".

The crystal substrate 11 may be a semiconductor substrate made of monocrystalline silicon or a semiconductor substrate made of polycrystalline silicon. A single crystal silicon substrate will be described below as an example.

Even if the conductivity type of the crystal substrate 11 is an n-type single crystal silicon substrate into which impurities (for example, phosphorus (P) atoms) that introduce electrons into silicon atoms are introduced, holes are introduced into silicon atoms. A p-type single crystal silicon substrate into which impurities (for example, boron (B)) atoms are introduced may be used. An n-type single crystal substrate, which is said to have a long carrier life, will be described below as an example.

In addition, from the viewpoint of confining the received light, the crystal substrate 11 has a texture structure TX (first texture structure) composed of peaks (convex) and valleys (concave) on the two main surfaces 11S. may have The texture structure TX (uneven surface) is formed, for example, by anisotropic etching that applies the difference between the etching rate of the crystal substrate 11 having a (100) plane orientation and the etching rate having a (111) plane orientation. can be formed.

The size of unevenness in the texture structure TX can be defined, for example, by the number of vertices. In the present embodiment, the number of vertices is preferably in the range of 50,000/mm ² or more and 100,000/mm ^{2 or} less, particularly 70,000/mm ² or more, from the viewpoint of light capturing performance and productivity. It is preferably 85000/mm ² or less.

The thickness of the crystal substrate 11 may be 250 μm or less. The measurement direction when measuring the thickness is perpendicular to the average plane of the crystal substrate 11 (the average plane means the plane of the entire substrate independent of the texture structure TX). Hereinafter, this vertical direction, that is, the direction in which the thickness is measured will be referred to as the perpendicular direction.

If the thickness of the crystal substrate 11 is set to 250 μm or less, the amount of silicon used can be reduced, so it becomes easier to secure the silicon substrate and the cost can be reduced. In addition, the back contact structure in which the holes and electrons generated by photoexcitation in the silicon substrate are recovered only on the back side is preferable from the viewpoint of the free path of each exciton.

On the other hand, if the thickness of the crystal substrate 11 is too small, the mechanical strength will be lowered, and the outside light (sunlight) will not be sufficiently absorbed, resulting in a decrease in the short-circuit current density. Therefore, the thickness of the crystal substrate 11 is preferably 50 μm or more, more preferably 70 μm or more. When the textured structure TX is formed on the main surface of the crystal substrate 11, the thickness of the crystal substrate 11 is represented by the distance between straight lines connecting the apexes of the convexes in the concave-convex structures on the light receiving side and the back side. be done.

The intrinsic semiconductor layers 12 (12U, 12p, 12n) cover both main surfaces 11S (11SU, 11SB) of the crystal substrate 11, thereby suppressing diffusion of impurities into the crystal substrate 11 and performing surface passivation. It should be noted that the term “intrinsic (i-type)” is not limited to a completely intrinsic material containing no conductive impurities, but rather a “weakly conductive material” containing a small amount of n-type or p-type impurities to the extent that the silicon-based layer can function as an intrinsic layer. It also includes layers that are substantially intrinsic of "n-type" or "weakly p-type."

Although the material of the intrinsic semiconductor layer 12 is not particularly limited, it may be an amorphous silicon thin film, or a hydrogenated amorphous silicon thin film containing silicon and hydrogen (a-Si:H thin film). good too. The term "amorphous" as used herein means a long-period, non-ordered structure. In other words, not only complete disorder but also short-period order are included. Also, the intrinsic semiconductor layers 12 (12U, 12p, 12n) are not essential, and may be appropriately formed as needed.

The thickness of the intrinsic semiconductor layer 12 is not particularly limited, but may be 2 nm or more and 20 nm or less. This is because when the thickness is 2 nm or more, the effect as a passivation layer is enhanced, and when the thickness is 20 nm or less, deterioration of conversion characteristics caused by high resistance can be suppressed.

A method for forming the intrinsic semiconductor layer 12 is not particularly limited, but a plasma enhanced chemical vapor deposition (CVD) method is used. According to this method, it is possible to effectively passivate the substrate surface while suppressing the diffusion of impurities into single crystal silicon. Further, with the plasma CVD method, by changing the hydrogen concentration in the intrinsic semiconductor layer 12 in the thickness direction, it is possible to form an energy gap profile effective for recovering carriers.

The conditions for forming a thin film by the plasma CVD method include, for example, a substrate temperature of 100° C. or higher and 300° C. or lower, a pressure of 20 Pa or higher and 2600 Pa or lower, and a high frequency power density of 0.003 W/cm ² or higher and 0.5 W/cm2. cm ² or less.

In the case of the intrinsic semiconductor layer 12, _the raw material gas used for forming the thin film includes silicon-containing gases such as monosilane ( _SiH4 ) and disilane ( _Si2H6 ), or these gases and hydrogen (H2 ₎ . ) may be a mixed gas.

Incidentally, a gas containing a different element such as methane (CH ₄ ), ammonia (NH ₃ ) or monogermane (GeH ₄ ) is added to the above gas to form silicon carbide (SiC) or silicon nitride (SiN _{X )} . ) or silicon alloys such as silicon germanium (SIGe) to change the energy gap of the thin film accordingly.

Conductive semiconductor layer 13 includes p-type semiconductor layer 13p and n-type semiconductor layer 13n. As shown in FIG. 1, p-type semiconductor layer 13p is formed on part of back surface 11SB of crystal substrate 11 with intrinsic semiconductor layer 12p interposed therebetween. N-type semiconductor layer 13n is formed on another portion of the back main surface of crystal substrate 11 with intrinsic semiconductor layer 12n interposed therebetween. In other words, between the p-type semiconductor layer 13p and the crystal substrate 11 and between the n-type semiconductor layer 13n and the crystal substrate 11, the intrinsic semiconductor layer 12 is interposed as an intermediate layer serving as passivation.

Each thickness of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n is not particularly limited, but may be 2 nm or more and 20 nm or less. This is because when the thickness is 2 nm or more, the effect as a passivation layer is enhanced, and when the thickness is 20 nm or less, deterioration of conversion characteristics caused by high resistance can be suppressed.

The p-type semiconductor layer 13p and the n-type semiconductor layer 13n are arranged on the back side of the crystal substrate 11 so that the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are electrically separated through the intrinsic semiconductor layer 12. be. The width of the conductive semiconductor layer 13 may be 50 μm or more and 3000 μm or less, or may be 80 μm or more and 500 μm or less. Unless otherwise specified, the widths of the semiconductor layers 12 and 13 and the widths of the electrode layers 17 and 18 are the lengths of part of each patterned layer. It means the length in the direction perpendicular to the extension direction.

When photoexcitons (carriers) generated in the crystal substrate 11 are taken out through the conductive semiconductor layer 13, holes have a larger effective mass than electrons. Therefore, from the viewpoint of reducing transport loss, the width of p-type semiconductor layer 13p may be narrower than that of n-type semiconductor layer 13n. For example, the width of the p-type semiconductor layer 13p may be 0.5 to 0.9 times the width of the n-type semiconductor layer 13n, or 0.6 to 0.8 times the width of the n-type semiconductor layer 13n. good too.

The p-type semiconductor layer 13p is a silicon layer to which a p-type dopant (such as boron) is added, and may be formed of amorphous silicon from the viewpoint of suppressing impurity diffusion or suppressing series resistance. On the other hand, the n-type semiconductor layer 13n is a silicon layer to which an n-type dopant (such as phosphorus) is added, and may be formed of an amorphous silicon layer like the p-type semiconductor layer 13p.

Silicon-containing gas such as monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ), or a mixed gas of silicon-based gas and hydrogen (H ₂ ) may be used as the material gas for the conductive semiconductor layer 13 . As the dopant gas, diborane (B ₂ H ₆ ) or the like is used for forming the p-type semiconductor layer 13p, and phosphine (PH ₃ ) or the like is used for forming the n-type semiconductor layer. Further, since the amount of impurities such as boron (B) or phosphorus (P) to be added may be very small, a mixed gas obtained by diluting a dopant gas with a raw material gas may be used.

Further, in order to adjust the energy gap of the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, a different kind of gas such as methane (CH ₄ ), carbon dioxide (CO ₂ ), ammonia (NH ₃ ) or monogermane (GeH ₄ ) is used. p-type semiconductor layer 13p or n-type semiconductor layer 13n may be alloyed by adding a gas containing the element

The low-reflection layer 14 is a layer that suppresses reflection of light received by the solar cell 10 . The material of the low-reflection layer 14 is not particularly limited as long as _it is a light-transmitting material that transmits _light . Titanium ( _TiOx ) can be mentioned. As a method for forming the low-reflection layer 14, for example, a resin material in which nanoparticles of an oxide such as zinc oxide or titanium oxide are dispersed may be applied.

Electrode layer 15 is formed to cover p-type semiconductor layer 13p or n-type semiconductor layer 13n, respectively, and is electrically connected to each conductive semiconductor layer 13 . Thereby, the electrode layer 15 functions as a transport layer that guides carriers generated in the p-type semiconductor layer 13p or the n-type semiconductor layer 13n. The electrode layers 15p and 15n corresponding to the semiconductor layers 13p and 13n are arranged apart from each other, thereby preventing a short circuit between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n.

In addition, from the viewpoint of electrical connection with each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, or from the viewpoint of suppressing the diffusion of atoms into both the metal semiconductor layers 13p and 13n, which are electrode materials, the transparent An electrode layer 15 made of a conductive oxide may be provided between the metal electrode layer and the p-type semiconductor layer 13p and between the metal electrode layer and the n-type semiconductor layer 13n.

In this embodiment, the electrode layer 15 made of a transparent conductive oxide is referred to as a transparent electrode layer 17 and the metal electrode layer 15 is referred to as a metal electrode layer 18 . Further, as shown in the plan view of the back main surface 11SB of the crystal substrate 11 shown in FIG. 2, in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n each having a comb-teeth shape, an electrode layer is formed on the back of the comb. are called busbar portions, and the electrode layers formed on the comb tooth portions are sometimes called finger portions.

_{The material} of the transparent electrode layer 17 is not particularly limited. SnO _x ), tungsten oxide (WO _x ), molybdenum oxide (MoO _x ), or the like is added in an amount of 1% by weight or more and 10% by weight or less.

The thickness of the transparent electrode layer 17 may be 20 nm or more and 200 nm or less. Methods for forming a transparent electrode layer suitable for this thickness include, for example, a physical vapor deposition (PVD) method such as a sputtering method, or a metal organic layer using a reaction between an organometallic compound and oxygen or water. Chemical vapor deposition method (MOCVD:Metal-Organic Chemical Vapor Deposition) method etc. are mentioned.

Although the material of the metal electrode layer 18 is not particularly limited, examples thereof include silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), and the like.

The thickness of the metal electrode layer 18 may be 1 μm or more and 80 μm or less. A method of forming the metal electrode layer 18 suitable for this thickness includes a printing method in which a material paste is printed by inkjet printing or screen printing, or a plating method. However, the method is not limited to this, and vapor deposition or sputtering may be employed when a vacuum process is employed.

Moreover, the width of the comb tooth portions in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n may be approximately the same as the width of the metal electrode layer 18 formed on the comb tooth portions. However, the width of the metal electrode layer 18 may be narrower than the width of the comb tooth portion. Moreover, the width of the metal electrode layer 18 may be wider than the width of the comb tooth portion as long as the structure prevents leakage between the metal electrode layers 18 .

In this embodiment, the intrinsic semiconductor layer 12, the conductive semiconductor layer 13, the low-reflection layer 14, and the electrode layer 15 are laminated on the back side main surface 11SB of the crystal substrate 11, and passivation and conduction of each joint surface are performed. A predetermined annealing treatment is performed for the purpose of suppressing generation of defect levels in the semiconductor layer 13 and its interface and crystallizing the transparent conductive oxide in the transparent electrode layer 17 .

An annealing treatment according to the present embodiment includes, for example, an annealing treatment in which the crystal substrate 11 having the above layers formed thereon is placed in an oven heated to 150° C. or higher and 200° C. or lower. In this case, the atmosphere in the oven may be the air, and if hydrogen or nitrogen is used, more effective annealing can be performed. Further, this annealing treatment may be an RTA (Rapid Thermal Annealing) treatment in which the crystal substrate 11 on which each layer is formed is irradiated with infrared rays from an infrared heater.

[Method for manufacturing solar cell]
A method for manufacturing the solar cell 10 according to this embodiment will be described below with reference to FIGS. 3 to 9. FIG.

First, as shown in FIG. 3, the crystal substrate 11 having the texture structure TX on each of the front main surface 11SU and the back main surface 11SB is prepared.

Next, as shown in FIG. 4, on the front main surface 11SU of the crystal substrate 11, for example, an intrinsic semiconductor layer 12U is formed. Subsequently, the low reflection layer 14 is formed on the formed intrinsic semiconductor layer 12U. Silicon nitride (SiN _x ) or silicon oxide (SiO _x ) having a suitable light absorption coefficient and refractive index is used for the low-reflection layer 14 from the viewpoint of light confinement.

Next, as shown in FIG. 5, on the back main surface 11SB of the crystal substrate 11, an intrinsic semiconductor layer 12p is formed using i-type amorphous silicon, for example. Subsequently, a p-type semiconductor layer 13p is formed on the formed intrinsic semiconductor layer 12p. As a result, p-type semiconductor layer 13p is formed on back side main surface 11SB, which is one main surface of crystal substrate 11 . As described above, in the present embodiment, the step of forming the p-type semiconductor layer (first semiconductor layer) 13p is performed on one side of the crystal substrate (semiconductor substrate) 11 before forming the p-type semiconductor layer 13p. A step of forming an intrinsic semiconductor layer (first intrinsic semiconductor layer) 12p on the main surface (back side main surface) 11S is included.

After that, a lift-off layer LF is formed on the formed p-type semiconductor layer 13p. Specifically, a lift-off layer LF containing silicon oxide (SiOX) as a main component is formed on the p-type semiconductor layer 13p.

Next, as shown in FIG. 6, on the back main surface 11SB of the crystal substrate 11, the lift-off layer LF and the p-type semiconductor layer 13p are patterned. As a result, the p-type semiconductor layer 13p is selectively removed to produce a non-formation area NA where the p-type semiconductor layer 13p is not formed. On the other hand, at least the lift-off layer LF and the p-type semiconductor layer 13p remain in the region of the back main surface 11SB of the crystal substrate 11 that has not been etched.

Such a patterning step can be realized by photolithography, for example, by forming a resist film (not shown) having a predetermined pattern on the lift-off layer LF and etching the region masked by the formed resist film. . As shown in FIG. 6, by patterning each of the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p and the lift-off layer LF, a non-formation region NA, that is, the back side, is formed in a partial region of the back side main surface 11SB of the crystal substrate 11. As shown in FIG. An exposed area of the main surface 11SB is produced. Details of the non-formation area NA will be described later.

As the etching solution used in the process shown in FIG. 6, for example, a mixed solution of hydrofluoric acid and an oxidizing solution (for example, hydrofluoric acid), or a solution obtained by dissolving ozone in hydrofluoric acid (hereinafter referred to as ozone/hydrofluoric acid liquid). The etching solution in this case corresponds to the second etching solution. Hydrogen fluoride is an etchant that contributes to the etching of the lift-off layer LF. Note that the patterning here is not limited to wet etching using an etching solution. The patterning may be, for example, dry etching or pattern printing using an etching paste or the like.

Next, as shown in FIG. 7, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed on the back main surface 11SB of the crystal substrate 11 including the lift-off layer LF, the p-type semiconductor layer 13p and the intrinsic semiconductor layer 12p. Form sequentially. As described above, in the present embodiment, the step of forming the n-type semiconductor layer (second semiconductor layer) 13n includes the step of forming the lift-off layer of the crystal substrate (semiconductor substrate) 11 before forming the n-type semiconductor layer 13n. A step of forming an intrinsic semiconductor layer (second intrinsic semiconductor layer) 12n on one main surface (back side main surface) 11S including the LF and the p-type semiconductor layer is included. As a result, the laminated film of the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n is formed on the non-formation region NA, the surface and side surfaces (end surfaces) of the lift-off layer LF, the lift-off layer LF, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer. It is formed so as to cover the side surfaces (end surfaces) of the layer 12p.

Next, as shown in FIG. 8, an etching solution is used to remove the laminated lift-off layer LF, thereby removing the n-type semiconductor layer 13n and the intrinsic semiconductor layer 12n covering the lift-off layer LF from the crystal substrate 11. Hydrofluoric acid, for example, is used as an etching solution used for this patterning.

In the process shown in FIG. 8, the lift-off layer LF is removed so that the p-type semiconductor layer 13p is partially covered with the lift-off layer LF. That is, as shown in FIG. 10, part of the lift-off layer LF remains on the p-type semiconductor layer 13, and part of the surface of the p-type semiconductor layer 13p opposite to the crystal substrate 11 is the remaining lift-off layer. The lift-off layer LF is removed so that it is covered by the layer LF.

Next, as shown in FIG. 9, separation grooves are formed on the back main surface 11SB of the crystal substrate 11, that is, on each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by sputtering using a mask, for example. A transparent electrode layer 17 (17p, 17n) is formed so as to produce 25 . The transparent electrode layers 17 (17p, 17n) may be formed in the following manner instead of the sputtering method. For example, a transparent conductive oxide film is formed on the entire back surface 11SB without using a mask, and then a transparent conductive film is formed on the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by photolithography. It may be formed by performing etching to leave a protective oxide film. Leakage is less likely to occur by forming separation groove 25 that separates and insulates p-type semiconductor layer 13p and n-type semiconductor layer 13n from each other.

After that, a linear metal electrode layer 18 (18p, 18n) is formed on the transparent electrode layer 17 using, for example, a mesh screen (not shown) having openings.

Through the steps described above, the back contact solar cell 10 is formed.

(Summary and effect)
The following can be said from the manufacturing method of the solar cell 10 mentioned above.

First, in the process shown in FIG. 8, when the lift-off layer LF is removed with an etchant, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n deposited on the lift-off layer LF are simultaneously removed from the crystal substrate 11. (So-called lift-off). This process does not require the resist coating process and the development process used in the photolithography method, as compared with the case of using the photolithography method, for example, in the process shown in FIG. Therefore, the n-type semiconductor layer 13n is easily patterned.

Further, since a part of the p-type semiconductor layer 13p is covered with the lift-off layer LF, the adhesion of the transparent electrode layer 17 in the region of the p-type semiconductor layer 13p is improved. That is, if a portion of the lift-off layer LF (hereinafter referred to as the covering portion 19) remains as a residue on the p-type semiconductor layer 13p, the surface area of the p-type semiconductor layer 13p is expanded by the amount of the covering portion 19. , the contact area of the transparent electrode layer 17 is increased. Further, for example, when the transparent electrode layer 17 is composed of tin oxide-indium oxide (ITO), since silicon oxide has higher adhesion to ITO than silicon, the covering portion 19 containing silicon oxide as a main component If there is, the transparent electrode layer 17 becomes difficult to peel off from the p-type semiconductor layer 13p. As a result, the adhesion of the transparent electrode layer 17 in the region of the p-type semiconductor layer 13p is improved.

On the other hand, if the covering portion 19 is too large, the contact area between the transparent electrode layer 17 and the p-type semiconductor layer 13p decreases, so the series resistance between the transparent electrode layer 17 and the p-type semiconductor layer 13p increases, The IV characteristics of the solar cell 10 may deteriorate. Therefore, when the area of the portion of the p-type semiconductor layer 13p covered with the covering portion 19 is S1, and the area of the entire surface of the p-type semiconductor layer 13p opposite to the crystal substrate 11 is S2, the following formula:
(Coverage (%)) = 100 x S1/S2
is preferably 0.2% or more and 16% or less. If the coverage is 0.2% or more and 16% or less, the contact area between the transparent electrode layer 17 and the p-type semiconductor layer 13p can be preferably ensured while improving the adhesion of the transparent electrode layer 17 .

Even if the coverage is 0.2% or more and 16% or less, if there is a locally large covering portion 19, excitons in the p-type semiconductor layer 13p (in the case of a p-type semiconductor, positive Due to the relationship between the effective mass of the hole) and the free path, there is a possibility that the excitons cannot be appropriately recovered from the p-type semiconductor layer 13p. Therefore, it is preferable that the maximum length of the covering portion 19 is 2.0 μm or less when viewed from the back mold main surface SB11 side in the perpendicular direction of the crystal substrate 11 . This makes it possible to appropriately collect excitons from the p-type semiconductor layer 13p while improving the adhesiveness of the transparent electrode layer 17 .

The coverage can be adjusted, for example, by devising the step of depositing the lift-off layer LF on the p-type semiconductor layer 13p. Specifically, as shown in FIG. 12, when the lift-off layer LF is deposited on the p-type semiconductor layer 13p, particles (here, silicon particles or silicon oxide particles) composed of elements constituting the lift-off layer LF are deposited. hereinafter referred to as crystal grains 20). In general, the lift-off layer LF is amorphous so as to facilitate etching during lift-off. Because the crystal grains 20 have a lower etching rate than amorphous due to the effect of density, etc., even if the amorphous portion of the lift-off layer LF is dissolved, the crystal grains 20 remain on the p-type semiconductor layer 13p without being dissolved. can be done. Therefore, the coverage can be adjusted by adjusting the amount of crystal grains to be mixed.

Further, when the lift-off layer LF is mainly composed of silicon oxide as in the present embodiment, the coverage can be adjusted by adjusting the refractive index of the lift-off layer LF. That is, the refractive index is proportional to the density, and the higher the refractive index, the higher the density. As the density increases, the etching rate decreases, so the covered portion 19 is likely to occur. Therefore, the coverage can be increased by increasing the refractive index of the lift-off layer LF. From the viewpoint of making the coverage ratio 0.2% or more and 16% or less, the refractive index preferably has a value of 1.45 or more and 1.90 or less for light with a wavelength of 632 nm.

In addition, in the lift-off layer LF containing silicon oxide as a main component, adjustment of the refractive index becomes possible by adjusting the pressure in the film formation using the CVD method, for example. Specifically, by increasing the pressure, it becomes easier to obtain a dense structure, and it becomes easier to obtain a lift-off layer LF with a high refractive index.

The method of mixing crystal grains into the lift-off layer LF and the method of adjusting the refractive index of the lift-off layer LF may be used alone or both.

In both the method of mixing the crystal grains 20 into the lift-off layer LF and the method of adjusting the refractive index of the lift-off layer LF, the lift-off layer LF is preferably composed of a plurality of layers. For example, as shown in FIG. 12, the lift-off layer LF is divided into two layers: a first lift-off layer LF1 laminated on the p-type semiconductor layer 13p and a second lift-off layer LF2 laminated on the first lift-off layer LF1. In the case of a layer configuration, only the first lift-off layer LF1 of the two layers is mixed with crystal grains 20 or has a high refractive index. This makes it possible to adjust the coverage while minimizing the time required to remove the lift-off layer LF. In addition, when the lift-off layer LF is composed of a plurality of layers, the lift-off layer LF may be composed of three layers or more, but considering the manufacturing cost and productivity, it is preferably composed of two layers.

Whether the number of lift-off layers LF is singular or plural, the thickness of the lift-off layers LF as a whole is preferably 20 nm or more and 600 nm or less, and particularly preferably 50 nm or more and 450 nm or less. When there are a plurality of lift-off layers LF, the thickness of the layer closest to the p-type semiconductor layer 13p is preferably the thinnest within this range.

Further, the crystal substrate 11 has a texture structure TX, and each surface of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n formed on the back surface 11SB of the crystal substrate 11 has the texture structure TX. It is preferable that a texture structure (second texture structure) reflecting the is included.

When the conductive semiconductor layer 13 has the texture structure TX on the surface, the etching solution easily permeates into the semiconductor layer 13 due to the unevenness of the texture structure TX. Therefore, the conductive semiconductor layer 13 is easily removed, that is, easily patterned.

In the present embodiment, the texture structure TX (first texture structure) is provided on both main surfaces 11S of the crystal substrate 11, that is, the front main surface 11SU and the back main surface 11SB, but only one of the main surfaces may be set to That is, when the texture structure TX is provided on the front main surface 11SU, the effect of capturing and confining the received light is enhanced. On the other hand, when the texture structure TX is provided on the back main surface 11SB, the effect of taking in light is improved and the patterning of the conductive semiconductor layer 13 is facilitated. Therefore, the texture structure TX of the crystal substrate 11 may be provided on at least one main surface 11S. Further, in the present embodiment, the texture structures TX on both main surfaces 11S have the same pattern, but this is not restrictive. good too.

In addition, in the process shown in FIG. 6, the back main surface 11SB of the crystal substrate 11 is exposed in the non-formation region NA, but it is not limited to this. That is, the intrinsic semiconductor layer 12p may remain on the non-formation region NA of the back main surface 11SB. This means that the p-type semiconductor layer 13p is selectively removed, and the region where the p-type semiconductor layer 13p is removed should be the non-formation region NA.

In such a case, the step of forming the intrinsic semiconductor layer 12n before depositing the n-type semiconductor layer 13n on the remaining lift-off layer LF and non-formation region NA can be reduced.

Further, for example, when the lift-off layer LF is composed of two layers of the first lift-off layer LF1 and the second lift-off layer LF2, in the process shown in FIG. A liquid may be applied to the first lift-off layer LF1 through the formed openings to remove the layer to which the etching solution is applied. Furthermore, in the process shown in FIG. 6, the lift-off layer LF is removed as described above, the etching solution is applied to the p-type semiconductor layer 13p, and the p-type semiconductor layer 13p to which the etching solution is attached is removed. good too. Note that the formation of the opening includes, for example, the generation of cracks.

Thus, by forming an opening in the second lift-off layer LF2 and passing the etching solution through the opening, the etching solution reliably adheres to the second lift-off layer LF2 and further to the first lift-off layer LF1. Therefore, the entire lift-off layer LF is efficiently removed. In addition, removing the lift-off layer LF ensures that the etching solution adheres to the p-type semiconductor layer 13p covered with the lift-off layer LF, thereby removing the p-type semiconductor layer 13p. As a result, undissolved portions of the lift-off layer LF and the p-type semiconductor layer 13p are suppressed.

The technology disclosed herein is not limited to the above-described embodiments, and substitutions are possible without departing from the scope of the claims.

For example, in the above embodiment, the semiconductor layer used in the process shown in FIG. 5 was the p-type semiconductor layer 13p, but it is not limited to this and may be the n-type semiconductor layer 13n. Also, the conductivity type of the crystal substrate 11 is not particularly limited, and may be either p-type or n-type.

The above-described embodiments are merely examples, and the technical scope of the present disclosure should not be construed to be limited. The technical scope of the present disclosure is defined by the claims, and all modifications and changes within the equivalent range of the claims are within the technical scope of the present disclosure.

Hereinafter, the technology according to the present disclosure will be specifically described with reference to examples. However, the technology according to the present disclosure is not limited to these examples. Examples and comparative examples were produced as follows (see [Table 1]). In the following description, Examples 1 to 3 and Comparative Examples 1 to 3 under the same conditions are not particularly distinguished.

[Crystal substrate]
First, a single crystal silicon substrate having a thickness of 200 μm was adopted as a crystal substrate. Anisotropic etching was performed on both main surfaces of the single crystal silicon substrate. As a result, a pyramidal textured structure was formed on the crystal substrate.

[Intrinsic semiconductor layer]
A crystal substrate was introduced into a CVD apparatus, and an intrinsic semiconductor layer made of silicon (thickness: 8 nm) was formed on both main surfaces of the introduced crystal substrate. The deposition conditions were a substrate temperature of 150° C., a pressure of 120 Pa, a SiH ₄ /H ₂ flow ratio of 3/10, and a power density of 0.011 W/cm ² .

[p-type semiconductor layer (first conductivity type semiconductor layer)]
A crystalline substrate having intrinsic semiconductor layers formed on both main surfaces was introduced into a CVD apparatus, and a p-type hydrogenated amorphous silicon thin film (thickness: 10 nm) was formed on the intrinsic semiconductor layer on the back main surface. The deposition conditions were a substrate temperature of 150° C., a pressure of 60 Pa, a SiH ₄ /B ₂ H ₆ flow ratio of 1/3, and a power density of 0.01 W/cm ² . Also, the flow rate of B ₂ H ₆ gas is the flow rate of diluent gas obtained by diluting B ₂ H ₆ with H ₂ to 5000 ppm.

[Lift-off layer]
Using a plasma CVD apparatus, a lift-off layer containing silicon oxide (SiO _x ) as a main component was formed on the p-type hydrogenated amorphous silicon thin film so as to have a thickness of 200 nm.

In Example 1, the deposition conditions for the lift-off layer were a substrate temperature of 150° C., a pressure of 50 Pa, a SiH ₄ /CO ₂ /H ₂ flow ratio of 1/10/750, and a power density of 0.15 W/ ^cm2 . In Example 2, the value of the SiH ₄ /CO ₂ /H ₂ flow rate ratio was set to 1/10/650, and other conditions were the same film forming conditions as in Example 1. In Example 3, the value of the SiH ₄ /CO ₂ /H ₂ flow rate ratio was set to 1/10/550, and other conditions were the same film formation conditions as in Example 1.

In Comparative Example 1, the film forming conditions were the same as in Examples 1 to 3, except that the SiH ₄ /CO ₂ /H ₂ flow rate ratio was set to 1/4/750.

In Comparative Example 2, film formation conditions were the same as in Examples 1 to 3, except that the SiH ₄ /CO ₂ /H ₂ flow rate ratio was set to 1/30/1000.

In Comparative Example 3, the film forming conditions were the same as in Examples 1 to 3, except that the SiH ₄ /CO ₂ /H ₂ flow rate ratio was set to 1/10/350.

[Patterning of lift-off layer and first conductivity type semiconductor layer]
First, a photosensitive resist film was formed on the back main surface of the crystal substrate on which the lift-off layer was formed. This was exposed and developed by photolithography to expose regions where the lift-off layer, p-type semiconductor layer and intrinsic semiconductor layer were to be removed. The crystal substrate on which the multiple layers were formed was immersed in hydrofluoric nitric acid containing 1% by weight of hydrogen fluoride as an etchant to remove the lift-off layer. After rinsing with pure water, the p-type semiconductor layer exposed by removing the lift-off layer and the intrinsic semiconductor layer immediately below it were immersed in an ozone/hydrofluoric acid solution in which 5.5% by weight of hydrofluoric acid was mixed with 20 ppm of ozone. and were removed. This process is hereinafter referred to as a patterning process.

[n-type semiconductor layer (second conductivity type semiconductor layer)]
After the first semiconductor layer patterning step, the crystal substrate whose exposed backside main surface was washed with hydrofluoric acid having a concentration of 2% by weight was introduced into a CVD apparatus, and an intrinsic semiconductor layer (thickness: 8 nm) was formed on the backside main surface. It was formed under the same film formation conditions as the first intrinsic semiconductor layer. Subsequently, an n-type hydrogenated amorphous silicon thin film (thickness: 10 nm) was formed on the formed intrinsic semiconductor layer. The deposition conditions were a substrate temperature of 150° C., a pressure of 60 Pa, a SiH ₄ /PH ₃ /H ₂ flow rate ratio of 1/2, and a power density of 0.01 W/cm ² . Also, the flow rate of PH ₃ gas is the flow rate of diluent gas obtained by diluting PH ₃ with H ₂ to 5000 ppm.

[Removal of lift-off layer and second conductivity type semiconductor layer]
A crystal substrate having an n-type semiconductor layer formed thereon is immersed in 5% by weight hydrofluoric acid to form a lift-off layer, an n-type semiconductor layer covering the lift-off layer, and between the lift-off layer and the n-type semiconductor layer. One intrinsic semiconductor layer was removed en bloc. This process is hereinafter referred to as a lift-off process.

[Electrode layer, low reflection layer]
Using a magnetron sputtering apparatus, an oxide film (thickness: 100 nm) serving as the base of the transparent electrode layer was formed on the conductive semiconductor layer of the crystal substrate. A silicon nitride layer was formed on the light-receiving surface side of the crystal substrate as a low-reflection layer. As a transparent conductive oxide, indium oxide (ITO) containing tin oxide at a concentration of 10% by weight was used as a target. A mixed gas of argon and oxygen was introduced into the chamber of the apparatus, and the pressure inside the chamber was set to 0.6 Pa. The mixing ratio of argon and oxygen was set to the lowest resistivity (so-called bottom) condition. In addition, film formation was performed using a DC power supply at a power density of 0.4 W/cm ² .

Next, etching was performed by photolithography so as to leave only the transparent conductive oxide film on the conductive semiconductor layer (p-type semiconductor layer and n-type semiconductor layer) to form a transparent electrode layer. The transparent electrode layer formed by this etching prevented conduction between the transparent conductive oxide film on the p-type semiconductor layer and the transparent conductive oxide film on the n-type semiconductor layer.

Further, an undiluted silver paste (Dotite FA-333 manufactured by Fujikura Kasei Co., Ltd.) was screen-printed on the transparent electrode layer and heat-treated in an oven at a temperature of 150° C. for 60 minutes. Thus, a metal electrode layer was formed.

Next, an evaluation method for back-contact solar cells will be described. Refer to [Table 1], FIGS. 13 and 14 for the evaluation results.

[Evaluation of film thickness and etchability]
The film thickness or etching state of the lift-off layer was evaluated using SEM (Field Emission Scanning Electron Microscope S4800: manufactured by Hitachi High-Technologies Corporation). After the first semiconductor layer patterning step, if the etching is performed according to the designed patterning removal area, it is marked as “○”, and if the lift-off layer is excessively etched and the solar cell characteristics are adversely affected, it is marked as “×”. and

[Evaluation of refractive index]
The refractive index of the lift-off layer was measured by spectroscopic ellipsometry (trade name: M2000, J. · It was obtained by measuring with A Woollam Co.). From the fitting results, the refractive index for light with a wavelength of 632 nm was extracted.

[Evaluation of coverage]
Using a laser microscope (device name OPTELICS, manufactured by Lasertec), the surface of the first conductivity type semiconductor layer was observed at a magnification of 100 on the back surface of the crystal substrate after the lift-off process. By image processing, the covering portion and the first conductivity type semiconductor layer were classified by color, and the area of the portion covered with the covering portion in the first conductivity type semiconductor layer was calculated. Then, the area of the portion of the semiconductor layer of the first conductivity type covered with the covering portion is S1, and the area of the entire surface of the semiconductor layer of the first conductivity type opposite to the crystal substrate is S2.
(Coverage (%)) = 100 x S1/S2
The coverage was calculated by

[Evaluation of adhesion]
An adhesive tape specified in JIS Z1522 was attached to the solar cell with the electrodes formed thereon, and the adhesive tape was pulled vertically for evaluation. When the electrode layer was peeled off when pulled, it was rated as "X", and when the electrode layer was not peeled off, it was rated as "○".

[Evaluation of IV characteristics]
An IV curve was observed when the standard sunlight of AM (air mass) 1.5 was irradiated with a light amount of 100 mW/cm ² . When scanning at -1.0 V to +1.5 V and the IV curve is S-shaped (when there is an extreme point in the range of -1.0 V to +1.5 V), "× ”, and when no S-shaped change was observed in the IV curve, it was indicated as “◯”.

[Evaluation of conversion efficiency]
A solar simulator was used to irradiate standard sunlight of AM (air mass) 1.5 at a light amount of 100 mW/cm ² to measure the conversion efficiency (Eff (%)) of the solar cell. Taking the conversion efficiency (solar cell characteristics) of Example 1 as 1.00, the relative values are shown in [Table 1].

[Reliability evaluation]
A module in which a solar cell with electrodes formed thereon was laminated with glass and a back sheet was subjected to an environmental test at a temperature of 85° C. and a humidity of 85%, and the conversion efficiency (Eff (%)) after 3000 hours was measured. The conversion efficiency was measured by irradiating standard sunlight of AM (air mass) 1.5 with a light intensity of 100 mW/cm ² using a solar simulator. Taking the initial conversion efficiency as 1.00, the relative values are shown in [Table 1].

Examples 1 to 3 were good in all of electrode adhesion, IV characteristics, solar cell characteristics and reliability.

Looking at the results of Examples 1 to 3 and Comparative Examples 1 to 3, it was confirmed that the adhesiveness of the electrode layer was good for those in which the coating portion was formed (other than Comparative Example 2). . On the other hand, it has been found that if the coverage is too high, the IV characteristics deteriorate and the solar cell specificity deteriorates. This is probably because excitons cannot be extracted from the portion of the first conductivity type semiconductor layer covered with the covering portion. That is, it was confirmed that the coverage should be within an appropriate range in order to improve the adhesion of the electrode layer and suppress the deterioration of the solar cell characteristics. Referring to FIG. 13, when the solar cell characteristic of Example 1 is 1.00, in order to make the solar cell characteristic 0.80 or more, the coverage should be 0.2% or more and 16% or less. I know it's good. For this reason, in the technology of the present disclosure, the range of 0.2% or more and 16% or less is a preferable coverage range.

Moreover, the results of Examples 1 to 3 and Comparative Examples 1 to 3 confirmed that the higher the refractive index of the lift-off layer, the higher the coverage. It is considered that this is because the higher the refractive index, the higher the density and the more difficult it is to dissolve during etching. Furthermore, it has been found that if the refractive index is too low, the lift-off layer will be excessively etched in the patterning process. It is considered that this is because the density became low, the structure of the lift-off layer became sparse, and the dissolution rate during etching increased. Referring to FIG. 14, when the solar cell characteristics of Example 1 are 1.00, in order to make the solar cell characteristics 0.80 or more, the refractive index for light with a wavelength of 632 nm must be 1.45 or more. 0.90 or less. For this reason, in the technique of the present disclosure, the preferable refractive index range is 1.45 or more and 1.90 or less.

In summary, by covering a part of the first conductivity type semiconductor layer with the lift-off layer, good electrical contact (adhesion) between the first conductivity type semiconductor layer and the electrode layer was obtained. . In particular, in comparison with the comparative example, it was found that the solar cell characteristics were improved by adjusting the coverage to an appropriate range. This improves the adhesion between the first-conductivity-type semiconductor layer and the electrode layer by leaving an appropriate amount of the substance (here, silicon oxide) constituting the lift-off layer on the first-conductivity-type semiconductor layer. It is thought that not only this, but also an increase in series resistance is suppressed.

In addition, it was found that the coverage can be set within the appropriate range by setting the refractive index of the lift-off layer to an appropriate value. In particular, when the refractive index of the lift-off layer is too low, the lift-off layer is excessively removed in the patterning process, resulting in insufficient solar cell characteristics. It has been found that there is a problem especially in reliability when the adhesiveness is poor.

10 solar cell 11 crystal substrate (semiconductor substrate)
12 intrinsic semiconductor layer 13 conductivity type semiconductor layer 13p p-type semiconductor layer [first conductivity type first semiconductor layer/second conductivity type second semiconductor layer]
13n n-type semiconductor layer [second conductivity type second semiconductor layer/first conductivity type first semiconductor layer]
15 Electrode layer 17 Transparent electrode layer 18 Metal electrode layer 19 Coating part 20 Crystal grains (grains made of crystals of substances constituting the lift-off layer)
LF lift-off layer

Claims (7)

forming a first semiconductor layer of a first conductivity type on one main surface of two main surfaces facing each other in a semiconductor substrate;
stacking a lift-off layer on the first semiconductor layer;
selectively removing the first semiconductor layer and the lift-off layer;
forming a second semiconductor layer of a second conductivity type on the one main surface including the first semiconductor layer and the lift-off layer;
removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer;
forming a transparent electrode layer made of oxide on each of the first semiconductor layer and the second semiconductor layer;
In the step of removing the lift-off layer, the lift-off layer is removed such that part of the first semiconductor layer is covered with the lift-off layer in a state where the second semiconductor layer covering the lift-off layer is removed. A method for manufacturing a solar cell. In the method for manufacturing a solar cell according to claim 1,
The lift-off layer covering the first semiconductor layer is defined as a covering portion, the area of the portion of the first semiconductor layer covered by the covering portion is defined as S1, and the area of the first semiconductor layer opposite to the semiconductor substrate is defined as S1. When the surface area is S2, the following formula:
(Coverage (%)) = 100 x S1/S2
A method for producing a solar cell having a coverage of 0.2% or more and 16% or less. In the method for manufacturing a solar cell according to claim 2,
A method for manufacturing a solar cell, wherein the covering portion has a maximum length of 2.0 μm or less when viewed from the one main surface side in the direction perpendicular to the plane of the semiconductor substrate. In the method for manufacturing a solar cell according to any one of claims 1 to 3,
The method for manufacturing a solar cell, wherein the lift-off layer contains silicon oxide as a main component and has a refractive index of 1.45 or more and 1.90 or less for light with a wavelength of 632 nm. In the method for manufacturing a solar cell according to claim 4,
The lift-off layer is composed of a plurality of layers,
Among the plurality of layers constituting the lift-off layer, the layer closest to the first semiconductor layer contains silicon oxide as a main component and has a refractive index of 1.45 or more and 1.90 or less for light with a wavelength of 632 nm. A method for manufacturing a solar cell comprising: In the method for manufacturing a solar cell according to any one of claims 1 to 5,
In the step of stacking the lift-off layer on the first semiconductor layer, when stacking the lift-off layer when there is a single lift-off layer, when stacking the lift-off layer, when there are a plurality of lift-off layers, the first semiconductor layer is the most A method for manufacturing a solar cell in which particles of an element constituting the lift-off layer are mixed into the lift-off layer when stacking close layers. In the method for manufacturing a solar cell according to any one of claims 1 to 6,
The semiconductor substrate has a first texture structure on each of the two main surfaces,
The method of manufacturing a solar cell, wherein the first semiconductor layer and the second semiconductor layer formed on the one main surface of the semiconductor substrate include a second texture structure reflecting the first texture structure.

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