JP7221276B2 - SOLAR CELL MANUFACTURING METHOD AND SOLAR CELL - Google Patents

Description

The present invention relates to a method for manufacturing a back electrode type (back contact type) solar cell and a back electrode type solar cell.

As solar cells using semiconductor substrates, there are double-sided electrode solar cells in which electrodes are formed on both the light-receiving side and the back side, and back electrode-type solar cells in which electrodes are formed only on the back side. In a double-sided electrode type solar cell, since electrodes are formed on the light receiving surface side, the electrodes block sunlight. On the other hand, in the back electrode type solar cell, no electrode is formed on the light receiving surface side, so the solar cell has a higher light receiving rate than the double electrode type solar cell.

In a back electrode type solar cell, it is necessary to form a semiconductor layer pattern such as a p-type semiconductor layer and an n-type semiconductor layer on the back side with high precision in order to improve performance. A method using a photolithographic technique is generally known as a method for forming a semiconductor layer pattern with high precision.
Further, Patent Document 1 describes a method of forming a semiconductor layer pattern using a metal mask.

Japanese Patent Application Laid-Open No. 2009-200267

However, in the method of forming a semiconductor layer pattern using photolithography, it is necessary to perform coating, exposure, development, and the like in order to form a mask for patterning. Therefore, although this method can improve the performance of the solar cell, the production of the solar cell becomes complicated.
On the other hand, the method of forming a semiconductor layer pattern using a metal mask described in Patent Document 1 can simplify the manufacture of solar cells compared to the method of forming a semiconductor layer pattern using photolithography. However, with this method, it is difficult to align the metal mask with high precision, and it is presumed that the performance of the solar cell will deteriorate compared to the method of forming the semiconductor layer pattern using the photolithography technique.

An object of the present invention is to provide a method for manufacturing a solar cell that can simplify the manufacturing of the solar cell while suppressing deterioration in the performance of the solar cell, and to provide a solar cell.

A method for manufacturing a solar cell according to the present invention comprises: a semiconductor substrate having two main surfaces; an intrinsic semiconductor layer disposed on one of the main surfaces of the semiconductor substrate; and a first electrode layer corresponding to the first conductivity type semiconductor layer and a second electrode layer corresponding to the second conductivity type semiconductor layer. In a method for manufacturing an electrode type solar cell, after forming a first conductivity type semiconductor material film on an intrinsic semiconductor layer on one main surface side of a semiconductor substrate, a mask is used to correspond to openings of the mask. a first conductivity type semiconductor layer forming step of forming a first conductivity type semiconductor layer by removing part of the first conductivity type semiconductor material film and the intrinsic semiconductor layer in the film thickness direction by plasma etching; a second conductivity type semiconductor layer forming step of forming a second conductivity type semiconductor layer on the intrinsic semiconductor layer corresponding to the opening of the mask on one main surface side.

A solar cell according to the present invention comprises a semiconductor substrate having two main surfaces, an intrinsic semiconductor layer arranged on one main surface of the semiconductor substrate, and an intrinsic semiconductor layer arranged on one main surface of the semiconductor substrate with the intrinsic semiconductor layer interposed therebetween. a first conductivity type semiconductor layer and a second conductivity type semiconductor layer; and a first electrode layer corresponding to the first conductivity type semiconductor layer and a second electrode layer corresponding to the second conductivity type semiconductor layer. In the solar cell, the thickness T1 of the intrinsic semiconductor layer sandwiched between the semiconductor layer of the first conductivity type and the semiconductor substrate and the thickness T2 of the intrinsic semiconductor layer sandwiched between the semiconductor layer of the second conductivity type and the semiconductor substrate are T1 > satisfies the relationship of T2.

ADVANTAGE OF THE INVENTION According to this invention, a high-performance solar cell is manufactured simply.

It is a side view which shows an example of the solar cell module which concerns on this embodiment. It is the figure which looked at the solar cell which concerns on this embodiment from the back surface side. FIG. 3 is a cross-sectional view taken along line III-III in the solar cell of FIG. 2; FIG. 4 is a cross-sectional view of a solar cell according to a modification of the embodiment; FIG. 10 is a cross-sectional view of a solar cell according to another modification of the embodiment; It is a figure which shows a part of intrinsic semiconductor layer formation process and 1st conductivity type semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows another part of 1st conductivity type semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 2nd conductivity type semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the electrode layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 2nd conductivity type semiconductor layer formation process in the manufacturing method of the solar cell which concerns on the modification of this embodiment. It is a figure which shows the 2nd conductivity type semiconductor layer formation process in the manufacturing method of the solar cell based on the other modified example of this embodiment. It is a figure which shows a part of intrinsic semiconductor layer formation process and 1st conductivity type semiconductor layer formation process in the manufacturing method of the conventional solar cell (photolithographic technique). It is a figure which shows another part of intrinsic semiconductor layer formation process and 1st conductivity type semiconductor layer formation process in the manufacturing method of the conventional solar cell (photolithographic technique). It is a figure which shows a part of intrinsic semiconductor layer formation process and 2nd conductivity type semiconductor layer formation process in the manufacturing method of the conventional solar cell (photolithographic technique). It is a figure which shows another part of intrinsic semiconductor layer formation process and 2nd conductivity type semiconductor layer formation process in the manufacturing method of the conventional solar cell (photolithographic technique). It is a figure which shows the intrinsic|native semiconductor layer formation process and the 2nd conductivity type semiconductor layer formation process in the manufacturing method of the conventional solar cell (metal mask technique). It is a figure which shows the intrinsic|native semiconductor layer formation process and the 1st conductivity type semiconductor layer formation process in the manufacturing method of the conventional solar cell (metal mask technique). It is a figure which shows the intrinsic|native semiconductor layer formation process and the 1st conductivity type semiconductor layer formation process in the manufacturing method of the conventional solar cell (ion implantation technique). It is a figure which shows the 2nd conductivity type semiconductor layer formation process in the manufacturing method of the conventional solar cell (ion implantation technique). It is a figure which shows a part of intrinsic semiconductor layer formation process and 1st conductivity type semiconductor layer formation process in the manufacturing method of the solar cell which concerns on the modification of this embodiment. It is a figure which shows another part of 1st conductivity type semiconductor layer formation process in the manufacturing method of the solar cell which concerns on the modification of this embodiment. It is a figure which shows a part of 2nd conductivity type semiconductor layer formation process in the manufacturing method of the solar cell which concerns on the modification of this embodiment. It is a figure which shows another part of 2nd conductivity type semiconductor layer formation process in the manufacturing method of the solar cell which concerns on the modification of this embodiment. It is a figure which shows a part of intrinsic semiconductor layer formation process and 1st conductivity type semiconductor layer formation process in the manufacturing method of the conventional solar cell (lift-off technique). It is a figure which shows another part of intrinsic semiconductor layer formation process and 1st conductivity type semiconductor layer formation process in the manufacturing method of the conventional solar cell (lift-off technique). It is a figure which shows a part of intrinsic semiconductor layer formation process and 2nd conductivity type semiconductor layer formation process in the manufacturing method of the conventional solar cell (lift-off technique). It is a figure which shows another part of intrinsic semiconductor layer formation process and 2nd conductivity type semiconductor layer formation process in the manufacturing method of the conventional solar cell (lift-off technique). 1 is a cross-sectional view of a conventional solar cell; FIG.

An example of an embodiment of the present invention will be described below with reference to the accompanying drawings. In each drawing, the same reference numerals are given to the same or corresponding parts. For the sake of convenience, hatching, member numbers, etc. may be omitted, but in such cases, other drawings shall be referred to.

(solar cell module)
FIG. 1 is a side view showing an example of a solar cell module according to this embodiment. As shown in FIG. 1, the solar cell module 100 includes a plurality of solar cells 1 arranged two-dimensionally.

Solar cells 1 are connected in series and/or in parallel by wiring members 2 . Specifically, the wiring member 2 is connected to a busbar portion (described later) in the electrode of the solar cell 1 . The wiring member 2 is, for example, a known interconnector such as a tab.

Solar cell 1 and wiring member 2 are sandwiched between light-receiving surface protective member 3 and back surface protective member 4 . A liquid or solid sealing material 5 is filled between the light-receiving surface protection member 3 and the back surface protection member 4 , thereby sealing the solar cells 1 and the wiring member 2 . The light-receiving surface protection member 3 is, for example, a glass substrate, and the back surface protection member 4 is, for example, a glass substrate, a metal plate, or a composite sheet formed by multilayering a metal layer and a resin layer. The sealing material 5 is, for example, transparent resin.
The solar cell (hereinafter referred to as solar cell) 1 will be described in detail below.

(solar cell)
FIG. 2 is a view of the solar cell according to this embodiment viewed from the back side. The solar cell 1 shown in FIG. 2 is a back electrode type solar cell. Solar cell 1 includes semiconductor substrate 11 having two main surfaces, and has first conductivity type region 7 and second conductivity type region 8 on the main surface of semiconductor substrate 11 .

The first conductivity type region 7 has a so-called comb shape, and includes a plurality of finger portions 7f corresponding to comb teeth and bus bar portions 7b corresponding to support portions of the comb teeth. The busbar portion 7b extends in the X direction (second direction) along one side of the semiconductor substrate 11, and the finger portions 7f extend from the busbar portion 7b in the Y direction (first direction) intersecting the X direction. extend to
Similarly, the second conductivity type region 8 has a so-called comb shape, and has a plurality of finger portions 8f corresponding to comb teeth and bus bar portions 8b corresponding to support portions of the comb teeth. The busbar portion 8b extends in the X direction (second direction) along one side portion of the semiconductor substrate 11 opposite to the other side portion, and the finger portions 8f extend from the busbar portion 8b in the Y direction (first direction). direction).
The finger portions 7f and the finger portions 8f are band-shaped extending in the Y direction (first direction) and are alternately arranged in the X direction (second direction).
The first conductivity type region 7 and the second conductivity type region 8 may be formed in stripes.

3A is a cross-sectional view taken along line III-III in the solar cell of FIG. 2. FIG. As shown in FIG. 3A, the solar cell 1 includes an intrinsic semiconductor layer 13 and an antireflection layer 15 laminated in order on the light-receiving surface side, which is one of the principal surfaces of the semiconductor substrate 11 on the light-receiving side. Prepare. In addition, the solar cell 1 is an intrinsic solar cell sequentially laminated on a part (mainly, the first conductivity type region 7) of the back surface side, which is the other main surface of the semiconductor substrate 11 opposite to the light receiving surface. It includes a semiconductor layer 23 , a first conductivity type semiconductor layer 25 , and a first electrode layer 27 . In addition, the solar cell 1 includes an intrinsic semiconductor layer 23, a second conductivity type semiconductor layer 35, and a second conductivity type semiconductor layer 35, which are laminated in order on another part (mainly, the second conductivity type region 8) of the back surface side of the semiconductor substrate 11. and a two-electrode layer 37 .

<Semiconductor substrate>
As the semiconductor substrate 11, a conductivity type single crystal silicon substrate such as an n-type single crystal silicon substrate or a p-type single crystal silicon substrate is used. This realizes high photoelectric conversion efficiency.
Semiconductor substrate 11 is preferably an n-type single crystal silicon substrate. This prolongs the lifetime of carriers in the crystalline silicon substrate. This is because, in a p-type single crystal silicon substrate, LID (Light Induced Degradation), which is a recombination center, may occur due to the influence of B (boron), which is a p-type dopant, due to light irradiation. This is to further suppress LID in the substrate.

The semiconductor substrate 11 may have a pyramid-shaped fine uneven structure called a texture structure on the back surface side. As a result, the efficiency of collecting the light that has passed through the semiconductor substrate 11 without being absorbed increases.
Further, the semiconductor substrate 11 may have a pyramid-shaped fine uneven structure called a texture structure on the light receiving surface side. As a result, the reflection of incident light on the light receiving surface is reduced, and the light confinement effect in the semiconductor substrate 11 is improved.

The thickness of the semiconductor substrate 11 is preferably 50 μm or more and 300 μm or less, more preferably 60 μm or more and 230 μm or less, and even more preferably 70 μm or more and 210 μm or less.
When the film thickness of the semiconductor substrate 11 is equal to or less than the above upper limit value, the amount of silicon used is reduced, so it becomes easier to secure the silicon substrate and the cost can be reduced. Furthermore, in the back contact structure in which the holes and electrons generated by photoexcitation in the silicon substrate are recovered only on the back surface side, the film thickness of the semiconductor substrate 11 is set to the above upper limit value also from the viewpoint of the free path of each exciton. It is preferable that it is below.
When the film thickness of the semiconductor substrate 11 is at least the above lower limit value, appropriate mechanical strength can be obtained, external light (sunlight) can be sufficiently absorbed, and an appropriate short-circuit current density can be obtained.
When a textured structure is formed on the main surface of the semiconductor substrate 11, the film thickness of the semiconductor substrate 11 is represented by the distance between straight lines connecting the apexes of the convexes in the concave-convex structures on the light-receiving surface side and the back surface side. .

As the semiconductor substrate 11, a conductive polycrystalline silicon substrate such as an n-type polycrystalline silicon substrate or a p-type polycrystalline silicon substrate may be used. In this case, solar cells are manufactured at a lower cost.

<Antireflection layer>
The antireflection layer 15 is formed on the light receiving surface side of the semiconductor substrate 11 with the intrinsic semiconductor layer 13 interposed therebetween. The antireflection layer 15 has a function of suppressing reflection of sunlight incident on the light receiving surface side of the semiconductor substrate 11 .
The material of the antireflection layer 15 is not particularly limited as long as it is a translucent material that allows sunlight to pass therethrough, and examples thereof include silicon oxide, silicon nitride, zinc oxide, and titanium oxide.
The intrinsic semiconductor layer 13 is formed of an intrinsic silicon-based layer. The intrinsic semiconductor layer 13 functions as a passivation layer and suppresses recombination of carriers in the semiconductor substrate 11 .

In this embodiment, since no electrode is formed on the light-receiving surface side (rear surface electrode type), the light receiving rate of sunlight is high, and the photoelectric conversion efficiency is improved.

<Intrinsic semiconductor layer>
The intrinsic semiconductor layer 23 is formed on the entire back surface side of the semiconductor substrate 11 . The intrinsic semiconductor layer 23 is mainly formed of an intrinsic silicon-based layer. The intrinsic semiconductor layer 23 functions as a passivation layer and suppresses recombination of carriers in the semiconductor substrate 11 . Further, the intrinsic semiconductor layer 23 suppresses diffusion of impurities from the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 to the semiconductor substrate 11 .
Note that the term “intrinsic (i-type)” is not limited to being completely intrinsic containing no conductivity type impurities, and includes a trace amount of n-type impurities or p-type impurities to the extent that the silicon-based layer can function as an intrinsic layer. Also included are "weak n-type" or "weak p-type" substantially intrinsic layers that contain impurities.

The intrinsic semiconductor layer 23 includes a first layer 23 a and a second layer 23 b that are laminated in order on the back surface side of the semiconductor substrate 11 . In other words, the second layer 23b is a part of the intrinsic semiconductor layer 23 near the interface with the first conductivity type semiconductor layer 25 in the film thickness direction (that is, a part of the intrinsic semiconductor layer 23 in the film thickness direction). and a portion of the surface of the intrinsic semiconductor layer 23 facing the first conductivity type semiconductor layer 25 ), and the first layer 23 a is the other portion of the intrinsic semiconductor layer 23 . Note that the first layer 23a and the second layer 23b may be integrated to such an extent that they cannot be visually recognized.
The first layer 23a of the intrinsic semiconductor layer 23 is not particularly limited, but is preferably an amorphous silicon-based thin film (amorphous silicon (a-Si)) in order to function as the passivation layer described above. A hydrogenated amorphous silicon thin film (a-Si:H thin film) containing
As the material for the second layer 23b of the intrinsic semiconductor layer 23, a material that is resistant to hydrogen plasma etching in the step of forming the first conductivity type semiconductor layer, which will be described later, is used. In other words, as the material of the second layer 23b, a material having a slower hydrogen plasma etching rate than those of the first layer 23a and the first conductivity type semiconductor layer 25 is used. Materials for such a second layer 23b include, for example, highly diluted silicon hydride, silicon oxide, silicon nitride, silicon carbide, or compounds thereof. Note that highly diluted hydrogenated silicon is formed by adding hydrogen to silane by 500 times or more at the time of film formation, and unlike amorphous silicon, it contains silicon with high crystallinity.

The thickness T2 of the portion of the intrinsic semiconductor layer 23 sandwiched between the second conductivity type semiconductor layer 35 and the semiconductor substrate 11 is the thickness of the portion of the intrinsic semiconductor layer 23 sandwiched between the first conductivity type semiconductor layer 25 and the semiconductor substrate 11. thinner than T1. That is, the thickness T1 of the intrinsic semiconductor layer 23 sandwiched between the semiconductor layer 25 of the first conductivity type and the semiconductor substrate 11 and the thickness T2 of the intrinsic semiconductor layer 23 sandwiched between the semiconductor layer 35 of the second conductivity type and the semiconductor substrate 11 satisfies the relationship of T1>T2 (details will be described later).
Although the thicknesses T1 and T2 of the intrinsic semiconductor layer 23 are not particularly limited, they are preferably 2 nm or more and 20 nm or less. When the thickness is 2 nm or more, the effect as a passivation layer is enhanced, and when the thickness is 20 nm or less, deterioration of conversion characteristics caused by high resistance is suppressed.

<First conductivity type semiconductor layer and second conductivity type semiconductor layer>
The first-conductivity-type semiconductor layer 25 is formed on a part (mainly, the first-conductivity-type region 7) of the back surface of the semiconductor substrate 11 with the intrinsic semiconductor layer 23 interposed therebetween, and the second-conductivity-type semiconductor layer 35 is , is formed on another portion (mainly, the second conductivity type region 8) of the back surface side of the semiconductor substrate 11 with an intrinsic semiconductor layer 23 interposed therebetween. More specifically, the first-conductivity-type semiconductor layers 25 and the second-conductivity-type semiconductor layers 35 are band-shaped extending in the Y direction (first direction), and are alternately arranged in the X direction (second direction). there is
In the solar cell 1, at least part of the boundary between the first-conductivity-type semiconductor layer 25 and the second-conductivity-type semiconductor layer 35, the first-conductivity-type semiconductor layer 25 and the second-conductivity-type semiconductor layer 35 Adjacent and non-overlapping. In other words, at these boundaries, there is substantially no region where the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 overlap, and the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 25 do not overlap. Part or all of the semiconductor layer 35 is in contact.

The first-conductivity-type semiconductor layer 25 is formed of a first-conductivity-type silicon-based layer, for example, a p-type silicon-based layer. The second conductivity type semiconductor layer 35 is formed of a silicon-based layer of a second conductivity type different from the first conductivity type, such as an n-type silicon-based layer. The first conductivity type semiconductor layer 25 may be an n-type silicon-based layer, and the second conductivity type semiconductor layer 35 may be a p-type silicon-based layer.
The p-type silicon-based layer and the n-type silicon-based layer are formed of an amorphous silicon layer or a microcrystalline silicon layer containing amorphous silicon and crystalline silicon. From the viewpoint of suppressing impurity diffusion or suppressing series resistance, the p-type silicon-based layer and the n-type silicon-based layer are preferably made of amorphous silicon. B (boron) is preferably used as the dopant impurity for the p-type silicon-based layer, and P (phosphorus) is preferably used as the dopant impurity for the n-type silicon-based layer.

Note that, as shown in FIGS. 3B and 3C, the thickness T4 of the side portion of the second conductivity type semiconductor layer 35 in the width direction is greater than the thickness T3 of the vicinity of the center of the second conductivity type semiconductor layer 35 in the width direction. It may be thin. That is, the thickness T3 of the second-conductivity-type semiconductor layer 35 near the center in the width direction may be thicker than the thickness T4 of the second-conductivity-type semiconductor layer 35 other than near the center in the width direction (details will be described later).
The film thickness of the first conductivity type semiconductor layer 25 and the film thicknesses T3 and T4 of the second conductivity type semiconductor layer 35 are not particularly limited, but are preferably 2 nm or more and 20 nm or less. If the thickness is less than the lower limit, the effect of the electric field will be insufficient, and if the thickness is greater than the upper limit, conversion characteristics will deteriorate due to increased resistance. It is preferable that the film thickness of the first conductivity type semiconductor layer 25 is as thin as possible within the above range (details will be described later).

The width of the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 is preferably 50 μm or more and 3000 μm or less, more preferably 80 μm or more and 500 μm or less. The gap between the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 is preferably 3000 μm or less, more preferably 1000 μm or less.
By the way, when the photoexcitons generated in the semiconductor substrate 11 are taken out through the first-conductivity-type semiconductor layer 25 or the second-conductivity-type semiconductor layer 35, the effective mass of holes is larger than the effective mass of electrons. Therefore, from the viewpoint of reducing transport loss, it is preferable that the width of the p-type semiconductor layer is narrower than the width of the n-type semiconductor layer. For example, the width of the p-type semiconductor layer is preferably 0.5 to 0.9 times the width of the n-type semiconductor layer, and is preferably 0.6 to 0.8 times the width of the n-type semiconductor layer. It is more preferable to have
Unless otherwise specified, the width of the semiconductor layer and the width of the electrode layer, which will be described later, are the length of a portion of each patterned layer, and are perpendicular to the extending direction of, for example, a belt-like portion of the patterned layer. is the length in the direction

<First electrode layer and second electrode layer>
The first electrode layer 27 is formed on the semiconductor layer 25 of the first conductivity type, and the second electrode layer 37 is formed on the semiconductor layer 35 of the second conductivity type. As a result, the first electrode layers 27 and the second electrode layers 37 form strips extending in the Y direction (first direction) and are alternately arranged in the X direction (second direction).
The first electrode layer 27 functions as a transport layer that guides carriers recovered by the semiconductor layer 25 of the first conductivity type, and the second electrode layer 37 is a transport layer that guides carriers recovered by the semiconductor layer 35 of the second conductivity type. function as

The first electrode layer 27 has a transparent electrode layer 28 and a metal electrode layer 29 that are sequentially laminated on the first conductivity type semiconductor layer 25 . The second electrode layer 37 has a transparent electrode layer 38 and a metal electrode layer 39 that are sequentially laminated on the second conductivity type semiconductor layer 35 .
By providing the transparent electrode layers 28 and 38 between the metal electrode layers 29 and 39 and the semiconductor layers 25 and 35 of the first conductivity type and the semiconductor layers 35 of the second conductivity type, the metal electrode layers 29 and 39 and the second conductivity type semiconductor layer 35 are provided. The electrical connection between the 1-conductivity-type semiconductor layer 25 and the 2nd-conductivity-type semiconductor layer 35 is improved, and the atomic diffusion from the metal electrode layers 29 and 39 to the 1st-conductivity-type semiconductor layer 25 and the 2nd-conductivity-type semiconductor layer 35 is improved. Suppressed.
Note that the first electrode layer 27 may be formed of only one of the transparent electrode layer 28 and the metal electrode layer 29 . Similarly, the second electrode layer 37 may be formed of only one of the transparent electrode layer 38 and the metal electrode layer 39 .

The width of the first electrode layer 27 (that is, the width of the transparent electrode layer 28 and the width of the metal electrode layer 29 ) is preferably substantially the same as the width of the first conductivity type semiconductor layer 25 . The width of the first electrode layer 27 may be narrower than the width of the first conductivity type semiconductor layer 25 . Further, the width of the first electrode layer 27 may be wider than the width of the first conductivity type semiconductor layer 25 as long as leakage between the first electrode layer 27 and the second electrode layer 37 is prevented.
Similarly, the width of the second electrode layer 37 (that is, the width of the transparent electrode layer 38 and the width of the metal electrode layer 39 ) is preferably substantially the same as the width of the semiconductor layer 35 of the second conductivity type. The width of the second electrode layer 37 may be narrower than the width of the second conductivity type semiconductor layer 35 . Further, the width of the second electrode layer 37 may be wider than the width of the second conductivity type semiconductor layer 35 as long as leakage between the first electrode layer 27 and the second electrode layer 37 is prevented.

<<Transparent electrode layer>>
The transparent electrode layers 28 and 38 are formed of transparent conductive layers made of a transparent conductive material. As the transparent conductive material, transparent conductive metal oxides such as indium oxide, tin oxide, zinc oxide, titanium oxide, tungsten oxide and composite oxides thereof are used. Among these, an indium-based composite oxide containing indium oxide as a main component is preferable. Indium oxide is particularly preferred from the viewpoint of high electrical conductivity and transparency. Additionally, dopants are preferably added to the indium oxide to ensure reliability or higher conductivity. Dopants include Sn, W, Zn, Ti, Ce, Zr, Mo, Al, Ga, Ge, As, Si, or S, for example.
The thickness of the transparent electrode layer is preferably 50 nm or more and 200 nm or less.

<<Metal electrode layer>>
The metal electrode layers 29 and 39 are made of metal material. Examples of metal materials include silver, copper, aluminum, nickel, and alloys thereof.
Moreover, the film thickness of the metal electrode layer is preferably 20 μm or more and 80 μm or less.

(Method for manufacturing solar cell)
Next, a method for manufacturing a solar cell according to this embodiment will be described with reference to FIGS. 4A to 4D. 4A and 4B are diagrams showing the intrinsic semiconductor layer forming step and the first conductivity type semiconductor layer forming step in the solar cell manufacturing method according to the present embodiment, and FIG. 4C shows the solar cell according to the present embodiment. FIG. 4D is a diagram showing a second conductivity type semiconductor layer forming step in the manufacturing method, and FIG. 4D is a diagram showing an electrode forming step in the solar cell manufacturing method according to the present embodiment.

<Intrinsic semiconductor layer forming step>
First, as shown in FIG. 4A, an intrinsic semiconductor layer (eg, intrinsic silicon-based layer) 23 is laminated on the entire back surface side of a semiconductor substrate (eg, n-type single crystal silicon substrate) 11 having an uneven structure on at least the back surface side. do. Specifically, for example, amorphous silicon (a-Si) is laminated as the first layer 23a on the entire back surface side of the semiconductor substrate 11 . After that, a material having higher resistance to hydrogen plasma etching than the first layer 23a and the first conductivity type semiconductor layer 25, in other words, a material having a lower hydrogen plasma etching rate, is formed on the first layer 23a as the second layer 23b. (eg, highly diluted silicon hydride or silicon oxide).
In this embodiment, at this time, an intrinsic semiconductor layer (for example, an intrinsic silicon-based layer) 13 is laminated on the entire light receiving surface side of the semiconductor substrate 11 .

Although the method for forming the intrinsic semiconductor layers 23 and 13 is not particularly limited, it is preferable to use a plasma CVD (Chemical Vapor Deposition) method. By using the plasma CVD method, the diffusion of impurities into the semiconductor substrate 11 is suppressed, and the passivation effect of the surface of the semiconductor substrate 11 can be effectively obtained. Further, according to the plasma CVD method, by changing the hydrogen concentration in the film of the intrinsic semiconductor layers 23 and 13 in the film thickness direction, an effective energy gap profile for carrier recovery can be formed.

Film formation conditions by the plasma CVD method include, for example, a substrate temperature of 100° C. to 300° C., a pressure of 20 Pa to 2600 Pa, and a high frequency power density of 0.003 W/cm ² to 0.5 W/cm ² . Silicon-containing gases such as SiH ₄ and Si ₂ H ₆ , or mixed gases of these silicon-based gases and H ₂ are preferably used as material gases.
Incidentally, by adding a gas containing different elements such as CH ₄ , NH ₃ , and GeH ₄ to the above material gases to form silicon carbide, silicon nitride, or silicon alloys such as silicon germanium, , may change the energy gap of the thin film.
Further, when an oxide, nitride, or carbide is produced as the second layer 23b, gases such as CO ₂ , NH ₃ , and CH ₄ may be added to the above material gases.

<First conductivity type semiconductor layer forming step>
Next, as shown in FIG. 4A, a first conductivity type semiconductor material film (for example, a p-type silicon-based layer) 25Z is laminated on the intrinsic semiconductor layer 23, that is, on the entire back surface side of the semiconductor substrate 11. Next, as shown in FIG.
Although the method for forming the first conductivity type semiconductor material film 25Z is not particularly limited, it is preferable to use the plasma CVD method as in the case of the intrinsic semiconductor layer 23 described above.
As the dopant additive gas for the first conductivity type semiconductor material film 25Z, for example, B ₂ H ₆ is suitably used. Note that a mixed gas obtained by diluting a dopant gas with a raw material gas may be used because the amount of impurities such as B (boron) to be added may be very small. The amount to be added should be as small as possible so as not to degrade the cell performance. Since the etching rate of the first conductivity type semiconductor, which is added in a small amount, is high, the difference in etching rate from the intrinsic semiconductor can be increased. Alternatively, the amount of addition may be large only on the outermost surface and the amount of addition near the interface with the intrinsic semiconductor may be small. Furthermore, the thinner the film thickness, the better. The thin film can reduce residue after etching. This is the same when P (phosphorus) or the like is used as a dopant.

Next, as shown in FIG. 4B, a mask 90 is placed on the first conductivity type semiconductor material film 25Z on the back side of the semiconductor substrate 11. Next, as shown in FIG. The outline of the mask 90 is larger than the outline of the semiconductor substrate 11 . In other words, the area of the region defined by the outline of mask 90 is larger than the area of semiconductor substrate 11 . As a result, the edge of the semiconductor substrate 11 is covered with the mask 90 in the step of forming the semiconductor layer of the first conductivity type and the step of forming the semiconductor layer of the second conductivity type which will be described later.
The mask 90 is, for example, a metal mask made of metal.

Next, the first conductivity type semiconductor material film 25Z corresponding to the opening of the mask 90, that is, the first conductivity type semiconductor material film 25Z exposed from the opening of the mask 90 is removed by hydrogen plasma etching, and the first conductivity type semiconductor material film 25Z is removed. A mold semiconductor layer 25 is formed.
In the hydrogen plasma etching, plasma discharge is performed while a gas containing hydrogen as a main component is introduced into the CVD chamber, and the first conductivity type semiconductor material film 25Z corresponding to the opening of the mask 90 is subjected to hydrogen plasma etching. Here, "main component" means that the content of hydrogen is 90% by volume or more (preferably 95% by volume or more) with respect to the total amount of gas introduced into the vacuum chamber. SiH ₄ or CH ₄ can be cited as types of introduced gas other than hydrogen.

At this time, the hydrogen plasma etching is controlled so as to remove a part (upper layer) in the film thickness direction of the second layer 23 b of the intrinsic semiconductor layer 23 corresponding to the opening of the mask 90 . As a result, the first conductivity type semiconductor material film 25Z does not remain in the openings of the mask 90, and deterioration of the performance of the solar cell 1 can be suppressed. Moreover, the first conductivity type semiconductor material film 25Z can be removed without impairing the passivation property of the intrinsic semiconductor layer 23 by hydrogen plasma etching. Rather, it is possible to improve the passivation property of the intrinsic semiconductor layer 23 by introducing hydrogen.
Since the rate of hydrogen plasma etching of the second layer 23b of the intrinsic semiconductor layer 23 is slow, a portion of the second layer 23b near the interface with the first conductivity type semiconductor material film 25Z side is removed, but the second layer 23b is removed. The rest of layer 23b and first layer 23a remain.
Therefore, as described above (FIGS. 3A to 3C), the thickness T2 of the portion of the intrinsic semiconductor layer 23 sandwiched between the semiconductor layer 35 of the second conductivity type and the semiconductor substrate 11 is equal to the thickness T2 of the intrinsic semiconductor layer 23 of the first conductivity type. It is thinner than the thickness T1 of the portion sandwiched between the semiconductor layer 25 and the semiconductor substrate 11 . That is, the thickness T1 of the intrinsic semiconductor layer 23 sandwiched between the semiconductor layer 25 of the first conductivity type and the semiconductor substrate 11 and the thickness T2 of the intrinsic semiconductor layer 23 sandwiched between the semiconductor layer 35 of the second conductivity type and the semiconductor substrate 11 satisfies the relationship of T1>T2. Note that the intrinsic semiconductor layer 23 may have portions with high plasma resistance and portions with weak plasma resistance in the film, and is not necessarily etched uniformly. All you have to do is

As described above, when the intrinsic semiconductor layer (amorphous silicon) 23 formed by the plasma CVD method is etched by hydrogen plasma etching, deterioration in performance of the intrinsic semiconductor layer 23 is suppressed. Also, the addition of silane in the hydrogen plasma etch enhances the etching uniformity.

<Second conductivity type semiconductor layer forming step>
Next, as shown in FIG. 4C , using the mask 90 as it is, the intrinsic semiconductor layer 23 exposed from the openings of the mask 90 is exposed on the second layer 23 b of the intrinsic semiconductor layer 23 corresponding to the openings of the mask 90 . A second conductivity type semiconductor layer (for example, an n-type silicon-based layer) 35 is stacked on the second layer 23b.
Although the method of forming the second conductivity type semiconductor layer 35 is not particularly limited, it is preferable to use the plasma CVD method as in the intrinsic semiconductor layer 23 and the first conductivity type semiconductor material film 25Z described above.
As the dopant addition gas for the second conductivity type semiconductor layer 35, for example, _PH3 is preferably used. A mixed gas obtained by diluting a dopant gas with a raw material gas may be used because the amount of impurities such as P (phosphorus) added may be very small.
After forming the second conductivity type semiconductor layer 35, the mask 90 is removed.

As shown in FIG. 4E , it may be difficult for gas to enter the vicinity of the opening of the mask 90 compared to the vicinity of the center of the opening of the mask 90 . Therefore, as shown in FIG. 4E and as described above (FIG. 3B), the thickness T4 of the side portion of the second conductivity type semiconductor layer 35 in the width direction is the width of the second conductivity type semiconductor layer 35 at the center of the width direction. It may be thinner than the nearby thickness T3. That is, the thickness T3 of the second conductivity type semiconductor layer 35 near the center in the width direction may be thicker than the thickness T4 of the second conductivity type semiconductor layer 35 other than near the center in the width direction.
Moreover, as shown in FIG. 4F, when the intrinsic semiconductor layer 23 is etched by plasma etching, not only the opening of the mask 90 but also part of the region immediately below the mask 90 may be etched. Therefore, as shown in FIG. 4F and as described above (FIG. 3C), the thickness T4 of the side portion in the width direction of the second conductivity type semiconductor layer 35 is the width of the center of the second conductivity type semiconductor layer 35 in the width direction. It may be thinner than the nearby thickness T3. That is, the thickness T3 of the second conductivity type semiconductor layer 35 near the center in the width direction may be thicker than the thickness T4 of the second conductivity type semiconductor layer 35 other than near the center in the width direction.
Note that by using this step, the mask can be used repeatedly when manufacturing a plurality of solar cells. In general, when film formation is repeated on a mask, stress is applied to the mask, making it difficult to form a film under desired conditions. On the other hand, by using this step, the mask 90 with the second conductivity type semiconductor layer formed thereon can be removed by plasma etching in the subsequent fabrication of the solar cell. Therefore, less film is deposited on the mask, stress can be relaxed, and the life of the mask can be extended.

<Electrode layer forming step>
Next, as shown in FIG. 4D , a first electrode layer 27 is formed on the first conductivity type semiconductor layer 25 and a second electrode layer 37 is formed on the second conductivity type semiconductor layer 35 .
First, the transparent electrode layer 28 is formed on the semiconductor layer 25 of the first conductivity type, and the transparent electrode layer 38 is formed on the semiconductor layer 35 of the second conductivity type. Methods for forming the transparent electrode layers 28 and 38 include, for example, physical vapor deposition (PVD) such as sputtering, or chemical vapor deposition (MOCVD) utilizing a reaction between an organometallic compound and oxygen or water. Law etc. are used.
Next, a metal electrode layer 29 is formed on the transparent electrode layer 28 and a metal electrode layer 39 is formed on the transparent electrode layer 38 . As a method for forming the metal electrode layers 29 and 39, for example, a screen printing method, a plating method, a wire bonding method, an inkjet method, a spray method, a vacuum deposition method, a sputtering method, or the like is used. In particular, a screen printing method using Ag paste and a plating method using copper plating are preferable.

At this time, an antireflection layer 15 may be formed on the intrinsic semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11 (not shown). A method for forming the antireflection layer 15 is not particularly limited, but a coating method is preferably used. For example, the antireflection layer 15 is formed by coating the intrinsic semiconductor layer 13 with a resin material in which nanoparticles of an oxide such as zinc oxide or titanium oxide are dispersed.

In addition, the intrinsic semiconductor layers 23 and 13, the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35, the first electrode layer 27 and the second electrode layer 37, and the antireflection layer 15 are laminated on the semiconductor substrate 11. At this stage, annealing is performed for the purpose of passivating each bonding interface, suppressing the generation of defect levels in the semiconductor layer and its interface, and crystallization of the transparent conductive oxide in the transparent electrode layer.
As the annealing treatment, for example, there is a heat treatment in which the semiconductor substrate 11 with the layers arranged is placed in an oven heated to 150° C. or more and 200° C. or less and heated. In this case, the atmosphere in the oven may be air, but if hydrogen or nitrogen is used, more effective annealing can be performed. Further, the annealing treatment may be RTA (Rapid Thermal Annealing) treatment in which the semiconductor substrate 11 on which each layer is arranged is irradiated with infrared rays using an infrared heater.
Through the above steps, the back electrode type solar cell 1 of the present embodiment is completed.

Conventionally, a method using a photolithographic technique is generally known as a method of forming an intrinsic semiconductor layer, a first conductivity type semiconductor layer and a second conductivity type semiconductor layer in a solar cell.
5A to 5D are diagrams showing steps of forming an intrinsic semiconductor layer, a first conductivity type semiconductor layer and a second conductivity type semiconductor layer using a conventional photolithographic technique.
For example, as shown in FIG. 5A, an intrinsic semiconductor material film 123Z and a first conductivity type semiconductor material film 125Z are formed on the entire back surface of the semiconductor substrate 111, and a mask 190 is formed using photolithography. Next, the intrinsic semiconductor material film 123Z and the first conductivity type semiconductor material film 125Z corresponding to the openings of the mask 190 are etched to form the intrinsic semiconductor layer 123 and the first conductivity type semiconductor layer 125 as shown in FIG. 5B. At the same time, the semiconductor substrate 111 corresponding to the opening of the mask 190 is exposed. After removing the mask 190, as shown in FIG. 5C, an intrinsic semiconductor material film 133Z and a second conductivity type semiconductor material film 135Z are formed on the entire back surface of the semiconductor substrate 111, and a mask is similarly formed using photolithography. Form 193. Next, the intrinsic semiconductor material film 133Z and the second conductivity type semiconductor material film 135Z corresponding to the openings of the mask 193 are etched to form the intrinsic semiconductor layer 133 and the second conductivity type semiconductor layer 135 as shown in FIG. 5D. At the same time, the first conductivity type semiconductor layer 125 is exposed. After that, the mask 193 is removed.

In such a method of forming a semiconductor layer pattern using a conventional photolithographic technique, the semiconductor patterns, particularly the intervals between the semiconductor patterns, can be formed with high accuracy, and the performance of the solar cell can be improved.
However, this method requires processes such as resist coating, exposure, development, and resist stripping in order to form the masks 190 and 193 for patterning the semiconductor pattern. Furthermore, these processes are required twice, that is, the step of forming the semiconductor layer of the first conductivity type and the step of forming the semiconductor layer of the second conductivity type. Become. Therefore, this method complicates the production of solar cells.
Further, in this method, after removing the intrinsic semiconductor material film 123Z and the first conductivity type semiconductor material film 125Z and before forming the intrinsic semiconductor material film 133Z and the second conductivity type semiconductor material film 135Z, the solar cell In order to improve the performance of the solar cell, it is necessary to clean the exposed surface of the semiconductor substrate 111, which complicates the manufacture of the solar cell.

Conventionally, as a method of forming an intrinsic semiconductor layer, a first conductivity type semiconductor layer and a second conductivity type semiconductor layer in a solar cell, there is a method using a metal mask (see, for example, Patent Document 1).
6A and 6B are diagrams showing steps of forming an intrinsic semiconductor layer, a first conductivity type semiconductor layer and a second conductivity type semiconductor layer using a conventional metal mask.
For example, as shown in FIG. 6A, a metal mask 290 is arranged on the back side of the semiconductor substrate 211, and the intrinsic semiconductor layer 233 and the second conductivity type semiconductor layer are formed on the back surface of the semiconductor substrate 211 corresponding to the openings of the metal mask 290. 235 is formed. After removing the mask 290, as shown in FIG. 5B, a metal mask 293 is placed on the back surface side of the semiconductor substrate 11, and the intrinsic semiconductor layer 223 and the second layer are formed on the back surface of the semiconductor substrate 211 corresponding to the openings of the metal mask 293. As shown in FIG. A one conductivity type semiconductor layer 225 is formed. After that, the metal mask 293 is removed.

Such a conventional method for forming a semiconductor layer pattern using a metal mask enables simplification of the manufacturing of solar cells compared to the method for forming a semiconductor layer pattern using the above-described conventional photolithography technique.
However, even in this method, the process of arranging and removing the metal mask is required twice in the step of forming the semiconductor layer of the second conductivity type and the step of forming the semiconductor layer of the first conductivity type. must be taken out multiple times. Therefore, this method does not sufficiently simplify the production of solar cells.
Furthermore, in this method, it is necessary to dispose metal masks individually in each of the second conductivity type semiconductor layer forming step and the first conductivity type semiconductor layer forming step. It is difficult to do Therefore, it is presumed that this method lowers the performance of the solar cell compared to the semiconductor layer pattern forming method using the photolithographic technique.

Conventionally, as a method of forming an intrinsic semiconductor layer, a first conductivity type semiconductor layer and a second conductivity type semiconductor layer in a solar cell, there is a method using an ion implantation technique.
7A and 7B are diagrams illustrating the formation process of an intrinsic semiconductor layer, a first conductivity type semiconductor layer and a second conductivity type semiconductor layer using conventional ion implantation techniques.
For example, as shown in FIG. 7A, the intrinsic semiconductor layer 323 and the first conductivity type semiconductor material film 325Z are formed on the entire back surface of the semiconductor substrate 311, and as shown in FIG. 7B, the metal mask 390 is arranged. Next, by implanting ions of the second conductivity type into the first conductivity type semiconductor material film 325Z corresponding to the openings of the metal mask 390, the first conductivity type semiconductor layer 325 and the second conductivity type semiconductor layer 335 are formed. do. After that, the metal mask 390 is removed.

In the method of forming a semiconductor layer pattern using such a conventional ion implantation technique, only one process of arranging and removing the metal mask is required in forming the second conductivity type semiconductor layer and the first conductivity type semiconductor layer. Therefore, in this method, the manufacturing of the solar cell can be simplified as compared with the above-described conventional method of forming a semiconductor layer pattern using a metal mask.
Furthermore, the semiconductor patterns, particularly the intervals between the semiconductor patterns, can be formed with high precision. Therefore, it is presumed that this method can improve the performance of the solar cell as compared with the above-described conventional method of forming a semiconductor layer pattern using a metal mask.
However, in this method, since ions are implanted only into the second conductivity type semiconductor layer 335, it is difficult to control the ion implantation depth of the semiconductor layer of about several nanometers. In comparison, it is speculated that the performance of the solar cell is degraded.

To solve these conventional problems, according to the solar cell manufacturing method of the present embodiment, a metal mask is used as the mask 90 for patterning the semiconductor layer pattern. , development, resist stripping, etc. are not required, and the manufacturing of the solar cell 1 can be simplified.
Further, according to the solar cell manufacturing method of the present embodiment, since the same mask 90 is used for the patterning of the first conductivity type semiconductor layer 25 and the patterning of the second conductivity type semiconductor layer 35, the arrangement and removal of the mask 90 are process is required only once, thereby requiring only one extraction to atmosphere during the plasma CVD process, when the mask 90 is placed. Therefore, manufacturing of the solar cell 1 can be simplified.
Furthermore, by using the same mask 90 for the patterning of the first conductivity type semiconductor layer 25 and the patterning of the second conductivity type semiconductor layer 35, the semiconductor pattern of the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 can be changed. can be formed with high precision, especially the spacing of the semiconductor patterns. As a result, it is possible to improve the performance of the solar cell 1 .

Further, according to the method of manufacturing the solar cell of the present embodiment, in the plasma etching of the first conductivity type semiconductor layer 25, the second layer 23b of the intrinsic semiconductor layer 23 is etched only partially in the film thickness direction. Substrate 11 is not exposed. Therefore, it is not necessary to wash the semiconductor substrate 11, and the manufacturing of the solar cell 1 can be simplified.
In addition, since the plasma etching rate of the second layer 23b of the intrinsic semiconductor layer 23 is slow, it is easy to control the etching up to a part of the second layer 23b of the intrinsic semiconductor layer 23 in the film thickness direction. Thereby, manufacturing of the solar cell 1 can be simplified.
Furthermore, by etching the second layer 23b of the intrinsic semiconductor layer 23 to a part in the film thickness direction, the first conductivity type semiconductor material film 25Z does not remain. As a result, it is possible to improve the performance of the solar cell 1 .

In addition, according to the solar cell manufacturing method of the present embodiment, the second layer 23b of the intrinsic semiconductor layer 23 functions as a stop layer for hydrogen plasma etching, so that the etching depth can be easily controlled. As a result, it is possible to improve the performance of the solar cell 1 .
In the case of mass production processes, the use of dry process removal for multiple substrates at the same time may result in poor performance of the solar cell due to the film thickness distribution of the semiconductor layers.
Regarding this point, according to the method for manufacturing a solar cell of the present embodiment, even when a plurality of substrates having different film thicknesses of the semiconductor layers are processed simultaneously, or the film thickness of the semiconductor layer in one substrate is reduced. Even if there is a thickness difference, the second layer 23b of the intrinsic semiconductor layer 23 functions as a stop layer for hydrogen plasma etching.

Moreover, according to the method for manufacturing a solar cell of this embodiment, the mask 90 can be used repeatedly. For example, even if the second-conductivity-type semiconductor material adheres to the mask 90 in the process of forming the second-conductivity-type semiconductor layer 35, the hydrogen plasma etching in the next process of forming the first-conductivity-type semiconductor layer 25 will cause the mask 90 to adhere to the second-conductivity-type semiconductor material. Since the adhered second conductivity type semiconductor material can be removed, warping of the mask 90 can be alleviated, and the mask 90 can be used repeatedly.

As described above, according to the solar cell manufacturing method of the present embodiment, it is possible to simplify the manufacturing of the solar cell while suppressing deterioration in the performance of the solar cell. As a result, manufacturing costs can be reduced.
Further, in the solar cell 1 manufactured by the solar cell manufacturing method of the present embodiment, the thickness T1 of the intrinsic semiconductor layer 23 sandwiched between the first conductivity type semiconductor layer 25 and the semiconductor substrate 11 and the thickness T1 of the second conductivity type semiconductor layer The thickness T2 of the intrinsic semiconductor layer 23 sandwiched between 35 and the semiconductor substrate 11 satisfies the relationship of T1>T2 (eg, see FIGS. 3A to 3C). In addition, in this solar cell 1, the thickness T3 of the second conductivity type semiconductor layer 35 near the center in the width direction of the second conductivity type semiconductor layer 35 is equal to the thickness T3 of the second conductivity type semiconductor layer 35 other than near the center in the width direction. (see, eg, FIGS. 3B and 3C, FIGS. 4E and 4F).

By the way, in the conventional solar cell described above, for example, as shown in FIG. 3, it was necessary to form a semiconductor layer pattern so that the first conductivity type semiconductor layer 125 (and the intrinsic semiconductor layer 123) and the second conductivity type semiconductor layer 135 (and the intrinsic semiconductor layer 133) overlap. Alternatively, as shown in FIG. 10, the first conductivity type semiconductor layer 125 and the second conductivity type semiconductor layer 135 overlap each other at the boundary between the first conductivity type semiconductor layer 125 and the second conductivity type semiconductor layer 135. It was necessary to form a semiconductor layer pattern. This is because there is no region where the semiconductor layer is not formed even if manufacturing errors are taken into consideration, and the carrier collection efficiency is improved, that is, the performance of the solar cell is improved.

On the other hand, in the solar cell 1 manufactured by the solar cell manufacturing method of the present embodiment, at least part of the boundary between the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 has There is substantially no overlapping region between the semiconductor layer 25 of the conductive type and the semiconductor layer 35 of the second conductive type, and part or all of the semiconductor layer 25 of the first conductive type and the semiconductor layer 35 of the second conductive type are in contact with each other.

(Modification)
In this embodiment, a metal mask is used to etch the first conductivity type semiconductor material film and form the second conductivity type semiconductor material film.
In the modified example of this embodiment, a lift-off layer (also referred to as a mask layer or a sacrificial layer) is used as a mask to etch the first conductivity type semiconductor material film and form the second conductivity type semiconductor material film.

8A to 8D are diagrams showing a method for manufacturing a solar cell according to a modification of this embodiment.
<Intrinsic Semiconductor Layer Forming Step and First Conductivity Type Semiconductor Layer Forming Step>
First, as shown in FIG. 8A, the intrinsic semiconductor layer 23 is stacked over the entire back surface side of the semiconductor substrate 11 in the same manner as described above. Specifically, for example, amorphous silicon (a-Si) is laminated as the first layer 23a on the entire back surface side of the semiconductor substrate 11 . After that, a material having stronger resistance to hydrogen plasma etching than the first layer 23a and the first conductivity type semiconductor layer 25 is laminated as the second layer 23b on the first layer 23a. In other words, a material with a slow hydrogen plasma etching rate (eg, highly diluted silicon hydride or silicon oxide) is deposited as the second layer 23b.
In addition, an intrinsic semiconductor layer 13 is laminated on the entire surface of the semiconductor substrate 11 on the light receiving surface side.
Next, in the same manner as described above, a first conductivity type semiconductor material film 25Z is laminated on the intrinsic semiconductor layer 23, that is, on the entire back surface side of the semiconductor substrate 11 (first step).

Next, a lift-off layer 95Z is formed on the first conductivity type semiconductor material film 25Z. The material of the lift-off layer 95Z may be an inorganic material such as metal, or an organic material such as dry film. The material of the lift-off layer 95Z preferably contains a silicon-based thin film material.
Next, a lift-off layer 95 having an opening is formed by removing a part of the lift-off layer 95Z on a part of the back surface side of the semiconductor substrate 11, as shown in FIG. 8B. The method for forming the lift-off layer 95 is not particularly limited, but may be wet etching using a resist film and an etching solution, dry etching, or pattern printing using an etching paste or the like. (second step).

Next, the first conductivity type semiconductor material film 25Z corresponding to the opening of the lift-off layer 95, that is, the first conductivity type semiconductor material film 25Z exposed from the opening of the lift-off layer 95 is removed by hydrogen plasma etching. A one conductivity type semiconductor layer 25 is formed. (Third step).
At this time, the hydrogen plasma etching is controlled so as to remove a part (upper layer) in the thickness direction of the second layer 23 b of the intrinsic semiconductor layer 23 corresponding to the opening of the lift-off layer 95 .
Since the rate of hydrogen plasma etching of the second layer 23b of the intrinsic semiconductor layer 23 is slow, a portion of the second layer 23b near the interface with the first conductivity type semiconductor material film 25Z side is removed, but the intrinsic semiconductor layer 23b is partially removed. The other part of the second layer 23b of the layer 23 and the first layer 23a remain.
Therefore, as described above (FIGS. 3A to 3C), the thickness T2 of the portion of the intrinsic semiconductor layer 23 sandwiched between the semiconductor layer 35 of the second conductivity type and the semiconductor substrate 11 is equal to the thickness T2 of the intrinsic semiconductor layer 23 of the first conductivity type. It is thinner than the thickness T1 of the portion sandwiched between the semiconductor layer 25 and the semiconductor substrate 11 . That is, the thickness T1 of the intrinsic semiconductor layer 23 sandwiched between the semiconductor layer 25 of the first conductivity type and the semiconductor substrate 11 and the thickness T2 of the intrinsic semiconductor layer 23 sandwiched between the semiconductor layer 35 of the second conductivity type and the semiconductor substrate 11 satisfies the relationship of T1>T2.

<Second conductivity type semiconductor layer forming step>
Next, as shown in FIG. 8C, the second layer of the intrinsic semiconductor layer 23 corresponding to the entire surface of the back surface of the semiconductor substrate 11, that is, the surface and side surfaces of the opening of the lift-off layer 95 and the opening of the lift-off layer 95 is formed. A second conductivity type semiconductor material film 35Z is laminated so as to cover 23b (fourth step).
In addition, in the vicinity of the lift-off layer 95 in the opening of the lift-off layer 95 and on the side of the opening of the lift-off layer 95, as in the case described above (FIG. 4E), it may be difficult for gas to enter compared to the vicinity of the center of the opening of the lift-off layer 95. . Therefore, as described above (FIG. 3B), the thickness T4 of the side portions in the width direction of the second conductivity type semiconductor layer 35 is thinner than the thickness T3 near the center of the second conductivity type semiconductor layer 35 in the width direction. can be. That is, the thickness T3 of the second conductivity type semiconductor layer 35 near the center in the width direction may be thicker than the thickness T4 of the second conductivity type semiconductor layer 35 other than near the center in the width direction.
Moreover, when the intrinsic semiconductor layer 23 is etched by plasma etching, not only the opening of the lift-off layer 95 but also part of the region immediately below the lift-off layer 95 may be etched. Therefore, as described above (FIG. 3C), the thickness T4 of the side portions in the width direction of the second conductivity type semiconductor layer 35 is thinner than the thickness T3 near the center of the second conductivity type semiconductor layer 35 in the width direction. can be. That is, the thickness T3 of the second conductivity type semiconductor layer 35 near the center in the width direction may be thicker than the thickness T4 of the second conductivity type semiconductor layer 35 other than near the center in the width direction.

Next, as shown in FIG. 8D, by removing the lift-off layer 95, the second-conductivity-type semiconductor material film 35Z stacked thereon is also removed to form the second-conductivity-type semiconductor layer 35 (fifth step). ). A method for removing the lift-off layer 95 is not particularly limited, but may be, for example, wet etching using a resist film and an etching solution, or dry etching.
After that, the surfaces of the semiconductor layer 25 of the first conductivity type and the semiconductor layer 35 of the second conductivity type are rinsed, and the electrode forming process described above is performed. is completed.

9A to 9D are diagrams showing the formation process of an intrinsic semiconductor layer, a first conductivity type semiconductor layer and a second conductivity type semiconductor layer using a conventional lift-off technique.
First, as shown in FIG. 9A, an intrinsic semiconductor material film (a-Si) 423Z and a first conductivity type semiconductor material film 425Z are formed on the back side of a semiconductor substrate 411. Then, as shown in FIG. Next, a lift-off layer 495Z is formed on the first conductivity type semiconductor material film 425Z.
Next, the lift-off layer 495Z, the first conductivity type semiconductor material film 425Z, and the intrinsic semiconductor material film 423Z are removed from part of the back surface of the semiconductor substrate 411, thereby forming the intrinsic semiconductor layer 423 and the intrinsic semiconductor material film 423Z as shown in FIG. 9B. A non-formation region of the first conductivity type semiconductor layer 425 is generated. As a result, the intrinsic semiconductor layer 423 and the first conductivity type semiconductor layer 425 are formed on the other portion of the semiconductor substrate 411 other than the portion on the back surface side. The lift-off layer 495 remains on the intrinsic semiconductor layer 423 and the first conductivity type semiconductor layer 425 .
Next, as shown in FIG. 9C, an intrinsic semiconductor material film (a-Si) 433Z and a second conductivity type semiconductor material film 435Z are formed on the lift-off layer 495 and the non-formation region.
Next, as shown in FIG. 9D, by removing the lift-off layer 495, the intrinsic semiconductor material film 433Z and the second conductivity type semiconductor material film 435Z stacked thereon are removed, and the intrinsic semiconductor layer 433 and the second conductivity type semiconductor material film 435Z are removed. A semiconductor layer 435 is formed.

In the method of forming a semiconductor layer pattern using such a conventional lift-off technique, at the boundary between the first conductivity type semiconductor layer 425 and the second conductivity type semiconductor layer 435, the first conductivity type semiconductor layer 425 and the second conductivity type semiconductor layer 425 are separated from each other. There is substantially no region of overlap with layer 435 .
However, in this method, the intrinsic semiconductor layer 433 remains between the first-conductivity-type semiconductor layer 425 and the second-conductivity-type semiconductor layer 435, and the carriers are collected by the first-conductivity-type semiconductor layer 425 and the second-conductivity-type semiconductor layer 435. Less efficient.

On the other hand, in the solar cell 1 manufactured by the solar cell manufacturing method of this modification, the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 do not substantially exist, and part or all of the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 are in contact with each other. This suppresses a decrease in carrier recovery efficiency due to the first conductivity type semiconductor layer and the second conductivity type semiconductor layer.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications are possible. For example, in the above-described embodiments, a heterojunction solar cell and a method for manufacturing the same were illustrated as shown in FIG. 3A. is applied not only to heterojunction solar cells but also to various solar cells such as homojunction solar cells and methods for manufacturing the same.

EXAMPLES The present invention will be specifically described below based on examples, but the present invention is not limited to the following examples.

(Example 1)
Solar cell 1 shown in FIGS. 2 and 3A was fabricated according to the steps shown in FIGS. 4A to 4D as follows.

<Semiconductor substrate>
First, a single crystal silicon substrate having a thickness of 200 μm was used as the semiconductor substrate 11 . By performing anisotropic etching on both surfaces of the single crystal silicon substrate, a semiconductor substrate 11 having a pyramid-shaped texture structure formed on both surfaces was obtained.

<Formation of intrinsic semiconductor layer>
A semiconductor substrate 11 was introduced into a CVD apparatus, and an amorphous silicon (a-Si) film was formed with a thickness of 8 nm as an intrinsic semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11 . Further, an amorphous silicon film is formed as the first layer 23a of the intrinsic semiconductor layer 23 on the back surface side of the semiconductor substrate 11, and then highly diluted hydrogen is deposited on the first layer 23a as the second layer 23b of the intrinsic semiconductor layer 23. A silicon oxide film was formed. The film thickness of the intrinsic semiconductor layer 23 was set to 8 nm.
The amorphous silicon film formation conditions were a substrate temperature of 150° C., a pressure of 120 Pa, a SiH ₄ /H ₂ flow ratio of 3/10, and a power density of 0.011 W/cm ² .
The film formation conditions for highly diluted hydrogenated silicon were a pressure of 100 Pa, a SiH ₄ /H ₂ flow ratio of 1/500, and a power density of 0.5 W/cm ² .

<Formation of first conductivity type semiconductor layer>
In a CVD apparatus, p-type hydrogenated amorphous silicon was deposited to a thickness of 10 nm as the first conductivity type semiconductor material film 25Z on the intrinsic semiconductor layer 23 on the back side of the semiconductor substrate 11 . The deposition conditions for p-type hydrogenated amorphous silicon were a substrate temperature of 150° C., a pressure of 60 Pa, a SiH ₄ /B ₂ H ₆ flow ratio of 1/3, and a power density of 0.01 W/cm ² . The B ₂ H ₆ gas flow rate is the flow rate of the diluent gas obtained by diluting B ₂ H ₆ with H ₂ to 5000 ppm.

Next, a mask 90 is arranged on the first conductivity type semiconductor material film 25Z on the back side of the semiconductor substrate 11 .
Next, the first conductivity type semiconductor material film 25Z corresponding to the opening of the mask 90 was removed by hydrogen plasma etching to form the first conductivity type semiconductor layer 25. Next, as shown in FIG. The hydrogen plasma etching conditions were a substrate temperature of 150° C., a pressure of 100 Pa, a SiH ₄ /H ₂ flow ratio of 1/1000, and a power density of 0.1 W/cm ² .

<Formation of second conductivity type semiconductor layer>
In a CVD apparatus, using the mask 90 as it is, 10 nm of n-type hydrogenated amorphous silicon is deposited as the second conductivity type semiconductor layer 35 on the second layer 23b of the intrinsic semiconductor layer 23 corresponding to the openings of the mask 90. A film was formed with a film thickness of The film forming conditions for the n-type hydrogenated amorphous silicon were a substrate temperature of 150° C. or 180° C., a pressure of 60 Pa, a SiH ₄ /PH ₃ flow ratio of 1/2, and a power density of 0.01 W/cm ² . The PH ₃ gas flow rate is the flow rate of the diluent gas obtained by diluting PH ₃ with H ₂ to 5000 ppm.

<Electrode layer formation>
Using a magnetron sputtering apparatus, a transparent conductive oxide film is formed with a thickness of 100 nm as a transparent electrode material film on the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35 on the back side of the semiconductor substrate 11. bottom. In the film formation of the transparent conductive oxide, indium oxide (ITO) containing 10% by weight of tin oxide is used as a target, and a mixed gas of argon and oxygen is introduced into the chamber of the apparatus, and the inside of the chamber is was set to 0.6 Pa. The mixing ratio of argon and oxygen was set to the condition that the resistivity was the lowest (so-called bottom condition). Further, in forming the film of the transparent conductive oxide, the film was formed using a DC power supply at a power density of 0.4 W/cm ² .
Next, etching was performed by photolithography so that only the transparent conductive material films on the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 remained, thereby forming a transparent electrode layer 28 and a transparent electrode layer 38. . Separating the transparent electrode layer 28 and the transparent electrode layer 38 in this manner prevents conduction between these transparent electrode layers.

Next, on the transparent electrode layer 28 and the transparent electrode layer 38, Ag paste (Dotite FA-333 manufactured by Fujikura Kasei Co., Ltd.) is applied by screen printing and heat-treated in an oven at 150° C. for 60 minutes to form a metal electrode layer. 29 and a metal electrode layer 39 were formed. The transparent electrode layer 28 and the metal electrode layer 29 constitute the first electrode layer 27 , and the transparent electrode layer 38 and the metal electrode layer 39 constitute the second electrode layer 37 .

(Example 2)
A solar cell 1 was fabricated in the same manner as in Example 1, except that hydrogenated silicon oxide was used as the material of the second layer 23b of the intrinsic semiconductor layer 23 instead of the highly diluted silicon hydride.

(Example 3)
A solar cell 1 was fabricated in the same manner as in Example 1, except that a single layer of amorphous silicon with a thickness of 8 nm was formed as the intrinsic semiconductor layer 23 .

The open-circuit voltage Voc, short-circuit current Isc, fill factor FF, and conversion efficiency Eff were simulated as the performance characteristics of the solar cells of Examples 1 to 3 fabricated as described above. In this simulation, a solar simulator was used, and AM (air mass) 1.5 standard sunlight was irradiated with a light amount of 100 mW/cm ² .
Table 1 shows the results. In Table 1, the results of Examples 2 and 3 are shown in relative proportions when the results of Voc, Isc, FF, and Eff of Example 1 are set to 1.00.
In addition, Table 2 shows the relative values of the etching rates of the respective thin films (with hydrogenated amorphous silicon, which is an intrinsic semiconductor, set to 1). A thin film was formed on a polished silicon substrate and obtained by measuring the film thickness, for example, by a spectroscopic ellipsometry method.

According to Table 2, amorphous silicon, highly diluted hydrogenated silicon, and hydrogenated silicon oxide, which are the materials of the intrinsic conductor layer, have slower etching rates than the first conductivity type semiconductor. According to Table 1, the example in which the intrinsic semiconductor layer 23 is two layers of amorphous silicon/highly diluted hydrogenated silicon compared to Example 3 in which the intrinsic semiconductor layer 23 is one layer of amorphous silicon. 1 and Example 2, in which the intrinsic semiconductor layer 23 is two layers of amorphous silicon/highly diluted hydrogenated silicon oxide, have high performance.
This is because even with poor uniformity in plasma etching, the use of highly diluted silicon hydride layers or hydrogenated silicon oxides etch more slowly, thus preventing partial loss of the passivation layer. It is thought that this is because

REFERENCE SIGNS LIST 1 solar cell 2 wiring member 3 light receiving surface protection member 4 back surface protection member 5 sealing material 7 first conductivity type regions 7b, 8b busbar portions 7f, 8f finger portions 8 second conductivity type regions 11, 111, 211, 311, 411 Semiconductor substrate 13, 23, 33, 113, 123, 133, 213, 223, 233, 313, 323, 333, 413, 423, 433 Intrinsic semiconductor layer 23a First layer 23b Second layer 15 Antireflection layer 25, 125, 225, 325, 425 first conductivity type semiconductor layer 27 first electrode layer 28, 38 transparent electrode layer 29, 39 metal electrode layer 35, 135, 235, 335, 435 second conductivity type semiconductor layer 37 second electrode layer 90, 95,190,193,290,293,390,495 Mask 100 Solar cell module

Claims (14)

A semiconductor substrate having two principal surfaces, an intrinsic semiconductor layer disposed on one principal surface of the semiconductor substrate, and a first conductor disposed on the one principal surface of the semiconductor substrate with the intrinsic semiconductor layer interposed therebetween. a back contact type solar cell comprising a type semiconductor layer, a second conductivity type semiconductor layer, and a first electrode layer corresponding to the first conductivity type semiconductor layer and a second electrode layer corresponding to the second conductivity type semiconductor layer. A manufacturing method of
an intrinsic semiconductor layer forming step of sequentially forming a first layer and a second layer of the intrinsic semiconductor layer on the one main surface side of the semiconductor substrate, after forming amorphous silicon as the first layer; , an intrinsic semiconductor layer forming step of forming highly diluted silicon hydride, silicon oxide, silicon nitride, silicon carbide, or a compound thereof as the second layer;
After forming a first conductivity type semiconductor material film on the intrinsic semiconductor layer on the one main surface side of the semiconductor substrate, a mask is used to form the first conductivity type semiconductor material film corresponding to the opening of the mask. and a first conductivity type semiconductor layer forming step of forming the first conductivity type semiconductor layer by removing part of the intrinsic semiconductor layer in the film thickness direction of the second layer by plasma etching;
a second conductivity type semiconductor layer forming step of forming the second conductivity type semiconductor layer on the second layer of the intrinsic semiconductor layer corresponding to the opening of the mask on the one main surface side of the semiconductor substrate;
A method of manufacturing a solar cell, comprising: The second layer, which is part of the intrinsic semiconductor layer in the film thickness direction and is located on the side of the intrinsic semiconductor layer facing the first conductivity type semiconductor layer , is made of a material resistant to the plasma etching. A method of manufacturing a solar cell according to claim 1, comprising: 3. The method of manufacturing a solar cell according to claim 2, wherein said second layer of said intrinsic semiconductor layer comprises a material having a slower plasma etching rate than said first layer of said intrinsic semiconductor layer. 4. The method of manufacturing a solar cell according to claim 2, wherein said second layer of said intrinsic semiconductor layer includes a material having a slower plasma etching rate than said first conductivity type semiconductor layer. 5. The method for manufacturing a solar cell according to claim 1, wherein said plasma etching is hydrogen plasma etching in which plasma discharge is performed while introducing hydrogen. 6. The method for manufacturing a solar cell according to claim 1, wherein said mask is a metal mask, or an organic or inorganic mask for a lift-off method. the outer shape of the mask is larger than the outer shape of the semiconductor substrate;
In the step of forming the semiconductor layer of the first conductivity type and the step of forming the semiconductor layer of the second conductivity type, the edge of the semiconductor substrate is covered with the mask.
A method for manufacturing a solar cell according to any one of claims 1 to 6 . In the step of forming the second conductivity type semiconductor layer, after forming an intrinsic semiconductor layer corresponding to the portion removed by the plasma etching on the intrinsic semiconductor layer corresponding to the opening of the mask, the second conductivity type semiconductor layer is formed. The method for manufacturing a solar cell according to any one of claims 1 to 7 , wherein The semiconductor substrate is an n-type semiconductor substrate,
the first conductivity type semiconductor layer is an n-type semiconductor layer,
The second conductivity type semiconductor layer is a p-type semiconductor layer,
A method for manufacturing a solar cell according to any one of claims 1 to 8 . A semiconductor substrate having two principal surfaces, an intrinsic semiconductor layer disposed on one principal surface of the semiconductor substrate, and a first conductor disposed on the one principal surface of the semiconductor substrate with the intrinsic semiconductor layer interposed therebetween. a back contact type solar cell comprising a type semiconductor layer, a second conductivity type semiconductor layer, and a first electrode layer corresponding to the first conductivity type semiconductor layer and a second electrode layer corresponding to the second conductivity type semiconductor layer. and
The intrinsic semiconductor layer includes a first layer and a second layer that are sequentially laminated on the one main surface side of the semiconductor substrate,
the first layer comprises amorphous silicon;
the second layer comprises highly diluted silicon hydride, silicon oxide, silicon nitride, silicon carbide, or a compound thereof;
Between the thickness T1 of the intrinsic semiconductor layer sandwiched between the semiconductor layer of the first conductivity type and the semiconductor substrate and the thickness T2 of the intrinsic semiconductor layer sandwiched between the semiconductor layer of the second conductivity type and the semiconductor substrate, T1 > satisfies the relation of T2,
solar cell. The thickness of the second conductivity type semiconductor layer near the center in the width direction of the second conductivity type semiconductor layer is thicker than the thickness of the second conductivity type semiconductor layer other than near the center in the width direction. Item 11. The solar cell according to item 10 . The second layer, which is a part of the intrinsic semiconductor layer in the film thickness direction and is located on the side of the intrinsic semiconductor layer facing the first conductivity type semiconductor layer, is for forming the first conductivity type semiconductor layer. 12. A solar cell according to claim 10 or 11 , comprising a material resistant to plasma etching of . 13. The solar cell of claim 12 , wherein said second layer of said intrinsic semiconductor layer comprises a material having a slower plasma etch rate than said first layer of said intrinsic semiconductor layer. 14. The solar cell according to claim 12 or 13, wherein said second layer of said intrinsic semiconductor layer comprises a material having a slower plasma etching rate than said first conductivity type semiconductor layer.

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