JP7353865B2 - How to manufacture solar cells - Google Patents

Description

The technology disclosed herein belongs to the technical field related to methods for manufacturing solar cells.

A typical solar cell is a double-sided electrode type in which electrodes are arranged on both sides (light-receiving surface and back surface) of a semiconductor substrate, but recently, solar cells without shielding loss due to electrodes have been developed as shown in Patent Document 1. A back-contact (back-electrode) solar cell has been developed in which electrodes are placed only on the back surface.

Back-contact type solar cells require semiconductor layer patterns such as a p-type semiconductor layer and an n-type semiconductor layer to be formed on the back surface with high precision, and the manufacturing method is more complicated than that of double-sided electrode type solar cells. As a technique for simplifying the manufacturing method, there is a technique for forming a semiconductor layer pattern using a lift-off method, as shown in Patent Document 1. That is, a patterning technique is being developed in which a semiconductor layer pattern is formed by removing a lift-off layer and removing a semiconductor layer formed on the lift-off layer.

JP2013-120863

However, in the method described in Patent Document 1, if the lift-off layer and the semiconductor layer have similar solubility, unintended layers may be removed, and patterning accuracy and productivity may not be high. be.

In addition, in back-contact solar cells, a transparent electrode layer made of an oxide is sometimes placed between the semiconductor layer and the metal electrode layer, but in this case, peeling of the transparent electrode layer from the semiconductor layer becomes a problem. There is.

The technology disclosed herein has been developed in view of these points, and its purpose is to provide high adhesion at various interfaces, for example, to improve the adhesion between an electrode layer and a semiconductor layer. The objective is to efficiently manufacture high-performance back-contact solar cells.

In order to solve the above problem, the technology disclosed herein includes, for example, a step of forming a first semiconductor layer of a first conductivity type on one of two main surfaces facing each other in a semiconductor substrate. , a step of stacking a lift-off layer on the first semiconductor layer, a step of selectively removing the first semiconductor layer and the lift-off layer, and the one main surface including the first semiconductor layer and the lift-off layer. forming a second semiconductor layer of a second conductivity type thereon; removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer; forming a transparent electrode layer made of an oxide on each of the second semiconductor layers, and in the step of removing the lift-off layer, the second semiconductor layer covering the lift-off layer is removed. wherein at least one of the two main surfaces is a covering portion made of a material constituting at least one of the lift-off layer or the second semiconductor layer, and the coating portion is a covering portion made of a material constituting at least one of the lift-off layer or the second semiconductor layer, and the residue is removed from the step of removing the lift-off layer. The lift-off layer can be removed so as to be covered by the remaining coating portion , and a high-performance back-contact solar cell with high adhesion at various interfaces can be efficiently manufactured.

That is, the present invention
forming a first semiconductor layer of a first conductivity type on one of two opposing main surfaces of the semiconductor substrate;
laminating a lift-off layer on the first semiconductor layer;
selectively removing the first semiconductor layer and the lift-off layer;
forming a second semiconductor layer of a second conductivity type on the one main surface including the first semiconductor layer and the lift-off layer;
removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer;
forming a transparent electrode layer made of an oxide on each of the first semiconductor layer and the second semiconductor layer,
In the step of removing the lift-off layer, in a state where the second semiconductor layer covering the lift-off layer is removed, the first semiconductor layer, the second semiconductor layer, and the other main surface of the two main surfaces are removed. At least a part of one or more surfaces selected from the group consisting of a coating made of a material constituting the lift-off layer and/or the second semiconductor layer, and a residue in the step of removing the lift-off layer. Regarding the method for manufacturing a solar cell in which the lift-off layer is removed so that the lift-off layer is covered by the remaining coating portion , it is possible to efficiently manufacture a high-performance back-contact type solar cell in which various interfaces have high adhesion.

In addition, in the step of removing the lift-off layer, the second semiconductor layer covering the lift-off layer is removed such that a part of the other main surface is covered with the covering portion . Remove the lift-off layer, and
It is preferable to include a step of forming an antireflection film on the other main surface after the step of removing the lift-off layer, so that the adhesion of the antireflection film to the other main surface is further improved.

In addition, in the step of removing the lift-off layer, in a state where the second semiconductor layer covering the lift-off layer is removed, a part of the surface of the first semiconductor layer and the second semiconductor layer is covered by the covering portion. removing the lift-off layer so as to
The area of the covering portion that covers a part of the second semiconductor layer is _T1 ,
When the area of the surface of the second semiconductor layer opposite to the semiconductor substrate is _T2 , the T coverage (%) expressed as 100× _T1 / _T2 is 0.2% or more, It is preferably 16% or less, and the adhesion of the oxide transparent electrode layer to the second semiconductor layer is further improved.

Further, in the step of removing the lift-off layer, the lift-off layer is removed such that a part of the first semiconductor layer is covered with the covering portion in a state where the second semiconductor layer covering the lift-off layer is removed. removing the layer, and
Let _S1 be an area of a covering part made of a material constituting the lift-off layer that covers a part of the first semiconductor layer,
When the area of the surface of the first semiconductor layer opposite to the semiconductor substrate is _S2 , the following formula:
(Coverage rate (%)) = 100 × S ₁ /S ₂
It is preferable that the coverage defined by is 0.2% or more and 16% or less, and the adhesion of the oxide transparent electrode layer to the first semiconductor layer is further improved.

Also,
It is preferable that the maximum length of the covering portion is 2.0 μm or less when viewed from the one main surface side in the direction perpendicular to the surface of the semiconductor substrate, and the oxide transparent electrode layer is in close contact with the first semiconductor layer. Sexuality further increases.

Also,
In the step of laminating the lift-off layer on the first semiconductor layer,
When the lift-off layer is single, when laminating the lift-off layer,
When the lift-off layer is plural, when stacking the layer closest to the first semiconductor layer,
It is preferable that particles made of an element constituting the lift-off layer are mixed into the lift-off layer.

Also,
The semiconductor substrate has a first texture structure on each of the two main surfaces,
It is preferable that the first semiconductor layer and the second semiconductor layer formed on the one main surface of the semiconductor substrate include a second texture structure reflecting the first texture structure.

According to the technology disclosed herein, it is possible to efficiently manufacture high-performance back-contact solar cells in which various interfaces have high adhesion.

FIG. 1 is a schematic cross-sectional view partially showing a solar cell according to an exemplary embodiment. FIG. 2 is a plan view showing the back main surface of a crystal substrate constituting a solar cell. FIG. 2 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. FIG. 2 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. FIG. 2 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. FIG. 2 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. FIG. 2 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. FIG. 2 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. FIG. 2 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell. FIG. 3 is an enlarged cross-sectional view of a part of the p-type semiconductor layer at the end of lift-off. FIG. 3 is a partial schematic cross-sectional view showing a lift layer mixed with crystal grains. FIG. 3 is a partial schematic cross-sectional view showing a case where the lift-off layer is composed of two layers. It is a graph showing the relationship between coverage and solar cell characteristics. It is a graph showing the relationship between refractive index and solar cell characteristics.

Hereinafter, exemplary embodiments will be described with reference to the drawings.

FIG. 1 shows a partial cross-sectional view of a solar cell (cell) according to this embodiment. As shown in FIG. 1, the solar cell 10 according to this embodiment uses a crystal substrate 11 made of silicon (Si). The crystal substrate 11 has two main surfaces 11S (11SU, 11SB) facing each other. Here, the main surface on which light is incident is called a front main surface 11SU, and the main surface opposite to this is called a back main surface 11SB. For convenience, the side of the front side main surface 11SU that more actively receives light than the back side main surface 11SB is defined as a light receiving side, and the side that does not actively receive light is defined as a non-light receiving side.

The solar cell 10 according to this embodiment is a so-called heterojunction crystal silicon solar cell, and is a back contact type (back electrode type) solar cell in which an electrode layer is disposed on the back main surface 11SB.

The solar cell 10 includes a crystal substrate 11, an intrinsic semiconductor layer 12, a conductive semiconductor layer 13 (p-type semiconductor layer 13p, n-type semiconductor layer 13n), a low reflection layer 14, and an electrode layer 15 (transparent electrode layer 17, metal electrode layer 18).

Hereinafter, for convenience, members that individually correspond to the p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be appended with "p" or "n" at the end of their reference numerals. Furthermore, since the conductivity types are different, such as p-type and n-type, one conductivity type is sometimes referred to as a "first conductivity type" and the other conductivity type is sometimes referred to as a "second conductivity type."

The crystal substrate 11 may be a semiconductor substrate made of single crystal silicon or a semiconductor substrate made of polycrystalline silicon. In the following, description will be made using a single crystal silicon substrate as an example.

The conductivity type of the crystal substrate 11 is that even if it is an n-type single crystal silicon substrate into which an impurity (for example, phosphorus (P) atoms) that introduces electrons into silicon atoms is introduced, it does not introduce holes into silicon atoms. A p-type single crystal silicon substrate into which an impurity (for example, boron (B) atoms) is introduced may be used. In the following, an n-type single crystal substrate, which is said to have a long carrier life, will be described as an example.

In addition, from the viewpoint of confining the received light, the crystal substrate 11 has a texture structure TX (first texture structure) consisting of peaks (convex) and valleys (concave) on the surfaces of the two main surfaces 11S. It may have. Note that the texture structure TX (uneven surface) is formed by, for example, anisotropic etching that applies the difference between the etching rate of the (100) plane of the crystal substrate 11 and the etching rate of the (111) plane of the crystal substrate 11. can be formed.

The size of the unevenness in the texture structure TX can be defined, for example, by the number of vertices. In this embodiment, from the viewpoint of light intake performance and productivity, the number of vertices is preferably in the range of 50,000 to 100,000/mm2, particularly 70,000 to 85,000/mm2. It is preferably less than mm2.

The thickness of the crystal substrate 11 may be 250 μm or less. Note that the measurement direction when measuring the thickness is a direction perpendicular to the average plane of the crystal substrate 11 (the average plane means the plane of the entire substrate that does not depend on the texture structure TX). Hereinafter, this vertical direction, that is, the direction in which the thickness is measured, will be referred to as the perpendicular direction.

When the thickness of the crystal substrate 11 is set to 250 μm or less, the amount of silicon used can be reduced, making it easier to secure silicon substrates and reducing costs. Furthermore, a back contact structure in which holes and electrons generated by photoexcitation within the silicon substrate are collected only on the back surface side is preferable from the viewpoint of the free path of each exciton.

On the other hand, if the thickness of the crystal substrate 11 is too small, the mechanical strength will be reduced, external light (sunlight) will not be absorbed sufficiently, and the short circuit current density will decrease. Therefore, the thickness of the crystal substrate 11 is preferably 50 μm or more, more preferably 70 μm or more. When the texture structure TX is formed on the main surface of the crystal substrate 11, the thickness of the crystal substrate 11 is expressed as the distance between the straight lines connecting the vertices of the convexities in the concavo-convex structures on the light-receiving side and the back side. be done.

The intrinsic semiconductor layer 12 (12U, 12p, 12n) covers both main surfaces 11S (11SU, 11SB) of the crystal substrate 11, thereby suppressing diffusion of impurities into the crystal substrate 11 and performing surface passivation. Note that "intrinsic (i-type)" is not limited to completely intrinsic, which does not contain conductive impurities, but also "weak", which contains a trace amount of n-type or p-type impurity to the extent that the silicon-based layer can function as an intrinsic layer. It also includes substantially intrinsic layers of "n-type" or "weak-p-type."

The material of the intrinsic semiconductor layer 12 is not particularly limited, but may be an amorphous silicon-based thin film, or a hydrogenated amorphous silicon-based thin film containing silicon and hydrogen (a-Si:H thin film). Good too. Note that the term "amorphous" here means a structure with a long period and no order. In other words, it includes not only completely disordered objects but also those that have short-period order. In addition, the intrinsic semiconductor layers 12 (12U, 12p, 12n) are not essential and may be formed as appropriate.

Further, the thickness of the intrinsic semiconductor layer 12 is not particularly limited, but may be 2 nm or more and 20 nm or less. This is because when the thickness is 2 nm or more, the effect as a passivation layer is enhanced, and when the thickness is 20 nm or less, deterioration in conversion characteristics caused by high resistance can be suppressed.

The method for forming the intrinsic semiconductor layer 12 is not particularly limited, but a plasma enhanced chemical vapor deposition (CVD) method is used. According to this method, the substrate surface can be effectively passivated while suppressing the diffusion of impurities into single crystal silicon. Furthermore, with the plasma CVD method, by changing the hydrogen concentration in the intrinsic semiconductor layer 12 in the thickness direction, it is possible to form an energy gap profile that is effective for carrier recovery.

The conditions for forming a thin film by the plasma CVD method include, for example, a substrate temperature of 100°C or more and 300°C or less, a pressure of 20Pa or more and 2600Pa or less, and a high frequency power density of 0.003W/cm2 or more and 0.5W/cm2. It may be the following.

In addition, in the case of the intrinsic semiconductor layer 12, the raw material gas used for forming the thin film is a silicon-containing gas such as monosilane (SiH4) and disilane (Si2H6), or a mixture of these gases and hydrogen (H2). It may be gas.

Note that a gas containing a different element such as methane (CH4), ammonia (NH3), or monogermane (GeH4) is added to the above gas to form silicon carbide (SiC), silicon nitride (SiNX), or silicon germanium. By forming a silicon alloy such as (SIGe), the energy gap of the thin film may be changed as appropriate.

Examples of the conductive semiconductor layer 13 include a p-type semiconductor layer 13p and an n-type semiconductor layer 13n. As shown in FIG. 1, the p-type semiconductor layer 13p is formed on a part of the back main surface 11SB of the crystal substrate 11 via the intrinsic semiconductor layer 12p. The n-type semiconductor layer 13n is formed on another part of the back main surface of the crystal substrate 11 via the intrinsic semiconductor layer 12n. That is, the intrinsic semiconductor layer 12 is interposed between the p-type semiconductor layer 13p and the crystal substrate 11 and between the n-type semiconductor layer 13n and the crystal substrate 11 as an intermediate layer serving as a passivation.

The thicknesses of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are not particularly limited, but may be 2 nm or more and 20 nm or less. This is because when the thickness is 2 nm or more, the effect as a passivation layer is enhanced, and when the thickness is 20 nm or less, deterioration in conversion characteristics caused by high resistance can be suppressed.

The p-type semiconductor layer 13p and the n-type semiconductor layer 13n are arranged on the back side of the crystal substrate 11 so that the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are electrically isolated via the intrinsic semiconductor layer 12. Ru. The width of the conductive semiconductor layer 13 may be 50 μm or more and 3000 μm or less, or 80 μm or more and 500 μm or less. Note that the widths of the semiconductor layers 12 and 13 and the widths of the electrode layers 17 and 18 are, unless otherwise specified, the length of a portion of each patterned layer. It means the length in the direction perpendicular to the extending direction.

When photoexcitons (carriers) generated within the crystal substrate 11 are taken out via the conductive semiconductor layer 13, holes have a larger effective mass than electrons. Therefore, from the viewpoint of reducing transport loss, the p-type semiconductor layer 13p may be narrower than the n-type semiconductor layer 13n. For example, the width of the p-type semiconductor layer 13p may be 0.5 times or more and 0.9 times or less, or 0.6 times or more and 0.8 times or less, the width of the n-type semiconductor layer 13n. Good too.

The p-type semiconductor layer 13p is a silicon layer doped with a p-type dopant (such as boron), and may be formed of amorphous silicon from the viewpoint of suppressing impurity diffusion or series resistance. On the other hand, the n-type semiconductor layer 13n is a silicon layer doped with an n-type dopant (such as phosphorus), and may be formed of an amorphous silicon layer similarly to the p-type semiconductor layer 13p.

As the raw material gas for the conductive semiconductor layer 13, a silicon-containing gas such as monosilane (SiH4) or disilane (Si2H6), or a mixed gas of a silicon-based gas and hydrogen (H2) may be used. As the dopant gas, diborane (B2H6) or the like is used to form the p-type semiconductor layer 13p, and phosphine (PH3) or the like is used to form the n-type semiconductor layer. Further, since the amount of impurities such as boron (B) or phosphorus (P) added may be small, a mixed gas in which the dopant gas is diluted with the source gas may be used.

Further, in order to adjust the energy gap of the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, different elements such as methane (CH4), carbon dioxide (CO2), ammonia (NH3), or monogermane (GeH4) are included. By adding gas, the p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be alloyed.

The low reflection layer 14 is a layer that suppresses reflection of light received by the solar cell 10. The material of the low reflection layer 14 is not particularly limited as long as it is a transparent material that transmits light, but examples include silicon oxide (SiOX), silicon nitride (SiNX), zinc oxide (ZnO), and titanium oxide ( TiOX). Further, as a method for forming the low reflection layer 14, for example, a resin material in which nanoparticles of an oxide such as zinc oxide or titanium oxide are dispersed may be applied.

The electrode layer 15 is formed to cover the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, respectively, and is electrically connected to each conductive type semiconductor layer 13. Thereby, the electrode layer 15 functions as a transport layer that guides carriers generated in the p-type semiconductor layer 13p or the n-type semiconductor layer 13n. Note that the electrode layers 15p and 15n corresponding to the semiconductor layers 13p and 13n are arranged apart from each other to prevent short circuit between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n.

In addition, from the viewpoint of electrical bonding with the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, or from the viewpoint of suppressing the diffusion of atoms into both the metal semiconductor layers 13p and 13n, which are electrode materials, transparent The electrode layer 15 made of a conductive oxide may be provided between the metal electrode layer and the p-type semiconductor layer 13p and between the metal electrode layer and the n-type semiconductor layer 13n.

In this embodiment, the electrode layer 15 formed of a transparent conductive oxide is called a transparent electrode layer 17, and the metal electrode layer 15 is called a metal electrode layer 18. Further, as shown in the plan view of the back main surface 11SB of the crystal substrate 11 shown in FIG. 2, in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n each having a comb-teeth shape, an electrode layer is formed on the comb back part. is sometimes referred to as a busbar portion, and the electrode layer formed on the comb tooth portion is sometimes referred to as a finger portion.

The transparent electrode layer 17 is made of, for example, zinc oxide (ZnO) or indium oxide (InOX), or indium oxide and various metal oxides, such as titanium oxide (TiOX) or tin oxide (SnOX), although the material of the transparent electrode layer 17 is not particularly limited. Examples include transparent conductive oxides to which tungsten oxide (WOX), molybdenum oxide (MoOX), or the like is added in an amount of 1% by weight or more and 10% by weight or less.

The thickness of the transparent electrode layer 17 may be 20 nm or more and 200 nm or less. Methods for forming transparent electrode layers suitable for this thickness include, for example, physical vapor deposition (PVD) methods such as sputtering, or metal-organic Examples include a chemical vapor deposition (MOCVD) method.

The material of the metal electrode layer 18 is not particularly limited, and examples thereof include silver (Ag), copper (Cu), aluminum (Al), and nickel (Ni).

The thickness of the metal electrode layer 18 may be 1 μm or more and 80 μm or less. Methods for forming the metal electrode layer 18 suitable for this thickness include a printing method in which a material paste is printed by inkjet printing or screen printing, or a plating method. However, the method is not limited to this, and when a vacuum process is employed, a vapor deposition or sputtering method may be employed.

Furthermore, the width of the comb teeth in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n may be approximately the same as the width of the metal electrode layer 18 formed on the comb teeth. However, the width of the metal electrode layer 18 may be narrower than the width of the comb teeth. Further, as long as the structure prevents leakage between the metal electrode layers 18, the width of the metal electrode layer 18 may be wider than the width of the comb tooth portion.

In this embodiment, an intrinsic semiconductor layer 12, a conductive semiconductor layer 13, a low reflection layer 14, and an electrode layer 15 are laminated on the back main surface 11SB of the crystal substrate 11, and the passivation and conductivity of each bonding surface are A predetermined annealing treatment is performed for the purpose of suppressing the generation of defect levels in the type semiconductor layer 13 and its interface, and crystallizing the transparent conductive oxide in the transparent electrode layer 17.

The annealing process according to the present embodiment includes, for example, an annealing process in which the crystal substrate 11 on which each of the layers described above is formed is placed in an oven heated to 150° C. or more and 200° C. or less. In this case, the atmosphere in the oven may be the air, and more effective annealing can be achieved by using hydrogen or nitrogen. Further, this annealing treatment may be an RTA (Rapid Thermal Annealing) treatment in which the crystal substrate 11 on which each layer is formed is irradiated with infrared rays using an infrared heater.

[Method for manufacturing solar cells]
Hereinafter, a method for manufacturing the solar cell 10 according to this embodiment will be described with reference to FIGS. 3 to 9.

First, as shown in FIG. 3, a crystal substrate 11 having a texture structure TX on each of the front main surface 11SU and the back main surface 11SB is prepared.

Next, as shown in FIG. 4, for example, an intrinsic semiconductor layer 12U is formed on the front main surface 11SU of the crystal substrate 11. Subsequently, a low reflection layer 14 is formed on the formed intrinsic semiconductor layer 12U. For the low reflection layer 14, silicon nitride (SiNX) or silicon oxide (SiOX) having a suitable light absorption coefficient and refractive index is used from the viewpoint of light confinement. This step may be performed between FIG. 3 and FIG. 5, but is not particularly limited, and may be performed after the lift-off layer LF is removed. When the lift-off layer LF is removed, the lift-off layer LF is removed so that the top surface 11SU is covered with at least one of the lift-off layer LF, the intrinsic semiconductor layer 12n, or the n-type semiconductor layer 13n. The adhesion of the reflective layer 14 can be improved.

Next, as shown in FIG. 5, an intrinsic semiconductor layer 12p made of, for example, i-type amorphous silicon is formed on the back main surface 11SB of the crystal substrate 11. Subsequently, a p-type semiconductor layer 13p is formed on the formed intrinsic semiconductor layer 12p. As a result, a p-type semiconductor layer 13p is formed on the back side main surface 11SB, which is one main surface of the crystal substrate 11. As described above, in the present embodiment, the step of forming the p-type semiconductor layer (first semiconductor layer) 13p is performed by forming one of the crystal substrates (semiconductor substrates) 11 before forming the p-type semiconductor layer 13p. It includes a step of forming an intrinsic semiconductor layer (first intrinsic semiconductor layer) 12p on the main surface (back main surface) 11S.

After that, a lift-off layer LF is formed on the formed p-type semiconductor layer 13p. Specifically, a lift-off layer LF containing silicon oxide (SiOX) as a main component is formed on the p-type semiconductor layer 13p.

Next, as shown in FIG. 6, the lift-off layer LF and the p-type semiconductor layer 13p are patterned on the back main surface 11SB of the crystal substrate 11. As a result, the p-type semiconductor layer 13p is selectively removed, resulting in a non-formation region NA where the p-type semiconductor layer 13p is not formed. On the other hand, at least the lift-off layer LF and the p-type semiconductor layer 13p remain in the region of the back side main surface 11SB of the crystal substrate 11 that is not etched.

Such a patterning process can be realized by a photolithography method, for example, by forming a resist film (not shown) having a predetermined pattern on the lift-off layer LF, and etching a region masked by the formed resist film. . As shown in FIG. 6, by patterning each layer of the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the lift-off layer LF, a non-formation area NA is formed in a part of the back main surface 11SB of the crystal substrate 11, that is, the back side. An exposed area of the main surface 11SB is generated. Note that details regarding the non-formation area NA will be described later.

Examples of the etching solution used in the process shown in FIG. liquid). The etching solution in this case corresponds to the second etching solution. Furthermore, the etchant that contributes to etching the lift-off layer LF is hydrogen fluoride. Note that the patterning here is not limited to wet etching using an etching solution. The patterning may be, for example, dry etching or pattern printing using an etching paste or the like.

Next, as shown in FIG. 7, an intrinsic semiconductor layer 12n and an n-type semiconductor layer 13n are formed on the back main surface 11SB of the crystal substrate 11, including the lift-off layer LF, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer 12p. Form sequentially. As described above, in the present embodiment, the step of forming the n-type semiconductor layer (second semiconductor layer) 13n is performed by forming the lift-off layer of the crystal substrate (semiconductor substrate) 11 before forming the n-type semiconductor layer 13n. It includes a step of forming an intrinsic semiconductor layer (second intrinsic semiconductor layer) 12n on one main surface (back main surface) 11S including the LF and p-type semiconductor layers. As a result, the stacked film of the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n is formed on the non-formation region NA, on the surface and side surfaces (end faces) of the lift-off layer LF, on the lift-off layer LF, on the p-type semiconductor layer 13p, and on the intrinsic semiconductor layer 13n. It is formed so as to cover the side surfaces (end surfaces) of the layer 12p.

Next, as shown in FIG. 8, the n-type semiconductor layer 13n and the intrinsic semiconductor layer 12n covering the lift-off layer LF are removed from the crystal substrate 11 by removing the stacked lift-off layer LF using an etching solution. Note that as the etching solution used for this patterning, for example, hydrofluoric acid is used.

In the step shown in FIG. 8, the lift-off layer LF is formed such that at least one of the two main surfaces is covered with the lift-off layer LF, the intrinsic semiconductor layer 12n, or the n-type semiconductor layer 13n. remove. FIG. 8 shows an example in which the lift-off layer LF is removed so that a part of the p-type semiconductor layer 13p is covered with the lift-off layer LF. That is, as shown in FIG. 10, a part of the lift-off layer LF remains on the p-type semiconductor layer 13, and a part of the surface of the p-type semiconductor layer 13p opposite to the crystal substrate 11 is covered with the remaining lift-off layer LF. Lift-off layer LF is removed so that it is covered by layer LF.

Next, as shown in FIG. 9, separation grooves are formed on the back main surface 11SB of the crystal substrate 11, that is, on each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, by sputtering using a mask, for example. A transparent electrode layer 17 (17p, 17n) is formed so as to form a transparent electrode layer 25. Note that the transparent electrode layer 17 (17p, 17n) may be formed as follows instead of the sputtering method. For example, a transparent conductive oxide film is formed on the entire back surface 11SB without using a mask, and then a transparent conductive oxide film is formed on the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by photolithography. It may also be formed by performing etching that leaves a permanent oxide film. Here, by forming the isolation groove 25 that isolates and insulates the p-type semiconductor layer 13p and the n-type semiconductor layer 13n from each other, leakage becomes less likely to occur.

Thereafter, linear metal electrode layers 18 (18p, 18n) are formed on the transparent electrode layer 17 using, for example, a mesh screen (not shown) having openings.

Through the above steps, a back-side bonding type solar cell 10 is formed.

(Summary and effects)
The following can be said from the method for manufacturing the solar cell 10 described above.

First, in the step shown in FIG. 8, when the lift-off layer LF is removed using an etching solution, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n deposited on the lift-off layer LF are also removed from the crystal substrate 11 at the same time. (so-called lift-off). This step does not require a resist coating step and a developing step used in the photolithography method, compared to the step shown in FIG. 6, which uses, for example, a photolithography method. Therefore, the n-type semiconductor layer 13n can be easily patterned.

Further, since at least a portion of either the p-type semiconductor layer 13p or the n-type semiconductor layer 13n is covered with the lift-off layer LF, the transparent electrode layer in the region of the p-type semiconductor layer 13p or the n-type semiconductor layer 13n The adhesion of No. 17 is improved. Although an example in which the p-type semiconductor layer 13p is covered will be described below, the same argument holds true for the n-type semiconductor layer 13n. That is, if a part of the lift-off layer LF (hereinafter referred to as the covering part 19) remains as a residue on the p-type semiconductor layer 13p, the surface area increases by the covering part 19, and in the region of the p-type semiconductor layer 13p. , the contact area of the transparent electrode layer 17 becomes wider. For example, when the transparent electrode layer 17 is made of tin oxide-indium oxide (ITO), silicon oxide has higher adhesion to ITO than silicon, so the covering portion 19 mainly composed of silicon oxide If there is, the transparent electrode layer 17 will be difficult to peel off from the p-type semiconductor layer 13p. As a result, the adhesion of the transparent electrode layer 17 in the region of the p-type semiconductor layer 13p is improved.

On the other hand, if there are too many covering portions 19, the contact area between the transparent electrode layer 17 and the p-type semiconductor layer 13p decreases, so the series resistance between the transparent electrode layer 17 and the p-type semiconductor layer 13p increases, There is a possibility that the IV characteristics of the solar cell 10 may deteriorate. Therefore, when the area of the portion of the p-type semiconductor layer 13p covered with the covering portion 19 is S1, and the area of the entire surface of the p-type semiconductor layer 13p opposite to the crystal substrate 11 is S2, the following formula:
(Coverage rate (%)) = 100 × S1/S2
It is preferable that the coverage defined by is 0.2% or more and 16% or less. If the coverage is 0.2% or more and 16% or less, the contact area between the transparent electrode layer 17 and the p-type semiconductor layer 13p can be suitably secured while improving the adhesion of the transparent electrode layer 17.

Furthermore, even if the coverage ratio is 0.2% or more and 16% or less, if there is a locally large-sized covering portion 19, excitons (in the case of a p-type semiconductor, excitons) in the p-type semiconductor layer 13p Due to the relationship between the effective mass of the hole (hole) and the free path, there is a possibility that the exciton cannot be appropriately collected from the p-type semiconductor layer 13p. For this reason, it is preferable that the maximum length of the covering portion 19 is 2.0 μm or less when viewed from the back mold main surface SB11 side in the direction perpendicular to the surface of the crystal substrate 11. Thereby, excitons can be appropriately recovered from the p-type semiconductor layer 13p while improving the adhesion of the transparent electrode layer 17.

The coverage ratio can be adjusted, for example, by devising the process of depositing the lift-off layer LF on the p-type semiconductor layer 13p. Specifically, as shown in FIG. 12, when the lift-off layer LF is deposited on the p-type semiconductor layer 13p, particles (here, silicon particles or silicon oxide particles) made of the elements constituting the lift-off layer LF are used. Hereinafter, crystal grains 20) are mixed. Generally, the lift-off layer LF is made of amorphous material so that it can be easily etched during lift-off. Due to the influence of density, etc., the etching rate of the crystal grains 20 is slower than that of amorphous, so even if the amorphous portion of the lift-off layer LF is dissolved, the crystal grains 20 remain on the p-type semiconductor layer 13p without being dissolved. I can do it. Therefore, by adjusting the amount of crystal grains to be mixed, the coverage can be adjusted.

Further, when the lift-off layer LF has silicon oxide as a main component as in this embodiment, the coverage can also be adjusted by adjusting the refractive index of the lift-off layer LF. That is, the refractive index is proportional to the density, and when the refractive index is high, the density basically becomes high. As the density increases, the etching rate decreases, making it easier for the covering portion 19 to occur. Therefore, by increasing the refractive index of the lift-off layer LF, the coverage can be increased. From the viewpoint of setting the coverage to 0.2% or more and 16% or less, the refractive index preferably has a value of 1.45 or more and 1.90 or less for light with a wavelength of 632 nm.

In the lift-off layer LF containing silicon oxide as a main component, the refractive index can be adjusted, for example, by adjusting the pressure during film formation using the CVD method. Specifically, by increasing the pressure, it becomes easier to obtain a dense structure and a lift-off layer LF with a high refractive index.

The method of mixing crystal grains into the lift-off layer LF and the method of adjusting the refractive index of the lift-off layer LF may be used alone or both may be used.

In both the method of mixing crystal grains 20 into the lift-off layer LF and the method of adjusting the refractive index of the lift-off layer LF, it is preferable that the lift-off layer LF is composed of a plurality of layers. For example, as shown in FIG. 12, the lift-off layer LF is composed of a first lift-off layer LF1 stacked on the p-type semiconductor layer 13p and a second lift-off layer LF2 stacked on the first lift-off layer LF1. When the first lift-off layer LF1 is composed of two layers, crystal grains 20 are mixed in or the refractive index is increased in only the first lift-off layer LF1. Thereby, the coverage can be adjusted while minimizing the time required to remove the lift-off layer LF. Note that when the lift-off layer LF is composed of a plurality of layers, the lift-off layer LF may be composed of three or more layers, but in consideration of manufacturing cost and productivity, it is preferably composed of two layers.

Regardless of whether there is a single lift-off layer LF or a plurality of lift-off layers LF, the overall film thickness of the lift-off layer LF is preferably 20 nm or more and 600 nm or less, particularly preferably 50 nm or more and 450 nm or less. When there is a plurality of lift-off layers LF, it is preferable that the layer closest to the p-type semiconductor layer 13p has the thinnest thickness within this range.

Further, the crystal substrate 11 has a texture structure TX, and each surface of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n formed on the back main surface 11SB of the crystal substrate 11 has the texture structure TX. It is preferable that a texture structure (second texture structure) reflecting the above is included.

When the conductive semiconductor layer 13 has a texture structure TX on its surface, the etching solution easily permeates into the semiconductor layer 13 due to the unevenness of the texture structure TX. Therefore, the conductive semiconductor layer 13 is easily removed, that is, easily patterned.

In the present embodiment, the texture structure TX (first texture structure) is provided on both main surfaces 11S of the crystal substrate 11, that is, the front main surface 11SU and the back main surface 11SB, but the texture structure TX (first texture structure) is provided on either main surface may be provided. That is, when the texture structure TX is provided on the front main surface 11SU, the effect of capturing and confining the received light is enhanced. On the other hand, when the texture structure TX is provided on the back main surface 11SB, the light capturing effect is improved and the patterning of the conductive semiconductor layer 13 is facilitated. Therefore, the texture structure TX of the crystal substrate 11 may be provided on at least one main surface 11S. Further, in this embodiment, the texture structure TX on both main surfaces 11S has the same pattern, but the pattern is not limited to this, and the size of the unevenness of the texture structure TX can be changed between the front main surface 11SU and the back main surface 11SB. Good too.

When the low reflection layer forming step shown in FIG. 4 is also performed after removing the lift-off layer LF, the front main surface 11SU is covered with at least one of the lift-off layer LF, the intrinsic semiconductor layer 12n, or the n-type semiconductor layer 13n. By removing the lift-off layer LF in this way, the adhesion of the low reflection layer 14 can be improved.

Note that in the step shown in FIG. 6, the back main surface 11SB of the crystal substrate 11 is exposed in the non-formation area NA, but the invention is not limited thereto. That is, the intrinsic semiconductor layer 12p may remain on the non-formation area NA of the back main surface 11SB. It is sufficient that the p-type semiconductor layer 13p is selectively removed, and the region where the p-type semiconductor layer 13p is removed becomes the non-formation region NA.

In such a case, the step of forming the intrinsic semiconductor layer 12n before depositing the n-type semiconductor layer 13n on the remaining lift-off layer LF and non-formation area NA can be reduced.

Further, for example, when the lift-off layer LF is composed of two layers, the first lift-off layer LF1 and the second lift-off layer LF2, in the step shown in FIG. The etching solution may be applied to the first lift-off layer LF1 through the formed opening, and the layer to which the etching solution has adhered may be removed. Furthermore, in the step shown in FIG. 6, the lift-off layer LF is removed as described above, and the etching solution is also applied to the p-type semiconductor layer 13p, and the p-type semiconductor layer 13p to which the etching solution has adhered is removed. Good too. Note that the formation of this opening includes, for example, generating cracks.

In this way, by forming an opening in the second lift-off layer LF2 and passing the etching solution through the opening, the etching solution reliably adheres to the second lift-off layer LF2 and further to the first lift-off layer LF1. Therefore, the entire lift-off layer LF is efficiently removed. In addition, by removing the lift-off layer LF, the etching solution reliably adheres to the p-type semiconductor layer 13p covered with the lift-off layer LF, so that the p-type semiconductor layer 13p is also removed. This suppresses undissolved portions of the lift-off layer LF and the p-type semiconductor layer 13p.

The technology disclosed herein is not limited to the embodiments described above, and may be substituted without departing from the spirit of the claims.

For example, in the embodiment described above, the semiconductor layer used in the step shown in FIG. 5 is the p-type semiconductor layer 13p, but is not limited thereto, and may be the n-type semiconductor layer 13n. Furthermore, the conductivity type of the crystal substrate 11 is not particularly limited, and may be p-type or n-type.

The embodiments described above are merely illustrative and should not be construed as limiting the scope of the technology of the present disclosure. The scope of the technology of the present disclosure is defined by the scope of the claims, and all modifications and changes that fall within the scope of equivalents of the claims are within the scope of the technology of the present disclosure.

Hereinafter, the technology according to the present disclosure will be specifically explained using examples. However, the technology according to the present disclosure is not limited to these examples. Examples and comparative examples were produced as follows (see [Table 1]). Note that, in the following explanation, there is no particular distinction between Examples 1 to 3 and Comparative Examples 1 to 3 when the conditions are the same.

[Crystal substrate]
First, a single crystal silicon substrate with a thickness of 200 μm was used as a crystal substrate. Anisotropic etching was performed on both main surfaces of a single crystal silicon substrate. As a result, a pyramid-shaped texture structure was formed on the crystal substrate.

[Intrinsic semiconductor layer]
The crystal substrate was introduced into a CVD apparatus, and silicon intrinsic semiconductor layers (film thickness: 8 nm) were formed on both main surfaces of the introduced crystal substrate. The film forming conditions were a substrate temperature of 150° C., a pressure of 120 Pa, a SiH4/H2 flow rate ratio of 3/10, and a power density of 0.011 W/cm2.

[P-type semiconductor layer (first conductivity type semiconductor layer)]
A crystal substrate with intrinsic semiconductor layers formed on both main surfaces was introduced into a CVD apparatus, and a p-type hydrogenated amorphous silicon thin film (thickness: 10 nm) was formed on the intrinsic semiconductor layer on the back main surface. The film forming conditions were a substrate temperature of 150° C., a pressure of 60 Pa, a SiH4/B2H6 flow rate ratio of 1/3, and a power density of 0.01 W/cm2. Further, the flow rate of B2H6 gas is the flow rate of diluted gas in which B2H6 is diluted with H2 to 5000 ppm.

[Lift-off layer]
A lift-off layer containing silicon oxide (SiOX) as a main component was formed to a thickness of 200 nm on the p-type hydrogenated amorphous silicon thin film using a plasma CVD apparatus.

In Example 1, the film forming conditions for the lift-off layer were a substrate temperature of 150° C., a pressure of 50 Pa, a SiH4/CO2/H2 flow rate ratio of 1/10/750, and a power density of 0.15 W/cm2. . In Example 2, the value of the SiH4/CO2/H2 flow rate ratio was set to 1/10/650, and the other conditions were the same as those in Example 1. In Example 3, the value of the SiH4/CO2/H2 flow rate ratio was set to 1/10/550, and the other conditions were the same as those in Example 1.

In Comparative Example 1, the film forming conditions were the same as in Examples 1 to 3, except that the value of the SiH4/CO2/H2 flow rate ratio was set to 1/4/750.

In Comparative Example 2, the film forming conditions were the same as in Examples 1 to 3, except that the SiH4/CO2/H2 flow rate ratio was set to 1/30/1000.

In Comparative Example 3, the film forming conditions were the same as in Examples 1 to 3, except that the SiH4/CO2/H2 flow rate ratio was set to 1/10/350.

[Patterning of lift-off layer and first conductivity type semiconductor layer]
First, a photosensitive resist film was formed on the back main surface of the crystal substrate on which the lift-off layer was formed. This was exposed and developed by photolithography to expose the regions where the lift-off layer, p-type semiconductor layer, and intrinsic semiconductor layer were to be removed. The crystal substrate on which a plurality of layers were formed was immersed in hydrofluoric nitric acid containing 1% by weight of hydrogen fluoride as an etching agent to remove the lift-off layer. After rinsing with pure water, the p-type semiconductor layer exposed by removing the lift-off layer and the intrinsic semiconductor layer immediately below it were immersed in an ozone/hydrofluoric acid solution containing 5.5% by weight of hydrofluoric acid and 20 ppm of ozone. and were removed. Hereinafter, this process will be referred to as a patterning process.

[N-type semiconductor layer (second conductivity type semiconductor layer)]
After the first semiconductor layer patterning step, the crystal substrate whose exposed backside main surface was cleaned with hydrofluoric acid having a concentration of 2% by weight is introduced into a CVD apparatus, and an intrinsic semiconductor layer (film thickness 8 nm) is formed on the backside main surface. It was formed under the same film forming conditions as the first intrinsic semiconductor layer. Subsequently, an n-type hydrogenated amorphous silicon thin film (thickness: 10 nm) was formed on the formed intrinsic semiconductor layer. The film forming conditions were a substrate temperature of 150° C., a pressure of 60 Pa, a SiH4/PH3/H2 flow rate ratio of 1/2, and a power density of 0.01 W/cm2. Further, the flow rate of PH3 gas is the flow rate of diluted gas in which PH3 is diluted to 5000 ppm with H2.

[Removal of lift-off layer and second conductivity type semiconductor layer]
The crystal substrate on which the n-type semiconductor layer is formed is immersed in 5% by weight hydrofluoric acid to form a lift-off layer, an n-type semiconductor layer covering the lift-off layer, and a space between the lift-off layer and the n-type semiconductor layer. A certain intrinsic semiconductor layer was removed all together. Hereinafter, this process will be referred to as a lift-off process.

[Electrode layer, low reflection layer]
Using a magnetron sputtering device, an oxide film (thickness: 100 nm) that would become the base of a transparent electrode layer was formed on the conductive semiconductor layer of the crystal substrate. Furthermore, a silicon nitride layer was formed as a low reflection layer on the light-receiving surface side of the crystal substrate. As a transparent conductive oxide, indium oxide (ITO) containing tin oxide at a concentration of 10% by weight was used as a target. A mixed gas of argon and oxygen was introduced into the chamber of the apparatus, and the pressure inside the chamber was set to 0.6 Pa. The mixing ratio of argon and oxygen was set to the lowest resistivity (so-called bottom) condition. Further, film formation was performed using a DC power source at a power density of 0.4 W/cm2.

Next, by photolithography, etching was performed so that only the transparent conductive oxide film on the conductive semiconductor layers (p-type semiconductor layer and n-type semiconductor layer) was left, thereby forming a transparent electrode layer. The transparent electrode layer formed by this etching prevented electrical conduction between the transparent conductive oxide film on the p-type semiconductor layer and the transparent conductive oxide film on the n-type semiconductor layer.

Further, a silver paste (Dotite FA-333 manufactured by Fujikura Kasei Co., Ltd.) was screen printed on the transparent electrode layer without dilution, and heat treatment was performed in an oven at a temperature of 150° C. for 60 minutes. As a result, a metal electrode layer was formed.

Next, an evaluation method for back contact type solar cells will be explained. For the evaluation results, refer to [Table 1], FIGS. 13 and 14.

[Evaluation of film thickness and etching properties]
The film thickness or etching state of the lift-off layer was evaluated using SEM (field emission scanning electron microscope S4800: manufactured by Hitachi High-Technologies). After the first semiconductor layer patterning process, mark "○" if the area is etched according to the designed pattern removal area, and mark "x" if the lift-off layer is excessively etched and the solar cell characteristics are adversely affected. And so.

[Evaluation of refractive index]
The refractive index of the lift-off layer was measured by spectroscopic ellipsometry (trade name M2000,・Determined by measurement using A-Woollam Co., Ltd.). From the fitting results, the refractive index for light with a wavelength of 632 nm was extracted.

[Evaluation of coverage]
After the lift-off process, the surface of the first conductive type semiconductor layer was observed on the back surface of the crystal substrate at a magnification of 100 times using a laser microscope (equipment name: OPTELICS, manufactured by Lasertech). The covering portion and the first conductive type semiconductor layer were color-coded by image processing, and the area of the portion of the first conductive type semiconductor layer covered with the covering portion was calculated. Then, the area of the portion of the first conductive type semiconductor layer covered by the covering portion is set as S1, and the area of the entire surface of the first conductive type semiconductor layer opposite to the crystal substrate is set as S2, and the following formula is used:
(Coverage rate (%)) = 100 × S1/S2
The coverage rate was calculated.

[Evaluation of adhesion]
An adhesive tape specified in JIS Z1522 was attached to the solar cell with electrodes formed thereon, and evaluated by being pulled vertically. If the electrode layer peeled off when it was pulled, it was marked as "x", and if the electrode layer did not peel off, it was marked as "○".

[Evaluation of IV characteristics]
The IV curve was observed when reference sunlight of AM (air mass) 1.5 was irradiated with a light intensity of 100 mW/cm2. If you scan from -1.0V to +1.5V and the IV curve is S-shaped (if there is an extreme point in the range of -1.0V to +1.5V), ", and if no S-shaped change was observed in the IV curve, it was marked as "〇".

[Evaluation of conversion efficiency]
A solar simulator was used to irradiate reference sunlight with an AM (air mass) of 1.5 at a light intensity of 100 mW/cm 2 to measure the conversion efficiency (Eff (%)) of the solar cell. The conversion efficiency (solar cell characteristics) of Example 1 was set to 1.00, and the relative values are listed in [Table 1].

[Reliability evaluation]
A module in which a solar cell with an electrode formed thereon was laminated with glass and a back sheet was subjected to an environmental test at a temperature of 85° C. and a humidity of 85%, and the conversion efficiency (Eff (%)) was measured after 3000 hours. The conversion efficiency was measured using a solar simulator by irradiating reference sunlight with an AM (air mass) of 1.5 at a light intensity of 100 mW/cm 2 . The initial conversion efficiency was assumed to be 1.00, and the relative values are listed in [Table 1].

Examples 1 to 3 were good in all aspects of electrode adhesion, IV characteristics, solar cell characteristics, and reliability.

Looking at the results of Examples 1 to 3 and Comparative Examples 1 to 3, it was confirmed that the electrode layer had good adhesion in those in which a coating was formed (other than Comparative Example 2). . On the other hand, it has been found that when the coverage is too high, the IV characteristics deteriorate and solar cell identification deteriorates. This is considered to be due to the fact that excitons cannot be taken out from the portion of the first conductivity type semiconductor layer covered with the covering portion. In other words, it was confirmed that in order to suppress deterioration of solar cell characteristics while improving the adhesion of the electrode layer, it is necessary to keep the coverage within an appropriate range. Referring to FIG. 13, when the solar cell characteristics of Example 1 are set to 1.00, in order to make the solar cell characteristics 0.80 or more, the coverage must be set to 0.2% or more and 16% or less. I know it's good. For this reason, in the technology of the present disclosure, a preferable range of coverage is 0.2% or more and 16% or less.

Furthermore, looking at the results of Examples 1 to 3 and Comparative Examples 1 to 3, it was confirmed that the higher the refractive index of the lift-off layer, the higher the coverage. This is thought to be because the higher the refractive index, the higher the density and the harder it is to dissolve during etching. Furthermore, it has been found that if the refractive index is too low, the lift-off layer will be excessively etched during the patterning process. This is considered to be because the density became low and the structure of the lift-off layer became sparse, and the dissolution rate during etching became high. Referring to FIG. 14, when the solar cell characteristics of Example 1 are 1.00, in order to make the solar cell characteristics 0.80 or more, the refractive index for light with a wavelength of 632 nm must be 1.45 or more. It can be seen that the value should be set to .90 or less. For this reason, in the technology of the present disclosure, a preferable refractive index range is 1.45 or more and 1.90 or less.

In summary, the results showed that covering a portion of the first conductivity type semiconductor layer with the lift-off layer improves the electrical contact (adhesion) between the first conductivity type semiconductor layer and the electrode layer. . In particular, compared to the comparative examples, the results obtained in the examples showed that the solar cell characteristics were improved by setting the coverage within an appropriate range. This improves the adhesion between the first conductivity type semiconductor layer and the electrode layer by leaving an appropriate amount of the material (silicon oxide in this case) constituting the lift-off layer on the first conductivity type semiconductor layer. This is thought to be because not only this, but also an increase in series resistance is suppressed.

Furthermore, the results showed that by setting the refractive index of the lift-off layer to an appropriate value, it is possible to bring the coverage within the above-mentioned appropriate range. In particular, if the refractive index of the lift-off layer is too low, the lift-off layer is excessively removed during the patterning process, resulting in failure to obtain sufficient solar cell characteristics. It was found that there was a problem with reliability, especially for those with poor adhesion.

10 Solar cell 11 Crystal substrate (semiconductor substrate)
12 Intrinsic semiconductor layer 13 Conductivity type semiconductor layer 13p P-type semiconductor layer [first semiconductor layer of first conductivity type/second semiconductor layer of second conductivity type]
13n n-type semiconductor layer [second semiconductor layer of second conductivity type/first semiconductor layer of first conductivity type]
15 Electrode layer 17 Transparent electrode layer 18 Metal electrode layer 19 Coating portion 20 Crystal grains (grains made of crystals of the substance forming the lift-off layer)
LF lift-off layer

Claims (7)

forming a first semiconductor layer of a first conductivity type on one of two opposing main surfaces of the semiconductor substrate;
laminating a lift-off layer on the first semiconductor layer;
selectively removing the first semiconductor layer and the lift-off layer;
forming a second semiconductor layer of a second conductivity type on the one main surface including the first semiconductor layer and the lift-off layer;
removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer;
forming a transparent electrode layer made of an oxide on each of the first semiconductor layer and the second semiconductor layer,
In the step of removing the lift-off layer, in a state where the second semiconductor layer covering the lift-off layer is removed, the first semiconductor layer, the second semiconductor layer, and the other main surface of the two main surfaces are removed. At least a part of one or more surfaces selected from the group consisting of a coating made of a material constituting the lift-off layer and/or the second semiconductor layer, and a residue in the step of removing the lift-off layer. A method of manufacturing a solar cell, wherein the lift-off layer is removed so that the lift-off layer is covered by a remaining covering portion . A method for manufacturing a solar cell according to claim 1, comprising:
In the step of removing the lift-off layer, the lift-off layer is removed so that a part of the other main surface is covered with the covering portion in a state where the second semiconductor layer covering the lift-off layer is removed. and further,
A method for manufacturing a solar cell, comprising a step of forming an antireflection film on the other main surface after the step of removing the lift-off layer. A method for manufacturing a solar cell according to claim 1 or 2, comprising:
In the step of removing the lift-off layer, in a state where the second semiconductor layer covering the lift-off layer is removed, parts of the surfaces of the first semiconductor layer and the second semiconductor layer are covered with the covering portion. removing the lift-off layer, and
The area of the covering portion that covers a part of the second semiconductor layer is _T1 ,
When the area of the surface of the second semiconductor layer opposite to the semiconductor substrate is _T2 , the T coverage (%) expressed as 100× _T1 / _T2 is 0.2% or more, 16% or less, a method for manufacturing a solar cell. A method for manufacturing a solar cell according to claim 1 or 2 , comprising:
In the step of removing the lift-off layer, the lift-off layer is removed so that a part of the first semiconductor layer is covered with the covering portion in a state where the second semiconductor layer covering the lift-off layer is removed. remove, and
The area of the covering portion covering a part of the first semiconductor layer is _S1 ,
When the area of the surface of the first semiconductor layer opposite to the semiconductor substrate is _S2 , the following formula:
(Coverage rate (%)) = 100 × S ₁ /S ₂
A method for manufacturing a solar cell, wherein the coverage ratio defined by is 0.2% or more and 16% or less. A method for manufacturing a solar cell according to claim 4, comprising:
A method for manufacturing a solar cell, wherein the maximum length of the covering portion is 2.0 μm or less when viewed from the one main surface side in a direction perpendicular to the surface of the semiconductor substrate. A method for manufacturing a solar cell according to claim 1 or 2 , comprising:
In the step of laminating the lift-off layer on the first semiconductor layer,
When the lift-off layer is single, when laminating the lift-off layer,
When the lift-off layer is plural, when stacking the layer closest to the first semiconductor layer,
A method for manufacturing a solar cell, comprising mixing particles of an element constituting the lift-off layer into the lift-off layer. A method for manufacturing a solar cell according to claim 1 or 2 , comprising:
The semiconductor substrate has a first texture structure on each of the two main surfaces,
A method for manufacturing a solar cell, wherein the first semiconductor layer and the second semiconductor layer formed on the one main surface of the semiconductor substrate include a second texture structure reflecting the first texture structure.

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