JP2020096126A - Manufacturing method of back electrode type solar cell - Google Patents

Abstract

To provide a manufacturing method of a back electrode type solar cell in which a lift-off layer is less likely to remain on the surface of a substrate during pattern formation using a lift-off method.SOLUTION: A manufacturing method of a back electrode type solar cell includes a step of forming a lift-off layer pattern 116 on a first surface of a substrate 100, a step of forming a second conductivity type semiconductor layer 114 so as to cover the lift-off layer pattern 116, a step of etching the lift-off layer pattern 116, and a step of removing the lift-off layer pattern 116 remaining on the surface of the substrate 100 by immersing the substrate 100 in a rinse liquid after the step of etching the lift-off layer pattern 116. The immersion of the substrate 100 in the rinse liquid is repeated a plurality of times such that the position of the substrate 100 which first comes into contact with the rinse liquid is a position different from that in the previous immersion.SELECTED DRAWING: Figure 5

Description

The present disclosure relates to a method for manufacturing a back electrode type solar cell.

As a solar cell that does not have a shielding loss due to an electrode, a back electrode type solar cell in which an electrode is arranged only on the back surface has attracted attention.

The back electrode type solar cell needs to accurately form a pattern including a p-type semiconductor layer and an n-type semiconductor layer on the back surface. There is a lift-off method as a method of forming a pattern of a semiconductor layer. The lift-off method is a method in which a lift-off layer that is more easily etched than the semiconductor layer is selectively provided in a lower layer of the semiconductor layer, and the lift-off layer is etched to selectively remove the upper semiconductor layer together with the lift-off layer. It is expected that a highly accurate pattern can be easily formed on the back surface of the solar cell by using the lift-off method (for example, see Patent Document 1).

JP, 2013-120863, A

However, the lift-off layer etched in the lift-off method may remain without being completely detached from the surface of the substrate. Therefore, in the lift-off method, a technique for appropriately detaching the lift-off layer from the surface of the substrate is required.

An object of the present disclosure is to realize a method for manufacturing a back electrode type solar cell in which a lift-off layer is less likely to remain on the surface of a substrate during pattern formation using the lift-off method.

One mode of a method for manufacturing a back electrode type solar cell according to the present disclosure is a step of forming a first conductivity type semiconductor layer on a first surface of a substrate, and a step of forming a lift-off layer on the first conductivity type semiconductor layer. A step of selectively removing the lift-off layer to form a lift-off layer pattern; a step of forming a second conductive type semiconductor layer so as to cover the lift-off layer pattern; a step of etching the lift-off layer pattern; And a step of removing the lift-off layer pattern remaining on the surface of the substrate by immersing the substrate in a rinse liquid after the step of etching the pattern. Repeat multiple times so that the position in contact with is different from the position during the previous immersion.

According to the method of manufacturing a back electrode type solar cell of the present disclosure, it is possible to prevent the lift-off layer from remaining on the substrate surface during pattern formation using the lift-off method.

It is sectional drawing which shows 1 process of the manufacturing method of the back electrode type solar cell which concerns on one Embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the back electrode type solar cell which concerns on one Embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the back electrode type solar cell which concerns on one Embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the back electrode type solar cell which concerns on one Embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the back electrode type solar cell which concerns on one Embodiment. It is a figure which shows the etching process of the lift-off layer pattern in the manufacturing method of the back surface electrode type solar cell which concerns on one Embodiment. It is a figure which shows the rinse process in the manufacturing method of the back electrode type solar cell which concerns on one Embodiment. It is a figure which shows the rinse process in the manufacturing method of the back electrode type solar cell which concerns on one Embodiment. It is a top view which shows the modification of the lift-off layer pattern in the back electrode type solar cell which concerns on one Embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the back electrode type solar cell which concerns on one Embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the back electrode type solar cell which concerns on one Embodiment.

First, as shown in FIG. 1, a substrate 100 having a texture structure TX on each of a first surface 101 and a second surface 102 is prepared.

Next, as shown in FIG. 2, a second-plane intrinsic semiconductor layer 121 made of, for example, i-type amorphous silicon is formed on the second surface 102 of the substrate 100. Subsequently, the low reflection layer 124 is formed on the formed second surface intrinsic semiconductor layer 121. From the viewpoint of light confinement, the low reflective layer 124 may be made of silicon nitride (SiN _x ) or silicon oxide (SiO _x ) having a suitable light absorption coefficient and refractive index. The second-face intrinsic semiconductor layer and the low-reflection layer 124 may be formed as necessary and need not be formed.

Next, as shown in FIG. 3, the first intrinsic semiconductor layer 111 is formed on the first surface 101 of the substrate 100. Then, the first conductivity type semiconductor layer 113 is formed on the formed first intrinsic semiconductor layer 111. The first conductivity type semiconductor layer 113 can be, for example, a p-type semiconductor layer. Note that the first intrinsic semiconductor layer 111 may be provided as necessary and need not be provided. The first intrinsic semiconductor layer 111 can also be formed in the same process as the second-face intrinsic semiconductor layer 121.

Next, the lift-off layer 116a is formed on the first conductivity type semiconductor layer 113. The lift-off layer 116a can be, for example, a layer containing silicon oxide (SiO _x ) as a main component.

Next, as shown in FIG. 4, the lift-off layer 116a, the first conductivity type semiconductor layer 113, and the first intrinsic semiconductor layer 111 are selectively removed. As a result, the lift-off layer 116a is patterned and the lift-off layer pattern 116 is formed. A portion where the lift-off layer 116a, the first conductivity type semiconductor layer 113, and the first intrinsic semiconductor layer 111 are selectively removed becomes an area NA where the lift-off layer pattern 116 does not exist.

Patterning of each layer including the lift-off layer 116a is performed by a photolithography method, for example, a resist film (not shown) having a predetermined pattern is formed on the lift-off layer 116a, and a region masked by the resist film is not dissolved by etching, This can be achieved by melting the unmasked area. The etching can be performed with, for example, a mixed solution of hydrofluoric acid and an oxidizing solution (for example, hydrofluoric nitric acid), a solution of ozone dissolved in hydrofluoric acid (hereinafter, ozone/hydrofluoric acid solution), or the like. The patterning is not limited to wet etching using an etching solution, but may be performed by dry etching or pattern printing using an etching paste or the like.

Although FIG. 4 shows an example in which the first intrinsic semiconductor layer 111 is removed in the region NA, the first intrinsic semiconductor layer 111 may be left. In this case, the second intrinsic semiconductor layer does not have to be formed in a later step.

Next, as shown in FIG. 5, the second intrinsic semiconductor is formed on the entire surface of the first surface 101 including the lift-off layer pattern 116, the first conductivity type semiconductor layer 113 and the first intrinsic semiconductor layer 111. The layer 112 and the second conductivity type semiconductor layer 114 are sequentially formed. The second conductivity type semiconductor layer 114 is a layer having a conductivity type opposite to that of the first conductivity type semiconductor layer 113, and can be, for example, an n-type semiconductor layer. Note that the second intrinsic semiconductor layer 112 may be formed as necessary and need not be formed.

Next, as shown in FIG. 6, the lift-off layer pattern 116 is etched using an etching solution. Although the lift-off layer pattern 116 that has been etched has a portion that is immediately released from the substrate, most of it remains in a state of being attached to the surface of the substrate 100. The lift-off layer pattern 116 can be etched by, for example, wet etching using hydrofluoric acid. Specifically, it can be performed by immersing the substrate 100 in an etching bath 140 filled with the etching solution 141 and pulling it up. The immersion (etching) time of the substrate 100 may be appropriately set according to the shape and material of the lift-off layer pattern 116. However, from the viewpoint of suppressing a decrease in passivation, the etching time is preferably 15 minutes or less, more preferably 10 minutes or less, and preferably 3 minutes or more, more preferably from the viewpoint of sufficiently promoting the etching of the lift-off layer pattern 116. Is more than 5 minutes.

Next, as shown in FIG. 7, a rinsing process is performed to remove the etchant and the lift-off layer remaining on the surface of the substrate 100. The rinsing step can be performed by lowering, immersing, and lifting the etched substrate 100 in the rinsing bath 150 filled with the rinsing liquid 151. By immersing the substrate 100 after etching in the rinse liquid 151, the lift-off layer pattern 116 remaining on the surface of the substrate 100 and the second intrinsic semiconductor layer 112 and the second conductivity type semiconductor layer 114 formed thereon are formed. The first conductivity type semiconductor layer 113 can be exposed by removing the first conductivity type semiconductor layer 113. The portion of the second conductivity type semiconductor layer 114 formed in the region NA where the lift-off layer pattern 116 is not provided remains on the substrate 100.

The immersion of the substrate 100 in the rinse liquid is repeated a plurality of times. When the immersion is repeated, the position of the substrate 100 that first comes into contact with the rinse liquid is set to a position different from the position of the previous immersion. For example, when the thickness direction of the substrate 100 is the z-axis, the substrate 100 may be rotated around the z-axis before the next immersion.

When the lift-off layer pattern 116 after etching remains on the surface of the substrate 100, a part thereof is lifted as shown in FIG. By contacting the rinse liquid 151 from the raised portion 161, the remaining lift-off layer pattern 116 is more easily detached from the substrate 100 than when the rinse liquid 151 is contacted from the non-lifted portion. Since the position of the lifted portion 161 of the lift-off layer pattern 116 is not constant, it is possible that the lifted portion 161 contacts the rinse liquid 151 when the substrate 100 is rotated to contact the rinse liquid 151 from a different position. Can be raised.

The rotation angle of the substrate 100 is not particularly limited, but from the viewpoint of increasing the possibility of contacting the rinse liquid 151 from the raised portion 161, it is preferably ±45° or more with respect to the state in which the immersion is performed once. , More preferably ±90° or more, still more preferably 180°. The positive sign of the angle means clockwise and the negative sign means counterclockwise. When the immersion is repeated three times or more, the part that first comes into contact with the rinse liquid 151 may be different each time, or the same part may come into contact with the rinse liquid 151 first every other or every several times. You can also For example, the substrate 100 can be rotated 180° for immersion for the first time, and the substrate 100 can be rotated 90° for the third time. It is also possible to rotate the third time by 180° and dip in the same direction as the first time.

As shown in FIG. 7, in the lift-off layer pattern 116, the direction in which the trunk pattern 116A extends (first direction) is along the X axis, and the direction in which the plurality of branch patterns 116B are extended (second direction) is along the Y axis. In this case, it is preferable that the substrate 100 is moved along the Y-axis direction in which the branch pattern 116B extends so that the substrate 100 is immersed in the rinse tank 150 and pulled up. By performing the dipping along the Y-axis direction in which the branch pattern 116B extends, the entire end of the trunk pattern 116A extending in the X-axis direction comes into contact with the rinse liquid 151 first, so that the lift-off layer is lifted from the lifted portion 161. There is a high possibility that the pattern 116 will come into contact with the rinse liquid 151. In this case, at the time of the next immersion, it is preferable to rotate the substrate 100 by 180° about the z-axis and move it so that the branch pattern 116B extends in the Y-axis direction again. However, it is sufficient to move the branch pattern 116B along the extending direction for at least one of the repeated immersions, and the moving direction of the substrate 100 may not be along the extending direction of the branch pattern 116B. Although FIGS. 6 and 7 show an example in which the trunk pattern 116A is arranged on the end side of the substrate, the trunk pattern 116A may be arranged on the center side of the substrate.

When the lift-off layer pattern 116 containing silicon oxide as a main component is etched by hydrofluoric acid, hydrogen is generated, and the generated hydrogen causes a portion 161 lifted from the substrate 100 in the lift-off layer pattern 116. Although the line widths of the trunk pattern 116A and the branch patterns 116B are various, the line width of a general trunk pattern is about 1 mm or more and 5 mm or less, which is wider than the line width of the branch pattern of about 500 μm. Therefore, the amount of hydrogen generated in the portion of the trunk pattern 116A is larger than that of the portion of the branch pattern 116B, and the portion 161 lifted from the substrate 100 is likely to occur. For this reason, when the substrate 100 is immersed in the rinse tank 150, it is preferable that the portion of the trunk pattern 116A is immersed in contact with the rinse liquid 151 before the portion of the branch pattern 116B.

For example, when two lift-off layer patterns 116 are provided upside down on the substrate 100 as shown in FIG. 7, a state in which the side close to one of the trunk patterns 116A is faced down is a position of 0°. The state in which the side close to the other trunk pattern 116A is faced down is the position of 180°. In this case, the first immersion lowers the substrate 100 along the extending direction of the branch pattern 116B at the 0° position, and the second immersion at the 180° position along the extending direction of the branch pattern 116B. It is preferable to lower the substrate 100 by using the above method. However, if the first immersion is at 0°, the second immersion can be performed at 90° or 270° by lowering the substrate 100 along the extending direction of the trunk pattern 116A. ..

As shown in FIG. 9, one lift-off layer pattern 116 is provided on the substrate 100, and the trunk pattern 116A is provided along the first side 100A at a position closer to the first side 100A than the branch pattern 116B. In such a case, when the substrate 100 is first immersed in the rinse liquid 151, it is preferable to perform the immersion so that the first side 100A comes into contact with the rinse liquid 151 before the other sides. In this case, the second immersion can be performed by rotating the substrate 100 at an arbitrary angle around the z axis, but it is preferable to rotate it by 180°.

Although the lift-off layer pattern 116 has a shape in which the branch pattern 116B projects from the trunk pattern 116A in only one direction, it may have a shape in which the branch pattern 116B projects in both directions around the trunk pattern 116A. .. Also in this case, it is preferable that the substrate 100 is lowered along the direction in which the branch pattern 116B extends at least once and immersed in the rinse tank 150.

When the substrate 100 is lowered toward the rinse tank 150, the substrate 100 can be made to enter perpendicularly to the liquid surface of the rinse liquid 151, but it may also be made at an angle. From the viewpoint of allowing the substrate 100 to smoothly enter the rinse liquid 151, the angle of the substrate with respect to the liquid surface is preferably 5° or more and 60° or less, and from the viewpoint of equipment design and operability, preferably 15° or more and 45°. It is below.

When the immersion in the rinse solution 151 is repeated, the same rinse solution 151 can be used repeatedly, but from the viewpoint of reducing reattachment of a small piece floating in the rinse solution after lift-off to the substrate 100, It is preferable to use a new rinse solution each time. The rinse liquid 151 is preferably water, more preferably ultrapure water, from the viewpoint of accelerating the detachment of the lift-off layer pattern 116, contamination, and cost.

After the lift-off layer pattern 116 is etched and lift-off is completed by rinsing, as shown in FIG. 10, separation grooves 125 are formed on the first surface 101 of the substrate 100 by, for example, a sputtering method using a mask. The transparent electrode layer 117 (117A, 117B) is formed. The transparent electrode layer 117 may be formed as follows instead of the sputtering method. For example, a transparent conductive oxide film is formed on the entire surface of the first surface 101 without using a mask, and then the first conductive type semiconductor layer 113 and the second conductive type semiconductor layer 114 are formed by photolithography. The transparent conductive oxide film may be formed on the upper surface by etching. By forming the isolation trench 125 that isolates and insulates the first conductive type semiconductor layer 113 and the second conductive type semiconductor layer 114 from each other, it is possible to suppress the occurrence of leakage.

Next, as shown in FIG. 11, a linear metal electrode layer 118 (118A, 118B) is formed on the transparent electrode layer 117 by using, for example, a mesh screen (not shown) having openings. Through the above steps, a back electrode type solar cell can be formed.

The lift-off layer 116a can be a uniform single layer, but can also be a stacked film of two or more kinds of silicon oxide films having different densities. In this case, from the viewpoint of facilitating lift-off, it is preferable that the layer on the side closer to the substrate 100 has a lower density and a higher etching rate.

The film thickness of the lift-off layer 116a is not particularly limited, but is preferably 20 nm or more and 600 nm or less, more preferably 50 nm or more and 450 nm or less. When the lift-off layer is a laminated film, the total film thickness may be set within this range. In this case, it is preferable that the thickest film closest to the substrate 100 be the thinnest.

In the present embodiment, the substrate 100 may be a semiconductor substrate formed of single crystal silicon or a semiconductor substrate formed of polycrystalline silicon. The conductivity type of the substrate 100 may be n-type or p-type. An n-type single crystal substrate is preferable because it has a long carrier life.

The thickness of the substrate 100 can be 250 μm or less. The measurement direction when measuring the thickness is a direction perpendicular to the average surface of the substrate 100 (the average surface means the surface of the entire substrate that does not depend on the texture structure TX).

In addition, in the present embodiment, an example is shown in which both the first surface 101 and the second surface 102 of the substrate 100 have the texture structure TX. By providing the texture structure TX on the first surface 101, the effect of capturing light is improved. When the texture structure TX is provided on the second surface 102, the effect of capturing the received light and the effect of confining the light are enhanced.

In the present embodiment, an example in which the texture structure TX having the same pattern is provided on the first surface 101 and the second surface 102 has been described, but the textures on the first surface 101 and the second surface 102 are textured. The size of the irregularities of the structure TX may be changed. The texture structure TX may be provided only on one of the first surface 101 and the second surface, or the texture structure TX may not be provided.

The texture structure TX can be formed, for example, by anisotropic etching that applies the difference between the etching rate of the (100) plane in the plane orientation and the etching rate of the (111) plane in the plane orientation. The size of the unevenness in the texture structure TX can be defined by the number of vertices, for example. In the present embodiment, although not particularly limited, the number of vertices is preferably in the range of 50,000 pieces/mm ² or more and 100,000 pieces/mm ² or less, and more preferably 70,000 pieces from the viewpoint of light-trapping performance and productivity. /Mm ² or more and 85,000/mm ² or less.

In the present embodiment, an example in which the texture structure reflecting the texture structure TX of the substrate 100 exists also on the surfaces of the first conductivity type semiconductor layer 113 and the second conductivity type semiconductor layer 114 has been shown. When the second conductivity type semiconductor layer 114 has the texture structure TX, when the lift-off layer pattern 116 is lifted off, the recess of the texture structure TX has a small film thickness and cracks easily occur in the film thickness direction. Since the etching solution easily reaches the lift-off layer pattern 116 from here, there is an advantage that the lift-off is facilitated.

In the present embodiment, the second intrinsic semiconductor layer 121, the first intrinsic semiconductor layer 111, and the second intrinsic semiconductor layer 112 perform surface passivation while suppressing diffusion of impurities into the substrate 100. Note that “intrinsic (i-type)” is not limited to complete intrinsicity that does not include conductive impurities, but “weakness” that includes a trace amount of n-type impurities or p-type impurities within a range in which a silicon-based layer can function as an intrinsic layer. Also included are substantially intrinsic layers of "n-type" or "weak p-type".

The material of the second-plane intrinsic semiconductor layer 121, the first intrinsic semiconductor layer 111, and the second intrinsic semiconductor layer 112 is not particularly limited, but may be an amorphous silicon-based thin film, and hydrogenated containing silicon and hydrogen. It may be an amorphous silicon thin film (a-Si:H thin film). The term "amorphous" used herein means a structure having no long-range order. That is, not only completely disordered but also those having a short period of order are included.

The thicknesses of the second-plane intrinsic semiconductor layer 121, the first intrinsic semiconductor layer 111, and the second intrinsic semiconductor layer 112 are not particularly limited, but are preferably 2 nm or more from the viewpoint of the effect as a passivation layer, and have high resistance. The thickness is preferably 20 nm or less from the viewpoint of suppressing the deterioration of conversion characteristics caused by the above.

The method for forming the second-plane intrinsic semiconductor layer 121, the first intrinsic semiconductor layer 111, and the second intrinsic semiconductor layer 112 is not particularly limited, but a plasma chemical vapor deposition (CVD) method can be used. According to this method, it is possible to effectively passivate the substrate surface while suppressing the diffusion of impurities into the single crystal silicon. Further, in the case of the plasma CVD method, by changing the hydrogen concentration in the intrinsic semiconductor layer in the thickness direction, it is possible to form an energy bandgap profile effective for carrier recovery. ..

The conditions for forming a thin film by the plasma CVD method are, for example, a substrate temperature of 100° C. or higher and 300° C. or lower, a pressure of 20 Pa or higher and 2600 Pa or lower, and a high frequency power density of 0.003 W/cm ² or higher, and 0. It can be 5 W/cm ² or less.

In the case of an intrinsic semiconductor layer, raw material gases used for film formation are silicon-containing gases such as monosilane (SiH ₄ ) and disilane (Si ₂ H ₆ ), or those gases and hydrogen (H ₂ ). It can be a mixed gas.

It should be noted that a gas containing a different element such as methane (CH ₄ ), ammonia (NH ₃ ) or monogermane (GeH ₄ ) is added to the above gas to obtain silicon carbide (SiC), silicon nitride (SiN _x ). Alternatively, the energy band gap of the thin film may be changed as appropriate by forming a silicon compound such as silicon germanium (SiGe).

Although the example in which the first conductivity type semiconductor layer 113 is p-type and the second conductivity type semiconductor layer 114 is n-type is shown in the present embodiment, the conductivity types may be opposite.

The film thicknesses of the first conductive type semiconductor layer 113 and the second conductive type semiconductor layer 114 are not particularly limited, but from the viewpoint of the effect as a passivation layer, it is preferably 2 nm or more, and the conversion characteristics deteriorate due to high resistance. From the viewpoint of suppressing the above, the thickness is preferably 20 nm or less.

In the first conductive type semiconductor layer 113 and the second conductive type semiconductor layer 114, the first conductive type semiconductor layer 113 and the second conductive type semiconductor layer 114 are electrically separated via the intrinsic semiconductor layer on the back side of the substrate 100. It is arranged as. The width of the first conductivity type semiconductor layer 113 and the second conductivity type semiconductor layer 114 is preferably 50 μm or more and 3000 μm or less, more preferably 80 μm or more and 1000 μm or less. Note that the widths of the first-conductivity-type semiconductor layer 113 and the second-conductivity-type semiconductor layer 114 are the lengths of a part of each patterned layer unless otherwise specified, and are, for example, linear when patterned. It means the length in the direction orthogonal to the extending direction of a part.

The p-type semiconductor layer is a silicon layer to which a p-type dopant (boron or the like) is added, and is a layer formed of amorphous silicon from the viewpoint of suppressing impurity diffusion or series resistance. You can On the other hand, the n-type semiconductor layer is a silicon layer to which an n-type dopant (phosphorus or the like) is added, and like the p-type semiconductor layer, it may be a layer formed of an amorphous silicon layer. it can.

The first-conductivity-type semiconductor layer 113 and the second-conductivity-type semiconductor layer 114 have a silicon-containing gas such as monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) or a silicon-based gas and hydrogen (H ₂ ) as a source gas. It can be formed by a plasma CVD method using a mixed gas of When forming a p-type semiconductor layer, diborane (B ₂ H ₆ ) or the like may be added as a dopant gas. When forming an n-type semiconductor layer, phosphine (PH ₃ ) or the like may be added as a dopant gas. Further, since the added amount of impurities such as boron (B) or phosphorus (P) may be small, a mixed gas obtained by diluting the dopant gas with the source gas may be used.

Further, in order to adjust the energy band gap as a dopant gas, a gas containing a different element such as methane (CH ₄ ), carbon dioxide (CO ₂ ), ammonia (NH ₃ ) or monogermane (GeH ₄ ) is added. Then, at least one of the first conductivity type semiconductor layer 113 and the second conductivity type semiconductor layer 114 may be alloyed.

The low reflection layer 124 is a layer that suppresses reflection of light received by the solar cell. The low-reflection layer 124 is not particularly limited as long as it is a layer made of a light-transmitting material that transmits light. For example, silicon oxide SiO _x ), silicon nitride (SiN _x ), zinc oxide (ZnO), or titanium oxide. The layer may be made of (TiO _x ) or the like. The low reflection layer 124 can also be formed, for example, by applying a resin material in which nanoparticles of oxide such as zinc oxide or titanium oxide are dispersed.

In the present embodiment, the example in which the low reflection layer 124 is formed before the lift-off process has been shown, but the low reflection layer 124 can be formed after the lift-off process.

The electrode layer 119 is formed on the comb-shaped first conductive type semiconductor layer 113 and the second conductive type semiconductor layer 114 having a trunk pattern and a branch pattern. The portion of the electrode layer 119 formed on the trunk pattern portion is a so-called bus bar portion, and the portion formed on the branch pattern portion is a so-called finger portion.

The line width of the finger portion may be the same as the line width of the branch pattern portions of the first conductivity type semiconductor layer 113 and the second conductivity type semiconductor layer 114. Further, the line width of the finger portion can be made narrower than the line width of the branch pattern portion. In addition, the width of the finger portions can be made wider than the line width of the branch pattern portion as long as the adjacent finger portions can be prevented from being short-circuited.

The electrode layer 119 functions as a transport layer that guides carriers generated in the first conductive type semiconductor layer 113 and the second conductive type semiconductor layer 114. The electrode layer 119 may be formed so as to cover each of the first conductive type semiconductor layer 113 and the second conductive type semiconductor layer 114 so as to be electrically connected to each layer. Note that the electrode layer 119A covering the first conductivity type semiconductor layer 113 and the electrode layer 119B covering the second conductivity type semiconductor layer 114 are arranged apart from each other, so that the first conductivity type semiconductor layer 113 and the second conductivity type A short circuit with the type semiconductor layer 114 is prevented.

In the present embodiment, the electrode layer 119 is a laminated electrode in which the transparent electrode layer 117 made of a transparent conductive oxide and the metal electrode layer 118 are sequentially laminated. By providing the transparent electrode layer 117 between the metal electrode layer 118 and the semiconductor layer, it is possible to prevent the metal element forming the metal electrode layer 118 from diffusing into the first conductive type semiconductor layer 113 and the second conductive type semiconductor layer 114. The suppressing effect is obtained. In addition, the effect of improving the electrical connection can be obtained.

The transparent electrode layer 117 is not particularly limited, but can be formed of, for example, zinc oxide (ZnO) or indium oxide (InO _x ). Further, it is formed of a transparent conductive oxide in which various metal oxides such as titanium oxide (TiO _x ), tin oxide (SnO _x ), tungsten oxide (WO _x ), or molybdenum oxide (MoO _x ) are added to indium oxide. You can also do it. The amount of the metal oxide added to indium oxide is preferably 1% by weight or more and 15% by weight or less.

The thickness of the transparent electrode layer 117 is preferably 20 nm or more and 200 nm or less. As a method for forming the transparent electrode layer 117 having this thickness, for example, a physical vapor deposition (PVD: Physical Vapor Deposition) method such as a sputtering method, or a metal organic chemistry utilizing a reaction between an organic metal compound and oxygen or water. A vapor deposition (MOCVD: Metal-Organic Chemical Vapor Deposition) method etc. are mentioned.

The metal electrode layer 118 is not particularly limited, but can be formed of, for example, silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), or the like.

The thickness of the metal electrode layer 118 is preferably 1 μm or more and 80 μm or less. Examples of the method for forming the metal electrode layer 118 having this thickness include a printing method in which a material paste is printed by inkjet or screen printing, or a plating method. However, the present invention is not limited to this, and a vacuum process such as vapor deposition or sputtering may be adopted.

In the present embodiment, with the structure up to the electrode layer 119 formed, passivation of the bonding surface of each layer, suppression of generation of defect levels in the p-type and n-type semiconductor layers and their interfaces, and the transparent electrode layer 117. Annealing treatment can be performed for the purpose of crystallization of the transparent conductive oxide in FIG.

The annealing treatment can be performed, for example, by placing the substrate 100 on which each layer is formed in an oven preferably at 150° C. or higher and 200° C. or lower. In this case, the inside of the oven may be in an air atmosphere. Further, from the viewpoint of performing a more effective annealing treatment, a hydrogen or nitrogen atmosphere may be used. Further, the annealing treatment can also be performed by RTA (Rapid Thermal Annealing) or the like in which the substrate 100 on which each layer is formed is irradiated with infrared rays by an infrared heater.

Hereinafter, the invention of the present disclosure will be described in more detail with reference to Examples. The following examples are illustrative and are not intended to limit the invention of the present disclosure thereto.

<Calculation of amount of residue>
The amount of the residue was calculated by obtaining an image of the entire cell in which the lift-off layer pattern 116 was lifted off by etching and rinsing with a scanner and binarized the image. The amount of the residue was 0% when the lift-off layer was completely removed, and 100% when the lift-off layer pattern 116 was completely left without the lift-off.

<Measurement of electrical characteristics>
Using a solar simulator having a spectral distribution of AM1.5, the obtained back electrode type solar cell was irradiated with pseudo sunlight at an energy density of 100 mW/cm ² at 25° C. to open circuit voltage V _OC (Voltage Open Circuit), short-circuit current _JSC (Short Circuit Current), fill factor (FF), and photoelectric conversion efficiency were measured. Each measured value was standardized with the measured value of the back electrode type solar cell of Example 1 being 1.00.

<Manufacture of back electrode type solar cell>
First, a single crystal silicon substrate having a thickness of 200 μm was adopted as the substrate. Anisotropic etching was performed on the first surface and the second surface of the single crystal silicon substrate to form a pyramid type texture structure on the substrate.

The substrate was introduced into a CVD apparatus, and an intrinsic semiconductor layer (film thickness 8 nm) made of silicon was formed on the first surface and the second surface of the introduced substrate. The film forming conditions were a substrate temperature of 150° C., a pressure of 120 Pa, a SiH ₄ /H ₂ flow ratio value of 3/10, and a power density of 0.011 W/cm ² .

A first conductivity type semiconductor layer made of a p-type hydrogenated amorphous silicon thin film (film thickness 10 nm) was formed on the intrinsic semiconductor layer on the first surface by using a CVD device. The film forming conditions were a substrate temperature of 150° C., a pressure of 60 Pa, a SiH ₄ /B ₂ H ₆ flow rate ratio value of 1/3, and a power density of 0.01 W/cm 2. The flow rate of B ₂ H ₆ gas is the flow rate of the diluent gas B ₂ H ₆ was diluted by H ₂ to 5000 ppm.

A lift-off layer containing silicon oxide (SiO _x ) as a main component was formed on the first conductivity type semiconductor layer using a plasma CVD apparatus. The film thickness of the lift-off layer was 400 nm.

A photosensitive resist film was formed on the first surface on which the lift-off layer was formed. This was exposed and developed by a photolithography method to expose a region where the lift-off layer, the first conductivity type semiconductor layer and the intrinsic semiconductor layer were removed. Next, the substrate is immersed in ozone/hydrofluoric acid in which 7 wt% of hydrogen fluoride is mixed with 40 ppm of ozone, and lift-off is performed by selectively removing the lift-off layer, the first conductivity type semiconductor layer and the intrinsic semiconductor layer. A layer pattern was formed.

Next, after cleaning the exposed first surface with hydrofluoric acid having a concentration of 2% by weight, the substrate is introduced into a CVD apparatus, and an intrinsic semiconductor layer (film thickness 8 nm) is formed on the second surface for the first time. The film was formed under the same film forming conditions as the intrinsic semiconductor layer. Subsequently, a second conductivity type semiconductor layer made of an n-type hydrogenated amorphous silicon thin film (film thickness 10 nm) was formed on the formed intrinsic semiconductor layer. The film forming conditions were a substrate temperature of 150° C., a pressure of 60 Pa, a SiH ₄ /PH ₃ /H ₂ flow ratio value of 1/2, and a power density of 0.01 W/cm ² . The flow rate of the PH ₃ gas is the flow rate of the diluent gas PH ₃ is diluted by H ₂ to 5000 ppm.

The lift-off layer pattern was etched by immersing the substrate on which the second conductivity type semiconductor layer was formed in an etching bath under predetermined conditions. Next, a rinse process was performed on the substrate on which the lift-off layer pattern was etched under predetermined conditions.

Next, a silicon nitride layer was formed on the second surface of the substrate as a low reflection layer. Then, using a magnetron sputtering device, an oxide film (film thickness 80 nm) to be a transparent electrode layer was formed on the first conductive type semiconductor layer and the second conductive type semiconductor layer of the substrate. As the transparent conductive oxide, indium oxide (ITO) containing tin oxide at a concentration of 10% by weight was used as a target. A mixed gas of argon and oxygen was introduced into the chamber of the apparatus, and the pressure inside the chamber was set to 0.3 Pa. The mixing ratio of argon and oxygen was set so that the resistivity was the lowest (so-called bottom). A DC power supply was used to form a film at a power density of 0.4 W/cm ² .

Next, the transparent conductive oxide film extending over the first conductive type semiconductor layer and the second conductive type semiconductor layer was selectively etched by photolithography to form a transparent electrode layer. The transparent electrode layer formed by this etching prevented conduction between the transparent conductive oxide film on the p-type semiconductor layer and the transparent conductive oxide film on the n-type semiconductor layer.

Next, a silver paste was screen-printed on the transparent electrode layer, and heat treatment was performed for 60 minutes in an oven at a temperature of 180° C. to form a metal electrode layer.

(Example 1)
The etching solution for etching the lift-off layer pattern was 7 wt% hydrofluoric acid, and the immersion time in the etching solution was 10 minutes.

The rinse step after etching the lift-off layer pattern was performed by successively immersing the substrate in a first rinse tank and a second rinse tank filled with a rinse liquid made of ultrapure water. When the substrate is dipped in the first rinse tank, the substrate is placed at a position where one side near the trunk pattern is downward (hereinafter, this arrangement is referred to as a 0° position), and the branch pattern extends in the extending direction. By lowering the substrate along, the side near one of the trunk patterns first comes into contact with the rinse liquid. After dipping for 10 seconds, the substrate was pulled up, and the substrate was rotated 180° with respect to the original position around the z axis (hereinafter, this position is referred to as a 180° position). Subsequently, the substrate was lowered along the extending direction of the branch pattern and immersed in the second rinse bath. After dipping for 10 seconds, the substrate was pulled up and the amount of residue was measured.

The amount of residue after pulling up from the second rinse tank was 4%. In addition, V _OC , J _SC , FF and photoelectric conversion efficiency after forming the electrode were good.

(Example 2)
After the substrate was pulled up from the first rinse tank, the substrate was rotated 90° to the position of 90°, lowered along the extending direction of the trunk pattern, and immersed in the second rinse tank. I did the same.

The amount of residue after pulling up from the second rinse tank was 10%. Further, the standardized V _OC and the standardized J _{SC based} on the back electrode type solar cell of Example 1 are both 1.00, and the standardized FF and the standardized photoelectric conversion efficiency are both 0.98. It was

(Example 3)
After pulling the substrate out of the second rinse tank, the substrate is rotated by −90° to the position of 90°, lowered along the extending direction of the trunk pattern, and immersed in the third rinse tank to make the substrate Same as Example 1 except that the substrate was rotated 180° to a position of 270° after being pulled up from the rinse tank of No. 3, lowered along the extending direction of the trunk pattern, and immersed in the fourth rinse tank. I chose

The amount of residue after pulling up from the fourth rinse tank was 0%. Further, the normalized V _OC and the normalized J _{SC based} on the back electrode type solar cell of Example 1 were 1.00, and the normalized FF and the normalized photoelectric conversion efficiency were all 1.01.
(Example 4)
Example 1 except that after the substrate was pulled out of the first rinse tank, the substrate was rotated by 180° to the position of 180°, lowered along the direction in which the branch pattern extends, and immersed again in the first rinse tank. Same as.

The amount of residue after dipping the substrate in the first rinse tank at a position of 180° and then withdrawing it was 9%. Further, the standardized V _OC and the standardized I _SC of the back electrode type solar cell of Example 1 were both 1.00, and the standardized FF and the standardized photoelectric conversion efficiency were both 0.98. It was

(Example 5)
As shown in FIG. 9, the lift-off layer pattern has a shape in which the trunk pattern is provided only near one side of the substrate, and when the lift-off layer pattern is immersed in the first rinse bath, the first side near the trunk pattern is formed. Example 1 was performed in the same manner as in Example 1 except that the substrate was placed so that 100A first came into contact with the rinse liquid and this position was set at a position of 0°.

The amount of residue after pulling up from the second rinse tank was 4%. Further, the normalized V _OC , the normalized J _SC , the normalized FF, and the photoelectric conversion efficiency based on the back electrode type solar cell of Example 1 were all 1.00.

(Example 6)
When immersed in the first rinse tank, the substrate was lowered so that the side adjacent to the first side 100A first comes into contact with the rinse liquid at a position of 90°, and the substrate was pulled up from the second rinse tank. Thereafter, the same procedure as in Example 5 was performed, except that the substrate was rotated 180° to the position of 270° and then immersed in the second rinse tank.

The amount of residue after being pulled out from the second rinse tank was 13%. Further, the standardized V _OC and the standardized J _{SC based} on the back electrode type solar cell of Example 1 are both 1.00, and the standardized FF and the standardized photoelectric conversion efficiency are both 0.97. It was

(Comparative Example 1)
The rinse after etching the lift-off layer pattern was performed in the same manner as in Example 1 except that immersion in the second rinse tank was not performed.

The amount of residue after being pulled out from the first rinse tank was 20%. Further, the normalized V _OC and the normalized J _SC of the back electrode type solar cell of Example 1 were both 1.00, and the normalized FF and the normalized photoelectric conversion efficiency were both 0.95. It was

(Comparative example 2)
In the rinse after etching the lift-off layer pattern, when the substrate was immersed in the first rinse bath, the position of the substrate was set at 90° and the substrate was lowered along the extending direction of the trunk pattern. Same as 1.

The amount of residue after being pulled out from the first rinse tank was 23%. Further, the standardized V _OC and the standardized J _{SC based} on the back electrode type solar cell of Example 1 are both 1.00, and the standardized FF and the standardized photoelectric conversion efficiency are both 0.94. It was

(Comparative example 3)
Before immersing the substrate in the second rinse tank, the same procedure was performed as in Example 1 except that the substrate was not rotated and the substrate was immersed in the second rinse tank while the substrate was kept at 0°.

The amount of residue after being pulled out from the second rinse tank was 15%. Further, the normalized V _OC and the normalized J _SC of the back electrode type solar cell of Example 1 are both 1.00, and the normalized FF and the normalized photoelectric conversion efficiency are both 0.96. It was

(Comparative example 4)
The procedure of Comparative Example 3 was repeated, except that the immersion time for etching the lift-off layer pattern was 20 minutes.

The amount of residue after being pulled out from the second rinse tank was 13%. Further, the normalized V _{OC based} on the back electrode type solar cell of Example 1 is 0.95, the normalized J _SC is 1.00, the normalized FF is 0.93, and the normalized photoelectric conversion efficiency is 0.88. Yes, there was a decrease in passivation.

(Comparative example 5)
The procedure of Comparative Example 3 was repeated, except that the immersion time for etching the lift-off layer pattern was 30 minutes.

The amount of residue after pulling up from the second rinse tank was 11%. Further, the normalized V _{OC based} on the back electrode type solar cell of Example 1 is 0.90, the normalized J _SC is 1.00, the normalized FF is 0.90, and the normalized photoelectric conversion efficiency is 0.81. Yes, there was a decrease in passivation.

Table 1 collectively shows the conditions and results of each Example and Comparative Example.

100 substrate 100A first side 101 first surface 102 second surface 111 first intrinsic semiconductor layer 112 second intrinsic semiconductor layer 113 first conductivity type semiconductor layer 114 second conductivity type semiconductor layer 116 lift-off layer pattern 116A trunk pattern 116B Branch pattern 116a Lift-off layer 117 Transparent electrode layer 118 Metal electrode layer 119 Electrode layer 119A Electrode layer 119B Electrode layer 121 Second surface intrinsic semiconductor layer 124 Low reflection layer 125 Separation groove 140 Etching tank 141 Etching solution 150 Rinsing tank 151 Rinsing solution 161 The raised part

Claims (6)

Forming a first conductivity type semiconductor layer on the first surface of the substrate;
Forming a lift-off layer on the first conductivity type semiconductor layer;
Forming a lift-off layer pattern by selectively removing the lift-off layer;
Forming a second conductive type semiconductor layer so as to cover the lift-off layer pattern;
Etching the lift-off layer pattern,
After the step of etching the lift-off layer pattern, the step of immersing the substrate in a rinse liquid to remove the lift-off layer pattern remaining on the surface of the substrate,
Immersion of the substrate in the rinse liquid is repeated a plurality of times so that the position of the substrate in contact with the rinse liquid at the beginning is different from the position at the time of the previous immersion, a method for manufacturing a back electrode type solar cell. .. The method for manufacturing a back electrode type solar cell according to claim 1, wherein a new rinse liquid is used every time the substrate is repeatedly immersed in the rinse liquid. The method for manufacturing a back electrode type solar cell according to claim 1 or 2, wherein when the substrate is repeatedly immersed in the rinse liquid, the substrate is rotated 180° for immersion at least once. The lift-off layer pattern has a trunk pattern extending in a first direction, and a plurality of branch patterns extending in a second direction intersecting the first direction,
The back electrode according to any one of claims 1 to 3, wherein when the substrate is repeatedly immersed in the rinse liquid, the substrate is moved along the second direction at least once for immersion. Type solar cell manufacturing method. The method of manufacturing a back electrode type solar cell according to claim 4, wherein the line width of the branch pattern is smaller than the line width of the trunk pattern. The trunk pattern is formed along the first side at a position closer to the first side of the substrate than the branch pattern,
The back electrode type solar cell according to claim 4 or 5, wherein the first immersion of the substrate in the rinse liquid is performed so that the first side comes into contact with the rinse liquid before other sides. Method.

Images