JP7361045B2 - How to manufacture solar cells - Google Patents

Description

The present invention relates to a method for manufacturing a solar cell.

A typical solar cell is a double-sided electrode type in which electrodes are placed on both sides (light-receiving surface and back surface) of a semiconductor substrate. BACKGROUND ART Recently, as a solar cell without shielding loss due to electrodes, a back contact (back electrode) type solar cell in which an electrode is disposed only on the back surface, as shown in Patent Document 1, has been developed.

Back-contact type solar cells require semiconductor layer patterns such as a p-type semiconductor layer and an n-type semiconductor layer to be formed on the back surface with high precision, and the manufacturing method is more complicated than that of double-sided electrode type solar cells. As a technique for simplifying the manufacturing method, there is a technique for forming a semiconductor layer pattern using a lift-off method, as shown in Patent Document 1. That is, progress is being made in developing patterning techniques for forming a semiconductor layer pattern by removing a lift-off layer and removing a semiconductor layer formed on the lift-off layer.

Japanese Patent Application Publication No. 2013-120863

However, in the method described in Patent Document 1, if the lift-off layer and the semiconductor layer have similar solubility, unintended layers may be removed, and patterning accuracy or productivity may not be high. be.

Additionally, the solvent used for the etching or lift-off layer may limit the layer configuration or structure design. For example, it is the order in which p-type semiconductor layers and n-type semiconductor layers are formed, or the thickness or width of each semiconductor layer.

Further, in the method described in Patent Document 1, a lift-off layer is formed after patterning a semiconductor layer using photolithography and etching, and the lift-off layer is further patterned using photolithography and etching. Therefore, it is necessary to form a resist layer or the like for each patterning process, which complicates the process, resulting in an increase in manufacturing time and cost.

An object of the present invention is to provide a method for manufacturing a solar cell that can efficiently manufacture a back-contact type solar cell with higher performance than conventional methods.

One aspect of the present invention includes a first semiconductor layer forming step of forming a first semiconductor layer of a first conductivity type on a first main surface side of a semiconductor substrate, and a lift-off step of laminating a lift-off layer on the first semiconductor layer. a layer stacking step; a patterning step of selectively removing the first semiconductor layer and the lift-off layer by etching; and a step of removing the first semiconductor layer from the portions of the first semiconductor layer and the lift-off layer removed in the patterning step. and a second semiconductor layer forming step of forming a second semiconductor layer of a second conductivity type on the first main surface side so as to straddle the laminated portion of the lift-off layer, and removing the lift-off layer. a lift-off step of removing the second semiconductor layer covering the second semiconductor layer, and in the patterning step, the etching area of the first semiconductor layer is The first semiconductor layer and the lift-off layer are removed using two or more types of etching solutions so that the etching area is equal to or less than the etching area of the lift-off layer. This is a method for manufacturing batteries.

The "type" of the etching solution used herein includes not only its properties and form but also its concentration. That is, "two or more types of etching solutions" refers to two or more types of etching solutions that differ in at least one of properties, forms, and concentrations.

One aspect of the present invention is that a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first electrode layer, and a second electrode layer are provided on the first main surface side of a semiconductor substrate. , the first semiconductor layer is interposed between the semiconductor substrate and the first electrode layer, and the second semiconductor layer is further interposed between the semiconductor substrate and the second electrode layer. a first semiconductor layer forming step of forming the first semiconductor layer on the first main surface side of the semiconductor substrate; a lift-off layer laminating step of laminating a lift-off layer on the first semiconductor layer; using two or more types of etching solutions having different etching rates, the etching area of the first semiconductor layer becomes equal to or less than the etching area of the lift-off layer when viewed from the first main surface side in a direction perpendicular to the surface of the semiconductor substrate. The method of manufacturing a solar cell includes a patterning step of removing a portion of each of the first semiconductor layer and the lift-off layer, and the lift-off layer contains metal as a main component.

One aspect of the present invention is a step of forming a first semiconductor layer of a first conductivity type on one of two main surfaces facing each other in a semiconductor substrate, and on the first semiconductor layer, a step of laminating a lift-off layer containing metal as a main component; a step of selectively removing the first semiconductor layer and the lift-off layer by etching; and one main surface including the first semiconductor layer and the lift-off layer. The method further includes forming a second semiconductor layer of a second conductivity type, and removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer. In the step of selectively removing the first semiconductor layer and the lift-off layer, the etching area of the first semiconductor layer is equal to The method of manufacturing a solar cell includes removing the first semiconductor layer and the lift-off layer by wet etching using two or more different etching solutions so that the etching area of the layer is equal to or less than the etching area of the layer.

According to the present invention, a back-contact solar cell with higher performance than conventional solar cells can be manufactured efficiently.

FIG. 1 is a schematic cross-sectional view partially showing a solar cell according to an exemplary embodiment of the present invention. FIG. 2 is a plan view showing the back main surface of a crystal substrate constituting the solar cell of FIG. 1. FIG. FIG. 2 is an exploded perspective view of essential parts of the solar cell in FIG. 1, and is an exploded view of an electrode layer from the solar cell. Note that for ease of understanding, the texture structure is omitted from the drawing. FIG. 2 is a partial schematic cross-sectional view showing a state after a crystal substrate preparation step, which is one step of the method for manufacturing the solar cell of FIG. 1. FIG. FIG. 2 is a partial schematic cross-sectional view showing a state after a front side semiconductor layer forming step, which is one step of the method for manufacturing the solar cell of FIG. 1; FIG. 2 is a partial schematic cross-sectional view showing a state after a lift-off layer lamination step, which is one step of the method for manufacturing the solar cell of FIG. 1. FIG. FIG. 2 is a partial schematic cross-sectional view showing a state after a lift-off layer removal step, which is one step of the method for manufacturing the solar cell of FIG. 1. FIG. FIG. 2 is a partial schematic cross-sectional view showing a state after a first semiconductor layer removal step, which is one step of the method for manufacturing the solar cell of FIG. 1; FIG. 2 is a partial schematic cross-sectional view showing a state after an n-side semiconductor layer forming step, which is one step of the method for manufacturing the solar cell of FIG. 1. FIG. FIG. 2 is a partial schematic cross-sectional view showing a state after a lift-off step, which is one step of the method for manufacturing the solar cell of FIG. 1. FIG. FIG. 2 is a partial schematic cross-sectional view showing a state after an electrode layer forming step, which is one step of the method for manufacturing the solar cell of FIG. 1. FIG. FIG. 9 is a plan view of the state at the end of the process in FIG. 8 as viewed from the back main surface side in the direction perpendicular to the surface of the crystal substrate. FIG. 2 is a partial schematic cross-sectional view showing each step of the solar cell manufacturing method of the present embodiment, (a) is a cross-sectional perspective view schematically showing the state after the first semiconductor layer removal step, and (b) ) is a cross-sectional perspective view schematically showing the state after the n-side semiconductor layer forming process, and (c) is a cross-sectional perspective view schematically showing the state after the lift-off process. Note that in order to facilitate understanding, the texture structure is omitted in each figure. It is an explanatory diagram when a lift-off layer is not removed in the first semiconductor layer removal process, (a) is a cross-sectional view schematically showing the state after the first semiconductor layer removal process, and (b) is a cross-sectional view schematically showing the state after the first semiconductor layer removal process. FIG. 4 is a cross-sectional view schematically showing the state after the side semiconductor layer forming process, and FIG. 10(c) is a cross-sectional view schematically showing the state after the lift-off process. It is an explanatory view when the thickness of the lift-off layer is thick in the first semiconductor layer removal step, (a) is a cross-sectional view schematically showing the state after the first semiconductor layer removal step, and (b) is a cross-sectional view on the n side. FIG. 4 is a cross-sectional view schematically showing the state after the semiconductor layer forming process, and FIG. 10(c) is a cross-sectional view schematically showing the state after the lift-off process. FIG. 10 is a schematic cross-sectional view showing a state after the n-side semiconductor layer forming step, which corresponds to FIG. 9 and shows a modification of the present embodiment. FIG. 11 is a schematic cross-sectional view showing a state after a lift-off process corresponding to FIG. 10 showing a modification of the present embodiment.

An embodiment of the present invention will be described as follows, but it is not limited thereto. Note that, for convenience, hatching, member symbols, etc. may be omitted, but in such cases, other drawings will be referred to. Further, the dimensions of various members in the drawings have been adjusted for convenience and ease of viewing.

As shown in FIG. 1, the solar cell 10 uses a crystal substrate 11 made of silicon (Si). The crystal substrate 11 has two main surfaces 11S (11SU, 11SB) facing each other.
Here, the main surface on which light is incident is called a front main surface 11SU, and the main surface opposite to this is called a back main surface 11SB. For convenience, the front side main surface 11SU is a side that actively receives light more than the back side main surface 11SB, so it is referred to as a light receiving side, and the side that does not actively receive light is referred to as a non-light receiving side.

The solar cell 10 is a so-called heterojunction crystalline silicon solar cell, and as shown in FIG. (electrode type) solar cell.

The solar cell 10 includes a crystal substrate 11, an intrinsic semiconductor layer 12, a conductive semiconductor layer 13 (p-type semiconductor layer 13p, n-type semiconductor layer 13n), a low reflection layer 14, and an electrode layer 15 (transparent electrode layer 17, metal electrode layer 18).

Hereinafter, for convenience, members that individually correspond to the p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be appended with "p" or "n" at the end of their reference numerals. Furthermore, since the conductivity types are different, such as p-type and n-type, one conductivity type is sometimes referred to as a "first conductivity type" and the other conductivity type is sometimes referred to as a "second conductivity type."

In the solar cell 10 of this embodiment, as shown in FIG. 1, an intrinsic semiconductor layer 12U and a low reflection layer 14 are laminated in this order on a front side main surface 11SU (second main surface) of a crystal substrate 11 (semiconductor substrate). There is.
In the solar cell 10, an intrinsic semiconductor layer 12p, a p-type semiconductor layer 13p, and a first electrode layer 15p are stacked in this order on a part of the back main surface 11SB (first main surface) of the crystal substrate 11. In the solar cell 10, an intrinsic semiconductor layer 12n, an n-type semiconductor layer 13n, and a second electrode layer 15n are stacked in this order on the other part of the back main surface 11SB of the crystal substrate 11.
Further, in the solar cell 10, a part of the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n overlap with a part of the p-type semiconductor layer 13p, and in the overlapped part, the p-type semiconductor layer 13p and the n-type An intrinsic semiconductor layer 12n is interposed between the semiconductor layers 13n.

The crystal substrate 11 may be a semiconductor substrate made of single crystal silicon or a semiconductor substrate made of polycrystalline silicon. In the following, description will be made using a single crystal silicon substrate as an example.

The conductivity type of the crystal substrate 11 may be an n-type single crystal silicon substrate into which impurities (for example, phosphorus (P) atoms) that introduce electrons into silicon atoms are introduced. Further, the conductivity type of the crystal substrate 11 may be a p-type single crystal silicon substrate into which an impurity (for example, boron (B) atoms) that introduces holes into silicon atoms is introduced. In the following, an n-type single crystal substrate, which is said to have a long carrier life, will be described as an example.

From the viewpoint of confining the received light, the crystal substrate 11 has a texture structure TX (first texture structure) composed of peaks (convex) and valleys (concave) on the surfaces of the two main surfaces 11S. You may do so. Note that the texture structure TX (uneven surface) is formed by, for example, anisotropic etching that applies the difference between the etching rate of the (100) plane of the crystal substrate 11 and the etching rate of the (111) plane of the crystal substrate 11. It is formed.

The thickness of the crystal substrate 11 may be 250 μm or less.
Note that the measurement direction when measuring the thickness is a direction perpendicular to the average plane of the crystal substrate 11 (the average plane means the plane of the entire substrate that does not depend on the texture structure TX). Hereinafter, this vertical direction, that is, the direction in which the thickness is measured, will be referred to as the perpendicular direction.

The size of the unevenness in the texture structure TX can be defined, for example, by the number of vertices. In this embodiment, from the viewpoint of light intake performance and productivity, the number of vertices is preferably in the range of 50,000 pieces/ ^mm2 or more and 100,000 pieces/ ^mm2 or less, particularly 70,000 pieces/ ^mm2 or more. It is preferable that the number is 85,000 pieces/mm ² or less.

Note that when the thickness of the crystal substrate 11 is set to 250 μm or less, the amount of silicon used can be reduced, making it easier to secure silicon substrates and reducing costs. Furthermore, a back contact structure in which holes and electrons generated by photoexcitation within the silicon substrate are collected only on the back surface side is preferable from the viewpoint of the free path of each exciton.

On the other hand, if the thickness of the crystal substrate 11 is too small, the mechanical strength will be reduced, external light (sunlight) will not be absorbed sufficiently, and the short circuit current density will decrease. Therefore, the thickness of the crystal substrate 11 is preferably 50 μm or more, more preferably 70 μm or more.
When the texture structure TX is formed on the main surface of the crystal substrate 11, the thickness of the crystal substrate 11 is expressed as the distance between the straight lines connecting the vertices of the convexities in the concavo-convex structures on the light-receiving side and the back side. be done.

The intrinsic semiconductor layer 12 (12U, 12p, 12n) covers both main surfaces 11S (11SU, 11SB) of the crystal substrate 11, thereby suppressing diffusion of impurities into the crystal substrate 11 and performing surface passivation.
Note that "intrinsic (i-type)" is not limited to completely intrinsic, which does not contain conductive impurities, but also "weak", which contains a trace amount of n-type or p-type impurity to the extent that the silicon-based layer can function as an intrinsic layer. It also includes substantially intrinsic layers of "n-type" or "weak-p-type."

Note that the intrinsic semiconductor layers 12 (12U, 12p, 12n) are not essential and may be formed as appropriate, if necessary.

The material of the intrinsic semiconductor layer 12 is not particularly limited, but may be an amorphous silicon-based thin film, or a hydrogenated amorphous silicon-based thin film containing silicon and hydrogen (a-Si:H thin film). Good too. Note that the term "amorphous" here means a structure with a long period and no order. In other words, it includes not only completely disordered objects but also those that have short-period order.

The thickness of the intrinsic semiconductor layer 12 is not particularly limited, but may be 2 nm or more and 20 nm or less. This is because when the thickness is 2 nm or more, the effect as a passivation layer is enhanced, and when the thickness is 20 nm or less, deterioration in conversion characteristics caused by high resistance can be suppressed.

The method for forming the intrinsic semiconductor layer 12 is not particularly limited, but a plasma enhanced chemical vapor deposition (CVD) method is used. According to this method, the substrate surface can be effectively passivated while suppressing the diffusion of impurities into single crystal silicon. Furthermore, with the plasma CVD method, by changing the hydrogen concentration in the intrinsic semiconductor layer 12 in the thickness direction, it is possible to form an energy gap profile that is effective for carrier recovery.

The conditions for forming a thin film by the plasma CVD method include, for example, a substrate temperature of 100° C. or more and 300° C. or less, a pressure of 20 Pa or more and 2,600 Pa or less, and a high frequency power density of 0.003 W/cm 2 or more and 0.5 W/cm ² or more. It may be less than ^cm2 .

In addition, in the case of the intrinsic semiconductor layer 12, the raw material gas used for forming the thin film is silicon-containing gas such as monosilane (SiH ₄ ) and disilane (Si ₂ H ₆ ), or these gases and hydrogen (H ₂ ) may also be used.

Note that by adding a gas containing a different element such as methane (CH ₄ ), ammonia (NH ₃ ), or monogermane (GeH ₄ ) to the above gas, silicon carbide (SiC), silicon nitride ( _SiN ) or a silicon compound such as silicon germanium (SiGe), the energy gap of the thin film may be changed as appropriate.

Examples of the conductive semiconductor layer 13 include a p-type semiconductor layer 13p and an n-type semiconductor layer 13n. As shown in FIG. 1, the p-type semiconductor layer 13p is formed on a part of the back main surface 11SB of the crystal substrate 11 via the intrinsic semiconductor layer 12p. The n-type semiconductor layer 13n is formed on the other part of the back main surface 11SB of the crystal substrate 11 via the intrinsic semiconductor layer 12n. That is, between the p-type semiconductor layer 13p and the crystal substrate 11, and between the n-type semiconductor layer 13n and the crystal substrate 11, the intrinsic semiconductor layers 12 (12p and 12n) are provided as intermediate layers that play the role of passivation. intervene.

The thicknesses of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are not particularly limited, but may be 2 nm or more and 20 nm or less. This is because when the thickness is 2 nm or more, the effect as a passivation layer is enhanced, and when the thickness is 20 nm or less, deterioration in conversion characteristics caused by high resistance can be suppressed.

The p-type semiconductor layer 13p and the n-type semiconductor layer 13n are arranged on the back side of the crystal substrate 11 so as to be electrically separated via the intrinsic semiconductor layer 12. The width of the conductive semiconductor layer 13 may be 50 μm or more and 3000 μm or less, or 80 μm or more and 500 μm or less.

Note that the widths of the semiconductor layers 12 and 13 and the widths of the electrode layers 17 and 18 are, unless otherwise specified, the length of a portion of each patterned layer. It means the length in the direction perpendicular to the extending direction.

In the solar cell 10, a part of the intrinsic semiconductor layer 12n and a part of the n-type semiconductor layer 13n are formed on the p-type semiconductor layer 13p. The portions of the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n that are formed on the p-type semiconductor layer 13p are formed so that their edges in the width direction are substantially flush with each other.

By the way, when photoexciton (carriers) generated within the crystal substrate 11 are taken out via the conductive semiconductor layer 13, the effective mass of holes is larger than that of electrons. Therefore, from the viewpoint of reducing transport loss, the p-type semiconductor layer 13p may be narrower than the n-type semiconductor layer 13n. For example, the width of the p-type semiconductor layer 13p may be 0.5 times or more and 0.9 times or less, or 0.6 times or more and 0.8 times or less, the width of the n-type semiconductor layer 13n. Good too.

The p-type semiconductor layer 13p is a silicon layer doped with a p-type dopant (such as boron), and may be formed of amorphous silicon from the viewpoint of suppressing impurity diffusion or series resistance. On the other hand, the n-type semiconductor layer 13n is a silicon layer doped with an n-type dopant (such as phosphorus), and may be formed of an amorphous silicon layer similarly to the p-type semiconductor layer 13p.
As the raw material gas for the conductive semiconductor layer 13, a silicon-containing gas such as monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ), or a mixed gas of a silicon-based gas and hydrogen (H ₂ ) may be used.

Note that, as the dopant gas, diborane (B ₂ H ₆ ) or the like is used to form the p-type semiconductor layer 13p, and phosphine (PH ₃ ) or the like is used to form the n-type semiconductor layer. Further, since the amount of impurities such as boron (B) or phosphorus (P) added may be small, a mixed gas in which the dopant gas is diluted with the source gas may be used.

In order to adjust the energy gap of the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, a different material such as methane (CH ₄ ), carbon dioxide (CO ₂ ), ammonia (NH ₃ ), or monogermane (GeH ₄ ) may be used. The p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be alloyed by adding a gas containing the element.

The p-type semiconductor layer 13p and the n-type semiconductor layer 13n each have a comb shape when the crystal substrate 11 is viewed from the back main surface 11SB side, as shown in FIG. That is, the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are connected to the bus bar base portions 30 (30p, 30n) (base comb back portion) extending in a predetermined direction when the crystal substrate 11 is viewed from the back side main surface 11SB side. , a plurality of finger base portions 31 (31p, 31n) (base comb tooth portions) extending from the bus bar base portion 30 in a direction intersecting the extending direction of the bus bar base portion 30.
The n-type semiconductor layer 13n covers a part of the p-type semiconductor layer 13p, and overlaps with a part of the p-type semiconductor layer 13p when the crystal substrate 11 is viewed from the back main surface 11SB side.

The low reflection layer 14 is a layer that suppresses reflection of light received by the solar cell 10. The material of the low reflection layer 14 is not particularly limited as long as it is a transparent material that transmits light, and examples thereof include silicon oxide (SiO _x ), silicon nitride (SiN _x ), zinc oxide (ZnO), and oxide. Titanium ( _TiOx ) is mentioned. Further, as a method for forming the low reflection layer 14, for example, a resin material in which nanoparticles of an oxide such as zinc oxide or titanium oxide are dispersed may be applied.

The electrode layer 15 is formed to cover the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, respectively, and is electrically connected to each conductive type semiconductor layer 13. Thereby, the electrode layer 15 functions as a transport layer that guides carriers generated in the p-type semiconductor layer 13p or the n-type semiconductor layer 13n.
Note that the electrode layers 15p and 15n corresponding to the semiconductor layers 13p and 13n are arranged apart from each other to prevent short circuit between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n.

The electrode layer 15 may be formed only of highly conductive metal.
From the viewpoint of electrical bonding with the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, or from the viewpoint of suppressing the diffusion of atoms into both the metal semiconductor layers 13p and 13n, which are electrode materials, the solar cell 10 The transparent electrode layer 17 made of a transparent conductive oxide is placed between the metal electrode layer 18 and the p-type semiconductor layer 13p and between the metal electrode layer 18 and the n-type semiconductor layer 13n, respectively. It may be provided.
In this embodiment, the electrode layer 15 formed of a transparent conductive oxide is called a transparent electrode layer 17, and the metal electrode layer 15 is called a metal electrode layer 18.

As shown in the plan view of the back main surface 11SB of the crystal substrate 11 shown in FIG. 2, in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n each having a comb-teeth shape, an electrode layer 15 formed on the underlying comb back portion may be referred to as a busbar portion 20, and the electrode layer 15 formed on the base comb tooth portion may be referred to as a finger portion 21.
That is, in the solar cell 10 of this embodiment, as shown in FIG. 2, when the crystal substrate 11 is viewed from the back main surface 11SB side, the comb-shaped first electrode layer 15p and the comb-shaped second electrode layer 15n are formed. It is formed. Each electrode layer 15 (15p, 15n) includes a busbar portion 20 (20p, 20n) extending in a predetermined direction, and a plurality of finger portions 21 (21p) extending from the busbar portion 20 in a direction crossing the direction in which the busbar portion 20 extends. , 21n).
The busbar parts 20 (20p, 20n) are formed on the busbar base part 30 (30p, 30n) along the busbar base part 30, as shown in FIG.
The finger portions 21 (21p, 21n) are formed on the finger base portions 31 (31p, 31n) along the finger base portions 31.
In the solar cell 10, when the crystal substrate 11 is viewed from the back main surface 11SB side, there is a gap between the first electrode layer 15p and the second electrode layer 15n, and they are not in contact with each other.

The material of the transparent electrode layer 17 is not particularly limited, but for example, zinc oxide (ZnO) or indium oxide (InO _x ), or indium oxide and various metal oxides such as titanium oxide (TiO _x ), tin oxide ( Examples include transparent conductive oxides to which 1% by weight or more and 10% by weight or less of tungsten oxide ( _WOx ), molybdenum oxide ( _MoOx ), or the _like is added.

The thickness of the transparent electrode layer 17 may be 20 nm or more and 200 nm or less. A method for forming the transparent electrode layer 17 suitable for this thickness includes, for example, a physical vapor deposition (PVD) method such as a sputtering method, or a reaction between an organometallic compound and oxygen or water. Examples include metal-organic chemical vapor deposition (MOCVD).

The material of the metal electrode layer 18 is not particularly limited, and examples thereof include silver (Ag), copper (Cu), aluminum (Al), and nickel (Ni).

The thickness of the metal electrode layer 18 may be 1 μm or more and 80 μm or less. Methods for forming the metal electrode layer 18 suitable for this thickness include a printing method in which a material paste is printed by inkjet printing or screen printing, or a plating method. However, the method is not limited to this, and when a vacuum process is employed, a vacuum evaporation method (hereinafter also simply referred to as evaporation method) or a sputtering method may be employed.

Furthermore, the width of the finger base portions 31p, 31n, which are comb-teeth portions in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, and the width of the metal electrode layer 18 formed on the comb-teeth portions (finger portions 21p, 21n) are also determined. width) may be approximately the same. However, the width of the finger portions 21p, 21n may be narrower than the width of the finger base portions 31p, 31n. Further, as long as leakage between the metal electrode layers 18 is prevented, the widths of the finger parts 21p and 21n may be wider than the widths of the finger base parts 31p and 31n.

In this embodiment, the intrinsic semiconductor layer 12, the conductive semiconductor layer 13, the low reflection layer 14, and the electrode layer 15 are laminated on the back main surface 11SB of the crystal substrate 11, and each bonding surface is passivated. A predetermined annealing treatment is performed for the purpose of suppressing the generation of defect levels in the conductive semiconductor layer 13 and its interface, and crystallizing the transparent conductive oxide in the transparent electrode layer 17.

This annealing treatment includes, for example, an annealing treatment in which the crystal substrate 11 on which each of the above layers is formed is placed in an oven heated to 150° C. or more and 200° C. or less. In this case, the atmosphere in the oven may be the air, and more effective annealing can be achieved by using hydrogen or nitrogen. Further, this annealing treatment may be an RTA (Rapid Thermal Annealing) treatment in which the crystal substrate 11 on which each layer is formed is irradiated with infrared rays using an infrared heater.

[Method for manufacturing solar cells]
Hereinafter, a method for manufacturing the solar cell 10 according to this embodiment will be described with reference to FIGS. 4 to 10.

First, as shown in FIG. 4, a crystal substrate 11 having a texture structure TX on each of the front side main surface 11SU and the back side main surface 11SB is prepared (crystal substrate preparation step).

Next, as shown in FIG. 5, for example, an intrinsic semiconductor layer 12U is formed on the front main surface 11SU of the crystal substrate 11. Subsequently, the low reflection layer 14 is formed on the formed intrinsic semiconductor layer 12U (front side semiconductor layer forming step).

At this time, from the viewpoint of light confinement, silicon nitride (SiN _x ) or silicon oxide (SiO _x ) having a suitable light absorption coefficient and refractive index is used for the low reflection layer 14 .

Next, a p-side semiconductor layer forming step is performed to form semiconductor layers 12p and 13p on the back side. Specifically, as shown in FIG. 6, an intrinsic semiconductor layer 12p using, for example, i-type amorphous silicon is formed on the back main surface 11SB of the crystal substrate 11 (first intrinsic semiconductor layer forming step). ).
Subsequently, a p-type semiconductor layer 13p is formed on the formed intrinsic semiconductor layer 12p (first semiconductor layer forming step).
Through these steps, the p-type semiconductor layer 13p is formed on the back side main surface 11SB, which is one main surface of the crystal substrate 11.

In this way, the first semiconductor layer forming step for forming the p-type semiconductor layer 13p (first semiconductor layer) is performed on the crystal substrate 11 (semiconductor layer) before the first semiconductor layer forming step for forming the p-type semiconductor layer 13p. The method includes a first semiconductor layer forming step of forming an intrinsic semiconductor layer 12p (first intrinsic semiconductor layer) on one main surface 11S (back side main surface 11SB) of the substrate.

After that, a lift-off layer LF is laminated on the formed p-type semiconductor layer 13p (lift-off layer lamination step).

This lift-off layer LF preferably contains metal as a main component (the main component is a material component that accounts for 50% or more of the material forming the lift-off layer LF).

Specifically, the lift-off layer LF contains as a main component an element selected from silver or one or more metal elements having an atomic number of 5n+4 (n is an integer of 4 to 15).
Metals with an atomic number of 5n+4 include chromium (atomic number 24), copper (atomic number 29), yttrium (atomic number 39), indium (atomic number 49), gadolinium (atomic number 64), and thulium (atomic number 69). ), tungsten (atomic number 74), or gold (atomic number 79).
The properties required for the lift-off layer LF include the selectivity of the solution in which it is dissolved, and although it is not clear why the 5n+4 relationship holds true for metals other than silver, the number of electrons in the d and f orbits and the etching solution It can be considered that there is a relationship between the ionization rate and the ionization rate.
The lift-off layer LF may be a pure metal or a metal alloy, and preferably contains 90% or more of the pure metal or metal alloy, more preferably 95% or more.

Note that the lift-off layer LF is formed by a vacuum process, particularly by a chemical vapor deposition method (CVD method) or a physical vapor deposition method (PVD method). In these methods, film quality such as density is controlled by film forming conditions such as flow rate ratio of raw material gas, pressure, or set voltage of power supply. Furthermore, the etching characteristics in the film thickness direction may be adjusted by changing the film forming conditions described above in the film thickness direction.

Particularly in the case of the PVD method, the vacuum evaporation method may be more preferable than the sputtering method. This is because the crystal quality of the formed metal film affects the etching lift-off characteristics. For example, in the case of copper or silver, it is easier to obtain good results when the crystal grain size is increased, so it may be preferable to select a vacuum evaporation method.
The "vacuum evaporation method" used herein includes a resistance heating vacuum evaporation method, an electron beam evaporation method, and a flash evaporation method.

Next, as shown in FIGS. 7 and 8, the lift-off layer LF and the p-type semiconductor layer 13p are patterned on the back main surface 11SB of the crystal substrate 11 (patterning step).
This creates a non-formation region NA where the p-type semiconductor layer 13p is not formed. On the other hand, the lift-off layer LF and the p-type semiconductor layer 13p remain in the region of the back side main surface 11SB of the crystal substrate 11 that is not etched.

In the patterning process shown in FIGS. 7 and 8, the area melted by the etching of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p (hereinafter referred to as etching area) is the ) is less than the etching area of the lift-off layer LF, the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the lift-off layer LF are removed by wet etching using two or more different types of etching solutions.

More specifically, the intrinsic semiconductor layer 12p is formed so that the widths of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are greater than or equal to the width of the lift-off layer LF when viewed from the rear main surface 11SB side in the direction perpendicular to the surface of the crystal substrate 11. , the p-type semiconductor layer 13p and the lift-off layer LF are removed.

In the actual process, as shown in FIG. 7, after the lift-off layer LF is selectively removed by wet etching using a first etching solution, the intrinsic semiconductor layer 12 and the p-type semiconductor layer are removed as shown in FIG. 13p is selectively removed by wet etching using a second etching solution.
That is, the patterning process includes a lift-off layer removal process in which the lift-off layer LF is mainly etched using the first etching liquid, and a lift-off layer removing process in which the intrinsic semiconductor layer 12 and the p-type semiconductor layer 13p are mainly etched using the second etching liquid. The first semiconductor layer removing step is performed in this order.

Such a patterning process is performed using a photolithography method, for example, a resist film (not shown) having a predetermined pattern is formed on the lift-off layer LF, and the region masked by the resist film is not melted by etching and remains unmasked. This is achieved by dissolving the area. As shown in FIGS. 7 and 8, by patterning each layer of the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the lift-off layer LF, a non-formation area NA is formed in a part of the back main surface 11SB of the crystal substrate 11. That is, an exposed area of the back side main surface 11SB is generated.

As the first etching solution used in the lift-off layer removal process shown in FIG. 7, for example, in addition to a strong acid-based etching solution such as hydrochloric acid or sulfuric acid, an alkaline-based etching solution such as a sodium hypochlorite aqueous solution or an alkali can be used. It will be done.
On the other hand, as the second etching solution used in the first semiconductor layer removal step shown in FIG. 8, for example, a solution in which ozone is dissolved in hydrofluoric acid (hereinafter referred to as ozone/hydrofluoric acid solution) is used. .

Note that the ozone/hydrofluoric acid solution that is the second etching solution may etch or corrode not only the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p but also the lift-off layer LF. In this case, in the state after the first semiconductor layer removal step shown in FIG. 8, the edge portion in the width direction of the lift-off layer LF is recessed compared to the state after the lift-off layer removal step shown in FIG.
As a result, the edge of the lift-off layer LF is set back from the edge of the p-type semiconductor layer 13p. That is, as can be read from FIG. 13A, the p-type semiconductor layer 13p has a portion (exposed portion 35) exposed from the lift-off layer LF, and the exposed portion 35 is formed along the edge of the lift-off layer LF. There is. In other words, the end face of the p-type semiconductor layer 13p and the end face of the lift-off layer LF are continuous in a stepped manner via a part of the main surface of the p-type semiconductor layer 13p.
As a result, as shown in FIG. 12, the widths of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p become larger than the width of the lift-off layer LF when viewed from the back main surface 11SB side in the direction perpendicular to the surface of the crystal substrate 11.

Next, as shown in FIG. 9, an n-side semiconductor layer forming step is performed to form an intrinsic semiconductor layer 12n and an n-type semiconductor layer 13n. That is, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are sequentially formed on the back main surface 11SB of the crystal substrate 11, including the lift-off layer LF, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer 12p.
That is, the n-side semiconductor layer forming step includes a second intrinsic semiconductor layer forming step of laminating the intrinsic semiconductor layer 12n from above the back side main surface 11SB of the crystal substrate 11 over the laminated portion of the p-type semiconductor layer 13p and the lift-off layer LF. , a second semiconductor layer forming step is performed in which an n-type semiconductor layer 13n is laminated on the intrinsic semiconductor layer 12n. In other words, the intrinsic semiconductor layer 12n and A type semiconductor layer 13n is stacked.

The second semiconductor layer forming step of forming such an n-type semiconductor layer 13n (second semiconductor layer) is performed by forming the crystal substrate 11 (semiconductor substrate 11) before the second semiconductor layer forming step of forming the n-type semiconductor layer 13n. ) A second intrinsic semiconductor layer forming step is performed to form an intrinsic semiconductor layer 12n (second intrinsic semiconductor layer) on one main surface 11S (back main surface 11SB) including the lift-off layer LF and the p-type semiconductor layer 13p. be done.
As a result, the stacked film of the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n is formed on the non-formation region NA, on the surface and side surfaces (end faces) of the lift-off layer LF, on the lift-off layer LF, on the p-type semiconductor layer 13p, and on the intrinsic semiconductor layer 13n. It is formed so as to cover the side surfaces (end surfaces) of the layer 12p.

Here, in this embodiment, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed in a state in which the edge of the lift-off layer LF is set back from the edge of the p-type semiconductor layer 13p. Therefore, as shown in FIGS. 9 and 13(b), a part of the intrinsic semiconductor layer 12n and a part of the n-type semiconductor layer 13n are formed directly on the p-type semiconductor layer 13p.

Next, as shown in FIGS. 10 and 13(c), by removing the stacked lift-off layer LF using an etching solution, the n-type semiconductor layer 13n and the intrinsic semiconductor layer 12n covering the lift-off layer LF are crystallized. It is removed from the substrate 11 (lift-off process).
Here, there is no need to dissolve the second intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n that cover the lift-off layer LF, and they are peeled off from the crystal substrate 11 at the same time as the lift-off layer LF is removed, and a part of the p-type semiconductor layer 13p is removed. be exposed.

Note that the etching solution used in this lift-off step is preferably a solvent that dissolves the lift-off layer LF but does not dissolve each intrinsic semiconductor layer 12 and the conductive semiconductor layer 13.

For example, when the lift-off layer LF is made of chromium, yttrium, gadolinium, or thulium, the etching solution is preferably dilute hydrochloric acid or dilute sulfuric acid, and when the lift-off layer LF is made of copper, the etching solution is preferably an aqueous iron chloride solution.
When the lift-off layer LF is made of silver, the etching solution is preferably dilute nitric acid or an aqueous solution in which a large excess of aqueous ammonia is added to dilute nitric acid. When the lift-off layer LF is made of indium, the etching solution is preferably hydrochloric acid or dilute sulfuric acid. and preferable.
When the lift-off layer LF is made of tungsten, the etching solution is preferably a sodium hypochlorite aqueous solution, and when the lift-off layer LF is gold, the etching solution is preferably a potassium cyanide aqueous solution.

Next, an electrode layer forming step is performed. Specifically, as shown in FIG. 11, a transparent layer is formed on the back main surface 11SB of the crystal substrate 11, that is, on each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, by sputtering using a mask, for example. Electrode layers 17 (17p, 17n) are formed (transparent electrode layer forming step).
Note that the transparent electrode layer 17 (17p, 17n) may be formed as follows instead of the sputtering method.

For example, the transparent electrode layer 17 is formed by forming a transparent conductive oxide film on the entire back surface 11SB without using a mask, and then using a photolithography method to form a transparent conductive oxide film on the p-type semiconductor layer 13p and the n-type semiconductor layer. Alternatively, etching may be performed to leave a transparent conductive oxide film on each layer 13n.

Thereafter, linear metal electrode layers 18 (18p, 18n) are formed on the transparent electrode layer 17 using, for example, a mesh screen (not shown) having openings (metal electrode layer forming step).
In this way, the electrode layer forming step includes a transparent electrode layer forming step and a metal electrode layer forming step in this order, and the first electrode layer 15p is laminated on the exposed portion of the p-type semiconductor layer 13p from the n-type semiconductor layer 13n. , a second electrode layer 15n is stacked on the n-type semiconductor layer 13n.

Through the above steps, a back-side bonding type solar cell 10 is formed.

(Summary and effects)
The following can be said from the method for manufacturing the solar cell 10 described above.

First, in the lift-off step shown in FIG. 10, when the lift-off layer LF is removed using an etching solution, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n deposited on the lift-off layer LF are also removed from the crystal substrate 11 at the same time. (so-called lift-off).
This step does not require a resist coating step and a developing step used in the photolithography method, compared to the lift-off layer removal step shown in FIG. 7, which uses, for example, a photolithography method. Therefore, the n-type semiconductor layer 13n can be easily patterned.

The lift-off layer LF contains metal as a main component, and in the patterning step of patterning the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the lift-off layer LF, the intrinsic semiconductor layer 12p is The intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the lift-off layer LF are etched by wet etching using two or more different etching solutions so that the etching area of the p-type semiconductor layer 13p is equal to or less than the etching area of the lift-off layer LF. is removed.

In this way, by etching so that the etching area of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p is equal to or less than the etching area of the lift-off layer LF, at the stage of forming the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n, , exposure of the crystal substrate 11 is prevented.

That is, if the etching area of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p is larger than the etching area of the lift-off layer LF when viewed from the back side in the perpendicular direction of the crystal substrate 11, as shown in FIG. Then, the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p become in a state where they are set back from the lift-off layer LF (side-cut state).
When the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed in this state, the lift-off layer LF plays a role like a mask, and the intrinsic semiconductor layer 12n on the non-formation area NA is formed as shown in FIG. A gap S is created between the side surface and the side surfaces of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p.

Then, when the lift-off layer LF, the intrinsic semiconductor layer 12n covering it, and the n-type semiconductor layer 13n are removed, the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the intrinsic semiconductor layers 12n and The back main surface 11SB of the crystal substrate 11 is exposed between the crystal substrate 11 and the semiconductor layer 13n. If the back side main surface 11SB of the crystal substrate 11 is exposed, the effective area from which holes and electrons can be collected will be reduced by the exposed area, and the performance of the solar cell 10 will deteriorate.

On the other hand, when the lift-off layer LF contains metal as a main component as in this embodiment, the etching characteristics of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p and the etching characteristics of the lift-off layer LF are different. to differ greatly. By using different etching solutions for etching the lift-off layer LF and etching solutions for etching the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p, the etching area of each layer can be controlled, especially the intrinsic semiconductor layer. The patterning accuracy in the width direction of the p-type semiconductor layer 12p and the p-type semiconductor layer 13p is increased. As a result, the etching area of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p becomes equal to or less than the etching area of the lift-off layer LF.

As a result, the side surfaces of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p and the side surfaces of the lift-off layer LF become flush with each other, or the lift-off layer LF recedes from the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p. It becomes a state. If the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed in this state, the intrinsic semiconductor layer 12n is formed so as to be in contact with at least the side surfaces of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p. Therefore, exposure of the crystal substrate 11 is suppressed. Therefore, deterioration of the performance of the solar cell 10 is suppressed, and a high-performance solar cell 10 is manufactured.

For these reasons, according to this embodiment, a high-performance back-contact solar cell can be efficiently manufactured.

As mentioned above, in order to control the etching area of each layer, the etching rate of the first etching solution used in the lift-off layer removal process of FIG. 7 is determined by the following relational expression (1):
Etching rate of intrinsic semiconductor layer 12p≦Etching rate of p-type semiconductor layer 13p<<Etching rate of lift-off layer LF (1)
The following relational expression (2) is satisfied, and the etching rate of the second etching solution used in the first semiconductor layer removal step shown in FIG.
Etching rate of intrinsic semiconductor layer 12p≦Etching rate of p-type semiconductor layer 13p≦Etching rate of lift-off layer LF (2)
It is preferable to satisfy the following.

That is, it is preferable that the etching rate of the intrinsic semiconductor layer 12p of the first etchant is lower than the etching rate of the p-type semiconductor layer 13p. It is preferable that the etching rate of the p-type semiconductor layer 13p of the first etchant is lower than the etching rate of the lift-off layer LF, and is much slower than the etching rate of the lift-off layer LF.
The etching rate of the p-type semiconductor layer 13p of the first etchant is preferably 1/10 or less, more preferably 1/100 or less of the etching rate of the lift-off layer LF.
Moreover, it is preferable that the etching rate of the intrinsic semiconductor layer 12p of the second etchant is equal to or lower than the etching rate of the p-type semiconductor layer 13p. It is preferable that the etching rate of the p-type semiconductor layer 13p of the second etchant is lower than the etching rate of the lift-off layer LF.

If the first etching solution satisfies the above relational expression (1), the lift-off layer LF can be selectively and quickly dissolved in the lift-off layer removal step shown in FIG.
Since the second etching solution satisfies the relational expression (2), the lift-off layer LF is also removed when the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are dissolved in the first semiconductor layer removal step shown in FIG. dissolve together.
Therefore, the etching area of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p does not become larger than the etching area of the lift-off layer LF, and side cuts of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are less likely to occur.

The above-mentioned relational expressions (1) and (2) can be satisfied depending on the type of etching solution (including etching solutions with different concentrations).

The thickness of the lift-off layer LF is preferably 20 nm or more and 250 nm or less, particularly preferably 50 nm or more and 200 nm or less. That is, if the thickness of the lift-off layer LF is too thick, there is a concern that insufficient etching or a decrease in productivity may occur in the lift-off layer removal step shown in FIG. 7. Furthermore, if the thickness of the lift-off layer LF is too thick, a reverse tapered undercut may occur in the lift-off layer LF due to side etching.

When a reverse tapered undercut occurs in the lift-off layer LF as shown in FIG. 15(a), the width of the lift-off layer LF becomes narrower as it approaches the p-type semiconductor layer 13p compared to the surface of the lift-off layer LF. Therefore, in the state after etching the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p, the edge portions of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are on the farthest side from the p-type semiconductor layer 13p in the lift-off layer LF. It is set back from the edge of the part.

In this state, when the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed as shown in FIG. A gap S is generated between the side surface of the semiconductor layer 12n and the side surfaces of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p, and finally, as shown in FIG. 15(c), the back main surface 11SB of the crystal substrate 11 is It will be exposed.

Therefore, the thickness of the lift-off layer LF needs to be set to a thickness that can prevent the above-mentioned reverse tapered undercut. On the other hand, if the film thickness is too thin, there is a risk that the lift-off layer LF will be completely removed (lifted off) when patterning the lift-off layer LF in the lift-off layer removal process shown in FIG. Therefore, a certain degree of film thickness is required. Therefore, the thickness of the lift-off layer LF is preferably 20 nm or more and 250 nm or less.

In the solar cell 10, a crystal substrate 11 has a texture structure TX, and each surface of a p-type semiconductor layer 13p and an n-type semiconductor layer 13n formed on a back side main surface 11SB of this crystal substrate 11 includes: It is preferable that a texture structure (second texture structure) reflecting the texture structure TX is included. That is, it is preferable that the p-type semiconductor layer 13p and the n-type semiconductor layer 13n have a second texture structure in which the texture structure TX of the underlying crystal substrate 11 is reflected.

When the conductive semiconductor layer 13 has a texture structure TX on its surface, the etching solution easily permeates into the conductive semiconductor layer 13 due to the unevenness of the texture structure TX. Therefore, the conductive semiconductor layer 13 is easily removed, that is, easily patterned.

In the present embodiment, the texture structure TX (first texture structure) is provided on both main surfaces 11S of the crystal substrate 11, that is, the front main surface 11SU and the back main surface 11SB, but the texture structure TX (first texture structure) is provided on either main surface It may also be provided only on

When the texture structure TX is provided on the front main surface 11SU, the effect of capturing and confining the received light is enhanced.
On the other hand, when the texture structure TX is provided on the back main surface 11SB, the light capturing effect is improved and the patterning of the conductive semiconductor layer 13 is facilitated.
Therefore, the texture structure TX of the crystal substrate 11 may be provided on at least one main surface 11S.
Further, in this embodiment, the texture structure TX on both main surfaces 11S has the same pattern, but the pattern is not limited to this, and the size of the unevenness of the texture structure TX can be changed between the front main surface 11SU and the back main surface 11SB. Good too.

The technology disclosed herein is not limited to the embodiments described above, and may be substituted without departing from the spirit of the claims.

For example, in the above-described embodiment, in the first semiconductor layer removal step shown in FIG. The intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are patterned to have a width larger than that of the p-type semiconductor layer 13p.
However, the present invention is not limited to this, and the width of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p may be formed to be approximately the same as the width of the lift-off layer LF (actually, the width of the lift-off layer LF is slightly smaller). Patterning (etching) may also be performed.

That is, when the widths of the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p are approximately the same as the width of the lift-off layer LF, the edge portions of the lift-off layer LF and the edge portions of the p-type semiconductor layer 13p are located at approximately the same position. do. When the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are formed in this state, as shown in FIG. It is formed.

As a result, when the n-type semiconductor layer 13n and the intrinsic semiconductor layer 12n deposited on the lift-off layer LF are removed from the crystal substrate 11 by removing the lift-off layer LF, the n-type semiconductor layer 13n is removed as shown in FIG. is not formed on the p-type semiconductor layer 13p, but is separated from the p-type semiconductor layer 13p via the intrinsic semiconductor layer 12n in the width direction. Note that when forming the p-type semiconductor layer 13p and the n-type semiconductor layer 13n in this way, a separation groove is formed at the boundary between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n from the viewpoint of suppressing the occurrence of leakage. It is preferable to form

Further, in the above embodiment, the semiconductor layer used in the first semiconductor layer forming step shown in FIG. 6 is the p-type semiconductor layer 13p, but is not limited to this, and may be the n-type semiconductor layer 13n. do not have. Furthermore, the conductivity type of the crystal substrate 11 is not particularly limited, and may be p-type or n-type.
That is, in the embodiments described above, p-type and n-type may be exchanged.

The embodiments described above are merely illustrative and should not be construed as limiting the scope of the technology of the present disclosure. The scope of the technology of the present disclosure is defined by the scope of the claims, and all modifications and changes that fall within the scope of equivalents of the claims are within the scope of the technology of the present disclosure.

Hereinafter, the technology according to the present disclosure will be specifically explained using examples. However, the technology according to the present disclosure is not limited to these examples. Note that in the following explanation, there is no particular distinction between Examples 1 to 8 and Comparative Example 1 under the same conditions.

[Crystal substrate]
First, a single crystal silicon substrate with a thickness of 200 μm was used as a crystal substrate. Anisotropic etching was performed on both main surfaces of a single crystal silicon substrate. As a result, a pyramid-shaped texture structure was formed on the crystal substrate.

[Intrinsic semiconductor layer]
The crystal substrate was introduced into a CVD apparatus, and silicon intrinsic semiconductor layers (film thickness: 8 nm) were formed on both main surfaces of the introduced crystal substrate. The film forming conditions were a substrate temperature of 150° C., a pressure of 120 Pa, a SiH ₄ /H ₂ flow rate ratio of 3/10, and a power density of 0.011 W/cm ² .

[P-type semiconductor layer (first conductivity type semiconductor layer)]
A crystal substrate with intrinsic semiconductor layers formed on both main surfaces was introduced into a CVD apparatus, and a p-type hydrogenated amorphous silicon thin film (thickness: 10 nm) was formed on the intrinsic semiconductor layer on the back main surface. The film forming conditions were a substrate temperature of 150° C., a pressure of 60 Pa, a SiH ₄ /B ₂ H ₆ flow rate ratio of 1/3, and a power density of 0.01 W/cm ² . Further, the flow rate of B ₂ H ₆ gas is the flow rate of diluted gas in which B ₂ H ₆ is diluted with H ₂ to 5000 ppm.

[Lift-off layer]
In Examples 1 to 5 and Examples 7 to 8, using an electron beam (EB) evaporation apparatus (EBX-2000, manufactured by ULVAC), the materials shown in Table 1 were deposited on a p-type hydrogenated amorphous silicon thin film. A lift-off layer containing the metal shown as a main component was formed to have a thickness of 100 nm. Using each metal as a vapor deposition source, vacuum evacuation was performed until the pressure reached 10 ⁻⁴ Pa or less, and film formation was performed with an output of 800 VA and a substrate temperature of room temperature. That is, in Examples 1 to 5 and 7 to 8, films were formed by vacuum evaporation.

In Example 6, a lift-off layer containing tungsten as a main component was formed to a thickness of 100 nm on a p-type hydrogenated amorphous silicon thin film using a magnetron sputtering device. Argon gas was introduced into the chamber of the apparatus using tungsten as a target and the substrate temperature was set at 150° C., and the pressure inside the chamber was set to 0.8 Pa. Film formation was performed using an AC power source at a power density of 0.4 W/cm ² .

In Comparative Example 1, a lift-off layer containing silicon oxide (SiO _x ) as a main component was formed to a thickness of 150 nm on a p-type hydrogenated amorphous silicon thin film using a CVD apparatus. The film forming conditions were a substrate temperature of 150° C., a pressure of 0.9 kPa, a SiH ₄ /CO ₂ /H ₂ flow rate ratio of 1/10/750, and a power density of 0.15 W/cm ² .

[Patterning of lift-off layer and first conductivity type semiconductor layer]
First, for each of Examples 1 to 8 and Comparative Example 1, a photosensitive resist film was formed on the back main surface of the crystal substrate on which the lift-off layer was formed. This was exposed and developed by photolithography to expose the regions where the lift-off layer, p-type semiconductor layer, and intrinsic semiconductor layer were to be removed.

In Example 1, after exposure and development, the exposed area of the lift-off layer was removed by immersion in 3% by weight nitric acid. After cleaning with a large excess of ammonia water, rinse with pure water, and then immerse in an ozone/hydrofluoric acid solution containing 5.5% by weight hydrofluoric acid and 20 ppm ozone to remove the exposed areas. The p-type semiconductor layer and the intrinsic semiconductor layer were removed.

In Example 2, after exposure and development, the exposed region of the lift-off layer was removed by immersion in a 5% by weight iron(III) chloride aqueous solution. After rinsing with pure water, the exposed areas of the p-type semiconductor layer and the intrinsic semiconductor layer are removed by immersion in an ozone/hydrofluoric acid solution containing 5.5% by weight of hydrofluoric acid and 20 ppm of ozone. did.

In Examples 3, 4, 7, and 8, after exposure and development, the exposed areas of the lift-off layer were removed by immersion in 3% by weight hydrochloric acid. After rinsing with pure water, the exposed areas of the p-type semiconductor layer and the intrinsic semiconductor layer are removed by immersion in an ozone/hydrofluoric acid solution containing 5.5% by weight of hydrofluoric acid and 20 ppm of ozone. did.

In Example 5, after exposure and development, the exposed area of the lift-off layer was removed by immersion in 3% by weight sulfuric acid. After rinsing with pure water, the exposed areas of the p-type semiconductor layer and the intrinsic semiconductor layer are removed by immersion in an ozone/hydrofluoric acid solution containing 5.5% by weight of hydrofluoric acid and 20 ppm of ozone. did.

In Example 6, after exposure and development, the exposed area of the lift-off layer was removed by immersion in a 30% by weight aqueous sodium hypochlorite solution. After rinsing with pure water, the exposed areas of the p-type semiconductor layer and the intrinsic semiconductor layer are removed by immersion in an ozone/hydrofluoric acid solution containing 5.5% by weight of hydrofluoric acid and 20 ppm of ozone. did.

In Comparative Example 1, after exposure and development, the exposed region of the lift-off layer was removed by immersion in 5% by weight hydrofluoric acid. After rinsing with pure water, the exposed areas of the p-type semiconductor layer and the intrinsic semiconductor layer are removed by immersion in an ozone/hydrofluoric acid solution containing 5.5% by weight of hydrofluoric acid and 20 ppm of ozone. did.

The above process is called a patterning process.

[N-type semiconductor layer (second conductivity type semiconductor layer)]
After the patterning process, the crystal substrate whose exposed backside main surface was cleaned with hydrofluoric acid having a concentration of 2% by weight is introduced into a CVD apparatus, and an intrinsic semiconductor layer (film thickness 8 nm) is formed on the backside main surface for the first time. It was formed under the same film formation conditions as the semiconductor layer.
Subsequently, an n-type hydrogenated amorphous silicon thin film (thickness: 10 nm) was formed on the formed intrinsic semiconductor layer. The film forming conditions were a substrate temperature of 150° C., a pressure of 60 Pa, a SiH ₄ /PH ₃ /H ₂ flow rate ratio of 1/2, and a power density of 0.01 W/cm ² . Further, the flow rate of PH ₃ gas is the flow rate of diluted gas in which PH ₃ is diluted to 5000 ppm with H ₂ .

[Removal of lift-off layer and second conductivity type semiconductor layer]
In Example 1, a crystal substrate on which an n-type semiconductor layer is formed is immersed in nitric acid having a concentration of 7% by weight as an etching solution to form a lift-off layer, an n-type semiconductor layer covering the lift-off layer, and a lift-off layer and an n-type semiconductor layer. The intrinsic semiconductor layer between the semiconductor layer and the semiconductor layer was removed all at once.

In Example 2, a crystal substrate on which an n-type semiconductor layer is formed is immersed in an aqueous iron chloride solution having a concentration of 10% by weight as an etching solution to form a lift-off layer, an n-type semiconductor layer covering the lift-off layer, And the intrinsic semiconductor layer between the lift-off layer and the n-type semiconductor layer was removed all together.

In Examples 3, 4, 7, and 8, the crystal substrate on which the n-type semiconductor layer was formed was immersed in hydrochloric acid having a concentration of 7% by weight as an etching solution to form a lift-off layer and an n-type semiconductor on the lift-off layer. layer, and the intrinsic semiconductor layer between the lift-off layer and the n-type semiconductor layer were removed all together.

In Example 5, a crystal substrate on which an n-type semiconductor layer was formed was immersed in sulfuric acid with a concentration of 7% by weight as an etching solution to form a lift-off layer, an n-type semiconductor layer covering the lift-off layer, and a lift-off layer and an n-type semiconductor layer. The intrinsic semiconductor layer between the semiconductor layer and the semiconductor layer was removed all at once.

In Example 6, a crystal substrate on which an n-type semiconductor layer was formed was immersed in a sodium hypochlorite aqueous solution having a concentration of 50% by weight as an etching solution to form a lift-off layer, an n-type semiconductor layer covering the lift-off layer, And the intrinsic semiconductor layer between the lift-off layer and the n-type semiconductor layer was removed all together.

In Comparative Example 1, a crystal substrate on which an n-type semiconductor layer was formed was immersed in hydrofluoric acid having a concentration of 5% by weight as an etching solution to remove the lift-off layer, the n-type semiconductor layer on the lift-off layer, and The intrinsic semiconductor layer between the lift-off layer and the n-type semiconductor layer was removed all together.

The above process is called a lift-off process.

[Electrode layer, low reflection layer]
Using a magnetron sputtering device, an oxide film (thickness: 100 nm) that would become the base of a transparent electrode layer was formed on the conductive semiconductor layer of the crystal substrate. Furthermore, a silicon nitride layer was formed as a low reflection layer on the light-receiving surface side of the crystal substrate.
As a transparent conductive oxide, indium oxide (ITO) containing tin oxide at a concentration of 10% by weight was used as a target. A mixed gas of argon and oxygen was introduced into the chamber of the apparatus, and the pressure inside the chamber was set to 0.6 Pa. The mixing ratio of argon and oxygen was set to the lowest resistivity (so-called bottom) condition. Further, film formation was performed using a DC power source at a power density of 0.4 W/cm ² .

Next, by photolithography, etching was performed so that only the transparent conductive oxide film on the conductive semiconductor layers (p-type semiconductor layer and n-type semiconductor layer) was left, thereby forming a transparent electrode layer. The transparent electrode layer formed by this etching prevented electrical conduction between the transparent conductive oxide film on the p-type semiconductor layer and the transparent conductive oxide film on the n-type semiconductor layer.

Further, a silver paste (Dotite FA-333 manufactured by Fujikura Kasei Co., Ltd.) was screen printed on the transparent electrode layer without dilution, and heat treatment was performed in an oven at a temperature of 150° C. for 60 minutes. As a result, a metal electrode layer was formed.

Next, an evaluation method for back contact type solar cells will be explained. For the evaluation results, refer to [Table 1].

[Evaluation of film thickness and etching properties]
The film thickness or etching state of the lift-off layer was evaluated using an optical microscope (BX51: manufactured by Olympus Optical Industries, Ltd.) and an SEM (field emission scanning electron microscope S4800: manufactured by Hitachi High-Technologies). After the patterning process, the p-type semiconductor layer is etched according to the designed pattern removal area, and when observed with an optical microscope from the back main surface of the crystal substrate, it is found that the p-type semiconductor layer is less etched than the lift-off layer (the p-type semiconductor layer is etched less than the lift-off layer). If the edge part was not recessed from the edge part of the lift-off layer, it was rated "A". On the other hand, when the lift-off layer was excessively etched and the solar cell characteristics were adversely affected, it was rated "B".

In the lift-off process, when the lift-off layer was removed, it was designated as "A", and when the lift-off layer remained, it was designated as "B".

[Evaluation of conversion efficiency]
A solar simulator was used to irradiate reference sunlight with an AM (air mass) of 1.5 at a light intensity of 100 mW/cm ² to measure the conversion efficiency (Eff (%)) of the solar cell. The conversion efficiency (solar cell characteristics) of Comparative Example 1 was set to 1.00, and the relative values are listed in [Table 1].

In Examples 1 to 8, as in Comparative Example 1, both the patterning process and the lift-off process were rated A, and there was no B rating.

Examples 1 to 8 had good pattern accuracy and solar cell characteristics. In addition, Examples 1 to 8 in which the lift-off layer contained metal as a main component had higher conversion efficiency than Comparative Example 1 in which a metal oxide layer was used as the lift-off layer.

In particular, in Example 2, by forming a copper film by vapor deposition, it was possible to form a film with larger crystal grains than by forming a film by sputtering. Thereby, over-etching of the lift-off layer LF could be suppressed in the patterning process, and it could be removed in the lift-off process.

By the way, while Examples 1 to 8 use different types of etching solutions, Comparative Example 1 uses one type of hydrofluoric acid as the etching solution with varying concentrations of hydrogen fluoride.
By using a plurality of types of etching solutions as in Examples 1 to 8, it is expected that the lift-off layer, the first conductivity type semiconductor layer, and the intrinsic semiconductor layer can be etched more effectively and suitably. This can be explained as follows.

The ozone/hydrofluoric acid that etches the first conductivity type semiconductor layer and the intrinsic semiconductor layer not only etches the first conductivity type semiconductor layer and the intrinsic semiconductor layer but also slightly etches the lift-off layer. This suppresses side cuts (undercuts) in the first conductivity type semiconductor layer and the intrinsic semiconductor layer.

On the other hand, if the lift-off layer is not etched at all during the etching of the first conductivity type semiconductor layer and the intrinsic semiconductor layer, the etching solution passes from the surface of the lift-off layer through the crystal grain boundaries of that layer and etches the first conductivity type semiconductor layer and the intrinsic semiconductor layer. Priority may be given to processes that reach the type semiconductor layer and the intrinsic semiconductor layer.

However, in the solar cell manufacturing methods as in Examples 1 to 8, the lift-off layer is also slightly etched during the etching of the first conductivity type semiconductor layer and the intrinsic semiconductor layer. Accordingly, when the edge portions of the first conductivity type semiconductor layer and the intrinsic semiconductor layer recede due to etching, the edge portion of the lift-off layer also recedes due to etching. That is, the first semiconductor layer removing step is performed, and while the first conductivity type semiconductor layer and the intrinsic semiconductor layer are being etched, the lift-off layer is etched at the same time.
In addition, in the method for manufacturing a solar cell as in Examples 1 to 8, the etching solution passes from the surface of the lift-off layer through the crystal grain boundaries of that layer, and etches the semiconductor layer of the first conductivity type located below the lift-off layer. And etching of the intrinsic semiconductor layer is suppressed.

In summary, the results showed that solar cell characteristics were improved by forming a lift-off layer containing metal as the main component and performing wet etching using two types of etching solutions.
This is done by etching each layer as quickly as possible using two types of etching solutions, and when etching the first conductivity type semiconductor layer and the intrinsic semiconductor layer, the lift-off layer is slightly etched by the etching solution. As a result, uniform and accurate patterning can be achieved in both the patterning process and the lift-off process.
This is considered to be because the arrangement of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer or the electrical contact with the electrode layer (suppression of increase in series resistance) is improved.

In particular, when etching the first conductivity type semiconductor layer and the intrinsic semiconductor layer, the lift-off layer is slightly etched with the second etching solution, resulting in side cuts in the first conductivity type semiconductor layer and the intrinsic semiconductor layer. suppressed. Therefore, it is considered that sufficient solar cell characteristics can be obtained.

From the above, with the lift-off layer stacked on the semiconductor layer, etching is performed using two or more types of etching solutions having different etching rates. It was found that by doing so, it was possible to pattern uniformly and accurately in both the patterning process and the lift-off process.
It has been found that by using a lift-off layer whose main component is a metal, the photoelectric conversion efficiency can be improved compared to the case where a lift-off layer whose main component is a metal oxide is used.

10 Solar cell 11 Crystal substrate (semiconductor substrate)
12 Intrinsic semiconductor layer 13 Conductivity type semiconductor layer 13p P-type semiconductor layer [first semiconductor layer of first conductivity type/second semiconductor layer of second conductivity type]
13n n-type semiconductor layer [first semiconductor layer of second conductivity type/second semiconductor layer of first conductivity type]
15 Electrode layer 17 Transparent electrode layer 18 Metal electrode layer LF Lift-off layer

Claims (12)

a first semiconductor layer forming step of forming a first semiconductor layer of a first conductivity type on the first main surface side of the semiconductor substrate;
a lift-off layer lamination step of laminating a lift-off layer on the first semiconductor layer;
a patterning step of selectively removing each of the first semiconductor layer and the lift-off layer by etching;
A second semiconductor of a second conductivity type is provided on the first main surface side so as to extend from the removed portion of the first semiconductor layer and the lift-off layer in the patterning step to the laminated portion of the first semiconductor layer and the lift-off layer. a second semiconductor layer forming step of forming a layer;
a lift-off step of removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer,
In the patterning step, two or more types of etching solutions are used so that the etching area of the first semiconductor layer is equal to or less than the etching area of the lift-off layer when viewed from the first main surface side in the direction perpendicular to the surface of the semiconductor substrate. the first semiconductor layer and the lift-off layer are removed using
The lift-off layer has metal as a main component,
The patterning step includes a lift-off layer removing step of removing the lift-off layer and a first semiconductor layer removing step of removing the first semiconductor layer, and the first semiconductor layer removing step is performed after the lift-off layer removing step. It is a thing,
A method for manufacturing a solar cell , wherein the type of etching liquid used in the lift-off layer removing step is different from the type of etching liquid used in the first semiconductor layer removing step . When the etching solution used in the lift-off layer removal step is a first etching solution, and the etching solution used in the first semiconductor layer removal step is a second etching solution,
The first etching solution has a faster etching rate for the lift-off layer than an etching rate for the first semiconductor layer,
The etching rate of the lift-off layer of the second etchant is higher than or equal to the etching rate of the first semiconductor layer, and is lower than the etching rate of the lift-off layer of the first etchant. Method of manufacturing solar cells. 3. The method for manufacturing a solar cell according to claim 2 , wherein the first etchant has an etching rate of the lift-off layer that is 10 times or more than an etching rate of the first semiconductor layer. a first semiconductor layer forming step of forming a first semiconductor layer of a first conductivity type on the first main surface side of the semiconductor substrate;
a lift-off layer lamination step of laminating a lift-off layer on the first semiconductor layer;
a patterning step of selectively removing each of the first semiconductor layer and the lift-off layer by etching;
A second semiconductor of a second conductivity type is provided on the first main surface side so as to extend from the removed portion of the first semiconductor layer and the lift-off layer in the patterning step to the laminated portion of the first semiconductor layer and the lift-off layer. a second semiconductor layer forming step of forming a layer;
a lift-off step of removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer,
In the patterning step, two or more types of etching solutions are used so that the etching area of the first semiconductor layer is equal to or less than the etching area of the lift-off layer when viewed from the first main surface side in the direction perpendicular to the surface of the semiconductor substrate. the first semiconductor layer and the lift-off layer are removed using
The lift-off layer has metal as a main component,
In the lift-off layer lamination step, the lift-off layer is formed to have a thickness of 20 nm or more and 250 nm or less. The method for manufacturing a solar cell according to any one of claims 1 to 4, wherein the lift-off layer contains 90% or more of a pure metal or a metal alloy. Production of the solar cell according to any one of claims 1 to 5, wherein the lift-off layer contains silver or a metal element having an atomic number of 5n+4 (n is an integer of 4 or more and 15 or less) as a main component. Method. 7. The method for manufacturing a solar cell according to claim 6, wherein the lift-off layer contains a metal element such as silver, copper, chromium, yttrium, indium, tungsten, gadolinium, or thulium as a main component. The method for manufacturing a solar cell according to any one of claims 1 to 7 , wherein the lift-off layer is formed by a physical vapor deposition method. The method for manufacturing a solar cell according to claim 8 , wherein the lift-off layer is formed by a vacuum evaporation method. The semiconductor substrate has a first texture structure on at least the first main surface,
The method for manufacturing a solar cell according to claim 1, wherein the first semiconductor layer and the second semiconductor layer include a second texture structure reflecting the first texture structure. The solar cell according to any one of claims 1 to 10 , wherein in the patterning step, etching is performed so that an edge of the lift-off layer is formed to be set back from an edge of the first semiconductor layer. manufacturing method. A first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first electrode layer, and a second electrode layer are provided on the first main surface side of the semiconductor substrate, and the semiconductor substrate and the first A method for manufacturing a solar cell, wherein the first semiconductor layer is interposed between electrode layers, and the second semiconductor layer is further interposed between the semiconductor substrate and the second electrode layer,
a first semiconductor layer forming step of forming the first semiconductor layer on the first main surface side of the semiconductor substrate;
a lift-off layer lamination step of laminating a lift-off layer on the first semiconductor layer;
Using two or more types of etching solutions having different etching rates for the lift-off layer, the etching area of the first semiconductor layer is equal to the etching area of the lift-off layer when viewed from the first main surface side in a direction perpendicular to the surface of the semiconductor substrate. a patterning step of removing a portion of each of the first semiconductor layer and the lift-off layer as follows,
The method for manufacturing a solar cell, wherein the lift-off layer contains metal as a main component.

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