JPWO2019163786A1 - How to manufacture solar cells - Google Patents

Abstract

A step of forming an n-type semiconductor layer (13n) on one main surface of a crystal substrate (11) including a p-type semiconductor layer (13p) and a lift-off layer (LF) selectively removed, and a lift-off layer (lift-off layer). The step of removing the n-type semiconductor layer (13n) covering the lift-off layer (LF) by removing the LF) and the transparency on each of the p-type semiconductor layer (13p) and the n-type semiconductor layer (13n). In the step of removing the lift-off layer (LF) including the step of forming the electrode layer (17), a part of the p-type semiconductor layer (13p) is a lift-off layer with the n-type semiconductor layer (13n) removed. The lift-off layer (LF) is removed so that it is covered by (LF).

Description

The technology disclosed herein belongs to the technical field relating to a method for manufacturing a solar cell.

A general solar cell is a double-sided electrode type in which electrodes are arranged on both sides (light receiving surface and back surface) of a semiconductor substrate, but these days, as a solar cell without shielding damage by the electrodes, as shown in Patent Document 1. , Back contact (back electrode) type solar cells in which electrodes are arranged only on the back surface have been developed.

The back contact type solar cell must form a semiconductor layer pattern such as a p-type semiconductor layer and an n-type semiconductor layer on the back surface with high accuracy, and the manufacturing method is complicated as compared with the double-sided electrode type solar cell. As a technique for simplifying the manufacturing method, as shown in Patent Document 1, a technique for forming a semiconductor layer pattern by a lift-off method can be mentioned. That is, the development of a patterning technique for forming a semiconductor layer pattern by removing the lift-off layer and removing the semiconductor layer formed on the lift-off layer is underway.

JP 2013-128063

However, in the method described in Patent Document 1, when the lift-off layer and the semiconductor layer have similar solubility, even an unintended layer may be removed, and the patterning accuracy and productivity may not be improved. is there.

Further, in a back contact type solar cell, a transparent electrode layer made of an oxide may be arranged between a semiconductor layer and a metal electrode layer, but at this time, peeling of the transparent electrode layer from the semiconductor layer becomes a problem. There is.

The technology disclosed here has been made in view of these points, and the purpose thereof is to provide a high-performance back-contact solar cell in which the adhesion between the electrode layer and the semiconductor layer is improved. It is to manufacture efficiently.

In order to solve the above problems, the techniques disclosed herein include a step of forming a first conductive type first semiconductor layer on one main surface of two main surfaces facing each other in a semiconductor substrate, and the above-mentioned. A step of laminating a lift-off layer on the first semiconductor layer, a step of selectively removing the first semiconductor layer and the lift-off layer, and a step of selectively removing the first semiconductor layer and the lift-off layer, and on one of the main surfaces including the first semiconductor layer and the lift-off layer. , A step of forming the second conductive type second semiconductor layer, a step of removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer, and the first semiconductor layer and the second semiconductor layer. In the step of forming a transparent electrode layer made of an oxide on each of the semiconductor layers and removing the lift-off layer, in a state where the second semiconductor layer covering the lift-off layer is removed, The lift-off layer is removed so that a part of the first semiconductor layer is covered with the lift-off layer.

According to the technique disclosed herein, a high-performance back-contact type solar cell having improved adhesion between the electrode layer and the semiconductor layer can be efficiently manufactured.

It is a schematic cross-sectional view which partially shows the solar cell which concerns on an exemplary embodiment. It is a top view which shows the back side main surface of the crystal substrate which constitutes a solar cell. It is a partial schematic cross-sectional view which shows one process of the manufacturing method of a solar cell. It is a partial schematic cross-sectional view which shows one process of the manufacturing method of a solar cell. It is a partial schematic cross-sectional view which shows one process of the manufacturing method of a solar cell. It is a partial schematic cross-sectional view which shows one process of the manufacturing method of a solar cell. It is a partial schematic cross-sectional view which shows one process of the manufacturing method of a solar cell. It is a partial schematic cross-sectional view which shows one process of the manufacturing method of a solar cell. It is a partial schematic cross-sectional view which shows one process of the manufacturing method of a solar cell. It is an enlarged cross-sectional view which enlarged a part of the p-type semiconductor layer at the end of lift-off. It is a partial schematic cross-sectional view which shows the lift layer which mixed the crystal grain. It is a partial schematic sectional view which shows the case where the lift-off layer is composed of two layers. It is a graph which shows the relationship between the coverage and the solar cell characteristic. It is a graph which shows the relationship between the refractive index and the solar cell characteristic.

Hereinafter, exemplary embodiments will be described with reference to the drawings.

FIG. 1 shows a partial cross-sectional view of a solar cell (cell) according to the present embodiment. As shown in FIG. 1, the solar cell 10 according to the present embodiment uses a crystal substrate 11 made of silicon (Si). The crystal substrate 11 has two main surfaces 11S (11SU, 11SB) facing each other. Here, the main surface on which light is incident is referred to as the front main surface 11SU, and the main surface on the opposite side is referred to as the back main surface 11SB. For convenience, the front side main surface 11SU has a side that positively receives light from the back side main surface 11SB as a light receiving side, and a side that does not positively receive light as a non-light receiving side.

The solar cell 10 according to the present embodiment is a so-called heterojunction crystalline silicon solar cell, which is a back contact type (back surface electrode type) solar cell in which an electrode layer is arranged on a back side main surface 11SB.

The solar cell 10 includes a crystal substrate 11, an intrinsic semiconductor layer 12, a conductive semiconductor layer 13 (p-type semiconductor layer 13p, n-type semiconductor layer 13n), a low-reflection layer 14, and an electrode layer 15 (transparent electrode layer 17, metal electrode). Includes layer 18).

In the following, for convenience, the members individually corresponding to the p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be suffixed with "p" or "n". Further, since the conductive type is different such as p type and n type, one conductive type may be referred to as "first conductive type" and the other conductive type may be referred to as "second conductive type".

The crystal substrate 11 may be a semiconductor substrate formed of single crystal silicon or a semiconductor substrate formed of polycrystalline silicon. In the following, a single crystal silicon substrate will be described as an example.

The conductive type of the crystal substrate 11 is an n-type single crystal silicon substrate in which an impurity that introduces an electron into a silicon atom (for example, a phosphorus (P) atom) is introduced, but a hole is introduced into the silicon atom. It may be a p-type single crystal silicon substrate into which impurities (for example, boron (B)) atoms to be introduced have been introduced. In the following, an n-type single crystal substrate, which is said to have a long carrier life, will be described as an example.

Further, the crystal substrate 11 has a texture structure TX (first texture structure) composed of peaks (convex) and valleys (concave) on the surfaces of the two main surfaces 11S from the viewpoint of confining the received light. May have. The texture structure TX (concavo-convex surface) is obtained by, for example, anisotropic etching in which the difference between the etching rate of the (100) plane and the etching rate of the (111) plane in the crystal substrate 11 is applied. Can be formed.

The size of the unevenness in the texture structure TX can be defined by, for example, the number of vertices. In the present embodiment, from the viewpoint of light uptake performance and productivity, the number of vertices is preferably in the range of 50,000 / mm ² or more and 100,000 / mm ² or less, and in particular, 70,000 / mm ² or more. It is preferably 85,000 pieces / mm ² or less.

The thickness of the crystal substrate 11 may be 250 μm or less. The measurement direction when measuring the thickness is the direction perpendicular to the average plane of the crystal substrate 11 (the average plane means the plane of the entire substrate that does not depend on the texture structure TX). From this point onward, this vertical direction, that is, the direction in which the thickness is measured is defined as the plane perpendicular direction.

When the thickness of the crystal substrate 11 is 250 μm or less, the amount of silicon used can be reduced, so that it becomes easier to secure the silicon substrate and the cost can be reduced. Moreover, a back contact structure in which holes and electrons generated by photoexcitation in a silicon substrate are recovered only on the back surface side is preferable from the viewpoint of the free path of each exciton.

On the other hand, if the thickness of the crystal substrate 11 is excessively small, the mechanical strength is lowered, the external light (sunlight) is not sufficiently absorbed, and the short-circuit current density is reduced. Therefore, the thickness of the crystal substrate 11 is preferably 50 μm or more, more preferably 70 μm or more. When the texture structure TX is formed on the main surface of the crystal substrate 11, the thickness of the crystal substrate 11 is represented by the distance between the straight lines connecting the convex vertices in the uneven structures on the light receiving side and the back surface side. Will be done.

The intrinsic semiconductor layer 12 (12U, 12p, 12n) covers both main surfaces 11S (11SU, 11SB) of the crystal substrate 11 to perform surface passivation while suppressing diffusion of impurities to the crystal substrate 11. The term "intrinsic (i-type)" is not limited to perfect authenticity that does not contain conductive impurities, and is "weak" that contains trace amounts of n-type impurities or p-type impurities within the range in which the silicon-based layer can function as an intrinsic layer. It also includes layers that are substantially true of "n-type" or "weak p-type".

The material of the intrinsic semiconductor layer 12 is not particularly limited, but may be an amorphous silicon-based thin film, and is a hydrogenated amorphous silicon-based thin film (a-Si: H thin film) containing silicon and hydrogen. May be good. The term "amorphous" as used herein means a structure having a long period and no order. That is, not only completely disordered but also those having order in a short cycle are included. Further, the intrinsic semiconductor layer 12 (12U, 12p, 12n) is not indispensable and may be appropriately formed as needed.

The thickness of the intrinsic semiconductor layer 12 is not particularly limited, but may be 2 nm or more and 20 nm or less. This is because when the thickness is 2 nm or more, the effect as a passivation layer is enhanced, and when the thickness is 20 nm or less, the deterioration of the conversion characteristics caused by the high resistance can be suppressed.

The method for forming the intrinsic semiconductor layer 12 is not particularly limited, but a plasma CVD (Plasma enhanced Chemical Vapor Deposition) method is used. According to this method, the passivation of the substrate surface can be effectively performed while suppressing the diffusion of impurities into the single crystal silicon. Further, in the plasma CVD method, an energy gap profile effective for recovering carriers can be formed by changing the hydrogen concentration in the layer of the intrinsic semiconductor layer 12 in the thickness direction.

The conditions for forming a thin film by the plasma CVD method include, for example, a substrate temperature of 100 ° C. or higher and 300 ° C. or lower, a pressure of 20 Pa or higher and 2600 Pa or lower, and a high frequency power density of 0.003 W / cm ² or higher and 0.5 W /. It may be cm ² or less.

In the case of the intrinsic semiconductor layer 12, the raw material gas used for forming the thin film is a silicon-containing gas such as monosilane (SiH ₄ ) and disilane (Si ₂ H ₆ ), or their gas and hydrogen (H _2). ) May be a mixed gas.

Incidentally, the above gas, methane _(CH 4), ammonia (NH ₃₎ or by the addition of monogermane (GeH ₄₎ gas including an element heterogeneous like, silicon carbide (SiC), silicon nitride (SiN _X ) Or by forming a silicon alloy such as silicon germanium (SIGe), the energy gap of the thin film may be appropriately changed.

Examples of the conductive semiconductor layer 13 include a p-type semiconductor layer 13p and an n-type semiconductor layer 13n. As shown in FIG. 1, the p-type semiconductor layer 13p is formed on a part of the back side main surface 11SB of the crystal substrate 11 via the intrinsic semiconductor layer 12p. The n-type semiconductor layer 13n is formed on the other part of the back side main surface of the crystal substrate 11 via the intrinsic semiconductor layer 12n. That is, the intrinsic semiconductor layer 12 is interposed between the p-type semiconductor layer 13p and the crystal substrate 11 and between the n-type semiconductor layer 13n and the crystal substrate 11 as intermediate layers that play a passivation role.

The thickness of each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n is not particularly limited, but may be 2 nm or more and 20 nm or less. This is because when the thickness is 2 nm or more, the effect as a passivation layer is enhanced, and when the thickness is 20 nm or less, the deterioration of the conversion characteristics caused by the high resistance can be suppressed.

The p-type semiconductor layer 13p and the n-type semiconductor layer 13n are arranged on the back side of the crystal substrate 11 so that the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are electrically separated via the intrinsic semiconductor layer 12. To. The width of the conductive semiconductor layer 13 may be 50 μm or more and 3000 μm or less, and may be 80 μm or more and 500 μm or less. Unless otherwise specified, the widths of the semiconductor layers 12 and 13 and the widths of the electrode layers 17 and 18 are the lengths of a part of each patterned layer, and the width of the patterned part is, for example, a linear part. It means the length in the direction orthogonal to the extension direction.

When the photoexciters (carriers) generated in the crystal substrate 11 are taken out through the conductive semiconductor layer 13, the holes have a larger effective mass than the electrons. Therefore, the width of the p-type semiconductor layer 13p may be narrower than that of the n-type semiconductor layer 13n from the viewpoint of reducing the transportation loss. For example, the width of the p-type semiconductor layer 13p may be 0.5 times or more and 0.9 times or less the width of the n-type semiconductor layer 13n, or 0.6 times or more and 0.8 times or less. May be good.

The p-type semiconductor layer 13p is a silicon layer to which a p-type dopant (boron or the like) is added, and may be formed of amorphous silicon from the viewpoint of suppressing impurity diffusion or suppressing series resistance. On the other hand, the n-type semiconductor layer 13n is a silicon layer to which an n-type dopant (phosphorus or the like) is added, and may be formed of an amorphous silicon layer in the same manner as the p-type semiconductor layer 13p.

As the raw material gas of the conductive semiconductor layer 13, a silicon-containing gas such as monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ), or a mixed gas of a silicon-based gas and hydrogen (H ₂ ) may be used. As the dopant gas, diborane (B ₂ H ₆ ) or the like is used for forming the p-type semiconductor layer 13p, and phosphine (PH ₃ ) or the like is used for forming the n-type semiconductor layer. Further, since the amount of impurities such as boron (B) and phosphorus (P) added may be very small, a mixed gas obtained by diluting the dopant gas with the raw material gas may be used.

Further, in order to adjust the energy gap of the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, different types such as methane (CH ₄ ), carbon dioxide (CO ₂ ), ammonia (NH ₃ ) or monogerman (GeH ₄ ) are used. The p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be alloyed by adding a gas containing the above elements.

The low reflection layer 14 is a layer that suppresses the reflection of light received by the solar cell 10. The material of the low reflective layer 14, if translucency of the material to transmit light, is not particularly limited, for example, silicon oxide _(SiO X), silicon nitride _(SiN X), zinc oxide (ZnO) or oxide Titanium (TIO _X ) can be mentioned. Further, as a method for forming the low reflection layer 14, for example, a resin material in which nanoparticles of an oxide such as zinc oxide or titanium oxide are dispersed may be applied.

The electrode layer 15 is formed so as to cover the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, respectively, and is electrically connected to each conductive type semiconductor layer 13. As a result, the electrode layer 15 functions as a transport layer for guiding carriers generated in the p-type semiconductor layer 13p or the n-type semiconductor layer 13n. The electrode layers 15p and 15n corresponding to the semiconductor layers 13p and 13n are arranged so as to be separated from each other to prevent a short circuit between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n.

Further, it is transparent from the viewpoint of electrical bonding with the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, or from the viewpoint of suppressing the diffusion of atoms with respect to both the semiconductor layers 13p and 13n of the metal as the electrode material. The electrode layer 15 made of a conductive oxide may be provided between the metal electrode layer and the p-type semiconductor layer 13p and between the metal electrode layer and the n-type semiconductor layer 13n, respectively.

In the present embodiment, the electrode layer 15 formed of the transparent conductive oxide is referred to as a transparent electrode layer 17, and the metal electrode layer 15 is referred to as a metal electrode layer 18. Further, as shown in the plan view of the back side main surface 11SB of the crystal substrate 11 shown in FIG. 2, the electrode layer formed on the back of the comb in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n having a comb tooth shape, respectively. Is referred to as a bus bar portion, and the electrode layer formed on the comb tooth portion may be referred to as a finger portion.

The transparent electrode layer 17 is not particularly restricted but includes materials such as zinc (ZnO) or indium oxide _(InO X), or various metal oxides in indium oxide, such as titanium oxide _(TiO X), tin oxide ( Examples thereof include transparent conductive oxides to which SnO _X ), tungsten oxide (WO _X ), molybdenum oxide (MoO _X ) and the like are added in an amount of 1% by weight or more and 10% by weight or less.

The thickness of the transparent electrode layer 17 may be 20 nm or more and 200 nm or less. Methods for forming a transparent electrode layer suitable for this thickness include, for example, a physical vapor deposition (PVD) method such as a sputtering method, or a metalorganic organic metal compound using a reaction between oxygen or water. Examples thereof include a chemical vapor deposition method (MOCVD: Metal-Organic Chemical Vapor Deposition).

The material of the metal electrode layer 18 is not particularly limited, and examples thereof include silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), and the like.

The thickness of the metal electrode layer 18 may be 1 μm or more and 80 μm or less. Examples of the method for forming the metal electrode layer 18 suitable for this thickness include a printing method in which the material paste is printed by inkjet or screen printing, or a plating method. However, the present invention is not limited to this, and when a vacuum process is adopted, a vapor deposition or sputtering method may be adopted.

Further, the width of the comb tooth portion in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n and the width of the metal electrode layer 18 formed on the comb tooth portion may be about the same. However, the width of the metal electrode layer 18 may be narrower than the width of the comb tooth portion. Further, the width of the metal electrode layer 18 may be wider than the width of the comb tooth portion as long as the structure prevents leakage between the metal electrode layers 18.

In the present embodiment, the intrinsic semiconductor layer 12, the conductive semiconductor layer 13, the low reflection layer 14, and the electrode layer 15 are laminated on the back side main surface 11SB of the crystal substrate 11, and the passivation and conductivity of each joint surface are formed. A predetermined annealing treatment is performed for the purpose of suppressing the generation of defect levels at the type semiconductor layer 13 and its interface and crystallizing the transparent conductive oxide in the transparent electrode layer 17.

Examples of the annealing treatment according to the present embodiment include an annealing treatment in which the crystal substrate 11 on which each of the above layers is formed is placed in an oven heated to 150 ° C. or higher and 200 ° C. or lower. In this case, the atmosphere in the oven may be the atmosphere, and more effective annealing treatment can be performed by using hydrogen or nitrogen. Further, this annealing treatment may be an RTA (Rapid Thermal Annealing) treatment in which the crystal substrate 11 on which each layer is formed is irradiated with infrared rays by an infrared heater.

[Solar cell manufacturing method]
Hereinafter, the method for manufacturing the solar cell 10 according to the present embodiment will be described with reference to FIGS. 3 to 9.

First, as shown in FIG. 3, a crystal substrate 11 having a texture structure TX on each of the front side main surface 11SU and the back side main surface 11SB is prepared.

Next, as shown in FIG. 4, for example, an intrinsic semiconductor layer 12U is formed on the front main surface 11SU of the crystal substrate 11. Subsequently, the low reflection layer 14 is formed on the formed intrinsic semiconductor layer 12U. The low reflective layer 14, from the viewpoint of light confinement, silicon nitride having a suitable light absorption coefficient and refractive index (SiN _X) or silicon oxide (SiO _X) is used.

Next, as shown in FIG. 5, an intrinsic semiconductor layer 12p using, for example, i-type amorphous silicon is formed on the back side main surface 11SB of the crystal substrate 11. Subsequently, the p-type semiconductor layer 13p is formed on the formed intrinsic semiconductor layer 12p. As a result, the p-type semiconductor layer 13p is formed on the back side main surface 11SB, which is one of the main surfaces of the crystal substrate 11. As described above, in the present embodiment, the step of forming the p-type semiconductor layer (first semiconductor layer) 13p is one of the crystal substrates (semiconductor substrates) 11 before forming the p-type semiconductor layer 13p. The step of forming an intrinsic semiconductor layer (first intrinsic semiconductor layer) 12p on the main surface (back side main surface) 11S is included.

Then, the lift-off layer LF is formed on the formed p-type semiconductor layer 13p. Specifically, a lift-off layer LF containing silicon oxide (SiOX) as a main component is formed on the p-type semiconductor layer 13p.

Next, as shown in FIG. 6, the lift-off layer LF and the p-type semiconductor layer 13p are patterned on the back side main surface 11SB of the crystal substrate 11. As a result, the p-type semiconductor layer 13p is selectively removed, and a non-formed region NA in which the p-type semiconductor layer 13p is not formed is generated. On the other hand, at least the lift-off layer LF and the p-type semiconductor layer 13p remain in the region not etched on the back side main surface 11SB of the crystal substrate 11.

Such a patterning step can be realized by a photolithography method, for example, by forming a resist film (not shown) having a predetermined pattern on the lift-off layer LF and etching a region masked by the formed resist film. .. As shown in FIG. 6, by patterning each layer of the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the lift-off layer LF, the non-formed region NA, that is, the back side is formed in a part of the back side main surface 11SB of the crystal substrate 11. An exposed area of the main surface 11SB is generated. The details of the non-formed region NA will be described later.

As the etching solution used in the step shown in FIG. 6, for example, a mixed solution of hydrofluoric acid and an oxidizing solution (for example, hydrofluoric acid) or a solution in which ozone is dissolved in hydrofluoric acid (hereinafter, ozone / hydrofluoric acid). Liquid). The etching solution in this case corresponds to the second etching solution. The etching agent that contributes to the etching of the lift-off layer LF is hydrogen fluoride. The patterning here is not limited to wet etching using an etching solution. The patterning may be, for example, dry etching or pattern printing using an etching paste or the like.

Next, as shown in FIG. 7, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n are placed on the back side main surface 11SB of the crystal substrate 11 including the lift-off layer LF, the p-type semiconductor layer 13p and the intrinsic semiconductor layer 12p. Form sequentially. As described above, in the present embodiment, the step of forming the n-type semiconductor layer (second semiconductor layer) 13n is performed before the n-type semiconductor layer 13n is formed, and the lift-off layer of the crystal substrate (semiconductor substrate) 11 is lifted off. The step of forming an intrinsic semiconductor layer (second intrinsic semiconductor layer) 12n on one main surface (back side main surface) 11S including an LF and a p-type semiconductor layer is included. As a result, the laminated film of the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n is formed on the non-formed region NA, the surface and side surfaces (end faces) of the lift-off layer LF, the lift-off layer LF, the p-type semiconductor layer 13p, and the intrinsic semiconductor. It is formed so as to cover the side surface (end surface) of the layer 12p.

Next, as shown in FIG. 8, the n-type semiconductor layer 13n and the intrinsic semiconductor layer 12n covering the lift-off layer LF are removed from the crystal substrate 11 by removing the laminated lift-off layer LF using an etching solution. As the etching solution used for this patterning, for example, hydrofluoric acid is used.

In the step shown in FIG. 8, the lift-off layer LF is removed so that a part of the p-type semiconductor layer 13p is covered with the lift-off layer LF. That is, as shown in FIG. 10, a part of the lift-off layer LF remains on the p-type semiconductor layer 13, and a part of the surface of the p-type semiconductor layer 13p opposite to the crystal substrate 11 remains. The lift-off layer LF is removed so that it is covered by the layer LF.

Next, as shown in FIG. 9, separation grooves are formed on the back side main surface 11SB of the crystal substrate 11, that is, on each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by, for example, a sputtering method using a mask. The transparent electrode layer 17 (17p, 17n) is formed so as to generate 25. The transparent electrode layer 17 (17p, 17n) may be formed as follows instead of the sputtering method. For example, a transparent conductive oxide film is formed on the entire surface of the back side main surface 11SB without using a mask, and then transparent conductivity is formed on the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by a photolithography method. It may be formed by etching leaving a sex oxide film. Here, by forming the separation groove 25 that separates and insulates the p-type semiconductor layer 13p and the n-type semiconductor layer 13n from each other, leakage is less likely to occur.

Then, a linear metal electrode layer 18 (18p, 18n) is formed on the transparent electrode layer 17 by using, for example, a mesh screen (not shown) having an opening.

By the above steps, the back surface bonded type solar cell 10 is formed.

(Summary and effect)
The following can be said from the above-mentioned manufacturing method of the solar cell 10.

First, in the step shown in FIG. 8, when the lift-off layer LF is removed by the etching solution, the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n deposited on the lift-off layer LF are also removed from the crystal substrate 11 at the same time. (So-called lift-off). This step does not require the resist coating step and the developing step used in the photolithography method as compared with the step shown in FIG. 6, for example, when the photolithography method is used. Therefore, the n-type semiconductor layer 13n is easily patterned.

Further, since a part of the p-type semiconductor layer 13p is covered with the lift-off layer LF, the adhesion of the transparent electrode layer 17 in the region of the p-type semiconductor layer 13p is improved. That is, if a part of the lift-off layer LF (hereinafter referred to as the covering portion 19) remains as a residue on the p-type semiconductor layer 13p, the surface area increases by the amount of the covering portion 19, and in the region of the p-type semiconductor layer 13p. , The contact area of the transparent electrode layer 17 becomes wider. Further, for example, when the transparent electrode layer 17 is composed of tin oxide-indium oxide (ITO), silicon oxide has higher adhesion to ITO than silicon, so that the coating portion 19 containing silicon oxide as a main component If there is, the transparent electrode layer 17 is less likely to be peeled off from the p-type semiconductor layer 13p. As a result, the adhesion of the transparent electrode layer 17 in the region of the p-type semiconductor layer 13p is improved.

On the other hand, if the number of covering portions 19 is too large, the contact area between the transparent electrode layer 17 and the p-type semiconductor layer 13p decreases, so that the series resistance between the transparent electrode layer 17 and the p-type semiconductor layer 13p increases. The IV characteristics of the solar cell 10 may deteriorate. Therefore, when the area of the portion of the p-type semiconductor layer 13p covered by the covering portion 19 is S1 and the area of the entire surface of the p-type semiconductor layer 13p opposite to the crystal substrate 11 is S2, the following formula:
(Coverage (%)) = 100 x S1 / S2
The coverage defined in is preferably 0.2% or more and 16% or less. When the coverage is 0.2% or more and 16% or less, the contact area between the transparent electrode layer 17 and the p-type semiconductor layer 13p can be suitably secured while improving the adhesion of the transparent electrode layer 17.

Further, even if the coverage is 0.2% or more and 16% or less, if there is a locally large covering portion 19, excitons in the p-type semiconductor layer 13p (in the case of a p-type semiconductor, positive). Due to the relationship between the effective mass of the holes) and the free stroke, the excitons may not be properly recovered from the p-type semiconductor layer 13p. Therefore, it is preferable that the maximum length of the covering portion 19 is 2.0 μm or less when viewed from the back mold main surface SB11 side in the direction perpendicular to the surface of the crystal substrate 11. As a result, excitons can be appropriately recovered from the p-type semiconductor layer 13p while improving the adhesion of the transparent electrode layer 17.

The coverage can be adjusted, for example, by devising a step of depositing the lift-off layer LF on the p-type semiconductor layer 13p. Specifically, as shown in FIG. 12, when the lift-off layer LF is deposited on the p-type semiconductor layer 13p, particles composed of elements constituting the lift-off layer LF (here, silicon particles or silicon oxide particles). Hereinafter, crystal grains 20) are mixed. Generally, the lift-off layer LF is made of amorphous so that it can be easily etched during lift-off. Since the etching rate of the crystal grains 20 is slower than that of the amorphous due to the influence of density and the like, even if the amorphous portion in the lift-off layer LF is melted, the crystal grains 20 are not melted and remain on the p-type semiconductor layer 13p. Can be done. Therefore, the coverage can be adjusted by adjusting the amount of crystal grains to be mixed.

Further, when the lift-off layer LF contains silicon oxide as a main component as in the present embodiment, the coverage can be adjusted by adjusting the refractive index of the lift-off layer LF. That is, the refractive index is proportional to the density, and when the refractive index is high, the density is basically high. As the density increases, the etching rate decreases, so that the covering portion 19 is likely to occur. Therefore, if the refractive index of the lift-off layer LF is increased, the covering ratio can be increased. From the viewpoint of reducing the coverage to 0.2% or more and 16% or less, the refractive index preferably has a value of 1.45 or more and 1.90 or less in light having a wavelength of 632 nm.

In the lift-off layer LF containing silicon oxide as a main component, the refractive index can be adjusted, for example, by adjusting the pressure in the film formation using the CVD method. Specifically, by increasing the pressure, it becomes easy to obtain a dense structure, and it becomes easy to obtain a lift-off layer LF having a high refractive index.

The method of mixing crystal grains into the lift-off layer LF and the method of adjusting the refractive index of the lift-off layer LF may be used alone or both.

In both the method of mixing the crystal grains 20 into the lift-off layer LF and the method of adjusting the refractive index of the lift-off layer LF, it is preferable that the lift-off layer LF is composed of a plurality of layers. For example, as shown in FIG. 12, the lift-off layer LF is two, a first lift-off layer LF1 laminated on the p-type semiconductor layer 13p and a second lift-off layer LF2 laminated on the first lift-off layer LF1. When composed of layers, only the first lift-off layer LF1 of the two layers is mixed with crystal grains 20 or has a high refractive index. Thereby, the coverage can be adjusted while shortening the time required for removing the lift-off layer LF as much as possible. When the lift-off layer LF is composed of a plurality of layers, the lift-off layer LF may be composed of three or more layers, but it is preferably composed of two layers in consideration of manufacturing cost and productivity.

Regardless of whether the lift-off layer LF is singular or plural, the film thickness of the lift-off layer LF is preferably 20 nm or more and 600 nm or less as a whole, and particularly preferably 50 nm or more and 450 nm or less. When there are a plurality of lift-off layers LF, it is preferable that the thick film of the layer closest to the p-type semiconductor layer 13p is the thinnest within this range.

Further, the crystal substrate 11 has a texture structure TX, and each surface of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n formed on the back side main surface 11SB of the crystal substrate 11 has a texture structure TX. It is preferable that a texture structure (second texture structure) reflecting the above is included.

When the conductive semiconductor layer 13 has the texture structure TX on the surface, the etching solution easily permeates into the semiconductor layer 13 due to the unevenness of the texture structure TX. Therefore, the conductive semiconductor layer 13 is easily removed, that is, it is easily patterned.

In the present embodiment, the texture structure TX (first texture structure) is provided on both main surfaces 11S of the crystal substrate 11, that is, the front side main surface 11SU and the back side main surface 11SB, but one of the main surfaces is provided. It may be provided in. That is, when the texture structure TX is provided on the front main surface 11SU, the effect of capturing and confining the received light is enhanced. On the other hand, when the texture structure TX is provided on the back side main surface 11SB, the light uptake effect is improved and the patterning of the conductive semiconductor layer 13 becomes easy. Therefore, the texture structure TX of the crystal substrate 11 may be provided on at least one main surface 11S. Further, in the present embodiment, the texture structure TX of both main surfaces 11S has the same pattern, but the pattern is not limited to this, and the size of the unevenness of the texture structure TX is changed between the front main surface 11SU and the back main surface 11SB. May be good.

In the step shown in FIG. 6, the back side main surface 11SB of the crystal substrate 11 is exposed in the non-formed region NA, but the present invention is not limited to this. That is, the intrinsic semiconductor layer 12p may remain on the non-formed region NA of the back side main surface 11SB. The p-type semiconductor layer 13p is selectively removed, and the region from which the p-type semiconductor layer 13p is removed may be the non-forming region NA.

In such a case, the step of forming the intrinsic semiconductor layer 12n before depositing the n-type semiconductor layer 13n on the remaining lift-off layer LF and the non-forming region NA can be reduced.

Further, for example, when the lift-off layer LF is composed of two layers, the first lift-off layer LF1 and the second lift-off layer LF2, in the step shown in FIG. 6, an opening is formed in the second lift-off layer LF2 and etching is performed. The liquid may be attached to the first lift-off layer LF1 through the formed opening, and the layer to which the etching solution is attached may be removed. Further, in the step shown in FIG. 6, the lift-off layer LF is removed as described above, and the etching solution is also attached to the p-type semiconductor layer 13p to remove the p-type semiconductor layer 13p to which the etching solution is attached. May be good. The formation of this opening includes, for example, the generation of cracks.

By forming an opening in the second lift-off layer LF2 and passing the etching solution through the opening in this way, the etching solution is surely adhered to the second lift-off layer LF2 and further to the first lift-off layer LF1. Therefore, the entire lift-off layer LF is efficiently removed. Further, by removing the lift-off layer LF, the etching solution is surely adhered to the p-type semiconductor layer 13p covered with the lift-off layer LF, so that the p-type semiconductor layer 13p is also removed. As a result, the undissolved residue of the lift-off layer LF and the p-type semiconductor layer 13p is suppressed.

The technique disclosed herein is not limited to the above-described embodiment, and can be substituted without departing from the gist of the claims.

For example, in the above-described embodiment, the semiconductor layer used in the step shown in FIG. 5 is the p-type semiconductor layer 13p, but the present invention is not limited to this, and the n-type semiconductor layer 13n may be used. Further, the conductive type of the crystal substrate 11 is not particularly limited, and may be a p type or an n type.

The above embodiments are merely exemplary and should not be construed as limiting the scope of the techniques disclosed. The scope of the technology of the present disclosure is defined by the scope of claims, and all modifications and modifications belonging to the equivalent scope of the scope of claims are within the scope of the technology of the present disclosure.

Hereinafter, the technique according to the present disclosure will be specifically described with reference to Examples. However, the technique according to the present disclosure is not limited to these examples. Examples and comparative examples were prepared as follows (see [Table 1]). In the following description, in Examples 1 to 3 and Comparative Examples 1 to 3, those having the same conditions are not particularly distinguished.

[Crystal substrate]
First, as the crystal substrate, a single crystal silicon substrate having a thickness of 200 μm was adopted. Anisotropic etching was performed on both main surfaces of the single crystal silicon substrate. As a result, a pyramid-shaped texture structure was formed on the crystal substrate.

[Intrinsic semiconductor layer]
The crystal substrate was introduced into the CVD apparatus, and an intrinsic semiconductor layer (thickness 8 nm) made of silicon was formed on both main surfaces of the introduced crystal substrate. Deposition conditions are substrate temperature 0.99 ° C., pressure 120 Pa, the value of _SiH 4 / _{H 2} flow ratio 3/10, and the power density was 0.011W / cm ^2.

[P-type semiconductor layer (first conductive semiconductor layer)]
A crystal substrate having an intrinsic semiconductor layer formed on both main surfaces was introduced into a CVD apparatus, and a p-type hydrogenated amorphous silicon-based thin film (thickness 10 nm) was formed on the intrinsic semiconductor layer on the back main surface. The film forming conditions were a substrate temperature of 150 ° C., a pressure of 60 Pa, a SiH ₄ / B ₂ H ₆ flow rate ratio value of 1/3, and a power density of 0.01 W / cm ² . _The flow rate of B 2 _{H 6} gas _is the flow rate of the diluent gas B 2 _{H 6} was diluted by _{H 2} to 5000 ppm.

[Lift-off layer]
Using a plasma CVD apparatus, a lift-off layer containing silicon oxide (SiO _X ) as a main component was formed on a p-type hydrogenated amorphous silicon-based thin film so as to have a film thickness of 200 nm.

In Example 1, the film forming conditions of the lift-off layer are a substrate temperature of 150 ° C., a pressure of 50 Pa, a SiH ₄ / CO ₂ / H ₂ flow rate ratio value of 1/10/750, and a power density of 0.15 W /. It was set to cm ² . In Example 2, the value of the SiH ₄ / CO ₂ / H ₂ flow rate ratio was set to 1/10/650, and the other conditions were the same film forming conditions as in Example 1. In Example 3, the value of the SiH ₄ / CO ₂ / H ₂ flow rate ratio was set to 1/10/550, and the other conditions were the same film forming conditions as in Example 1.

In Comparative Example 1, the film forming conditions were the same as those of Examples 1 to 3 except that the value of the SiH ₄ / CO ₂ / H ₂ flow rate ratio was set to 1/4/750.

In Comparative Example 2, the film forming conditions were the same as those in Examples 1 to 3 except that the value of the SiH ₄ / CO ₂ / H ₂ flow rate ratio was set to 1/30/1000.

In Comparative Example 3, the film forming conditions were the same as those of Examples 1 to 3 except that the value of the SiH ₄ / CO ₂ / H ₂ flow rate ratio was set to 1/10/350.

[Patterning of lift-off layer and first conductive semiconductor layer]
First, a photosensitive resist film was formed on the back main surface of the crystal substrate on which the lift-off layer was formed. This was exposed and developed by a photolithography method to expose a region from which the lift-off layer, the p-type semiconductor layer and the intrinsic semiconductor layer were removed. The crystal substrate on which the plurality of layers were formed was immersed in hydrous nitric acid containing 1% by weight of hydrogen fluoride as an etching agent to remove the lift-off layer. After rinsing with pure water, the p-type semiconductor layer exposed by removing the lift-off layer by immersing it in an ozone / hydrofluoric acid solution in which 20 ppm of ozone is mixed with 5.5% by weight of hydrofluoric acid and the intrinsic semiconductor layer immediately below it. And was removed. Hereinafter, this step is referred to as a patterning step.

[N-type semiconductor layer (second conductive semiconductor layer)]
After the first semiconductor layer patterning step, a crystal substrate in which the exposed back side main surface is washed with hydrofluoric acid having a concentration of 2% by weight is introduced into the CVD apparatus, and an intrinsic semiconductor layer (thickness 8 nm) is formed on the back side main surface. It was formed under the same film forming conditions as the first intrinsic semiconductor layer. Subsequently, an n-type hydrogenated amorphous silicon-based thin film (thickness: 10 nm) was formed on the formed intrinsic semiconductor layer. The film forming conditions were a substrate temperature of 150 ° C., a pressure of 60 Pa, a SiH ₄ / PH ₃ / H ₂ flow rate ratio of 1/2, and a power density of 0.01 W / cm ² . The flow rate of the PH ₃ gas is the flow rate of the diluent gas PH ₃ is diluted by _{H 2} to 5000 ppm.

[Removal of lift-off layer and second conductive semiconductor layer]
A crystal substrate on which an n-type semiconductor layer is formed is immersed in 5% by weight of hydrofluoric acid to form a lift-off layer, an n-type semiconductor layer covering the lift-off layer, and between the lift-off layer and the n-type semiconductor layer. Certain intrinsic semiconductor layers were removed together. Hereinafter, this process is referred to as a lift-off process.

[Electrode layer, low reflection layer]
Using a magnetron sputtering apparatus, an oxide film (thickness 100 nm) as a base of the transparent electrode layer was formed on the conductive semiconductor layer of the crystal substrate. Further, as a low reflection layer, a silicon nitride layer was formed on the light receiving surface side of the crystal substrate. As the transparent conductive oxide, indium oxide (ITO) containing tin oxide at a concentration of 10% by weight was used as a target. A mixed gas of argon and oxygen was introduced into the chamber of the apparatus, and the pressure in the chamber was set to 0.6 Pa. The mixing ratio of argon and oxygen was set to the condition where the resistivity was the lowest (so-called bottom). Further, a film was formed at a power density of 0.4 W / cm ² using a DC power supply.

Next, a transparent electrode layer was formed by etching by a photolithography method so as to leave only the transparent conductive oxide film on the conductive semiconductor layer (p-type semiconductor layer and n-type semiconductor layer). The transparent electrode layer formed by this etching prevented the conduction between the transparent conductive oxide film on the p-type semiconductor layer and the transparent conductive oxide film on the n-type semiconductor layer.

Further, the silver paste (Fujikura Kasei Co., Ltd .: Dotite FA-333) was screen-printed on the transparent electrode layer without dilution, and heat-treated in an oven at a temperature of 150 ° C. for 60 minutes. As a result, a metal electrode layer was formed.

Next, an evaluation method for a back contact type solar cell will be described. For the evaluation results, refer to [Table 1], FIGS. 13 and 14.

[Evaluation of film thickness and etchability]
The film thickness or etching state of the lift-off layer was evaluated using an SEM (field emission scanning electron microscope S4800: manufactured by Hitachi High-Technologies Corporation). After the first semiconductor layer patterning step, if it is etched according to the patterning removal region in the design, it is marked with "○", and if the lift-off layer is excessively etched and the solar cell characteristics are adversely affected, it is marked with "x". And said.

[Evaluation of refractive index]
The refractive index of the lift-off layer is the refractive index of a thin film formed on a glass substrate under the same conditions as those of Examples 1 to 3 and Comparative Examples 1 to 3 by spectroscopic ellipsometry (trade name M2000, J.・ Obtained by measuring with A-Woolam). From the fitting results, the refractive index of light having a wavelength of 632 nm was extracted.

[Evaluation of coverage]
The back surface of the crystal substrate after the lift-off step was observed with a laser microscope (device name: OPTELICS, manufactured by Lasertec) at a magnification of 100 times on the surface of the first conductive semiconductor layer. The covering portion and the first conductive semiconductor layer were color-coded by image processing, and the area of the portion covered by the covering portion in the first conductive semiconductor layer was calculated. Then, the area of the portion of the first conductive semiconductor layer covered with the covering portion is S1, and the area of the entire surface of the first conductive semiconductor layer opposite to the crystal substrate is S2.
(Coverage (%)) = 100 x S1 / S2
The coverage was calculated by

[Evaluation of adhesion]
An adhesive tape specified in JIS Z1522 was attached to the solar cell on which the electrode was formed, and the evaluation was performed by pulling it vertically. If the electrode layer was peeled off when it was pulled, it was marked with "x", and if the electrode layer was not peeled off, it was marked with "○".

[Evaluation of IV characteristics]
The IV curve was observed when the standard sunlight of AM (air mass) 1.5 was irradiated with a light amount of 100 mW / cm ² . When scanning at -1.0V to + 1.5V and the IV curve is S-shaped (when there is an extreme point in the range of -1.0V to + 1.5V), "x" If no S-shaped change was observed in the IV curve, it was marked as "○".

[Evaluation of conversion efficiency]
The conversion efficiency (Eff (%)) of the solar cell was measured by irradiating the reference sunlight of AM (air mass) 1.5 with a light amount of 100 mW / cm ² by a solar simulator. The conversion efficiency (solar cell characteristics) of Example 1 was set to 1.00, and the relative values thereof are shown in [Table 1].

[Reliability evaluation]
A module in which a solar cell having electrodes formed was laminated with glass and a back sheet was put into an environmental test at a temperature of 85 ° C. and a humidity of 85%, and the conversion efficiency (Eff (%)) after 3000 hours was measured. The conversion efficiency was measured by irradiating the reference sunlight of AM (air mass) 1.5 with a light amount of 100 mW / cm ² by a solar simulator. The initial conversion efficiency was set to 1.00, and the relative values thereof are shown in [Table 1].

Examples 1 to 3 were good in all of electrode adhesion, IV characteristics, solar cell characteristics and reliability.

Looking at the results of Examples 1 to 3 and Comparative Examples 1 to 3, it was confirmed that the adhesion of the electrode layer was good for those having a covering portion (those other than Comparative Example 2). .. On the other hand, it was found that when the coverage is too high, the IV characteristics deteriorate and the solar cell identification deteriorates. It is considered that this is because excitons cannot be taken out from the portion of the first conductive semiconductor layer covered with the coating portion. That is, it was confirmed that the coverage must be in an appropriate range in order to improve the adhesion of the electrode layer and suppress the deterioration of the solar cell characteristics. With reference to FIG. 13, when the solar cell characteristic of Example 1 is 1.00, in order to make the solar cell characteristic 0.80 or more, the coverage should be 0.2% or more and 16% or less. It turns out to be good. For this reason, in the technique of the present disclosure, a range of 0.2% or more and 16% or less is a preferable range of the coverage ratio.

Further, looking at the results of Examples 1 to 3 and Comparative Examples 1 to 3, it was confirmed that the higher the refractive index of the lift-off layer, the higher the coverage. It is considered that this is because the higher the refractive index, the higher the density and the more difficult it is to dissolve during etching. Furthermore, it was found that if the refractive index is too low, the lift-off layer is excessively etched in the patterning process. It is considered that this is because the density became low, the structure of the lift-off layer became sparse, and the dissolution rate during etching increased. With reference to FIG. 14, when the solar cell characteristic of Example 1 is 1.00, the refractive index of light having a wavelength of 632 nm is 1.45 or more and 1 in order to make the solar cell characteristic 0.80 or more. It can be seen that the value should be 90 or less. For this reason, in the technique of the present disclosure, the range of 1.45 or more and 1.90 or less is considered to be a preferable range of the refractive index.

In summary, it was found that by covering a part of the first conductive semiconductor layer with a lift-off layer, the electrical contact (adhesion) between the first conductive semiconductor layer and the electrode layer is improved. .. In particular, it was obtained that the solar cell characteristics of the examples were improved by setting the coverage in an appropriate range as compared with the comparative examples. This improves the adhesion between the first conductive semiconductor layer and the electrode layer by appropriately leaving the substance (here, silicon oxide) constituting the lift-off layer on the first conductive semiconductor layer. It is considered that not only this, but also the increase in series resistance is suppressed.

Further, it was obtained that the covering ratio can be set in the appropriate range by setting the refractive index of the lift-off layer to an appropriate value. In particular, if the refractive index of the lift-off layer is too low, the lift-off layer is excessively removed in the patterning step, resulting in the inability to obtain sufficient solar cell characteristics. It was found that there is a problem in reliability especially for those with poor adhesion.

10 Solar cell 11 Crystal substrate (semiconductor substrate)
12 Intrinsic semiconductor layer 13 Conductive semiconductor layer 13pp type semiconductor layer [1st conductive type 1st semiconductor layer / 2nd conductive type 2nd semiconductor layer]
13n n-type semiconductor layer [second conductive type second semiconductor layer / first conductive type first semiconductor layer]
15 Electrode layer 17 Transparent electrode layer 18 Metal electrode layer 19 Coating part 20 Crystal grains (grains composed of crystals of substances constituting the lift-off layer)
LF lift-off layer

Claims (7)

A step of forming a first conductive type first semiconductor layer on one main surface of two main surfaces facing each other in a semiconductor substrate,
The step of laminating the lift-off layer on the first semiconductor layer and
A step of selectively removing the first semiconductor layer and the lift-off layer, and
A step of forming a second conductive type second semiconductor layer on the one main surface including the first semiconductor layer and the lift-off layer, and
A step of removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer, and a step of removing the second semiconductor layer.
A step of forming a transparent electrode layer made of an oxide on each of the first semiconductor layer and the second semiconductor layer is included.
In the step of removing the lift-off layer, the lift-off layer is removed so that a part of the first semiconductor layer is covered with the lift-off layer in a state where the second semiconductor layer covering the lift-off layer is removed. How to manufacture solar cells. In the method for manufacturing a solar cell according to claim 1,
The lift-off layer that covers the first semiconductor layer is used as a covering portion, the area of the portion of the first semiconductor layer covered by the covering portion is defined as S1, and the area of the first semiconductor layer opposite to that of the semiconductor substrate is defined as S1. When the area of the surface is S2, the following formula:
(Coverage (%)) = 100 x S1 / S2
A method for manufacturing a solar cell having a coverage of 0.2% or more and 16% or less as defined in. In the method for manufacturing a solar cell according to claim 2.
A method for manufacturing a solar cell in which the maximum length of the covering portion is 2.0 μm or less when viewed from the one main surface side in the direction perpendicular to the surface of the semiconductor substrate. In the method for manufacturing a solar cell according to any one of claims 1 to 3.
A method for manufacturing a solar cell, wherein the lift-off layer contains silicon oxide as a main component and has a refractive index of 1.45 or more and 1.90 or less in light having a wavelength of 632 nm. In the method for manufacturing a solar cell according to claim 4,
The lift-off layer is composed of a plurality of layers.
Of the plurality of layers constituting the lift-off layer, the layer closest to the first semiconductor layer contains silicon oxide as a main component and has a refractive index of 1.45 or more and 1.90 or less in light having a wavelength of 632 nm. A method of manufacturing a solar cell composed of. In the method for manufacturing a solar cell according to any one of claims 1 to 5.
In the step of laminating the lift-off layer on the first semiconductor layer, when the lift-off layer is laminated when the lift-off layer is singular, when the lift-off layer is plural, the first semiconductor layer is the most. A method for manufacturing a solar cell in which particles composed of elements constituting the lift-off layer are mixed with the lift-off layer when stacking close layers. In the method for manufacturing a solar cell according to any one of claims 1 to 6.
The semiconductor substrate has a first texture structure on each of the two main surfaces.
A method for manufacturing a solar cell, wherein the first semiconductor layer and the second semiconductor layer formed on one of the main surfaces of the semiconductor substrate include a second texture structure reflecting the first texture structure.

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