CN106449850B - A kind of efficient silicon based hetero-junction double-side cell and preparation method thereof - Google Patents
A kind of efficient silicon based hetero-junction double-side cell and preparation method thereof Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 110
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 110
- 239000010703 silicon Substances 0.000 title claims abstract description 110
- 238000002360 preparation method Methods 0.000 title claims abstract description 26
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 213
- 239000002184 metal Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims description 26
- 238000005229 chemical vapour deposition Methods 0.000 claims description 23
- 238000000151 deposition Methods 0.000 claims description 17
- 230000008021 deposition Effects 0.000 claims description 13
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 10
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 7
- 230000004044 response Effects 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 238000005240 physical vapour deposition Methods 0.000 claims 3
- 229910021419 crystalline silicon Inorganic materials 0.000 abstract description 9
- 230000004888 barrier function Effects 0.000 abstract description 4
- 150000001875 compounds Chemical class 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 76
- 239000007789 gas Substances 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008033 biological extinction Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002674 ointment Substances 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
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- 230000005611 electricity Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000000686 essence Substances 0.000 description 1
- 239000008246 gaseous mixture Substances 0.000 description 1
- 235000008216 herbs Nutrition 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- 239000002210 silicon-based material Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 210000002268 wool Anatomy 0.000 description 1
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- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
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- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
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- Y02E10/00—Energy generation through renewable energy sources
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Abstract
The invention discloses a kind of efficient silicon based hetero-junction double-side cell and preparation method thereof, wherein a kind of efficient silicon based hetero-junction double-side cell, including：N-type silicon chip；It is sequentially equipped with the first intrinsic amorphous silicon layer, the second intrinsic amorphous silicon layer, p-type doped amorphous silicon layer, transparent conductive film layer, metal grid lines electrode in the front of the N-type silicon chip；The electronic band gap of second intrinsic amorphous silicon layer is more than the first intrinsic amorphous silicon layer；It is sequentially equipped with third intrinsic amorphous silicon layer, n-type doping amorphous silicon layer, transparent conductive film layer, metal grid lines electrode in the reverse side of the N-type silicon chip.The present invention by the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer respectively in different chambers prepare complete, the preparation temperature of first intrinsic amorphous silicon layer is higher than the preparation temperature of the second intrinsic amorphous silicon layer, so that the second intrinsic amorphous silicon layer has relatively wide electronic band gap, it corresponds to the energy gap of crystalline silicon, therefore can be used as barrier layer stops electrons spread to emitter using the difference of bandwidth, reduce the compound of electronics and hole, to improve the electric property of cell piece.
Description
Technical field
The present invention relates to area of solar cell more particularly to a kind of efficient silicon based hetero-junction double-side cell and its preparation sides
Method.
Background technology
Thin-film solar cells is a kind of solar cell for depositing very thin photoelectric material on substrate and being formed.Film is too
Positive can still to generate electricity under battery low light condition, low energy consumption for production process, has and the latent of raw material and manufacturing cost is greatly lowered
Power, therefore, demand of the market to thin-film solar cells just gradually increase, and thin film solar cell technologies are even more to become in recent years
The research hotspot come.Photoelectric conversion efficiency is wherein improved, the ultimate aim that cost is solar energy industry is reduced.
Recently as the cost reduction of silicon materials, make silica-based solar cell more attractive.In order to improve silicon substrate too
The transfer efficiency of positive energy battery：Two of which technology has been widely studied and applied to large-scale production.One is lattice before removing
Grid and busbar integrate emitter and collector to the back side and integrate, referred to as interdigital back-contact electrode (IBC)；The other is being based on
Heteroj unction technologies increase open-circuit voltage, are primarily due to the electronic band gap of thin film amorphous silicon than crystalline silicon higher.Thin film silicon contains
There is hydrogen, is typically deposited to the surface of crystal silicon chip by the method for chemical vapor deposition, thickness is less than 10nm, for being passivated
The dangling bonds of silicon face.The advantages of heteroj unction technologies is simple for process, the outer positive and negative symmetrical configuration of viewing to form PN junction, therefore just
Anti- two sides can extinction, by optimize cell piece placed angle, reverse side also can absorb environment in scattering light for increase it is short
Road electric current so that cell piece output power can increase by 10~20%.
Silicon/crystalline silicon heterojunction solar battery generally use N-type crystalline silicon is primarily due to N-type crystalline silicon containing miscellaneous as substrate
Matter is few, and universal minority carrier life time is high, high because contacting the built-in field in the PN junction formed with P-type non-crystalline silicon film layer, so more holding
The height for easily obtaining cell piece opens pressure.Due to built-in field height, it is also easier to the carrier generated in separation PN junction and in crystalline silicon
That is electrons and holes, but due to the diffusion of electronics, electronics can also be moved to emitter, to cause electronics and hole to exist
Emitter region it is compound, reduce the short circuit current of cell piece, reduce the photoelectric conversion efficiency i.e. output power of cell piece.
Invention content
In order to solve the problems in the prior art, the object of the present invention is to provide a kind of efficient silicon based hetero-junction double-side cells
And preparation method thereof, it can be very good to prevent electrons spread in carrier to emitter region, reduce answering for electronics and hole
It closes, to increase the short circuit current of cell piece.
To achieve the above object, the present invention uses following technical scheme：
A kind of efficient silicon based hetero-junction double-side cell, including：N-type silicon chip；It is sequentially equipped with the in the front of the N-type silicon chip
One intrinsic amorphous silicon layer, the second intrinsic amorphous silicon layer, p-type doped amorphous silicon layer, transparent conductive film layer, metal grid lines electrode；Institute
The electronic band gap for stating the second intrinsic amorphous silicon layer is more than the first intrinsic amorphous silicon layer；It is sequentially equipped in the reverse side of the N-type silicon chip
Third intrinsic amorphous silicon layer, n-type doping amorphous silicon layer, transparent conductive film layer, metal grid lines electrode.
Preferably, the thickness of the second intrinsic amorphous silicon film layer is less than 1nm, the first intrinsic amorphous silicon film layer and third sheet
The thickness for levying amorphous silicon film layer is respectively 5-10nm, the thickness difference of the p-type doped amorphous silicon layer and n-type doping amorphous silicon layer
For 5-10nm, the thickness for being located at the positive transparent conductive film of N-type silicon chip is 70-110nm, is located at the transparent of N-type silicon chip reverse side and leads
The thickness of electrolemma is 25-110nm.
The present invention also provides a kind of preparation methods of efficient silicon based hetero-junction double-side cell, include the following steps：It provides
One N-type silicon chip；Under the first temperature condition, respectively by chemical vapour deposition technique on the tow sides of N-type silicon chip, deposition the
One intrinsic amorphous silicon film layer and third intrinsic amorphous silicon film layer；The deposited n-type doped amorphous silicon layer in third intrinsic amorphous silicon layer；
Under the conditions of second temperature, the second intrinsic amorphous silicon film layer and p-type doped amorphous silicon are deposited in the first intrinsic amorphous silicon film layer
The electronic band gap of layer, second intrinsic amorphous silicon layer is more than the first intrinsic amorphous silicon layer；Respectively in p-type doped amorphous silicon layer and
Pass through PVD magnetron sputtering deposition transparent conductive films on n-type doping amorphous silicon layer；In the electrically conducting transparent of the tow sides of N-type silicon chip
Metal grid lines electrode is formed on film.
Preferably, described intrinsic non-by chemical vapor deposition first respectively on the tow sides of N-type silicon chip
Crystal silicon film layer and third intrinsic amorphous silicon film layer are specially：It is past by N-type silicon chip placing response chamber under the first temperature condition
SiH is passed through in reaction chamber4And H2Mixed gas, be sequentially depositing on the tow sides of N-type silicon chip by chemical vapour deposition technique
Form the first intrinsic amorphous silicon film layer and third intrinsic amorphous silicon film layer.
Preferably, the deposited n-type doped amorphous silicon layer in third intrinsic amorphous silicon layer is specially：First will be formed
The N-type silicon chip of sign amorphous silicon film layer and third intrinsic amorphous silicon film layer is put into the first doping intracavitary, is passed through into the first doping chamber
SiH4、H2And the gas containing dopant, the thus deposited n-type doped amorphous silicon layer in third intrinsic amorphous silicon layer.
Preferably, described that the second intrinsic amorphous silicon film layer and p-type doping amorphous are deposited in the first intrinsic amorphous silicon film layer
Silicon layer is specially：Under the conditions of second temperature, the N-type silicon of n-type doping amorphous silicon layer will be formed in third intrinsic amorphous silicon layer
Piece is put into the second doping intracavitary, is first passed through SiH in the second doping intracavitary4And H2Mixed gas, pass through the side of chemical vapor deposition
After method deposits the second intrinsic amorphous silicon film layer in the first intrinsic amorphous silicon film layer；Continue to be passed through SiH4And H2Mixed gas, and
And synchronize and be passed through the gas containing dopant, p-type doped amorphous silicon layer is formed in the second intrinsic amorphous silicon film layer.
Preferably, the dopant is P or B.
Preferably, first temperature is 150-250 DEG C, and first temperature is at least 20 DEG C higher than second temperature.
The present invention also provides the preparation methods of another efficiently silicon based hetero-junction double-side cell, include the following steps：It provides
One N-type silicon chip；Under the first temperature condition, third sheet is deposited respectively by chemical vapour deposition technique on the reverse side of N-type silicon chip
Levy amorphous silicon film layer；The deposited n-type doped amorphous silicon layer in third intrinsic amorphous silicon layer；The passing through on the front of N-type silicon chip
The method for learning vapor deposition deposits the first intrinsic amorphous silicon film layer respectively；Under the conditions of second temperature, in the first intrinsic amorphous silicon
The second intrinsic amorphous silicon film layer and p-type doped amorphous silicon layer are deposited in film layer；The electronic band gap of second intrinsic amorphous silicon layer
More than the first intrinsic amorphous silicon layer；Pass through PVD magnetron sputterings on p-type doped amorphous silicon layer and n-type doping amorphous silicon layer respectively
Deposition of transparent conductive film；Metal grid lines electrode is formed simultaneously in the transparent conductive film of the tow sides of N-type silicon chip.
The present invention also provides the preparation methods of another efficiently silicon based hetero-junction double-side cell, include the following steps：It provides
One N-type silicon chip；Under the first temperature condition, first is deposited by chemical vapour deposition technique respectively on the front of N-type silicon chip
Levy amorphous silicon film layer；Under the conditions of second temperature, the second intrinsic amorphous silicon film layer and P are deposited in the first intrinsic amorphous silicon film layer
Type doped amorphous silicon layer；The electronic band gap of second intrinsic amorphous silicon layer is more than the first intrinsic amorphous silicon layer；In N-type silicon chip
Third intrinsic amorphous silicon film layer is deposited by the method for chemical vapor deposition respectively on reverse side；It sinks in third intrinsic amorphous silicon layer
Product n-type doping amorphous silicon layer；Pass through PVD magnetron sputtering depositions on p-type doped amorphous silicon layer and n-type doping amorphous silicon layer respectively
Mode form transparent conductive film；Metal grid lines electrode is formed simultaneously in the transparent conductive film of the tow sides of N-type silicon chip.
The present invention uses above technical scheme, and the first intrinsic amorphous silicon layer, the are equipped with by the one side in the N-type silicon chip
Two intrinsic amorphous silicon layers, and the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer have been prepared in different chambers respectively
At the preparation temperature of the first intrinsic amorphous silicon layer is higher than the preparation temperature of the second intrinsic amorphous silicon layer, so that second is intrinsic
Amorphous silicon layer has larger electronic band gap, therefore can be used as barrier layer to stop that electrons spread to emitter, is reduced
Electronics and hole it is compound, to improve the electric property of cell piece, the photoelectric conversion efficiency for increasing cell piece is i.e. defeated
Go out power.
Description of the drawings
Fig. 1 is the structural schematic diagram of the efficient silicon based hetero-junction double-side cell of the present invention；
Fig. 2 is the flow diagram of the preparation method embodiment one of the present invention；
Fig. 3 is the flow diagram of the preparation method embodiment two of the present invention；
Fig. 4 is the flow diagram of the preparation method embodiment three of the present invention.
Specific implementation mode
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
As shown in Figure 1, the invention discloses a kind of efficient silicon based hetero-junction double-side cells comprising：
N-type silicon chip 1；
The first intrinsic amorphous silicon layer 2, the second intrinsic amorphous silicon layer 3, p-type are sequentially equipped in the front of the N-type silicon chip 1 to mix
Miscellaneous amorphous silicon layer 4, transparent conductive film layer 5, metal grid lines electrode 6；
Third intrinsic amorphous silicon layer 7 is sequentially equipped in the reverse side of the N-type silicon chip, n-type doping amorphous silicon layer 8, transparent is led
Electrolemma layer 9, metal grid lines electrode 10.
Wherein, the electronic band gap of second intrinsic amorphous silicon layer 3 is more than the first intrinsic amorphous silicon layer 2.Described second
The thickness for levying amorphous silicon film layer is less than 1nm, and the thickness of the first intrinsic amorphous silicon film layer and third intrinsic amorphous silicon film layer is respectively
The thickness of 5-10nm, the n-type doping amorphous silicon layer and p-type doped amorphous silicon layer is respectively 5-10nm, is located at N-type silicon chip front
Transparent conductive film thickness be 70-110nm, be located at the transparent conductive film of N-type silicon chip reverse side thickness be 25-110nm.
Heretofore described N-type silicon chip can be monocrystalline silicon piece or polysilicon chip, and battery of the invention is in sunlight
Irradiation under, can a large amount of electronics and hole are generated in its PN junction and in the N-type crystalline silicon of substrate, in usual PN junction from
Electronics and the hole of generation can be detached by building electric field.For N-type crystalline silicon, few son is hole, therefore hole is moved to light-receiving surface
It is dynamic, and how sub- electrons move and generate electric current in the opposite direction.But due to the effect of electrons spread, part electronics also can
It is moved to light-receiving surface, to increase electronics with hole in the recombination probability of PN junction area, causes the loss of electronics, reduce battery
The short circuit current of piece.The present invention in the first intrinsic amorphous silicon layer 2 by increasing by the second intrinsic amorphous silicon layer 3, and second is intrinsic non-
The electronic band gap of crystal silicon layer 3 is more than the first intrinsic amorphous silicon layer 2, therefore can be used as barrier layer to stop that electrons spread arrives
PN junction area, i.e. emitter reduce the compound of electronics and hole, to improve the electric property of cell piece, increase battery
Photoelectric conversion efficiency, that is, output power of piece.
Embodiment one：
As shown in Fig. 2, the invention discloses a kind of preparation methods of efficient silicon based hetero-junction double-side cell comprising following
Step：
S101:One N-type silicon chip is provided；
S102:Under the first temperature condition, distinguished respectively by chemical vapour deposition technique on the tow sides of N-type silicon chip
Deposit the first intrinsic amorphous silicon film layer and third intrinsic amorphous silicon film layer；
S103:The deposited n-type doped amorphous silicon layer in third intrinsic amorphous silicon layer；
S104:Under the conditions of second temperature, the second intrinsic amorphous silicon film layer and P are deposited in the first intrinsic amorphous silicon film layer
Type doped amorphous silicon layer；
S105：Pass through PVD (physical vaporous deposition) on p-type doped amorphous silicon layer and n-type doping amorphous silicon layer respectively
The mode deposition of transparent conductive film of magnetron sputtering deposition；
S106：In the transparent conductive film on two sides simultaneously plating metal gate line electrode.
Specific step can be as follows：
Step 1：A N-type silicon chip is provided, to N-type silicon chip cleaning and making herbs into wool, then under 150-220 DEG C of temperature condition, by N
In type silicon chip placing response chamber, SiH is passed through into reaction chamber4And H2Mixed gas, wherein H2Content be 5 to 20%, pass through
The method of chemical vapor deposition deposits on the two sides of N-type silicon chip forms the first intrinsic amorphous silicon film layer and third intrinsic amorphous silicon
Film layer.
Step 2：The N-type silicon chip for forming the first intrinsic amorphous silicon film layer and third intrinsic amorphous silicon film layer is put into first to mix
Miscellaneous intracavitary is passed through SiH into the first doping chamber4、H2And the gas of the P containing dopant, thus sink in third intrinsic amorphous silicon layer
Product n-type doping amorphous silicon layer；
Step 3：Under at least low 20 DEG C of the temperature condition than 150-220 DEG C, N will be formed in third intrinsic amorphous silicon layer
The N-type silicon chip of type doped amorphous silicon layer is put into the second doping intracavitary, is first passed through SiH in the second doping intracavitary4And H2Gaseous mixture
Body deposits the second intrinsic amorphous silicon film layer by chemical vapour deposition technique in the first intrinsic amorphous silicon film layer；Continue to be passed through
SiH4And H2Gas, and the gas for being passed through the B containing dopant is synchronized, p-type is formed in the second intrinsic amorphous silicon film layer adulterates amorphous
Silicon layer；
Step 4：Pass through PVD respectively on the p-type doped amorphous silicon layer of light-receiving surface and the n-type doping amorphous silicon layer of shady face
The method of magnetron sputtering generates transparent conductive film layer and metal laminated, then again metal laminated upper progress dry film mask, exposure,
Metal grid lines pattern is formed after development；The metal grid lines pattern of leakage is thickeied by electric plating method later.
Step 5：Dry film is got rid of, and to metal laminated carry out selective corrosion, the metal laminated region meeting not being thickened
Transparent conductive film layer is leaked out, to form metal grid lines pattern on surface, battery is so far completed and prepares.
Embodiment two：
As shown in figure 3, what is different from the first embodiment is that its in the present embodiment mainly first prepares N-type silicon chip wherein one side
Third intrinsic amorphous silicon film layer and n-type doping amorphous silicon layer, then prepare again other one side the first intrinsic amorphous silicon layer,
Two intrinsic amorphous silicon layers and p-type doped amorphous silicon layer finally prepare transparent conductive film layer and metal grid lines electrode, specifically include
Following steps：
S201：One N-type silicon chip is provided；
S202：Under the first temperature condition, deposited respectively by the method for chemical vapor deposition on the reverse side of N-type silicon chip
Third intrinsic amorphous silicon film layer；
S203：The deposited n-type doped amorphous silicon layer in third intrinsic amorphous silicon layer；
S204：Deposit the first intrinsic amorphous silicon film layer respectively by chemical vapour deposition technique on the front of N-type silicon chip；
S205：Under the conditions of second temperature, the second intrinsic amorphous silicon film layer and P are deposited in the first intrinsic amorphous silicon film layer
Type doped amorphous silicon layer；
S206：Pass through the side of PVD magnetron sputtering depositions on p-type doped amorphous silicon layer and n-type doping amorphous silicon layer respectively
Formula forms transparent conductive film；
S207：In the transparent conductive film of the tow sides of N-type silicon chip simultaneously plating metal gate line electrode.
First temperature is at least 20 DEG C higher than second temperature.
Embodiment three：
As shown in figure 4, what is different from the first embodiment is that its in the present embodiment mainly first prepares N-type silicon chip wherein one side
The first intrinsic amorphous silicon layer, the second intrinsic amorphous silicon layer and p-type doped amorphous silicon layer, then prepare the third sheet of another side again
Levy amorphous silicon film layer and n-type doping amorphous silicon layer, finally prepare transparent conductive film layer and metal grid lines electrode, specifically include with
Lower step：
S301：One N-type silicon chip is provided；
S302：Under the first temperature condition, deposited respectively by the method for chemical vapor deposition on the front of N-type silicon chip
First intrinsic amorphous silicon film layer；
S303：Under the conditions of second temperature, the second intrinsic amorphous silicon film layer and P are deposited in the first intrinsic amorphous silicon film layer
Type doped amorphous silicon layer；
S304：Deposit third intrinsic amorphous silicon film layer respectively by chemical vapour deposition technique on the reverse side of N-type silicon chip；
S305：The deposited n-type doped amorphous silicon layer in third intrinsic amorphous silicon layer；
S306：Pass through the side of PVD magnetron sputtering depositions on p-type doped amorphous silicon layer and n-type doping amorphous silicon layer respectively
Formula forms transparent conductive film；
S307：In the transparent conductive film of the tow sides of N-type silicon chip simultaneously plating metal gate line electrode.
First temperature is at least 20 DEG C higher than second temperature.
The present invention is designed with metal grid lines electrode in the tow sides of N-type substrate, so that cell piece just, anti-two sides
Can extinction, increase the output power of cell piece, the first intrinsic amorphous silicon layer, the be equipped with by the one side in the N-type silicon chip
Two intrinsic amorphous silicon layers, and the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer have been prepared in different chambers respectively
At the preparation temperature of the first intrinsic amorphous silicon layer is higher than the preparation temperature of the second intrinsic amorphous silicon layer, so that second is intrinsic
Amorphous silicon layer has larger electronic band gap, therefore can be used as barrier layer to stop that electrons spread to PN junction area, that is, is sent out
Emitter-base bandgap grading reduces the loss of electronics, improves photoelectric conversion efficiency.Wherein, " silicon based hetero-junction double-side cell disclosed by the invention
Chip technology ", English are " Silicon-based Heterojunction Double-sided Solar Cell
Technology " is abbreviated as " HDT ".
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement etc., should all be included in the protection scope of the present invention made by within refreshing and principle.
Claims (10)
1. a kind of efficient silicon based hetero-junction double-side cell, it is characterised in that：Including：
N-type silicon chip；
It is sequentially equipped with the first intrinsic amorphous silicon layer, the second intrinsic amorphous silicon layer, p-type in the front of the N-type silicon chip and adulterates amorphous
Silicon layer, transparent conductive film layer, metal grid lines electrode；The electronic band gap of second intrinsic amorphous silicon layer is more than the first intrinsic amorphous
Silicon layer；
It is sequentially equipped with third intrinsic amorphous silicon layer, n-type doping amorphous silicon layer, transparent conductive film layer in the reverse side of the N-type silicon chip,
Metal grid lines electrode.
2. efficient silicon based hetero-junction double-side cell according to claim 1, it is characterised in that：Second intrinsic amorphous silicon
The thickness of film layer is less than 1nm, and the thickness of the first intrinsic amorphous silicon film layer and third intrinsic amorphous silicon film layer is respectively 5-10nm, institute
The thickness for stating p-type doped amorphous silicon layer and n-type doping amorphous silicon layer is respectively 5-10nm, is located at that N-type silicon chip is positive transparent to be led
The thickness of electrolemma is 70-110nm, and the thickness for being located at the transparent conductive film of N-type silicon chip reverse side is 25-110nm.
3. a kind of preparation method of efficient silicon based hetero-junction double-side cell, which is characterized in that include the following steps：
One N-type silicon chip is provided；
Under the first temperature condition, respectively by chemical vapour deposition technique on the tow sides of N-type silicon chip, deposition first is intrinsic
Amorphous silicon film layer and third intrinsic amorphous silicon film layer；
The deposited n-type doped amorphous silicon layer in third intrinsic amorphous silicon layer；
Under the conditions of second temperature, the second intrinsic amorphous silicon film layer is deposited in the first intrinsic amorphous silicon film layer and p-type doping is non-
The electronic band gap of crystal silicon layer, second intrinsic amorphous silicon layer is more than the first intrinsic amorphous silicon layer；
Pass through PVD magnetron sputtering deposition transparent conductive films on p-type doped amorphous silicon layer and n-type doping amorphous silicon layer respectively；
Metal grid lines electrode is formed in the transparent conductive film of the tow sides of N-type silicon chip.
4. the preparation method of efficient silicon based hetero-junction double-side cell according to claim 3, it is characterised in that：It is described in N-type
Pass through the first intrinsic amorphous silicon film layer of chemical vapor deposition and third intrinsic amorphous silicon on the tow sides of silicon chip respectively
Film layer is specially：Under the first temperature condition, by N-type silicon chip placing response chamber, SiH is passed through into reaction chamber4And H2Mixing
Gas, be sequentially depositing on the tow sides of N-type silicon chip by chemical vapour deposition technique to be formed the first intrinsic amorphous silicon film layer and
Third intrinsic amorphous silicon film layer.
5. the preparation method of efficient silicon based hetero-junction double-side cell according to claim 3, it is characterised in that：It is described in third
Deposited n-type doped amorphous silicon layer is specially in intrinsic amorphous silicon layer：The first intrinsic amorphous silicon film layer will be formed and third is intrinsic non-
The N-type silicon chip of crystal silicon film layer is put into the first doping intracavitary, and SiH is passed through into the first doping chamber4、H2And the gas containing dopant,
Thus the deposited n-type doped amorphous silicon layer in third intrinsic amorphous silicon layer.
6. the preparation method of efficient silicon based hetero-junction double-side cell according to claim 3, it is characterised in that：It is described first
The second intrinsic amorphous silicon film layer is deposited in intrinsic amorphous silicon film layer and p-type doped amorphous silicon layer is specially：In second temperature condition
Under, the N-type silicon chip that n-type doping amorphous silicon layer is formed in third intrinsic amorphous silicon layer is put into the second doping intracavitary, first the
Two doping intracavitary are passed through SiH4And H2Mixed gas, by the method for chemical vapor deposition in the first intrinsic amorphous silicon film layer
After depositing the second intrinsic amorphous silicon film layer；Continue to be passed through SiH4And H2Mixed gas, and synchronize and be passed through the gas containing dopant
Body forms p-type doped amorphous silicon layer in the second intrinsic amorphous silicon film layer.
7. according to the preparation method of the efficient silicon based hetero-junction double-side cell of claim 5 or 6, it is characterised in that：It is described to mix
Miscellaneous dose is P or B.
8. the preparation method of efficient silicon based hetero-junction double-side cell according to claim 3, it is characterised in that：First temperature
Degree is 150-250 DEG C, and first temperature is at least 20 DEG C higher than second temperature.
9. a kind of preparation method of efficient silicon based hetero-junction double-side cell, which is characterized in that include the following steps：
One N-type silicon chip is provided；
Under the first temperature condition, the intrinsic amorphous of third is deposited respectively by chemical vapour deposition technique on the reverse side of N-type silicon chip
Silicon film；
The deposited n-type doped amorphous silicon layer in third intrinsic amorphous silicon layer；
The first intrinsic amorphous silicon film layer is deposited by the method for chemical vapor deposition respectively on the front of N-type silicon chip；
Under the conditions of second temperature, the second intrinsic amorphous silicon film layer is deposited in the first intrinsic amorphous silicon film layer and p-type doping is non-
Crystal silicon layer；The electronic band gap of second intrinsic amorphous silicon layer is more than the first intrinsic amorphous silicon layer；
Pass through PVD magnetron sputtering deposition transparent conductive films on p-type doped amorphous silicon layer and n-type doping amorphous silicon layer respectively；
Metal grid lines electrode is formed simultaneously in the transparent conductive film of the tow sides of N-type silicon chip.
10. a kind of preparation method of efficient silicon based hetero-junction double-side cell, which is characterized in that include the following steps：
One N-type silicon chip is provided；
Under the first temperature condition, the first intrinsic amorphous is deposited respectively by chemical vapour deposition technique on the front of N-type silicon chip
Silicon film；
Under the conditions of second temperature, the second intrinsic amorphous silicon film layer is deposited in the first intrinsic amorphous silicon film layer and p-type doping is non-
Crystal silicon layer；The electronic band gap of second intrinsic amorphous silicon layer is more than the first intrinsic amorphous silicon layer；
Third intrinsic amorphous silicon film layer is deposited by the method for chemical vapor deposition respectively on the reverse side of N-type silicon chip；
The deposited n-type doped amorphous silicon layer in third intrinsic amorphous silicon layer；
It is formed by way of PVD magnetron sputtering depositions on p-type doped amorphous silicon layer and n-type doping amorphous silicon layer respectively transparent
Conductive film；
Metal grid lines electrode is formed simultaneously in the transparent conductive film of the tow sides of N-type silicon chip.
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