CN103107239B - Heterojunction solar battery and preparation method thereof - Google Patents
Heterojunction solar battery and preparation method thereof Download PDFInfo
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- CN103107239B CN103107239B CN201210529859.2A CN201210529859A CN103107239B CN 103107239 B CN103107239 B CN 103107239B CN 201210529859 A CN201210529859 A CN 201210529859A CN 103107239 B CN103107239 B CN 103107239B
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Abstract
A kind of heterojunction solar battery and preparation method thereof, the manufacture method of described heterojunction solar battery includes: provide substrate, it is provided that substrate, described substrate is the first doping type monocrystalline silicon piece；Forming the first stressor layers at described substrate surface, and make annealing treatment, the stress types of described first stressor layers is corresponding with the doping type of substrate；Remove described first stressor layers；The second doping type amorphous silicon layer is formed at described substrate surface；Transparency conducting layer is formed on described second doping type amorphous silicon layer surface；The first electrode is formed in described layer at transparent layer；The second electrode is formed at described substrate lower surface.The manufacture method of described heterojunction solar battery can improve the carrier mobility of heterojunction solar battery, improves the conversion efficiency of described heterojunction solar battery.
Description
Technical field
The present invention relates to area of solar cell, particularly to a kind of heterojunction solar battery and making thereof
Method.
Background technology
Solaode utilizes photoelectric effect to convert the light to electric energy.Basic solar battery structure, bag
Include single p-n junction, P-I-N/N-I-P knot and multijunction structure.Typical single p-n junction structure includes: p-type is mixed
Diamicton and n-type doping layer.Single p-n junction solaode has homojunction and two kinds of structures of hetero-junctions: homojunction
The p-type doped layer of structure and n-type doping layer are all made up of analog material (band gap of material is equal), different
Matter junction structure includes the material with at least two-layer difference band gap.P-I-N/N-I-P structure include p-type doped layer,
N-type doping layer and the intrinsic semiconductor layer (undoped p I layer) being sandwiched between P layer and N shell.Multijunction structure bag
Including multiple semiconductor layers with different band gap, the plurality of semiconductor layer stacks mutually.
In solar cells, light is absorbed near P-N junction, produces light induced electron and photohole, institute
Stating light induced electron and photohole diffuses into P-N junction and is built electric field separately, light induced electron is pushed into N
District, hole is pushed into P district.Form positive and negative charge accumulated in PN junction both sides, produce photo-induced voltage thus
Generate through described device and the electric current of external circuitry.
At present, utilizing amorphous silicon membrane as Window layer, monocrystalline silicon piece is as substrate, the hetero-junctions of formation
Solaode both make use of the thin film deposition processes of low temperature, has played again the advantage of crystalline silicon high mobility,
Preparation technology is simple simultaneously, has and realizes high efficiency, the development prospect of low-cost silicon solaode.Different
The conversion efficiency of matter joint solar cell is affected by several factors, needs further to be improved.
More manufacture methods about heterojunction solar battery, refer to Publication No. CN101866991A
Chinese patent.
Summary of the invention
The problem that the present invention solves is to provide a kind of heterojunction solar battery and preparation method thereof, improves different
The conversion efficiency of matter joint solar cell.
For solving the problems referred to above, technical scheme proposes the system of a kind of heterojunction solar battery
Make method, including: providing substrate, described substrate is the first doping type monocrystalline silicon piece；At described substrate
Surface forms the first stressor layers, and makes annealing treatment, the stress types of described first stressor layers and substrate
Doping type corresponding；Remove described first stressor layers；The second doping class is formed at described substrate surface
Type amorphous silicon layer；Transparency conducting layer is formed on described second doping type amorphous silicon layer surface；Described
Bright conductive layer surface forms the first electrode；The second electrode is formed at described substrate lower surface.
Optionally, described substrate is p type single crystal silicon sheet, and described first stressor layers has compressive stress, described
Second doping type amorphous silicon layer is N-type layer；Or described substrate is n type single crystal silicon sheet, described first
Stressor layers has tensile stress, and described second doping type amorphous silicon layer is P-type layer.
Optionally, the forming method of the stressor layers described in compressive stress includes: using plasma strengthens
Chemical vapor deposition method, wherein, NH3And SiH4As reacting gas, noble gas as carrier gas,
Reaction temperature is 200 DEG C～500 DEG C, and reaction pressure is 100mTorr～200mTorr, and provides a merit
Rate is 10W～100W, and frequency is the low frequency power source of 50KHz～500kHz.
Optionally, the forming method of the stressor layers described in tensile stress includes: using plasma strengthens
Chemical vapor deposition method, wherein, NH3With SiH4 as reacting gas, noble gas as carrier gas,
Reaction temperature is 200 DEG C～500 DEG C, and reaction pressure is 100mTorr～200mTorr, and provides a merit
Rate is 10W～100W, and frequency is the radio frequency power source of 10MHz～15MHz.
Optionally, the formation process of described first stressor layers includes that thermal chemical vapor deposition or plasma increase
Extensive chemical vapour deposition.
Optionally, described first stressor layers includes silicon nitride film or silicon oxide film, described first stress
The thickness of layer is 0.5nm～100nm, and the numerical range of stress is 200MPa～1000MPa.
Optionally, described in carry out making annealing treatment technique be rapid thermal anneal process, the temperature range of annealing
It it is 200 DEG C～800 DEG C.
Optionally, the technique of described removal the first stressor layers is dry etch process or wet etching.
Optionally, also include, before forming described transparency conducting layer, at the second doping type non-crystalline silicon
Layer surface forms the second stressor layers, the stress types of described second stressor layers and the second doping type non-crystalline silicon
Layer doping type corresponding, remove described second stressor layers after annealing, described second stressor layers have with
The stress types that first stressor layers is contrary.
Optionally, also include, before forming the second doping type amorphous silicon layer, the most on the substrate
Surface forms tunnel oxide, and the thickness range of described tunnel oxide isMaterial is oxygen
SiClx.
Optionally, also include, formed before the second electrode, sequentially form the at described substrate lower surface
One doping type heavily doped amorphous silicon layer, and it is positioned at described first doping type heavily doped amorphous silicon layer surface
The second transparency conducting layer.
For solving the problems referred to above, technical scheme also provides for a kind of heterojunction solar battery, bag
Including: substrate, described substrate is the first doping type monocrystalline silicon piece, and by the first stress effect, described
The stress types of the first stress is corresponding with the doping type of substrate；It is positioned at the second of described substrate upper surface
Doping type amorphous silicon layer；It is positioned at the transparency conducting layer on described second doping type amorphous silicon layer surface；Position
The first electrode in described layer at transparent layer；It is positioned at the second electrode of described substrate lower surface.
Optionally, described substrate is p type single crystal silicon sheet, and described first stress is compressive stress, described second
Doping type amorphous silicon layer is N-type layer；Or described substrate is n type single crystal silicon sheet, described first stress
Layer has tensile stress, and described second doping type amorphous silicon layer is P-type layer.
Optionally, described second doping type non-crystalline silicon by the second stress effect, described second stress is
Tensile stress or compressive stress, and described second stress and the doping type phase of the second doping type amorphous silicon layer
Corresponding.
Optionally, also include, between described second doping type amorphous silicon layer and substrate upper surface, also
Having tunnel oxide, the thickness range of described tunnel oxide isMaterial is silicon oxide.
Optionally, also include, between described second electrode and substrate lower surface, the first doping class
Type heavily doped amorphous silicon layer is transparent be positioned at described first doping type heavily doped amorphous silicon layer surface second
Conductive layer.
Compared with prior art, the invention have the advantages that
Technical scheme, forms the first stressor layers at described substrate surface, then carries out annealing treatment
After reason, remove described first stressor layers.Described first stressor layers makes substrate be stressed effect, substrate
Lattice deform upon, after anneal, the deformation of described lattice is cured, make substrate memory residence be subject to
The stress effect arrived, after removing described first stressor layers, described substrate nevertheless suffers from stress effect, institute
State stress and can improve the carrier mobility in described substrate, reduce the recombination rate of carrier, thus carry
The conversion efficiency of high heterojunction solar battery.
Further, the substrate surface after removing the first stressor layers forms the second doping type non-crystalline silicon
After Ceng, it is also possible to form the second stressor layers on the second doping type amorphous silicon layer surface, then anneal and go
Except described second stressor layers, again such that described second doping type amorphous silicon layer memory residence is stated second and answered
The stress effect of power layer so that described second doping type amorphous silicon layer is stressed effect, improves described
Carrier mobility in second doping type amorphous silicon layer.
Further, described substrate is n type single crystal silicon sheet, is formed on described n type single crystal silicon sheet surface
First stressor layers has tensile stress, removes described first stressor layers after annealing, and described n type single crystal silicon sheet is subject to
To tensile stress effect, it is possible to increase the mobility of light induced electron in n type single crystal silicon sheet；Described second doping
Type amorphous silicon layer is P-type layer, and the second stressor layers formed on described P-type layer surface has compressive stress,
Removing described second stressor layers after annealing, described P-type layer is by action of compressive stress, it is possible to increase P-type layer
The mobility of interior photohole.Improve the mobility of described light induced electron or photohole, it is possible to increase
Total electric current density of described heterojunction solar battery, improves the conversion efficiency of heterojunction solar battery.
Further, technical scheme can also between described second amorphous silicon layer and substrate shape
Become tunnel oxide.Described tunnel oxide, can reduce the surface state concentration of substrate, and then reduce tunnel
Wear electric current.
Further, before forming the second electrode, it is also possible to sequentially form first at substrate lower surface and mix
Miscellany type heavily doped amorphous silicon layer and the second transparency conducting layer, then in described second layer at transparent layer
Form the second electrode.Introduce same with substrate in the contact area of the substrate back of described heterojunction solar battery
First doping type heavily doped amorphous silicon layer of type, can produce potential barrier effect by son few to photoproduction, thus reduce
Photo-generated carrier overleaf compound, thus improve the conversion efficiency of heterojunction solar battery.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the manufacture method of the heterojunction solar battery in embodiments of the invention；
Fig. 2 to Fig. 7 is the section of the manufacture method of the heterojunction solar battery in embodiments of the invention
Schematic diagram.
Detailed description of the invention
As described in the background art, the conversion efficiency of current heterojunction solar battery needs further to be carried
High.
Research finds, the compound open-circuit voltage directly affecting solaode of photo-generated carrier.So
Carrier is during electrode movement, and the migration rate improving carrier can effectively reduce photoproduction load
Flow the recombination rate of son thus improve the conversion efficiency of solaode.
Embodiments of the invention propose a kind of heterojunction solar battery and preparation method thereof, at substrate table
Face uses stress memory technique, and after forming the first stressor layers, after annealing, described then removal is described
First stressor layers, described substrate remains able to the stress effect effect by described first stressor layers, thus
Improve the mobility of described substrate carriers, improve the conversion efficiency of described heterojunction solar battery.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The detailed description of the invention of the present invention is described in detail.Described embodiment be only the present invention can
A part for embodiment rather than they are whole.When describing the embodiment of the present invention in detail, for purposes of illustration only,
Schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not at this
Limit the scope of the invention.Additionally, the three of length, width and the degree of depth should be comprised in actual fabrication
Dimension space size.According to described embodiment, those of ordinary skill in the art is without creative work
Under premise, obtainable other embodiments all, broadly fall into protection scope of the present invention.Therefore the present invention
Do not limited by following public being embodied as.
Refer to Fig. 1, for the schematic flow sheet of the manufacture method of heterojunction solar battery in the present embodiment,
Including:
Step S1: providing substrate, described substrate is the first doping type monocrystalline silicon piece；
Step S2: the upper surface at described substrate forms the first stressor layers, and makes annealing treatment, described
The stress types of the first stressor layers is corresponding with the doping type of substrate；
Step S3: remove described first stressor layers；
Step S4: surface forms the second doping type amorphous silicon layer on the substrate；
Step S5: form transparency conducting layer on described second doping type amorphous silicon layer surface；
Step S6: form the first electrode in described layer at transparent layer, is formed at described substrate lower surface
Second electrode.
Refer to Fig. 2, it is provided that substrate 100, described substrate is the first doping type monocrystalline silicon piece.
Concrete, described substrate 100 is p type single crystal silicon sheet or n type single crystal silicon sheet, adopts in the present embodiment
Substrate be n type single crystal silicon sheet, described n type single crystal silicon sheet be formed silicon chip when to described silicon
Sheet carries out phosphonium ion doping, it is also possible to be described silicon chip is carried out in phosphorus, arsenic or antimony one or more from
The doping of son.
Refer to Fig. 3, the upper surface at described substrate 100 forms the first stressor layers 101, and anneals
Processing, the stress types of described first stressor layers is corresponding with the doping type of substrate.
Before surface forms the first stressor layers on the substrate, first described substrate is carried out, goes
Except the impurity of substrate surface, thus avoid the performance of impurity effect solaode.After the washing, also
Matte can be prepared at described substrate surface, with aqueous slkali, substrate surface be carried out anisotropic etch,
Described substrate surface forms matte, and described matte can improve the contact area of substrate surface and sunlight also
And reduce the reflection of sunlight.After preparing matte, then surface forms the first stressor layers on the substrate
101。
Described first stressor layers 101 includes silicon nitride film, silicon oxide film etc..Described first stressor layers
The formation process of 101 is plasma enhanced chemical vapor deposition (PECVD) or thermal chemical vapor deposition.
In the present embodiment, described substrate is n type single crystal silicon sheet, is formed on described n type single crystal silicon sheet surface
There is the first stressor layers of tensile stress, described in there is the first stressor layers of tensile stress include silicon nitride or oxidation
Silicon thin film etc..In one embodiment of the invention, first stressor layers described in tensile stress is nitridation
Silicon thin film, the formation process of employing is plasma enhanced chemical vapor deposition, and wherein, reacting gas is
NH3And SiH4, utilize the noble gases such as Ar as carrier gas, SiH4And NH3Gas flow ratio be 0.1～4,
Reaction temperature is 200 DEG C～500 DEG C, and reaction pressure is 100mTorr～200mTorr, and provides a merit
Rate is the radio frequency power source of 10W～100W, and frequency is 13.56MHz.The thickness of described first stressor layers
For 0.5nm～100nm, having tensile stress, tensile stress numerical range is 200MPa～1000MPa.Described
There is the first stressor layers of tensile stress, make n type single crystal silicon sheet acting on by the tensile stress in horizontal plane.
In other embodiments of the invention, described substrate 100 is p type single crystal silicon sheet, in described p-type
Monocrystalline silicon sheet surface is formed has the first stressor layers 101 of compressive stress, described in there is the stressor layers of compressive stress
101 is silicon nitride film, and the formation process of employing is plasma enhanced chemical vapor deposition, wherein, instead
Answering gas is NH3And SiH4, utilize the noble gases such as Ar as carrier gas, SiH4And NH3Gas stream
Amount ratio is 0.1～4, and reaction temperature is 200 DEG C～500 DEG C, and reaction pressure is 100mTorr～200mTorr,
The low frequency power source providing a power to be 10W～100W, frequency is 100KHz.Described stressor layers
Thickness is 0.5nm～100nm, has compressive stress, and the numerical range of compressive stress is 200MPa～1000MPa.
Described first stressor layers 101 with compressive stress, makes substrate 100 acting on by the compressive stress in horizontal plane.
After forming described first stressor layers 101, make annealing treatment.Described annealing treating process is fast
Speed thermal anneal process, the temperature range of annealing is 200 DEG C～800 DEG C.Described substrate 100 is made to produce stress
Memory effect, remembers described subjected to stress.In the present embodiment, described substrate 100 is n type single crystal silicon
Sheet, described first stressor layers 101 has tensile stress so that substrate under stress effect, lattice generation shape
Becoming, after anneal, the deformation of described lattice is cured, and makes substrate remember residence subjected to stress effect,
After follow-up removal the first stressor layers 101, described substrate 100 is also acted on by described tensile stress.
Electronics in described substrate is making stereo-motion, institute during the second electrode flowing in three-dimensional
State tensile stress and can improve the mobility of electronics in substrate 100, improve in the substrate 100 of described N-type
The mobility of light induced electron, reduces described light induced electron recombination probability during the second electrode movement,
Improve the quantity of the light induced electron collected at described second electrode, improve total electric current of solaode
Density, thus improve the efficiency of heterojunction solar battery.
In other embodiments of the invention, described substrate is p type single crystal silicon sheet, described first stressor layers
There is compressive stress, so after Tui Huo, described substrate has been remembered described in the compressive stress that is subject to, follow-up
After removing the first stressor layers, described substrate is also acted on by described compressive stress.Hole is to the second electricity
Making stereo-motion in three-dimensional during the flowing of pole, described compressive stress can improve hole in substrate
Mobility, improve the mobility of photohole in the substrate 100 of described p-type, reduce described photoproduction
Electronics recombination probability during the second electrode movement, improves the light collected at described second electrode
The quantity in raw hole, improves total electric current density of solaode, thus improves the effect of solaode
Rate.
Refer to Fig. 4, remove described first stressor layers 101 (refer to Fig. 3).
The method removing described first stressor layers 101 is dry etching or wet etching.In the present embodiment
Dry etch process is used to remove described first stressor layers 103.After removing described first stressor layers 101,
Described substrate, due to stress memory effect, nevertheless suffers from the effect of stress.
Owing to using the method for wet method or dry etching to remove described first stressor layers, removing described the
While one stressor layers, the surface of described substrate can be prepared matte, thus improve solaode table
The contact area in face, reduces the reflection to sunlight, improves the absorbance to sunlight.
Refer to Fig. 5, form the second doping type amorphous silicon layer 102 on described substrate 100 surface.
Concrete, described second doping type amorphous silicon layer 102 can be N-type layer or P-type layer, institute
The thickness stating the second doping type amorphous silicon layer 102 isDescribed second doping type amorphous
The formation process of silicon layer 102 can be low-pressure chemical vapor deposition, plasma activated chemical vapour deposition, liquid
The technique such as phase epitaxy or sputtering sedimentation.
In the present embodiment, using plasma strengthens chemical vapour deposition technique and forms described second doping type
Amorphous silicon layer 102, described second doping type amorphous silicon layer 102 is P-type layer, and concrete forming method is:
With SiH2Cl2、SiHCl3、SiCl4Or SiH4As reacting gas, under certain protective atmosphere, reaction is raw
Become silicon atom, at the upper surface formation of deposits amorphous silicon layer of substrate, more described amorphous silicon layer is carried out p-type
Ion doping, forms the second doping type amorphous silicon layer 102.Described second doping type ion doping, can
To use ion implanting or diffusion technique to be formed, it is also possible to use while forming amorphous silicon layer and mix in situ
General labourer's skill is formed.Described dopant ion includes one or more of boron, gallium or indium, the concentration of dopant ion
For 1E10/cm3～1E20/cm3。
In other embodiments of the invention, if described substrate 100 is p type single crystal silicon sheet, then described
Second doping type amorphous silicon layer 102 is N-type layer, uses the method in the present embodiment to form amorphous silicon layer
Afterwards, described amorphous silicon layer is carried out N-type ion doping, form the second doping type amorphous silicon layer.Institute
State N-type ion doping, ion implanting or diffusion technique can be used to be formed, it is also possible to forming non-crystalline silicon
Doping process in situ is used to be formed while Ceng.Dopant ion includes one or more in phosphorus, arsenic or antimony,
The concentration of dopant ion is 1E10/cm3～1E20/cm3。
In other embodiments of the invention, it is also possible to surface is initially formed intrinsic amorphous the most on the substrate
After silicon layer, then form the second doping type amorphous silicon layer on described intrinsic amorphous silicon layer surface.Concrete,
Described intrinsic amorphous silicon layer is low-doped or undoped amorphous silicon layer, the thickness of described intrinsic amorphous silicon layer
For 5nm～50nm.The formation process of described intrinsic amorphous silicon layer can be low-pressure chemical vapor deposition or etc. from
The techniques such as sub-body chemical vapor phase growing, liquid phase epitaxy or sputtering sedimentation.Described intrinsic amorphous silicon layer can be right
Substrate surface plays passivation, reduces the carrier recombination rate at substrate surface, improves solaode
Conversion efficiency.
In other embodiments of the present invention, it is also possible to after described substrate surface forms intrinsic amorphous silicon layer,
Use stress memory technique, form tertiary stress layer on described intrinsic amorphous silicon layer surface, after annealing
Removing described tertiary stress layer, described annealing treating process is rapid thermal anneal process, the temperature model of annealing
Enclosing is 200 DEG C～800 DEG C, and this annealing temperature can not be too high, because if annealing temperature too high easily make non-
Crystalline substance is converted into polycrystalline, thus affects the performance of heterojunction solar battery.Described intrinsic amorphous silicon layer is made to be subject to
To stress effect, then form the second doping type amorphous silicon layer on described intrinsic amorphous silicon layer surface.Described
The stress types of tertiary stress layer, can be tensile stress, it is also possible to be compressive stress.Due in solar-electricity
Chi Zhong, the effective mass in hole more than the effective mass of electronics, so hole migration rate less than electricity
The migration rate of son, so described tertiary stress layer can have compressive stress, makes intrinsic amorphous silicon layer be subject to
The effect of compressive stress, improves the mobility of photohole in described intrinsic amorphous silicon layer, improves described heterogeneous
Electric current density total in joint solar cell, thus improve the conversion efficiency of heterojunction solar battery.
In other embodiments of the invention, in order to reduce the surface state concentration of substrate, and then reduce tunnelling
Electric current, it is also possible to the upper surface at described substrate 100 is initially formed tunnel oxide, the most again at described tunnel
Wear oxide layer surface form the second doping type amorphous silicon layer or sequentially form on described tunnel oxide surface
Intrinsic amorphous silicon layer and the second doping type amorphous silicon layer.Described tunnel oxide can use Low Temperature Thermal oxygen
Metallization processes or wet oxidation process are formed.Specifically, the material of described tunnel oxide can be silicon oxide,
Its thickness range isSuch as: Or
Refer to Fig. 6, form transparency conducting layer 103 on described second doping type amorphous silicon layer 102 surface.
Concrete, described transparency conducting layer 103 is transparent conductive film, including SnO 2 thin film, oxidation
Zinc thin film, indium tin oxide films etc..In the present embodiment, described transparency conducting layer 103 is SnO 2 thin film,
Described transparency conducting layer 103 with transmission major part incident illumination, and can have electric current at transparency conducting layer 103
Middle flowing.In the present embodiment, described transparency conducting layer 103 uses magnetron sputtering technique to be formed, thickness model
Enclose forDescribed transparency conducting layer 103 is in addition to electric action, it is also possible to the second doping
The effect of passivated surface is played on type amorphous silicon layer surface, reduces the recombination rate of carrier.
In other embodiments of the invention, before forming described transparency conducting layer 103, it is also possible to
Described second doping type amorphous silicon layer 102 surface forms the second stressor layers, then makes annealing treatment, and goes
Except described second stressor layers.The type of described second stressor layers and the second doping type amorphous silicon layer 102
Doping type is corresponding, if described second doping type amorphous silicon layer is P-type layer, the most described second should
Power layer has compressive stress；If described second doping type amorphous silicon layer is N-type layer, the most described second should
Power layer has tensile stress.After removing described second stressor layers, due to lattice deformation, described second doping class
It is stressed effect in type amorphous silicon layer, described second doping type amorphous silicon layer carriers can be improved
Mobility.
Refer to Fig. 7, form the first electrode 104, at described substrate on described transparency conducting layer 103 surface
100 lower surfaces form the second electrode 105.
Form the concrete technology of described first electrode 104 and the second electrode 105 for those skilled in the art
Member does not repeats them here known to being.
In other embodiments of the invention, before forming the second electrode, it is also possible under described substrate
Surface sequentially forms the first doping type heavily doped amorphous silicon layer and the second transparency conducting layer, then described
Second layer at transparent layer forms the second electrode.Rear-face contact district at described heterojunction solar battery
Introduce with substrate with the first doping type heavily doped amorphous silicon layer of type, gesture can be produced by son few to photoproduction
Build effect, thus reduce carrier being combined at substrate lower surface, thus improve heterojunction solar battery
Conversion efficiency.
Embodiments of the invention also proposed a kind of heterojunction solar battery using said method to be formed.
Refer to Fig. 7, for the generalized section of the heterojunction solar battery of the present embodiment.
Described heterojunction solar battery includes: substrate 100, and described substrate is the first doping type monocrystal silicon
Sheet, and described substrate is by the first stress effect, the type of described first stress and the doping class of substrate
Type is corresponding；It is positioned at the second doping type amorphous silicon layer 102 of described substrate 100 upper surface；It is positioned at described
The transparency conducting layer 103 on the second doping type amorphous silicon layer 102 surface；It is positioned at described transparency conducting layer 103
First electrode 104 on surface；It is positioned at the second electrode 105 of described substrate 100 lower surface.
Concrete, in the present embodiment, described substrate 100 is n type single crystal silicon sheet, and described substrate 100 is subject to
To the first stress be tensile stress.Electronics in substrate 100 to second electrode flowing during three
Dimension makees stereo-motion in direction, and described tensile stress can improve the mobility of electronics in substrate 100, improves
The mobility of the light induced electron in the substrate 100 of described N-type, reduces described light induced electron to the second electrode
Recombination probability during motion, improves the quantity of the light induced electron collected at described second electrode,
Improve total electric current density of solaode, improve the efficiency of heterojunction solar battery.In the present invention
Other embodiments in, described substrate 100 can be p type single crystal silicon sheet, and described substrate 100 is subject to
First stress is compressive stress.Hole in substrate 100 to second electrode flowing during in three-dimensional side
Inwardly making stereo-motion, described compressive stress can improve the mobility of electronics in substrate 100, improves described P
The mobility of the photohole in the substrate 100 of type, reduces described photohole to the second electrode movement
During recombination probability, improve the quantity of the photohole collected at described second electrode, improve too
Total electric current density of sun energy battery, improves the efficiency of solaode.
In the present embodiment, described second doping type amorphous silicon layer 102 is P-type non-crystalline silicon layer.At this
In other bright embodiments, described second doping type amorphous silicon layer 102 can also be answered masterpiece by second
With.If described second doping type amorphous silicon layer 102 is P-type non-crystalline silicon layer, the most described second stress
For compressive stress；If described second doping type amorphous silicon layer 102 is N-type non-crystalline silicon layer, the most described
Two stress are tensile stress.
In other embodiments of the invention, between described second amorphous silicon layer 102 and substrate upper surface also
There is tunnel oxide.Described tunnel oxide can use low thermal oxidation technique or wet oxidation process shape
Become.Specifically, the material of described tunnel oxide can be silicon oxide, and its thickness range is
Such as: OrDescribed tunnel oxide can reduce the surface state of substrate
Concentration, and then reduce tunnelling current.
In other embodiments of the invention, between described second amorphous silicon layer 102 and substrate upper surface also
There is intrinsic amorphous silicon layer.Concrete, described intrinsic amorphous silicon layer is low-doped or undoped non-crystalline silicon
Layer, the thickness of described intrinsic amorphous silicon layer is 5nm～50nm.The formation process of described intrinsic amorphous silicon layer can
To be the work such as low-pressure chemical vapor deposition or plasma activated chemical vapour deposition, liquid phase epitaxy or sputtering sedimentation
Skill.Substrate surface can be played passivation by described intrinsic amorphous silicon layer, reduces carrier at substrate table
The recombination rate in face, improves the conversion efficiency of solaode.Described intrinsic amorphous silicon layer can also be by
The effect of three stress, described tertiary stress can be compressive stress, it is also possible to be tensile stress.
In other embodiments of the invention, described heterojunction solar battery can also include being positioned at described
The first doping type heavily doped amorphous silicon layer between second electrode 105 and substrate 100 lower surface and being positioned at
Second transparency conducting layer on described first doping type heavily doped amorphous silicon layer surface, described first doping class
Type heavily doped amorphous silicon layer is positioned at substrate lower surface.Substrate lower surface at described heterojunction solar battery
Introduce with substrate with the first doping type heavily doped amorphous silicon layer of doping type, can produce by son few to photoproduction
Growing situation builds effect, thus reduces carrier being combined at back surface, thus improves heterojunction solar battery
Conversion efficiency.
By the explanation of above-described embodiment, professional and technical personnel in the field should be able to be made to be more fully understood that the present invention,
And can reproduce and use the present invention.Those skilled in the art can according to principle specifically described herein
To above-described embodiment as various changes and modifications to be without departing from the spirit and scope of the present invention
Obviously.Therefore, the present invention should not be construed as being limited to above-described embodiment shown in this article, its
Protection domain should be defined by appending claims.
Claims (14)
1. the manufacture method of a heterojunction solar battery, it is characterised in that including:
Thering is provided substrate, described substrate is the first doping type monocrystalline silicon piece；
Form the first stressor layers at described substrate surface, and make annealing treatment, described first stressor layers
Stress types is corresponding with the doping type of substrate；
Remove described first stressor layers；
The second doping type amorphous silicon layer is formed at described substrate surface；
Form the second stressor layers on the second doping type amorphous silicon layer surface, described second stressor layers have with
The stress types that first stressor layers is contrary, and the stress types of described second stressor layers with second doping class
The doping type of type amorphous silicon layer is corresponding；
Described second stressor layers is annealed；
Described second stressor layers is removed after annealing；
Transparency conducting layer is formed on described second doping type amorphous silicon layer surface；
The first electrode is formed in described layer at transparent layer；
The second electrode is formed at described substrate lower surface.
The manufacture method of heterojunction solar battery the most according to claim 1, it is characterised in that described
Substrate is p type single crystal silicon sheet, and described first stressor layers has compressive stress, described second doping type amorphous
Silicon layer is N-type layer；Or described substrate is n type single crystal silicon sheet, described first stressor layers has tensile stress,
Described second doping type amorphous silicon layer is P-type layer.
The manufacture method of heterojunction solar battery the most according to claim 2, it is characterised in that described
The forming method of the stressor layers with compressive stress includes: using plasma strengthens chemical vapor deposition method,
Wherein, NH3And SiH4As reacting gas, noble gas is as carrier gas, and reaction temperature is 200 DEG C
～500 DEG C, reaction pressure is 100mTorr～200mTorr, and to provide a power be 10W～100W,
Frequency is the low frequency power source of 50KHz～500kHz.
The manufacture method of heterojunction solar battery the most according to claim 2, it is characterised in that described
The forming method of the stressor layers with tensile stress includes: using plasma strengthens chemical vapor deposition method,
Wherein, NH3And SiH4As reacting gas, noble gas is as carrier gas, and reaction temperature is 200 DEG C
～500 DEG C, reaction pressure is 100mTorr～200mTorr, and to provide a power be 10W～100W,
Frequency is the radio frequency power source of 10MHz～15MHz.
The manufacture method of heterojunction solar battery the most according to claim 1, it is characterised in that described
The formation process of the first stressor layers includes thermal chemical vapor deposition or plasma enhanced chemical vapor deposition.
The manufacture method of heterojunction solar battery the most according to claim 1, it is characterised in that described
First stressor layers includes that silicon nitride film or silicon oxide film, the thickness of described first stressor layers are
0.5nm～100nm, the numerical range of stress is 200MPa～1000MPa.
The manufacture method of heterojunction solar battery the most according to claim 1, it is characterised in that described
The technique carrying out making annealing treatment is rapid thermal anneal process, and the temperature range of annealing is 200 DEG C～800 DEG C.
The manufacture method of heterojunction solar battery the most according to claim 1, it is characterised in that described
The technique removing the first stressor layers is dry etch process or wet-etching technology.
The manufacture method of heterojunction solar battery the most according to claim 1, it is characterised in that also wrap
Including, before forming the second doping type amorphous silicon layer, surface forms tunnel oxide the most on the substrate
Layer, the thickness range of described tunnel oxide isMaterial is silicon oxide.
The manufacture method of heterojunction solar battery the most according to claim 1, it is characterised in that also wrap
Include, before forming the second electrode, sequentially form the first doping type heavy doping at described substrate lower surface
Amorphous silicon layer and the second transparency conducting layer being positioned at described first doping type heavily doped amorphous silicon layer surface.
11. 1 kinds of heterojunction solar batteries, it is characterised in that including:
Substrate, described substrate is the first doping type monocrystalline silicon piece, and by the first stress, described first
The stress types of stress is corresponding with the doping type of substrate；
It is positioned at the second doping type amorphous silicon layer of described substrate upper surface, wherein said second doping type
Non-crystalline silicon is by the second stress effect, the stress types of described second stress and the stress class of the first stressor layers
Type is contrary, and described second stress is tensile stress or compressive stress, and described second stress adulterates class with second
The doping type of type amorphous silicon layer is corresponding；
It is positioned at the transparency conducting layer on described second doping type amorphous silicon layer surface；
It is positioned at the first electrode of described layer at transparent layer；
It is positioned at the second electrode of described substrate lower surface.
12. heterojunction solar batteries according to claim 11, it is characterised in that described substrate is P
Type monocrystalline silicon piece, described first stress is compressive stress, and described second doping type amorphous silicon layer is N-type layer；
Or described substrate is n type single crystal silicon sheet, described first stressor layers has tensile stress, described second doping
Type amorphous silicon layer is P-type layer.
13. heterojunction solar batteries according to claim 11, it is characterised in that also include, in institute
State between the second doping type amorphous silicon layer and substrate upper surface, also there is tunnel oxide, described tunnelling
The thickness range of oxide layer isMaterial is silicon oxide.
14. heterojunction solar batteries according to claim 11, it is characterised in that also include, be positioned at
The first doping type heavily doped amorphous silicon layer between described second electrode and substrate lower surface, and it is positioned at institute
State second transparency conducting layer on the first doping type heavily doped amorphous silicon layer surface.
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| KR20110001821A (en) * | 2009-06-30 | 2011-01-06 | 엘지이노텍 주식회사 | Solar cell and method of fabricating the same |
| CN102446991A (en) * | 2011-12-14 | 2012-05-09 | 杭州赛昂电力有限公司 | Film solar battery based on crystalline silicon and manufacturing method thereof |
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| KR20110001821A (en) * | 2009-06-30 | 2011-01-06 | 엘지이노텍 주식회사 | Solar cell and method of fabricating the same |
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