CN103107239A - Hetero-junction solar cell and manufacturing method thereof - Google Patents
Hetero-junction solar cell and manufacturing method thereof Download PDFInfo
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- CN103107239A CN103107239A CN2012105298592A CN201210529859A CN103107239A CN 103107239 A CN103107239 A CN 103107239A CN 2012105298592 A CN2012105298592 A CN 2012105298592A CN 201210529859 A CN201210529859 A CN 201210529859A CN 103107239 A CN103107239 A CN 103107239A
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Abstract
Provided are a hetero-junction solar cell and a manufacturing method thereof. The manufacturing method of the hetero-junction solar cell comprises that a substrate is provided, and the substrate is a first doping type monocrystalline silicon piece; a first stress layer is formed on the surface of the substrate to carry out annealing treatment, and the stress type of the first stress layer corresponds to the doping type of the substrate; the first stress layer is removed; a second doping type monocrystalline silicon layer is formed on the surface of the intrinsic noncrystalline silicon layer; a transparent conducting layer is formed on the surface of the second doping type noncrystalline silicon layer; a first electrode is formed on the surface of the transparent conducting layer; and a second electrode is formed on the lower surface of the substrate. The manufacturing method of the hetero-junction solar cell can effectively improve carrier mobility of a solar cell, and improves conversion efficiency of the solar cell.
Description
Technical field
The present invention relates to area of solar cell, particularly a kind of heterojunction solar battery and preparation method thereof.
Background technology
Solar cell utilizes photoelectric effect to convert light to electric energy.Basic solar battery structure comprises single p-n junction, P-I-N/N-I-P knot and multijunction structure.Typical single p-n junction structure comprises: P type doped layer and N-type doped layer.The single p-n junction solar cell has homojunction and two kinds of structures of heterojunction: the P type doped layer of homojunction structure and N-type doped layer all are made of analog material (band gap of material equates), and heterojunction structure comprises the material with two-layer at least different band gap.The P-I-N/N-I-P structure comprise P type doped layer, N-type doped layer and be sandwiched in the P layer and the N layer between intrinsic semiconductor layer (the I layer does not adulterate).Multijunction structure comprises a plurality of semiconductor layers with different band gap, and described a plurality of semiconductor layers are stacking mutually.
In solar cell, light is absorbed near the P-N knot, produces light induced electron and photohole, and described light induced electron and photohole diffuse into the P-N knot and separated by internal electric field, and light induced electron is pushed into the N district, and the hole is pushed into the P district.Form positive and negative charge accumulated in PN junction both sides, generate thereby produce the photoproduction electromotive force electric current that passes described device and external circuit system.
At present, utilize amorphous silicon membrane as Window layer, monocrystalline silicon piece is as substrate, the heterojunction solar battery that forms had both utilized the thin film deposition processes of low temperature, brought into play again the advantage of crystalline silicon high mobility, preparation technology is simple simultaneously, has the development prospect of the high efficiency of realizing, low-cost silicon solar cell.The conversion efficiency of heterojunction solar battery is subject to the impact of several factors, remains further to be improved.
More manufacture methods about heterojunction solar battery please refer to the Chinese patent that publication number is CN101866991A.
Summary of the invention
The problem that the present invention solves is to provide a kind of heterojunction solar battery and preparation method thereof, improves the conversion efficiency of heterojunction solar battery.
For addressing the above problem, technical scheme of the present invention has proposed a kind of manufacture method of heterojunction solar battery, comprising: substrate is provided, and described substrate is the first doping type monocrystalline silicon piece; Form the first stressor layers at described substrate surface, and carry out annealing in process, the stress types of described the first stressor layers is corresponding with the doping type of substrate; Remove described the first stressor layers; Form the second doping type amorphous silicon layer at described substrate surface; At described the second doping type amorphous silicon layer surface formation transparency conducting layer; Form the first electrode in described layer at transparent layer; Form the second electrode at described substrate lower surface.
Optionally, described substrate is the p type single crystal silicon sheet, and described the first stressor layers has compression, and described the second doping type amorphous silicon layer is the N-type layer; Perhaps described substrate is the n type single crystal silicon sheet, and described the first stressor layers has tensile stress, and described the second doping type amorphous silicon layer is P type layer.
Optionally, described formation method with stressor layers of compression comprises: using plasma strengthens chemical vapor deposition method, wherein, and NH
2And SiH
4As reacting gas, inert gas is as carrier gas, and reaction temperature is 200 ℃ ~ 500 ℃, and reaction pressure is 100mTorr ~ 200mTorr, and a power is provided is 10W～100W, and frequency is the low frequency power source of 50KHz ~ 500kHz.
Optionally, described formation method with stressor layers of tensile stress comprises: using plasma strengthens chemical vapor deposition method, wherein, NH2 and SiH4 are as reacting gas, inert gas is as carrier gas, and reaction temperature is 200 ℃ ~ 500 ℃, and reaction pressure is 100mTorr ~ 200mTorr, and it is 10W～100W that a power is provided, and frequency is the radio frequency power source of 10MHz ~ 15MHz.
Optionally, the formation technique of described the first stressor layers comprises thermal chemical vapor deposition or plasma enhanced chemical vapor deposition.
Optionally, described the first stressor layers comprises silicon nitride film or silicon oxide film, and the thickness of described the first stressor layers is 0.5nm ~ 100nm, and the number range of stress is 200MPa ~ 1000MPa.
Optionally, described technique of carrying out annealing in process is rapid thermal anneal process, and the temperature range of annealing is 200 ℃～800 ℃.
Optionally, the technique of described removal the first stressor layers is dry etch process or wet etching.
Optionally, also comprise, before forming described transparency conducting layer, in second doping type amorphous silicon layer surface formation the second stressor layers, the stress types of described the second stressor layers is corresponding with the doping type of the second doping type amorphous silicon layer, remove described the second stressor layers after annealing, described the second stressor layers has the stress types opposite with the first stressor layers.
Optionally, also comprise, before forming the second doping type amorphous silicon layer, first form tunnel oxide at described substrate upper surface, the thickness range of described tunnel oxide is
Material is silica.
Optionally, also comprise, before forming the second electrode, form successively the first doping type heavily doped amorphous silicon layer at described substrate lower surface, and be positioned at second transparency conducting layer on described the first doping type heavily doped amorphous silicon layer surface.
For addressing the above problem, technical scheme of the present invention also provides a kind of heterojunction solar battery, comprising: substrate, described substrate are the first doping type monocrystalline silicon piece, and be subject to the first effect of stress, the stress types of described the first stress is corresponding with the doping type of substrate; Be positioned at the second doping type amorphous silicon layer of described substrate upper surface; Be positioned at the transparency conducting layer on described the second doping type amorphous silicon layer surface; Be positioned at the first electrode of described layer at transparent layer; Be positioned at the second electrode of described substrate lower surface.
Optionally, described substrate is the p type single crystal silicon sheet, and described the first stress is compression, and described the second doping type amorphous silicon layer is the N-type layer; Perhaps described substrate is the n type single crystal silicon sheet, and described the first stressor layers has tensile stress, and described the second doping type amorphous silicon layer is P type layer.
Optionally, described the second doping type amorphous silicon is subject to the second effect of stress, and described the second stress is tensile stress or compression, and described the second stress is corresponding with the doping type of the second doping type amorphous silicon layer.
Optionally, also comprise between described the second doping type amorphous silicon layer and substrate upper surface, also having tunnel oxide, the thickness range of described tunnel oxide is
Material is silica.
Optionally, also comprise, between described the second electrode and substrate lower surface, the first doping type heavily doped amorphous silicon layer and be positioned at second transparency conducting layer on described the first doping type heavily doped amorphous silicon layer surface.
Compared with prior art, the present invention has the following advantages:
Technical scheme of the present invention forms the first stressor layers at described substrate surface, after then carrying out annealing in process, removes described the first stressor layers.Described the first stressor layers makes substrate be subject to effect of stress, the lattice generation deformation of substrate, after annealing, the deformation of described lattice is cured, and makes substrate remember the effect of stress that the residence is subject to, after removing described the first stressor layers, described substrate still is subject to effect of stress, described stress can improve the carrier mobility in described substrate, reduces the recombination rate of charge carrier, thereby improves the conversion efficiency of heterojunction solar battery.
Further, after substrate surface after removing the first stressor layers forms the second doping type amorphous silicon layer, can also be in second doping type amorphous silicon layer surface formation the second stressor layers, then anneal and remove described the second stressor layers, make equally described the second doping type amorphous silicon layer remember the stress effect that the second stressor layers is stated in the residence, make described the second doping type amorphous silicon layer be subject to effect of stress, improve the carrier mobility in described the second doping type amorphous silicon layer.
Further, described substrate is the n type single crystal silicon sheet, has tensile stress in surperficial the first stressor layers that forms of described n type single crystal silicon sheet, removes described the first stressor layers after annealing, described n type single crystal silicon sheet is subject to the tensile stress effect, can improve the mobility of light induced electron in the n type single crystal silicon sheet; Described the second doping type amorphous silicon layer is P type layer, has compression in surperficial the second stressor layers that forms of described P type layer, removes described the second stressor layers after annealing, and described P type layer is subject to action of compressive stress, can improve the mobility of the interior photohole of P type layer.Improve the mobility of described light induced electron or photohole, can improve total current density of described heterojunction solar battery, improve the conversion efficiency of heterojunction solar battery.
Further, technical scheme of the present invention can also form tunnel oxide between described the second amorphous silicon layer and substrate.Described tunnel oxide can reduce the surface state concentration of substrate, and then reduce tunnelling current.
Further, before forming the second electrode, can also form successively the first doping type heavily doped amorphous silicon layer and the second transparency conducting layer at the substrate lower surface, then form the second electrode in described the second layer at transparent layer.Introduce the first doping type heavily doped amorphous silicon layer with the substrate homotype in the contact zone of the substrate back of described heterojunction solar battery, can produce the potential barrier effect to the few son of photoproduction, thereby reduce overleaf compound of photo-generated carrier, thereby improve the conversion efficiency of heterojunction solar battery.
Description of drawings
Fig. 1 is the schematic flow sheet of the manufacture method of the heterojunction solar battery in embodiments of the invention;
Fig. 2 to Fig. 7 is the generalized section of the manufacture method of the heterojunction solar battery in embodiments of the invention.
Embodiment
As described in the background art, the conversion efficiency of heterojunction solar battery remains further to be improved at present.
Research is found, the compound direct open circuit voltage that affects solar cell of photo-generated carrier.So at charge carrier in the process of electrode movement, thereby the migration rate that improves charge carrier can effectively reduce the conversion efficiency that the recombination rate of photo-generated carrier improves solar cell.
Embodiments of the invention have proposed a kind of heterojunction solar battery and preparation method thereof, adopt stress memory technique at substrate surface, after forming the first stressor layers, after annealing, describedly then remove described the first stressor layers, described substrate still can be subject to the stress effect effect of described the first stressor layers, thereby improves the mobility of charge carrier in described substrate, improves the conversion efficiency of described heterojunction solar battery.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Described embodiment is only the part of embodiment of the present invention, rather than they are whole.When the embodiment of the present invention was described in detail in detail, for ease of explanation, schematic diagram can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit protection scope of the present invention at this.The three-dimensional space that should comprise in addition, length, width and the degree of depth in actual fabrication.According to described embodiment, those of ordinary skill in the art belongs to protection scope of the present invention need not obtainable all other execution modes under the prerequisite of creative work.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
Please refer to Fig. 1, the schematic flow sheet for the manufacture method of heterojunction solar battery in the present embodiment comprises:
Step S1: substrate is provided, and described substrate is the first doping type monocrystalline silicon piece;
Step S2: the upper surface at described substrate forms the first stressor layers, and carries out annealing in process, and the stress types of described the first stressor layers is corresponding with the doping type of substrate;
Step S3: remove described the first stressor layers;
Step S4: form the second doping type amorphous silicon layer at described substrate upper surface;
Step S5: at described the second doping type amorphous silicon layer surface formation transparency conducting layer;
Step S6: form the first electrode in described layer at transparent layer, form the second electrode at described substrate lower surface.
Please refer to Fig. 2, substrate 100 is provided, described substrate is the first doping type monocrystalline silicon piece.
Concrete, described substrate 100 is p type single crystal silicon sheet or n type single crystal silicon sheet, the substrate that adopts in the present embodiment is the n type single crystal silicon sheet, described n type single crystal silicon sheet is when forming silicon chip, described silicon chip to be carried out the phosphonium ion doping, can also be described silicon chip to be carried out the doping of one or more ions in phosphorus, arsenic or antimony.
Please refer to Fig. 3, in upper surface formation first stressor layers 101 of described substrate 100, and carry out annealing in process, the stress types of described the first stressor layers is corresponding with the doping type of substrate.
Before described substrate upper surface forms the first stressor layers, at first described substrate is cleaned, remove the impurity of substrate surface, thereby avoid the performance of impurity effect solar cell.After cleaning, can also prepare matte at described substrate surface, with aqueous slkali, substrate surface is carried out anisotropic etch, form matte at described substrate surface, described matte can improve the contact area of substrate surface and sunlight and reduce sun reflection of light.After the preparation matte, then form the first stressor layers 101 at described substrate upper surface.
Described the first stressor layers 101 comprises silicon nitride film, silicon oxide film etc.The formation technique of described the first stressor layers 101 is plasma enhanced chemical vapor deposition (PECVD) or thermal chemical vapor deposition.
In the present embodiment, described substrate is the n type single crystal silicon sheet, has the first stressor layers of tensile stress in the surface formation of described n type single crystal silicon sheet, and described the first stressor layers with tensile stress comprises silicon nitride or silicon oxide film etc.In one embodiment of the invention, described the first stressor layers with tensile stress is silicon nitride film, and the formation technique of employing is plasma enhanced chemical vapor deposition, and wherein, reacting gas is NH
2And SiH
4, utilize the inert gases such as Ar as carrier gas, SiH
4And NH
2Gas flow ratio be 0.1 ~ 4, reaction temperature is 200 ℃ ~ 500 ℃, reaction pressure is 100mTorr ~ 200mTorr, and a power is provided is the radio frequency power source of 10W～100W, frequency is 13.56MHz.The thickness of described the first stressor layers is 0.5nm～100nm, has tensile stress, and the tensile stress number range is 200MPa ~ 1000MPa.Described the first stressor layers with tensile stress makes the n type single crystal silicon sheet be subject to the effect of the tensile stress in horizontal plane.
In other embodiments of the invention, described substrate 100 is the p type single crystal silicon sheet, the first stressor layers 101 that has compression in the surface formation of described p type single crystal silicon sheet, described stressor layers 101 with compression is silicon nitride film, the formation technique that adopts is plasma enhanced chemical vapor deposition, wherein, reacting gas is NH
2And SiH
4, utilize the inert gases such as Ar as carrier gas, SiH
4And NH
2Gas flow ratio be 0.1 ~ 4, reaction temperature is 200 ℃ ~ 500 ℃, reaction pressure is 100mTorr ~ 200mTorr, the low frequency power source that a power is provided is 10W～100W, frequency is 100KHz.The thickness of described stressor layers is 0.5nm～100nm, has compression, and the number range of compression is 200MPa～1000MPa.Described the first stressor layers 101 with compression makes substrate 100 be subject to the effect of the compression in horizontal plane.
After forming described the first stressor layers 101, carry out annealing in process.Described annealing treating process is rapid thermal anneal process, and the temperature range of annealing is 200 ℃～800 ℃.Make described substrate 100 produce the stress memory effect, remember the described stress that is subject to.In the present embodiment, described substrate 100 is the n type single crystal silicon sheet, described the first stressor layers 101 has tensile stress, make substrate under effect of stress, lattice generation deformation is after annealing, the deformation of described lattice is cured, make substrate remember the effect of stress that the residence is subject to, after follow-up removal the first stressor layers 101, described substrate 100 also is subject to the effect of described tensile stress.Electronics in described substrate is made stereo-motion in three-dimensional in the process that flows to the second electrode, described tensile stress can improve the mobility of substrate 100 interior electronics, improve the mobility of the light induced electron in the substrate 100 of described N-type, reduce the recombination probability of described light induced electron in the process of the second electrode movement, improve the quantity of the light induced electron of collecting at described the second electrode place, improve total current density of solar cell, thereby improve the efficient of heterojunction solar battery.
In other embodiments of the invention, described substrate is the p type single crystal silicon sheet, and described the first stressor layers has compression, so after annealing, remembered the described compression that is subject in described substrate, after follow-up removal the first stressor layers, described substrate also is subject to the effect of described compression.Stereo-motion is made in the hole in three-dimensional in the process that flows to the second electrode, described compression can improve the mobility in hole in substrate, improve the mobility of the photohole in the substrate 100 of described P type, reduce the recombination probability of described light induced electron in the process of the second electrode movement, improve the quantity of the photohole of collecting at described the second electrode place, improve total current density of solar cell, thereby improve the efficient of solar cell.
Please refer to Fig. 4, remove described the first stressor layers 101(and please refer to Fig. 3).
The method of removing described the first stressor layers 101 is dry etching or wet etching.Adopt dry etch process to remove described the first stressor layers 103 in the present embodiment.After removing described the first stressor layers 101, described substrate still is subject to the effect of stress due to the stress memory effect.
Because the method that adopts wet method or dry etching is removed described the first stressor layers, when removing described the first stressor layers, can prepare matte to the surface of described substrate, thereby improve the contact area of solar cell surface, the reflection of reduction to sunlight improves the absorptivity to sunlight.
Please refer to Fig. 5, at described substrate 100 surface formation the second doping type amorphous silicon layers 102.
Concrete, described the second doping type amorphous silicon layer 102 can be N-type layer or P type layer, the thickness of described the second doping type amorphous silicon layer 102 is
The formation technique of described the second doping type amorphous silicon layer 102 can be the techniques such as low-pressure chemical vapor deposition, plasma activated chemical vapour deposition, liquid phase epitaxy or sputtering sedimentation.
In the present embodiment, using plasma strengthens chemical vapour deposition technique and forms described the second doping type amorphous silicon layer 102, and described the second doping type amorphous silicon layer 102 is P type layer, and specifically formation method is: with SiH
2Cl
2, SiHCl
3, SiCl
4Or SiH
4As reacting gas, reaction generates silicon atom under certain protective atmosphere, at the upper surface deposition formation amorphous silicon layer of substrate, more described amorphous silicon layer is carried out P type ion doping, forms the second doping type amorphous silicon layer 102.Described the second doping type ion doping can adopt Implantation or diffusion technology to form, and also can adopt in-situ doped technique to form when forming amorphous silicon layer.Described doping ion comprises one or more of boron, gallium or indium, and the concentration of doping ion is 1E10/cm
3~ 1E20/cm
3
In other embodiments of the invention, if described substrate 100 is the p type single crystal silicon sheet, described the second doping type amorphous silicon layer 102 is the N-type layer, after adopting the method formation amorphous silicon layer in the present embodiment, described amorphous silicon layer is carried out the N-type ion doping, form the second doping type amorphous silicon layer.Described N-type ion doping can adopt Implantation or diffusion technology to form, and also can adopt in-situ doped technique to form when forming amorphous silicon layer.The doping ion comprises one or more in phosphorus, arsenic or antimony, and the concentration of doping ion is 1E10/cm
3~ 1E20/cm
3
In other embodiments of the invention, can also be first after described substrate upper surface first forms intrinsic amorphous silicon layer, then at described intrinsic amorphous silicon layer surface formation the second doping type amorphous silicon layer.Concrete, described intrinsic amorphous silicon layer is low-doped or undoped amorphous silicon layer, the thickness of described intrinsic amorphous silicon layer is 5nm ~ 50nm.The formation technique of described intrinsic amorphous silicon layer can be low-pressure chemical vapor deposition or the techniques such as plasma activated chemical vapour deposition, liquid phase epitaxy or sputtering sedimentation.Described intrinsic amorphous silicon layer can play passivation to substrate surface, reduces charge carrier in the recombination rate of substrate surface, improves the conversion efficiency of solar cell.
In other embodiment of the present invention, can also be after described substrate surface forms intrinsic amorphous silicon layer, adopt stress memory technique, at described intrinsic amorphous silicon layer surface formation tertiary stress layer, remove described tertiary stress layer after annealing in process, described annealing treating process is rapid thermal anneal process, the temperature range of annealing is 200 ℃～800 ℃, this annealing temperature can not be too high, because if the too high amorphous that easily makes of annealing temperature converts polycrystalline to, thereby affects the performance of heterojunction solar battery.Make described intrinsic amorphous silicon layer be subject to effect of stress, then at described intrinsic amorphous silicon layer surface formation the second doping type amorphous silicon layer.The stress types of described tertiary stress layer can be tensile stress, can be also compression.Due in solar cell, the effective mass in hole is greater than the effective mass of electronics, so the hole migration rate less than the migration rate of electronics, so described tertiary stress layer can have compression, make intrinsic amorphous silicon layer be subject to the effect of compression, improve the mobility of photohole in described intrinsic amorphous silicon layer, improve total current density in described heterojunction solar battery, thereby improve the conversion efficiency of heterojunction solar battery.
In other embodiments of the invention, in order to reduce the surface state concentration of substrate, and then reduce tunnelling current, can also first form tunnel oxide at the upper surface of described substrate 100, and then form the second doping type amorphous silicon layer on described tunnel oxide surface or form successively intrinsic amorphous silicon layer and the second doping type amorphous silicon layer on described tunnel oxide surface.Described tunnel oxide can adopt low thermal oxidation technique or wet oxidation process to form.Particularly, the material of described tunnel oxide can be silica, and its thickness range is
For example:
Or
Please refer to Fig. 6, at described the second doping type amorphous silicon layer 102 surface formation transparency conducting layers 103.
Concrete, described transparency conducting layer 103 is transparent conductive film, comprises SnO 2 thin film, zinc-oxide film, indium tin oxide films etc.In the present embodiment, described transparency conducting layer 103 is SnO 2 thin film, can the transmission most of incident light of described transparency conducting layer 103, and have electric current to flow in transparency conducting layer 103.In the present embodiment, described transparency conducting layer 103 adopts magnetron sputtering technique to form, and thickness range is
Described transparency conducting layer 103 can also play the effect of passivated surface to the second doping type amorphous silicon layer surface except electric action, reduce the recombination rate of charge carrier.
In other embodiments of the invention, before forming described transparency conducting layer 103, can also form the second stressor layers on described the second doping type amorphous silicon layer 102 surfaces, annealing in process then, and remove described the second stressor layers.The type of described the second stressor layers is corresponding with the doping type of the second doping type amorphous silicon layer 102, if described the second doping type amorphous silicon layer is P type layer, described the second stressor layers has compression; If described the second doping type amorphous silicon layer is the N-type layer, described the second stressor layers has tensile stress.After removing described the second stressor layers, due to lattice deformation, be subject to effect of stress in described the second doping type amorphous silicon layer, can improve the mobility of charge carrier in described the second doping type amorphous silicon layer.
Please refer to Fig. 7, at described transparency conducting layer 103 surface formation the first electrodes 104, form the second electrodes 105 at described substrate 100 lower surfaces.
The concrete technology that forms described the first electrode 104 and the second electrode 105 is known for those skilled in the art, does not repeat them here.
In other embodiments of the invention, before forming the second electrode, can also form successively the first doping type heavily doped amorphous silicon layer and the second transparency conducting layer at described substrate lower surface, then form the second electrode in described the second layer at transparent layer.The first doping type heavily doped amorphous silicon layer of the same type with substrate introduced in contact zone, the back side at described heterojunction solar battery, can produce the potential barrier effect to the few son of photoproduction, thereby the minimizing charge carrier is compound the substrate lower surface, thereby improves the conversion efficiency of heterojunction solar battery.
Embodiments of the invention have also proposed a kind of heterojunction solar battery that adopts said method to form.
Please refer to Fig. 7, be the generalized section of the heterojunction solar battery of the present embodiment.
Described heterojunction solar battery comprises: substrate 100, described substrate are the first doping type monocrystalline silicon piece, and described substrate is subject to the first effect of stress, and the type of described the first stress is corresponding with the doping type of substrate; Be positioned at the second doping type amorphous silicon layer 102 of described substrate 100 upper surfaces; Be positioned at the transparency conducting layer 103 on described the second doping type amorphous silicon layer 102 surfaces; Be positioned at first electrode 104 on described transparency conducting layer 103 surfaces; Be positioned at the second electrode 105 of described substrate 100 lower surfaces.
Concrete, in the present embodiment, described substrate 100 is the n type single crystal silicon sheet, the first stress that described substrate 100 is subject to is tensile stress.Electronics in substrate 100 is made stereo-motion in three-dimensional in the process that flows to the second electrode, described tensile stress can improve the mobility of substrate 100 interior electronics, improve the mobility of the light induced electron in the substrate 100 of described N-type, reduce the recombination probability of described light induced electron in the process of the second electrode movement, improve the quantity of the light induced electron of collecting at described the second electrode place, improve total current density of solar cell, improve the efficient of heterojunction solar battery.In other embodiments of the invention, described substrate 100 can be the p type single crystal silicon sheet, and the first stress that described substrate 100 is subject to is compression.Stereo-motion is made in hole in substrate 100 in three-dimensional in the process that flows to the second electrode, described compression can improve the mobility of substrate 100 interior electronics, improve the mobility of the photohole in the substrate 100 of described P type, reduce the recombination probability of described photohole in the process of the second electrode movement, improve the quantity of the photohole of collecting at described the second electrode place, improve total current density of solar cell, improve the efficient of solar cell.
In the present embodiment, described the second doping type amorphous silicon layer 102 is P type amorphous silicon layer.In other embodiments of the invention, described the second doping type amorphous silicon layer 102 also can be subject to the second effect of stress.If described the second doping type amorphous silicon layer 102 is P type amorphous silicon layer, described the second stress is compression; If described the second doping type amorphous silicon layer 102 is the N-type amorphous silicon layer, described the second stress is tensile stress.
In other embodiments of the invention, also has tunnel oxide between described the second amorphous silicon layer 102 and substrate upper surface.Described tunnel oxide can adopt low thermal oxidation technique or wet oxidation process to form.Particularly, the material of described tunnel oxide can be silica, and its thickness range is
For example:
Or
Described tunnel oxide can reduce the surface state concentration of substrate, and then reduces tunnelling current.
In other embodiments of the invention, also has intrinsic amorphous silicon layer between described the second amorphous silicon layer 102 and substrate upper surface.Concrete, described intrinsic amorphous silicon layer is low-doped or undoped amorphous silicon layer, the thickness of described intrinsic amorphous silicon layer is 5nm ~ 50nm.The formation technique of described intrinsic amorphous silicon layer can be low-pressure chemical vapor deposition or the techniques such as plasma activated chemical vapour deposition, liquid phase epitaxy or sputtering sedimentation.Described intrinsic amorphous silicon layer can play passivation to substrate surface, reduces charge carrier in the recombination rate of substrate surface, improves the conversion efficiency of solar cell.Described intrinsic amorphous silicon layer also can be subject to the effect of tertiary stress, and described tertiary stress can be compression, can be also tensile stress.
In other embodiments of the invention, described heterojunction solar battery can also comprise the first doping type heavily doped amorphous silicon layer between described the second electrode 105 and substrate 100 lower surfaces and be positioned at second transparency conducting layer on described the first doping type heavily doped amorphous silicon layer surface, and described the first doping type heavily doped amorphous silicon layer is positioned at the substrate lower surface.Introduce and the first doping type heavily doped amorphous silicon layer of substrate with doping type at the substrate lower surface of described heterojunction solar battery, can produce the potential barrier effect to the few son of photoproduction, carry on the back the compound of surface thereby reduce charge carrier, thereby improving the conversion efficiency of heterojunction solar battery.
By the explanation of above-described embodiment, should be able to make this area professional and technical personnel understand better the present invention, and can reproduce and use the present invention.Those skilled in the art can be in the situation that do not break away from that the spirit and scope of the invention are done various changes to above-described embodiment and modification is apparent according to described principle herein.Therefore, the present invention should not be understood to be limited to above-described embodiment shown in this article, and its protection range should be defined by appending claims.
Claims (16)
1. the manufacture method of a heterojunction solar battery, is characterized in that, comprising:
Substrate is provided, and described substrate is the first doping type monocrystalline silicon piece;
Form the first stressor layers at described substrate surface, and carry out annealing in process, the stress types of described the first stressor layers is corresponding with the doping type of substrate;
Remove described the first stressor layers;
Form the second doping type amorphous silicon layer at described substrate surface;
At described the second doping type amorphous silicon layer surface formation transparency conducting layer;
Form the first electrode in described layer at transparent layer;
Form the second electrode at described substrate lower surface.
2. the manufacture method of heterojunction solar battery according to claim 1, is characterized in that, described substrate is the p type single crystal silicon sheet, and described the first stressor layers has compression, and described the second doping type amorphous silicon layer is the N-type layer; Perhaps described substrate is the n type single crystal silicon sheet, and described the first stressor layers has tensile stress, and described the second doping type amorphous silicon layer is P type layer.
3. the manufacture method of heterojunction solar battery according to claim 2, is characterized in that, described formation method with stressor layers of compression comprises: using plasma strengthens chemical vapor deposition method, wherein, and NH
2And SiH
4As reacting gas, inert gas is as carrier gas, and reaction temperature is 200 ℃ ~ 500 ℃, and reaction pressure is 100mTorr ~ 200mTorr, and a power is provided is 10W～100W, and frequency is the low frequency power source of 50KHz ~ 500kHz.
4. the manufacture method of heterojunction solar battery according to claim 2, is characterized in that, described formation method with stressor layers of tensile stress comprises: using plasma strengthens chemical vapor deposition method, wherein, and NH
2And SiH
4As reacting gas, inert gas is as carrier gas, and reaction temperature is 200 ℃ ~ 500 ℃, and reaction pressure is 100mTorr ~ 200mTorr, and a power is provided is 10W～100W, and frequency is the radio frequency power source of 10MHz ~ 15MHz.
5. the manufacture method of heterojunction solar battery according to claim 1, is characterized in that, the formation technique of described the first stressor layers comprises thermal chemical vapor deposition or plasma enhanced chemical vapor deposition.
6. the manufacture method of heterojunction solar battery according to claim 1, it is characterized in that, described the first stressor layers comprises silicon nitride film or silicon oxide film, and the thickness of described the first stressor layers is 0.5nm ~ 100nm, and the number range of stress is 200MPa ~ 1000MPa.
7. the manufacture method of heterojunction solar battery according to claim 1, is characterized in that, described technique of carrying out annealing in process is rapid thermal anneal process, and the temperature range of annealing is 200 ℃ ~ 800 ℃.
8. the manufacture method of heterojunction solar battery according to claim 1, is characterized in that, the technique of described removal the first stressor layers is dry etch process or wet-etching technology.
9. the manufacture method of heterojunction solar battery according to claim 1, it is characterized in that, also comprise, before forming described transparency conducting layer, in second doping type amorphous silicon layer surface formation the second stressor layers, the stress types of described the second stressor layers is corresponding with the doping type of the second doping type amorphous silicon layer, removes described the second stressor layers after annealing, and described the second stressor layers has the stress types opposite with the first stressor layers.
10. the manufacture method of heterojunction solar battery according to claim 1, is characterized in that, also comprises, before forming the second doping type amorphous silicon layer, first forms tunnel oxide at described substrate upper surface, and the thickness range of described tunnel oxide is
Material is silica.
11. the manufacture method of heterojunction solar battery according to claim 1, it is characterized in that, also comprise, before forming the second electrode, form successively the first doping type heavily doped amorphous silicon layer and be positioned at second transparency conducting layer on described the first doping type heavily doped amorphous silicon layer surface at described substrate lower surface.
12. a heterojunction solar battery is characterized in that, comprising:
Substrate, described substrate are the first doping type monocrystalline silicon piece, and are subject to the first stress, and the stress types of described the first stress is corresponding with the doping type of substrate;
Be positioned at the second doping type amorphous silicon layer of described substrate upper surface;
Be positioned at the transparency conducting layer on described the second doping type amorphous silicon layer surface;
Be positioned at the first electrode of described layer at transparent layer;
Be positioned at the second electrode of described substrate lower surface.
13. heterojunction solar battery according to claim 12 is characterized in that, described substrate is the p type single crystal silicon sheet, and described the first stress is compression, and described the second doping type amorphous silicon layer is the N-type layer; Perhaps described substrate is the n type single crystal silicon sheet, and described the first stressor layers has tensile stress, and described the second doping type amorphous silicon layer is P type layer.
14. heterojunction solar battery according to claim 12, it is characterized in that, described the second doping type amorphous silicon is subject to the second effect of stress, and described the second stress is tensile stress or compression, and described the second stress is corresponding with the doping type of the second doping type amorphous silicon layer.
15. heterojunction solar battery according to claim 12 is characterized in that, also comprises, between described the second doping type amorphous silicon layer and substrate upper surface, also has tunnel oxide, the thickness range of described tunnel oxide is
Material is silica.
16. heterojunction solar battery according to claim 12, it is characterized in that, also comprise, the first doping type heavily doped amorphous silicon layer between described the second electrode and substrate lower surface, and be positioned at second transparency conducting layer on described the first doping type heavily doped amorphous silicon layer surface.
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| CN109273585A (en) * | 2018-08-28 | 2019-01-25 | 中国科学院上海微系统与信息技术研究所 | Membrane deposition method and Josephson junction preparation method |
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| KR20110001821A (en) * | 2009-06-30 | 2011-01-06 | 엘지이노텍 주식회사 | Solar cell and method of fabricating the same |
| CN102446991A (en) * | 2011-12-14 | 2012-05-09 | 杭州赛昂电力有限公司 | Film solar battery based on crystalline silicon and manufacturing method thereof |
| US20120222731A1 (en) * | 2011-03-02 | 2012-09-06 | National Tsing Hua University | Heterojunction Solar Cell Having Amorphous Silicon Layer |
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| CN1971882A (en) * | 2005-11-10 | 2007-05-30 | 国际商业机器公司 | Method of providing a dual stress memory technique and related structure |
| KR20110001821A (en) * | 2009-06-30 | 2011-01-06 | 엘지이노텍 주식회사 | Solar cell and method of fabricating the same |
| US20120222731A1 (en) * | 2011-03-02 | 2012-09-06 | National Tsing Hua University | Heterojunction Solar Cell Having Amorphous Silicon Layer |
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| CN109273585A (en) * | 2018-08-28 | 2019-01-25 | 中国科学院上海微系统与信息技术研究所 | Membrane deposition method and Josephson junction preparation method |
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