CN105895715A - Heterojunction solar cell and preparation method therefor - Google Patents
Heterojunction solar cell and preparation method therefor Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
- H01L31/0376—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors
- H01L31/03762—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors including only elements of Group IV of the Periodic System
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System
- H01L31/0288—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System characterised by the doping material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention relates to the field of solar cells, and specifically discloses a heterojunction solar cell. The solar cell comprises a crystalline silicon wafer, a first intrinsic layer, a second intrinsic layer, a first doped amorphous silicon layer, a first transparent conducting layer, a first electrode, and a second electrode, wherein the first intrinsic layer, the second intrinsic layer, the first doped amorphous silicon layer, the first transparent conducting layer and the first electrode are located at one side of the crystalline silicon wafer, and the second electrode is located at the other side of the crystalline silicon wafer. An optical band gap Eg1 of the first intrinsic layer is between an optical band gap Eg2 of the second intrinsic layer and an optical band gap Eg of the crystalline silicon wafer. Because the solar cell employs the first and second intrinsic layers and the optical band gap Eg1 of the first intrinsic layer is between the optical band gap Eg2 of the second intrinsic layer and the optical band gap Eg of the crystalline silicon wafer, the solar cell effectively improves the structural quality of the intrinsic layers, and improves the open-circuit voltage, wherein the increase range can reach 0.02V. The invention also discloses a preparation method for the solar cell.
Description
Technical field
The present invention relates to area of solar cell, particularly relate to a kind of heterojunction solar battery and preparation method thereof.
Background technology
Heterojunction solar battery (HIT battery) is by adding constructed by intrinsic structure between doped amorphous silicon layer and crystalline silicon substrate.Heterojunction solar battery had both had high efficiency and the high stability of crystal silicon solar energy battery, simultaneously because energy consumption is little, technique is relatively easy, temperature characterisitic is more preferable, the most also can have higher output.Receive much concern in recent years, one of main development direction having become as solaode.
The character of intrinsic structure is the key factor affecting heterojunction solar battery performance；The most important thing is, the character of intrinsic structure affects the open-circuit voltage of heterojunction solar battery.But the open-circuit voltage of current heterojunction solar battery is the most relatively low, need to be improved further.
Summary of the invention
Based on this, it is necessary to for the problem that open-circuit voltage in existing heterojunction solar battery is low, it is provided that the heterojunction solar battery that a kind of open-circuit voltage is high.
A kind of heterojunction solar battery, including: crystal silicon chip, the first intrinsic layer, the second intrinsic layer, the first doped amorphous silicon layer, the first transparency conducting layer and the first electrode being sequentially located on the side of described crystal silicon chip, and it is positioned at the second electrode of the opposite side of described crystal silicon chip；
Wherein, the optical band gap Eg of the first intrinsic layer1Optical band gap Eg between described second intrinsic layer2Optical band gap Eg with described crystal silicon chipBrilliantBetween.
Above-mentioned heterojunction solar battery, owing to using the first intrinsic layer and the second intrinsic layer, and the optical band gap Eg of the first intrinsic layer1Optical band gap Eg between the second intrinsic layer2Optical band gap Eg with crystal silicon chipBrilliantBetween, thus it is effectively increased the structural property of intrinsic layer, and improve the open-circuit voltage of heterojunction solar battery, amplification is up to 0.02V.
Wherein in an embodiment, the optical band gap Eg of described second intrinsic layer2For 1.6eV ＜ Eg2＜ 1.8eV.
Wherein in an embodiment, the optical band gap Eg of described first intrinsic layer1For 1.12eV ＜ Eg1＜ 1.8eV.
Wherein in an embodiment, described first intrinsic layer is intrinsic silicon hydride, and described second intrinsic layer is intrinsic silicon hydride.
Wherein in an embodiment, the thickness of described first intrinsic layer is less than the thickness of described second intrinsic layer.
Wherein in an embodiment, the thickness of described first intrinsic layer is 2～5nm.
Wherein in an embodiment, described heterojunction solar battery also includes the reinforcement electric field unit between described second electrode and described crystal silicon chip；Described reinforcement electric field unit includes the 3rd intrinsic amorphous silicon layer and the second doped amorphous silicon layer being sequentially located on the opposite side of described crystal silicon chip.
Wherein in an embodiment, described heterojunction solar battery also includes the 4th intrinsic amorphous silicon layer between described crystal silicon chip and the 3rd intrinsic amorphous silicon layer；The optical band gap of the 4th intrinsic amorphous silicon layer optical band gap between described 3rd intrinsic amorphous silicon layer and the optical band gap of described crystal silicon chip.
Wherein in an embodiment, the optical band gap of described first intrinsic layer is identical with the optical band gap of described 4th intrinsic amorphous silicon layer；The optical band gap of described second intrinsic layer is identical with the optical band gap of described 3rd intrinsic amorphous silicon layer.
Present invention also offers the preparation method of a kind of above-mentioned heterojunction solar battery.
The preparation method of a kind of heterojunction solar battery, comprises the steps:
The first intrinsic layer is formed in the side of crystal silicon chip；
Described first intrinsic layer forms the second intrinsic layer；The optical band gap of the first intrinsic layer optical band gap between described second intrinsic layer and the optical band gap of described crystal silicon chip；
Described second intrinsic layer forms the first doped amorphous silicon layer；
Described first doping amorphous layer forms the first transparency conducting layer；
Described first transparency conducting layer forms the first electrode；
Opposite side at described crystal silicon chip forms the second electrode.
Above-mentioned preparation method, can be effectively improved the open-circuit voltage of heterojunction solar battery, and technique is easily controlled, and production capacity is big, the beneficially industrialization large-scale production of heterojunction solar battery.
Wherein in an embodiment, before forming described second intrinsic layer, also include the step that described first intrinsic layer is carried out hydrogen passivation.
Accompanying drawing explanation
Fig. 1 is the structural representation of the heterojunction solar battery of one embodiment of the invention.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with detailed description of the invention, the present invention is further elaborated.Should be appreciated that detailed description of the invention described herein, only in order to explain the present invention, is not intended to limit the present invention.
It should be noted that be referred to as " being arranged at " another element when element, it can be directly on another element or can also there is element placed in the middle.When an element is considered as " connection " another element, and it can be directly to another element or may be simultaneously present centering elements.For illustrative purposes only, being not offered as is unique embodiment for term as used herein " vertical ", " level ", "left", "right" and similar statement.
Unless otherwise defined, all of technology used herein is identical with the implication that the those skilled in the art belonging to the present invention are generally understood that with scientific terminology.The term used the most in the description of the invention is intended merely to describe the purpose of specific embodiment, it is not intended that in limiting the present invention.Term as used herein " and/or " include the arbitrary and all of combination of one or more relevant Listed Items.
See Fig. 1, the heterojunction solar battery 100 of an embodiment of the present invention, including: crystal silicon chip 110, the first intrinsic layer the 121, second intrinsic layer the 122, first doped amorphous silicon layer the 131, first transparency conducting layer 151 and the first electrode 161 being sequentially located on the side (upside in Fig. 1) of crystal silicon chip 110；And it is sequentially located at the 4th intrinsic layer the 124, the 3rd intrinsic layer the 123, second doped amorphous silicon layer the 132, second transparency conducting layer 152 and the second electrode 162 of the opposite side (downside in Fig. 1) of crystal silicon chip 110.
In the present embodiment, heterojunction solar battery 100 the most symmetrically structure, so can reduce the thinning development of thermal stress and mechanical stress in production process, the most beneficially crystal silicon chip 110.Generated energy is made to increase it addition, two sides all can absorb light.
In the present invention, crystal silicon chip 110 and the first doped amorphous silicon layer 131 constitute PN junction.Crystal silicon chip 110 and the second doped amorphous silicon layer 132 composition add highfield (being also back of the body electric field).The open-circuit voltage of heterojunction solar battery 100 can be improved further by adding highfield.Highfield is added, say, that do not set the second doped amorphous silicon layer 132 it is, of course, understood that can not also set.
In the present embodiment, crystal silicon chip 110 is N-type crystalline silicon sheet (n-c-Si), accordingly, the first doped amorphous silicon layer 131 is P-type non-crystalline silicon layer (p-a-Si), and the second doped amorphous silicon layer 132 is N-type non-crystalline silicon layer (n-a-Si).It is, of course, understood that be not limited to above-mentioned form, in the heterojunction solar battery of the present invention, it is also possible to be crystal silicon chip 110 be p-type, accordingly, the first doped amorphous silicon layer 131 is N-type, and the second doped amorphous silicon layer 132 is p-type.
In the present embodiment, crystal silicon chip 110 uses N-type crystalline silicon sheet (n-c-Si), the performance that can make heterojunction solar battery 100 is more superior, the photic decay of battery using p-type can be overcome, additionally, the density at its high efficiency composition center is far below p-type so that electronics has higher life-span and diffusion length.Specifically, crystalline silicon can be monocrystal silicon or polysilicon.More specifically, the crystal silicon chip 110 of present embodiment is n type single crystal silicon sheet.
Specifically, the thickness of crystal silicon chip 110 is generally less than 200 μm.Preferably, the thickness of crystal silicon chip 110 is 100～200 μm.The most both can save the use of silicon materials, and then reduce cost；Technology stability can be improved again.
Preferably, the surface of crystal silicon chip 110 is matte；It is to say, crystalline silicon is carried out making herbs into wool.So can reduce the reflection of battery surface so that more photon can be absorbed by crystal silicon chip 110；The most also there is the effect that can remove surface of crystalline silicon damage.In the present embodiment, matte is Pyramid matte, is so more beneficial for light and slants the inside of crystal silicon chip 110, reduces the reflectance of the light of battery surface so that light path becomes big, and the number of photons quantitative change of absorption is many.
Wherein, first intrinsic layer 121 and the second intrinsic layer 122 constitute upper intrinsic structure, and the effect of upper intrinsic structure is, is used for being passivated crystal silicon chip 110, the interface making crystal silicon chip 110 and the first doped amorphous silicon layer 131 obtains purification, and then makes the open-circuit voltage of heterojunction solar battery 100 increase.The optical band gap of upper intrinsic structure is all between crystal silicon chip 110 and the first doped amorphous silicon layer 131.Specifically, the optical band gap Eg of the first intrinsic layer 1211Optical band gap Eg less than the second intrinsic layer 1222(Eg1＜ Eg2)；So it is to say, the optical band gap Eg of the first intrinsic layer 1211Optical band gap Eg between the second intrinsic layer 1222Optical band gap Eg with crystal silicon chip 110Brilliant(EgBrilliant＜ Eg1＜ Eg2).Namely from the first doped amorphous silicon layer to crystal silicon chip, the optical band gap of each layer tapers off state.So on the one hand, few sub-collection can be helped, increase minority carrier life time；On the other hand, the band gap after gradual change can increase the absorption efficiency of actual spectrum.Preferably, the optical band gap Eg of the first intrinsic layer 1211For 1.12eV ＜ Eg1＜ 1.8eV.The optical band gap Eg of the second intrinsic layer 1212For 1.6eV ＜ Eg2＜ 1.8eV.So can improve the performance of heterojunction solar battery further.
Usually, the thickness of upper intrinsic structure is not more than 10nm, preferably 5～10nm.So can reduce the upper intrinsic structure absorption to light simultaneously, reduce cell resistance simultaneously so that heterojunction solar battery has higher open-circuit voltage, improve fill factor, curve factor.Preferably, the thickness of the first intrinsic layer 121 is less than the thickness of the second intrinsic layer 122.While so can increasing heterojunction solar battery open-circuit voltage, reduce owing to series resistance increases the impact on fill factor, curve factor.It is highly preferred that the thickness of the first intrinsic layer 121 is 2～5nm；The thickness of the second intrinsic layer 122 is 3～8nm.In the present embodiment, the thickness of the first intrinsic layer 121 is 3nm, and the thickness of the second intrinsic layer 122 is 5nm.
In the present embodiment, the first intrinsic layer 121 is intrinsic silicon hydride, and the second intrinsic layer 122 is intrinsic silicon hydride.
4th intrinsic layer 124 and the 3rd intrinsic layer 123 are similar with the first intrinsic layer 121 and the second intrinsic layer 122.3rd intrinsic layer 123 and the 4th intrinsic layer 124 constitute lower intrinsic structure；The effect of lower intrinsic structure is, is used for being passivated crystal silicon chip 110, makes the interface of crystal silicon chip 110 and the second doped amorphous silicon layer 132 obtain purification, and then makes the open-circuit voltage of heterojunction solar battery 100 increase.The optical band gap of lower intrinsic structure is between crystal silicon chip 110 and the second doped amorphous silicon layer 132.Preferably, the optical band gap Eg of the 4th intrinsic layer 1244Optical band gap Eg less than the 3rd intrinsic layer 1233；It is to say, the optical band gap Eg of the 4th intrinsic layer 1244Optical band gap Eg between the 3rd intrinsic layer 1233Optical band gap Eg with crystal silicon chip 110Brilliant.Preferably, the optical band gap Eg of the 4th intrinsic layer 1243For 1.12eV ＜ Eg3＜ 1.8eV.The optical band gap Eg of the 3rd intrinsic layer 1234For 1.6eV ＜ Eg4＜ 1.8eV.
In the present embodiment, the optical band gap Eg of the first intrinsic layer 1211Optical band gap Eg with the 4th intrinsic layer 1244Identical；The optical band gap Eg of the second intrinsic layer 1222Optical band gap Eg with the 3rd intrinsic layer 1233Identical.
In the case of usually, the thickness of intrinsic structure is also not more than 10nm, preferably 5～10nm.So can reduce the lower intrinsic structure absorption to light simultaneously so that heterojunction solar battery has higher open-circuit voltage, reduce cell resistance simultaneously, improve fill factor, curve factor.Preferably, the thickness of the 4th intrinsic layer 124 is less than the thickness of the 3rd intrinsic layer 123.While so can increasing heterojunction solar battery open-circuit voltage, reduce owing to series resistance increases the impact on fill factor, curve factor.It is highly preferred that the thickness of the 4th intrinsic layer 124 is 2～5nm；The thickness of the 3rd intrinsic layer 123 is 3～8nm.In the present embodiment, the thickness of the 4th intrinsic layer 124 and the thickness of the first intrinsic layer 121 are identical；The thickness of the 3rd intrinsic layer 123 and the thickness of the second intrinsic layer 122 are identical.
In the present embodiment, the 4th intrinsic layer 124 is intrinsic silicon hydride, and the 3rd intrinsic layer 123 is intrinsic silicon hydride.
It is, of course, understood that the present invention can also be not provided with the 4th intrinsic layer 124, the 3rd intrinsic layer 123 is only set；Can also the 4th intrinsic layer 124 and the 3rd intrinsic layer 123 all be not provided with.
In the present embodiment, the first electrode 161 is anelectrode, and the second electrode 162 is back electrode.Specifically, the first electrode 161 becomes grid-like, is typically formed by silk screen printing.Second electrode 162 in stratiform, the most full silver electrode.
Wherein, the effect of the first transparency conducting layer 151 is, improves the first doped amorphous silicon layer 131 and the first electrode 161 electric conductivity, effectively increases the collection of carrier.In the present embodiment, the first transparency conducting layer 151 is tungsten-doped indium oxide (IWO) layer.Tungsten-doped indium oxide (IWO) layer has potential high carrier mobility characteristic, in the case of ensureing identical electrical conductivity, compared with ITO layer, IWO layer has relatively low carrier concentration, therefore there is less Carriers Absorption and bigger plasma wavelength, and then IWO layer has high transmission rate and low absorptivity in near-infrared region.Certainly, the first transparency conducting layer 151 can also is that tin indium oxide (ITO) layer, also or fluorine oxide stannum (FTO) layer.
Preferably, the thickness of the first transparency conducting layer 151 is 60～100nm.So its electric property and optical property is more excellent.
Wherein, in like manner, the effect of the second transparency conducting layer 152 is, improves the second doped amorphous silicon layer 132 and the second electrode 162 electric conductivity, effectively increases the collection of carrier.In the present embodiment, the second transparency conducting layer 152 is also tungsten-doped indium oxide (IWO) layer.Certainly, the second transparency conducting layer 152 can also is that tin indium oxide (ITO) layer, also or fluorine oxide stannum (FTO) layer.
Preferably, the thickness of the second transparency conducting layer 152 is 60～100nm.So its electric property and optical property is more excellent.
It is, of course, understood that the present invention can also arrange the second transparency conducting layer 152, also or arrange opaque conductive layer.
The heterojunction solar battery of the present invention, owing to using the first intrinsic layer and the second intrinsic layer, and first optical band gap of optical band gap between the second intrinsic layer of the optical band gap of intrinsic layer and crystal silicon chip, thus it is effectively increased the structural property of intrinsic layer, improve the open-circuit voltage of heterojunction solar battery, amplification is up to 0.02V.
Present invention also offers the preparation method of a kind of above-mentioned heterojunction solar battery.
The preparation method of a kind of heterojunction solar battery, comprises the steps:
The first intrinsic layer is formed in the side of crystal silicon chip；
First intrinsic layer is formed the second intrinsic layer；The optical band gap of the first intrinsic layer optical band gap between the second intrinsic layer and the optical band gap of crystal silicon chip；
Second intrinsic layer is formed the first doped amorphous silicon layer；
First doping amorphous layer forms the first transparency conducting layer；
First transparency conducting layer is formed the first electrode；
Opposite side at crystal silicon chip forms the second electrode.
Wherein, in order to improve the performance of heterojunction solar battery, it is preferable that first crystal silicon chip is carried out making herbs into wool and cleaning step.Wherein, making herbs into wool mode can use wet-method etching or dry method making herbs into wool；Wet-method etching generally uses the alkaline solution (such as: KOH, NaOH, tetramethyl oxyammonia etc.) of certain proportioning and carries out the anisotropic etch of certain time；Dry method making herbs into wool obtains figure generally by mask blank and re-uses reactive ion etching (RIE:Reactive Ion Etching) and perform etching and (mainly pass through C2H4And SF6)；Dry method making herbs into wool also can carry out reactive ion etching (RIE) by machine in the case of not having mask, and use gas is SF6And O2.To needing to be carried out step after crystal silicon chip making herbs into wool, the Main Function of cleaning remains in metal ion and the natural oxide film of crystal silicon chip surface formation on crystal silicon chip surface after being to remove making herbs into wool.It addition, when cleaning, the effect to crystal silicon chip partial deactivation can also be played for removing the chemical liquid of crystal silicon chip surface film oxide.For the cleaning of crystal silicon chip, can use Chemical cleaning, such as: use RCA washing liquid (alkalescence and acid hydrogen peroxide solution), alkaline hydrogen peroxide solution, proportioning is it may be that H2O:H2O2:NH4OH=5:1:1-5:2:1；Acid hydrogen peroxide solution, proportioning is it may be that H2O:H2O2: HC1=6:1:1-8:2:1；RCA washing liquid use condition is: 75 DEG C-85 DEG C, scavenging period 10-20 minute, and cleaning sequence is using acid hydrogen peroxide solution after first using alkaline hydrogen peroxide solution.
In order to improve the performance of heterojunction solar battery, the heterojunction solar battery of present embodiment also includes the 3rd intrinsic layer, the 4th intrinsic layer, the second doped amorphous silicon layer and the second transparency conducting layer etc..
Wherein, first intrinsic layer, the second intrinsic layer, the 3rd intrinsic layer, the 4th intrinsic layer, the first doped amorphous silicon layer, the plasma enhanced chemical vapor deposition method that is formed by (PECVD, Plasma Enhanced Chemical Vapor Deposition) of the second doped amorphous silicon layer.Certainly, it is understandable that, it is not limited to aforesaid way, can also is that hot filament CVD (HWCVD, Hot wire Chemical Vapor Deposition) or high-frequency plasma strengthen chemical gaseous phase and sink method (VHF-PECVD), also or other preparation methoies.
Preferably, the sedimentary condition of the first intrinsic layer is: reacting gas is SiH4And H2, deposition temperature range is more than or equal to 160 DEG C, less than or equal to 230 DEG C；Deposition pressure scope is more than or equal to 100Pa, less than or equal to 300Pa；SiH4Range of flow is more than or equal to 30sccm, less than or equal to 200sccm；H2Range of flow is more than or equal to 200sccm, less than or equal to 900sccm；Deposition power scope is more than or equal to 150W, less than or equal to 400W.
Preferably, the sedimentary condition of the second intrinsic layer is: reacting gas is SiH4And H2, deposition temperature range is more than or equal to 160 DEG C, less than or equal to 230 DEG C；Deposition pressure scope is more than or equal to 300Pa, less than or equal to 600Pa；SiH4Range of flow is more than or equal to 30sccm, less than or equal to 200sccm；H2Range of flow is more than or equal to 200sccm, less than or equal to 900sccm；Deposition power scope is more than or equal to 400W, less than or equal to 700W.
Preferably, before forming the second intrinsic layer, namely after forming the first intrinsic layer, also include the step that the first intrinsic layer is carried out hydrogen passivation.The concrete method passivation using glow discharge of hydrogen passivation.It is, of course, understood that in order to optimize further, it is also possible to the second intrinsic layer is carried out hydrogen passivation.
3rd intrinsic layer and the 4th intrinsic layer can refer to first, second intrinsic layer, do not repeat them here！
Preferably, the first transparency conducting layer, the second transparency conducting layer deposit (RPD) by reaction and plasma.It is highly preferred that when forming the first transparency conducting layer, the second transparency conducting layer, be passed through argon and oxygen, and oxygen/argon ratio be 2.5 the most simultaneously.
Preferably, the first electrode, the second electrode are formed by silk screen printing low-temperature silver slurry, and wherein drying temperature is 100 DEG C, and sintering temperature is 200 DEG C.
Preparation method provided by the present invention, can be effectively improved the open-circuit voltage of heterojunction solar battery, and technique is easily controlled, and production capacity is big, the beneficially industrialization large-scale production of heterojunction solar battery.
Below in conjunction with specific embodiment and comparative example, the present invention is further elaborated.
Embodiment 1
After the n type single crystal silicon sheet making herbs into wool of 150 μm being cleaned, using PECVD mode to deposit the first intrinsic layer at one side surface, sedimentary condition is: SiH4Flow is 95sccm, and hydrogen flowing quantity is 430sccm, power 230W, temperature 170 DEG C, pressure 260Pa, and deposit thickness is 3nm.
Then the first intrinsic layer glow discharge with hydrogen gas being carried out hydrogen passivation, passivating conditions is: hydrogen flowing quantity is 430sccm, power 600W, pressure 450Pa, time 4s.
Using PECVD mode to deposit the second intrinsic layer on the first intrinsic layer the most after passivation, sedimentary condition is: SiH4Flow is 95sccm, and hydrogen flowing quantity is 430sccm, power 600W, temperature 170 DEG C, pressure 510Pa, and deposit thickness is 4nm.
Second intrinsic layer uses PECVD deposit P-type non-crystalline silicon, P-type non-crystalline silicon uses RPD deposit IWO layer.
At another side the 4th intrinsic layer successively (sedimentary condition with the first intrinsic layer) of n type single crystal silicon sheet, the 3rd intrinsic layer (sedimentary condition is with the second intrinsic layer), N-type heavily doped amorphous silicon, IWO layer.
Silk screen printing is finally used to form gate electrode and the full silver electrode at the back side in front.Wherein, drying temperature is 100 DEG C, and sintering temperature is 200 DEG C.
Obtain heterojunction solar battery, be denoted as A1.
Comparative example 1
As different from Example 1, being not provided with the first intrinsic layer and the 4th intrinsic layer, the thickness of the second intrinsic layer is 5nm, and the thickness of the 3rd intrinsic layer is 5nm；Other parts are same as in Example 1.
Obtain heterojunction solar battery, be denoted as D1.
The open-circuit voltage of A1 and D1 after tested, the open-circuit voltage of A1 be the open-circuit voltage of 0.755V, D1 be 0.735V.
As seen from the above, the open-circuit voltage of A1 is more than the open-circuit voltage of D1, and difference reaches 0.02V.This explanation present invention can effectively promote the open-circuit voltage of heterojunction solar battery.
Each technical characteristic of above-described embodiment can combine arbitrarily, for making description succinct, all possible combination of each technical characteristic in above-described embodiment is not all described, but, as long as the combination of these technical characteristics does not exist contradiction, all it is considered to be the scope that this specification is recorded.
Embodiment described above only have expressed the several embodiments of the present invention, and it describes more concrete and detailed, but can not therefore be construed as limiting the scope of the patent.It should be pointed out that, for the person of ordinary skill of the art, without departing from the inventive concept of the premise, it is also possible to make some deformation and improvement, these broadly fall into protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (11)
1. a heterojunction solar battery, it is characterised in that including: crystal silicon chip, is sequentially located at described
The first intrinsic layer on the side of crystal silicon chip, the second intrinsic layer, the first doped amorphous silicon layer, first transparent
Conductive layer and the first electrode, and it is positioned at the second electrode of the opposite side of described crystal silicon chip；
Wherein, the optical band gap Eg of the first intrinsic layer1Optical band gap Eg between described second intrinsic layer2With institute
State the optical band gap Eg of crystal silicon chipBrilliantBetween.
Heterojunction solar battery the most according to claim 1, it is characterised in that described second intrinsic
The optical band gap Eg of layer2For 1.6eV ＜ Eg2＜ 1.8eV.
Heterojunction solar battery the most according to claim 1, it is characterised in that described first intrinsic
The optical band gap Eg of layer1For 1.12eV ＜ Eg1＜ 1.8eV.
Heterojunction solar battery the most according to claim 1, it is characterised in that described first intrinsic
Layer is intrinsic silicon hydride, and described second intrinsic layer is intrinsic silicon hydride.
Heterojunction solar battery the most according to claim 1, it is characterised in that described first intrinsic
The thickness of layer is less than the thickness of described second intrinsic layer.
Heterojunction solar battery the most according to claim 1, it is characterised in that described first intrinsic
The thickness of layer is 2～5nm.
Heterojunction solar battery the most according to claim 1, it is characterised in that described hetero-junctions is too
Sun can also include the reinforcement electric field unit between described second electrode and described crystal silicon chip by battery；Described
Strengthen electric field unit include the 3rd intrinsic amorphous silicon layer that is sequentially located on the opposite side of described crystal silicon chip and
Second doped amorphous silicon layer.
Heterojunction solar battery the most according to claim 7, it is characterised in that described hetero-junctions is too
Sun can also include the 4th intrinsic amorphous silicon between described crystal silicon chip and the 3rd intrinsic amorphous silicon layer by battery
Layer；The optical band gap of the 4th intrinsic amorphous silicon layer is between the optical band gap of described 3rd intrinsic amorphous silicon layer and institute
State the optical band gap of crystal silicon chip.
Heterojunction solar battery the most according to claim 8, it is characterised in that described first intrinsic
The optical band gap of layer is identical with the optical band gap of described 4th intrinsic amorphous silicon layer；The light of described second intrinsic layer
Learn band gap identical with the optical band gap of described 3rd intrinsic amorphous silicon layer.
10. the preparation method of the heterojunction solar battery described in a claim 1, it is characterised in that
Comprise the steps:
The first intrinsic layer is formed in the side of crystal silicon chip；
Described first intrinsic layer forms the second intrinsic layer；The optical band gap of the first intrinsic layer is between described
The optical band gap of two intrinsic layers and the optical band gap of described crystal silicon chip；
Described second intrinsic layer forms the first doped amorphous silicon layer；
Described first doping amorphous layer forms the first transparency conducting layer；
Described first transparency conducting layer forms the first electrode；
Opposite side at described crystal silicon chip forms the second electrode.
The preparation method of 11. heterojunction solar batteries according to claim 10, it is characterised in that
Before forming described second intrinsic layer, also include the step that described first intrinsic layer is carried out hydrogen passivation.
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