CN105304751A - Heterogeneous junction solar cell, preparation method thereof and surface passivation method - Google Patents
Heterogeneous junction solar cell, preparation method thereof and surface passivation method Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 186
- 238000002161 passivation Methods 0.000 title claims abstract description 46
- 238000002360 preparation method Methods 0.000 title claims abstract description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 136
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 124
- 239000010703 silicon Substances 0.000 claims abstract description 124
- 239000013078 crystal Substances 0.000 claims abstract description 87
- 230000008569 process Effects 0.000 claims description 118
- 238000000137 annealing Methods 0.000 claims description 107
- 230000008021 deposition Effects 0.000 claims description 80
- 239000002019 doping agent Substances 0.000 claims description 12
- 239000011261 inert gas Substances 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 18
- 238000006243 chemical reaction Methods 0.000 abstract description 13
- 238000009792 diffusion process Methods 0.000 abstract description 12
- 230000000694 effects Effects 0.000 abstract description 10
- 210000004027 cell Anatomy 0.000 abstract 3
- 238000000151 deposition Methods 0.000 description 76
- 229910021417 amorphous silicon Inorganic materials 0.000 description 27
- 238000007650 screen-printing Methods 0.000 description 24
- 238000005516 engineering process Methods 0.000 description 15
- 230000007306 turnover Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 12
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 11
- 229910052796 boron Inorganic materials 0.000 description 11
- 238000004140 cleaning Methods 0.000 description 11
- 230000007547 defect Effects 0.000 description 9
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 9
- 230000005012 migration Effects 0.000 description 9
- 238000013508 migration Methods 0.000 description 9
- 238000009766 low-temperature sintering Methods 0.000 description 8
- 238000004590 computer program Methods 0.000 description 7
- 235000008216 herbs Nutrition 0.000 description 7
- 210000002268 wool Anatomy 0.000 description 7
- 238000012545 processing Methods 0.000 description 6
- 229910021419 crystalline silicon Inorganic materials 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000007711 solidification Methods 0.000 description 2
- 230000008023 solidification Effects 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract
The invention discloses a heterogeneous junction solar cell, a preparation method thereof and a surface passivation method. An intrinsic layer is fully annealed to enhance a passivation effect. Boron atoms in a doped layer P layer are prevented from diffusion. The cell conversion efficiency and the battery performance are enhanced. The heterogeneous junction solar cell surface passivation method comprises the steps that a first intrinsic layer I layer is deposited on the surface of the first side of a crystal silicon sheet; the first intrinsic layer I layer is annealed; and the doped layer P layer is deposited on the surface of the annealed first intrinsic layer I layer.
Description
Technical field
The present invention relates to heterojunction solar battery technical field, particularly relate to a kind of heterojunction solar battery and preparation method thereof, surface passivation method.
Background technology
Along with the development in photovoltaic industry and market thereof, the solar cell of exploitation high efficiency, low cost becomes main direction of studying.Amorphous silicon hydride (a-Si:H)/crystalline silicon (c-Si) heterojunction solar battery combines the advantage of crystalline silicon and thin film silicon technology, both make use of the thin film deposition processes of low temperature, play again the advantage of crystalline silicon high mobility, there is the characteristics such as preparation technology is simple, conversion efficiency is high simultaneously.
A key character of heterojunction solar battery between P (or N) type a-Si:H and N (or P) type c-Si, inserts skim intrinsic hydrogenated amorphous silicon a-Si:H layer as resilient coating, this intrinsic layer has passivation to silicon chip surface, can interfacial characteristics be improved, thus improve the conversion efficiency of battery.
Existing silicon based hetero-junction solar cell preparation technology flow process as shown in Figure 1, comprise: crystal silicon chip making herbs into wool cleaning 102, silicon deposited film 104, nesa coating deposition 106, silk screen printing 108, annealing 110, wherein, after silk screen printing 108, annealing in process is carried out to the intrinsic layer I layer in heterojunction solar battery, the migration of hydrogen atom in intrinsic layer I layer can be promoted, be conducive to reducing the boundary defect density of states between crystal silicon chip and amorphous layer, improve the open circuit voltage of battery, improve the passivation quality of intrinsic layer I layer.
But, existing annealing process only has just can carry out annealing in process to the intrinsic layer I layer of heterojunction solar battery after screen printing, and after screen printing the diffusion that annealing in process can cause boron atom in doped layer P layer is carried out to the intrinsic layer I layer of heterojunction solar battery, worsen passivation quality, reduce the open circuit voltage of battery, thus reduce battery performance.
In sum, in existing heterojunction solar battery preparation technology flow process, annealing process after screen printing can cause the diffusion of boron atom in doped layer P layer, worsens passivation quality, reduces the open circuit voltage of battery, thus reduces battery performance.
Summary of the invention
Embodiments provide a kind of heterojunction solar battery and preparation method thereof, surface passivation method, in order to make intrinsic layer fully anneal, promote passivation effect, avoid the diffusion of boron atom in doped layer P layer simultaneously, thus lifting battery conversion efficiency, improve battery performance.
The surface passivation method of a kind of heterojunction solar battery that the embodiment of the present invention provides, comprising: on crystal silicon chip first side surface, deposit the first intrinsic layer I layer, carries out annealing in process to described first intrinsic layer I layer; At the first intrinsic layer I layer deposited on silicon doped layer P layer of annealed process.
In the said method that the embodiment of the present invention provides, crystal silicon chip first side surface deposits the first intrinsic layer I layer, annealing in process is carried out to the first intrinsic layer I layer, at the first intrinsic layer I layer deposited on silicon doped layer P layer of annealed process, also namely after the first intrinsic layer I layer deposition, before doped layer P layer deposition, annealing in process is carried out to the first intrinsic layer I layer, with in prior art after the first intrinsic layer I layer deposits, annealing in process is not carried out before doped layer P layer deposition, only have and just annealing in process is carried out to the intrinsic layer I layer of heterojunction solar battery after screen printing, boron atoms permeating in doped layer P layer is caused to be compared, by after the first intrinsic layer I layer deposition, before doped layer P layer deposition, annealing in process is carried out to the first intrinsic layer I layer, first intrinsic layer I layer is fully annealed, promote the migration of hydrogen atom in the first intrinsic layer I layer, reduce defect state density, promote passivation effect, improve open circuit voltage, make can take low temperature sintering technology during silk screen printing simultaneously, avoid the diffusion of boron atom in doped layer P layer, thus lifting battery conversion efficiency, improve battery performance.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, before crystal silicon chip first side surface deposits the first intrinsic layer I layer, the method also comprises: on described crystal silicon chip second side surface, deposit the second intrinsic layer I layer; Dopant deposition layer N layer on described second intrinsic layer I layer; Wherein, described crystal silicon chip first side surface is relative with the second side surface.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, after annealing in process is carried out to described first intrinsic layer I layer, before the first intrinsic layer I layer deposited on silicon doped layer P layer of annealed process, the method also comprises: on described crystal silicon chip second side surface, deposit the second intrinsic layer I layer; Dopant deposition layer N layer on described second intrinsic layer I layer; Wherein, described crystal silicon chip first side surface is relative with the second side surface.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, after crystal silicon chip first side surface deposits the first intrinsic layer I layer, before carrying out annealing in process to described first intrinsic layer I layer, the method also comprises: on described crystal silicon chip second side surface, deposit the second intrinsic layer I layer; Dopant deposition layer N layer on described second intrinsic layer I layer; Wherein, described crystal silicon chip first side surface is relative with the second side surface.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, before described crystal silicon chip first side surface deposits the first intrinsic layer I layer, the method also comprises: on described crystal silicon chip second side surface, deposit the second intrinsic layer I layer; After the first intrinsic layer I layer deposited on silicon doped layer P layer of annealed process, the method also comprises: dopant deposition layer N layer on described second intrinsic layer I layer; Wherein, described crystal silicon chip first side surface is relative with the second side surface.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, the temperature that described first intrinsic layer I layer carries out annealing in process is more than or equal to 150 DEG C and is less than or equal to 300 DEG C.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, the temperature that described first intrinsic layer I layer carries out annealing in process is more than or equal to 180 DEG C and is less than or equal to 220 DEG C.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, the time that described first intrinsic layer I layer carries out annealing in process is more than or equal to 15 minutes and is less than or equal to 60 minutes.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, the time that described first intrinsic layer I layer carries out annealing in process is more than or equal to 20 minutes and is less than or equal to 40 minutes.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, annealing in process is carried out to described first intrinsic layer I layer, comprising: under vacuum condition or inert gas conditions or atmospheric conditions, annealing in process is carried out to described first intrinsic layer I layer.
The preparation method of a kind of heterojunction solar battery that the embodiment of the present invention provides, comprise: adopt the surface passivation method that provides of the embodiment of the present invention to carry out annealing in process to the first intrinsic layer I layer in heterojunction solar battery, and carrying out the first intrinsic layer I layer deposited on silicon doped layer P layer after annealing in process.
In the said method that the embodiment of the present invention provides, the surface passivation method adopting the embodiment of the present invention to provide carries out annealing in process to the first intrinsic layer I layer in heterojunction solar battery, and carrying out the first intrinsic layer I layer deposited on silicon doped layer P layer after annealing in process, also namely on crystal silicon chip first side surface, deposit the first intrinsic layer I layer, annealing in process is carried out to the first intrinsic layer I layer, at the first intrinsic layer I layer deposited on silicon doped layer P layer of annealed process, also namely after the first intrinsic layer I layer deposition, before doped layer P layer deposition, annealing in process is carried out to the first intrinsic layer I layer, with in prior art after the first intrinsic layer I layer deposits, annealing in process is not carried out before doped layer P layer deposition, only have and just annealing in process is carried out to the intrinsic layer I layer of heterojunction solar battery after screen printing, boron atoms permeating in doped layer P layer is caused to be compared, by after the first intrinsic layer I layer deposition, before doped layer P layer deposition, annealing in process is carried out to the first intrinsic layer I layer, first intrinsic layer I layer is fully annealed, promote the migration of hydrogen atom in the first intrinsic layer I layer, reduce defect state density, promote passivation effect, improve open circuit voltage, make can take low temperature sintering technology during silk screen printing simultaneously, avoid the diffusion of boron atom in doped layer P layer, thus lifting battery conversion efficiency, improve battery performance.
A kind of heterojunction solar battery that the embodiment of the present invention provides, the preparation method that described heterojunction solar battery adopts the embodiment of the present invention to provide is prepared from.
The heterojunction solar battery that the embodiment of the present invention provides, the preparation method adopting the embodiment of the present invention to provide is prepared from, and also namely on crystal silicon chip first side surface, deposits the first intrinsic layer I layer, carries out annealing in process to the first intrinsic layer I layer, at the first intrinsic layer I layer deposited on silicon doped layer P layer of annealed process, also namely after the first intrinsic layer I layer deposition, before doped layer P layer deposition, annealing in process is carried out to the first intrinsic layer I layer, with in prior art after the first intrinsic layer I layer deposits, annealing in process is not carried out before doped layer P layer deposition, only have and just annealing in process is carried out to the intrinsic layer I layer of heterojunction solar battery after screen printing, boron atoms permeating in doped layer P layer is caused to be compared, by after the first intrinsic layer I layer deposition, before doped layer P layer deposition, annealing in process is carried out to the first intrinsic layer I layer, first intrinsic layer I layer is fully annealed, promote the migration of hydrogen atom in the first intrinsic layer I layer, reduce defect state density, promote passivation effect, improve open circuit voltage, make can take low temperature sintering technology during silk screen printing simultaneously, avoid the diffusion of boron atom in doped layer P layer, thus lifting battery conversion efficiency, improve battery performance.
Accompanying drawing explanation
Fig. 1 is the schematic flow diagram of heterojunction solar battery preparation technology in prior art;
The schematic flow diagram of the surface passivation method of a kind of heterojunction solar battery that Fig. 2 provides for the embodiment of the present invention;
The schematic flow diagram of a kind of execution mode of the surface passivation method that Fig. 3 provides for the embodiment of the present invention;
The schematic flow diagram of the another kind of execution mode of the surface passivation method that Fig. 4 provides for the embodiment of the present invention;
The schematic flow diagram of another execution mode of the surface passivation method that Fig. 5 provides for the embodiment of the present invention;
The schematic flow diagram of another execution mode of the surface passivation method that Fig. 6 provides for the embodiment of the present invention;
The structural representation of a kind of heterojunction solar battery that Fig. 7 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the embodiment of a kind of heterojunction solar battery that the embodiment of the present invention provides and preparation method thereof, surface passivation method is described in detail.
The surface passivation method of a kind of solar cell that the embodiment of the present invention provides, as shown in Figure 2, comprising:
Step 202, crystal silicon chip first side surface deposits the first intrinsic layer I layer, carries out annealing in process to the first intrinsic layer I layer;
Step 204, at the first intrinsic layer I layer deposited on silicon doped layer P layer of annealed process.
In the method that the embodiment of the present invention provides, crystal silicon chip first side surface deposits the first intrinsic layer I layer, annealing in process is carried out to the first intrinsic layer I layer, at the first intrinsic layer I layer deposited on silicon doped layer P layer of annealed process, also namely after the first intrinsic layer I layer deposition, before doped layer P layer deposition, annealing in process is carried out to the first intrinsic layer I layer, with in prior art after the first intrinsic layer I layer deposits, annealing in process is not carried out before doped layer P layer deposition, only have and just annealing in process is carried out to the intrinsic layer I layer of heterojunction solar battery after screen printing, boron atoms permeating in doped layer P layer is caused to be compared, by after the first intrinsic layer I layer deposition, before doped layer P layer deposition, annealing in process is carried out to the first intrinsic layer I layer, first intrinsic layer I layer is fully annealed, promote the migration of hydrogen atom in the first intrinsic layer I layer, reduce defect state density, promote passivation effect, improve open circuit voltage, make can take low temperature sintering technology during silk screen printing simultaneously, avoid the diffusion of boron atom in doped layer P layer, thus lifting battery conversion efficiency, improve battery performance.
What deserves to be explained is, in prior art after screen printing, carry out annealing in process, comprise drying and processing and solidification process, wherein, drying and processing makes the organic solvent in heterojunction solar battery depart from slurry, solidification process makes electrode and crystal silicon chip form good ohmic contact, and in the embodiment of the present invention after the first intrinsic layer I layer is formed, before the first intrinsic layer I layer surface deposition doped layer P layer, first intrinsic layer I layer is annealed, make the first intrinsic layer I layer annealing fully, promote the migration of hydrogen atom in the first intrinsic layer I layer, reduce defect state density, improve passivation effect, make can take low temperature sintering technology during silk screen printing simultaneously, avoid the diffusion of boron atom in doped layer P layer.
Certainly, those skilled in the art should be understood that, the first intrinsic layer I layer is deposited at crystal silicon chip first side surface, refer to that deposition of hydrogenated amorphous silicon forms the first intrinsic layer I layer on crystal silicon chip first side surface, and before on crystal silicon chip first side surface, deposition of hydrogenated amorphous silicon forms the first intrinsic layer I layer, need to carry out making herbs into wool cleaning to crystal silicon chip, then, on crystal silicon chip first side surface after making herbs into wool cleaning, deposition of hydrogenated amorphous silicon forms the first intrinsic layer I layer.At the first intrinsic layer I layer deposited on silicon doped layer P layer of annealed process, refer to the first intrinsic layer I layer deposited on silicon boron-doping amorphous silicon hydride formation doped layer P layer in annealed process.
During concrete enforcement, after on crystal silicon chip first side surface, deposition of hydrogenated amorphous silicon forms the first intrinsic layer I layer, annealing in process is carried out to the first intrinsic layer I layer, can be formed at crystal silicon chip both sides first intrinsic layer I layer and the second intrinsic layer I layer, and doped layer N layer is annealed after being formed, also can anneal between crystal silicon chip both sides first intrinsic layer I layer and the second intrinsic layer I layer are formed, can also after crystal silicon chip both sides first intrinsic layer I layer and the second intrinsic layer I layer be formed, doped layer P layer is annealed before being formed, be described in detail below in conjunction with the surface passivation method of specific embodiment to the solar cell that the embodiment of the present invention provides.
Embodiment one, to be formed and doped layer N layer is annealed after being formed at crystal silicon chip both sides first intrinsic layer I layer and the second intrinsic layer I layer, specifically:
Before crystal silicon chip first side surface deposits the first intrinsic layer I layer, the method also comprises: on crystal silicon chip second side surface, deposit the second intrinsic layer I layer; Dopant deposition layer N layer on the second intrinsic layer I layer; Wherein, crystal silicon chip first side surface is relative with the second side surface.During concrete enforcement, as shown in Figure 3, comprising:
Step 302, the second intrinsic layer I layer deposition, also namely deposition of hydrogenated amorphous silicon forms the second intrinsic layer I layer on crystal silicon chip second side surface after cleaning;
Step 304, doped layer N layer deposits, and also namely mixes phosphorus amorphous silicon hydride at the second intrinsic layer I layer deposited on silicon and forms doped layer N layer;
Step 306, the first intrinsic layer I layer deposition, also by crystal silicon chip turn-over, on crystal silicon chip first side surface, deposition of hydrogenated amorphous silicon forms the first intrinsic layer I layer;
Step 308, namely annealing, also carry out annealing in process to the first intrinsic layer I layer;
Step 310, doped layer P layer deposits, and also namely the first intrinsic layer I layer deposited on silicon boron-doping amorphous silicon hydride after annealing forms doped layer P layer.
Embodiment two, to anneal between crystal silicon chip both sides first intrinsic layer I layer and the second intrinsic layer I layer are formed, specifically:
After carrying out annealing in process to the first intrinsic layer I layer, before the first intrinsic layer I layer deposited on silicon doped layer P layer of annealed process, the method also comprises: on crystal silicon chip second side surface, deposit the second intrinsic layer I layer; Dopant deposition layer N layer on the second intrinsic layer I layer; Wherein, crystal silicon chip first side surface is relative with the second side surface.During concrete enforcement, as shown in Figure 4, comprising:
Step 402, the first intrinsic layer I layer deposition, also namely deposition of hydrogenated amorphous silicon forms the first intrinsic layer I layer on crystal silicon chip first side surface after cleaning;
Step 404, namely annealing, also carry out annealing in process to the first intrinsic layer I layer;
Step 406, the second intrinsic layer I layer deposition, also by crystal silicon chip turn-over, on crystal silicon chip second side surface, deposition of hydrogenated amorphous silicon forms the second intrinsic layer I layer;
Step 408, doped layer N layer deposits, and also namely mixes phosphorus amorphous silicon hydride at the second intrinsic layer I layer deposited on silicon and forms doped layer N layer;
Step 410, doped layer P layer deposits, and also namely the first intrinsic layer I layer deposited on silicon boron-doping amorphous silicon hydride after annealing forms doped layer P layer.
Embodiment three, to be formed and doped layer N layer is annealed after being formed at crystal silicon chip both sides first intrinsic layer I layer and the second intrinsic layer I layer, specifically:
After crystal silicon chip first side surface deposits the first intrinsic layer I layer, before carrying out annealing in process to the first intrinsic layer I layer, the method also comprises: on crystal silicon chip second side surface, deposit the second intrinsic layer I layer; Dopant deposition layer N layer on the second intrinsic layer I layer; Wherein, crystal silicon chip first side surface is relative with the second side surface.During concrete enforcement, as shown in Figure 5, comprising:
Step 502, the first intrinsic layer I layer deposition, also namely deposition of hydrogenated amorphous silicon forms the first intrinsic layer I layer on crystal silicon chip first side surface after cleaning;
Step 504, the second intrinsic layer I layer deposition, also by crystal silicon chip turn-over, on crystal silicon chip second side surface, deposition of hydrogenated amorphous silicon forms the second intrinsic layer I layer;
Step 506, doped layer N layer deposits, and also namely mixes phosphorus amorphous silicon hydride at the second intrinsic layer I layer deposited on silicon and forms doped layer N layer;
Step 508, namely annealing, also carry out annealing in process to the first intrinsic layer I layer;
Step 510, doped layer P layer deposits, and also by crystal silicon chip turn-over, the first intrinsic layer I layer deposited on silicon boron-doping amorphous silicon hydride after annealing forms doped layer P layer.
Embodiment four, after crystal silicon chip both sides first intrinsic layer I layer and the second intrinsic layer I layer are formed, doped layer P layer anneals before being formed, specifically:
Before crystal silicon chip first side surface deposits the first intrinsic layer I layer, the method also comprises: on crystal silicon chip second side surface, deposit the second intrinsic layer I layer; After the first intrinsic layer I layer deposited on silicon doped layer P layer of annealed process, the method also comprises: dopant deposition layer N layer on the second intrinsic layer I layer; Wherein, crystal silicon chip first side surface is relative with the second side surface.During concrete enforcement, as shown in Figure 6, comprising:
Step 602, the second intrinsic layer I layer deposition, also namely deposition of hydrogenated amorphous silicon forms the second intrinsic layer I layer on crystal silicon chip second side surface after cleaning;
Step 604, the first intrinsic layer I layer deposition, also by crystal silicon chip turn-over, on crystal silicon chip first side surface, deposition of hydrogenated amorphous silicon forms the first intrinsic layer I layer;
Step 606, namely annealing, also carry out annealing in process to the first intrinsic layer I layer;
Step 608, doped layer P layer deposits, and also namely the first intrinsic layer I layer deposited on silicon boron-doping amorphous silicon hydride after annealing forms doped layer P layer;
Step 610, doped layer N layer deposits, and also by crystal silicon chip turn-over, mixes phosphorus amorphous silicon hydride form doped layer N layer at the second intrinsic layer I layer deposited on silicon.
It should be noted that, the the first intrinsic layer I layer mentioned in the embodiment of the present invention and the second intrinsic layer I layer are identical intrinsic layer I layer, difference is only that the first intrinsic layer I is deposited upon crystal silicon chip first side surface, second intrinsic layer I is deposited upon crystal silicon chip second side surface, first intrinsic layer I layer and the second intrinsic layer I layer are only for distinguishing two intrinsic layer I layers, in the specific implementation, before arbitrary intrinsic layer deposits boron-doping amorphous silicon hydride formation doped layer P layer, annealing in process is carried out to this intrinsic layer I layer.
What deserves to be explained is, in embodiment one, embodiment two, in embodiment three and embodiment four, crystal silicon chip first side surface is relative with the second side surface, annealing is carried out under vacuum condition or inert gas conditions or atmospheric conditions, annealing temperature is 150 DEG C-300 DEG C, as comparatively preferred embodiment, annealing temperature is 180 DEG C-220 DEG C, annealing temperature can also be: 200 DEG C, 250 DEG C, 280 DEG C, annealing time is 15min-60min, as comparatively preferred embodiment, annealing time is 20min-40min, annealing time can also be: 30min, 50min, 55min.
In embodiment provided by the invention, by after the first intrinsic layer I layer deposition, before doped layer P layer deposition, annealing in process is carried out to the first intrinsic layer I layer, in the specific implementation, experimental result shows that the open circuit voltage of solar cell is increased to 720mV by 710mV, conversion efficiency rises to 20.7% by 20.4%, and the conversion efficiency of battery is improved, and performance obtains good lifting.
In a kind of possible execution mode, in the method that the embodiment of the present invention provides, the temperature of the first intrinsic layer I layer being carried out to annealing in process is more than or equal to 150 DEG C and is less than or equal to 300 DEG C.
In a kind of possible execution mode, in the method that the embodiment of the present invention provides, the temperature of the first intrinsic layer I layer being carried out to annealing in process is more than or equal to 180 DEG C and is less than or equal to 220 DEG C.
In a kind of possible execution mode, in the method that the embodiment of the present invention provides, the time of the first intrinsic layer I layer being carried out to annealing in process is more than or equal to 15 minutes and is less than or equal to 60 minutes.
In a kind of possible execution mode, in the method that the embodiment of the present invention provides, the time of the first intrinsic layer I layer being carried out to annealing in process is more than or equal to 20 minutes and is less than or equal to 40 minutes.
In a kind of possible execution mode, in the method that the embodiment of the present invention provides, annealing in process is carried out to the first intrinsic layer I layer, comprising: under vacuum condition or inert gas conditions or atmospheric conditions, annealing in process is carried out to the first intrinsic layer I layer.
Certainly, one skilled in the art will appreciate that inert gas conditions, comprising: the gas condition such as argon gas, helium.
The preparation method of a kind of heterojunction solar battery that the embodiment of the present invention provides, comprise: adopt the surface passivation method that provides of the embodiment of the present invention to carry out annealing in process to the first intrinsic layer I layer in heterojunction solar battery, and carrying out the first intrinsic layer I layer deposited on silicon doped layer P layer after annealing in process.
In the method that the embodiment of the present invention provides, the surface passivation method adopting the embodiment of the present invention to provide carries out annealing in process to the first intrinsic layer I layer in heterojunction solar battery, and carrying out the first intrinsic layer I layer deposited on silicon doped layer P layer after annealing in process, also namely on crystal silicon chip first side surface, deposit the first intrinsic layer I layer, annealing in process is carried out to the first intrinsic layer I layer, at the first intrinsic layer I layer deposited on silicon doped layer P layer of annealed process, after the first intrinsic layer I layer deposition, before doped layer P layer deposition, annealing in process is carried out to the first intrinsic layer I layer, with in prior art after the first intrinsic layer I layer deposits, annealing in process is not carried out before doped layer P layer deposition, only have and just annealing in process is carried out to the intrinsic layer I layer of heterojunction solar battery after screen printing, boron atoms permeating in doped layer P layer is caused to be compared, by after the first intrinsic layer I layer deposition, before doped layer P layer deposition, annealing in process is carried out to the first intrinsic layer I layer, first intrinsic layer I layer is fully annealed, promote the migration of hydrogen atom in the first intrinsic layer I layer, reduce defect state density, promote passivation effect, improve open circuit voltage, make can take low temperature sintering technology during silk screen printing simultaneously, avoid the diffusion of boron atom in doped layer P layer, thus lifting battery conversion efficiency, improve battery performance.
What deserves to be explained is, the surface passivation method that the embodiment of the present invention provides is in fact to plasma enhancing chemical vapour deposition technique (PlasmaEnhancedChemicalVaporDeposition in heterojunction solar battery preparation method, PEVCD) improvement, during concrete enforcement, the preparation method of heterojunction solar battery, comprising:
Preparation method one, crystal silicon chip making herbs into wool cleaning, deposit the second intrinsic layer I layer, deposit the first intrinsic layer I layer at the second intrinsic layer I layer surface deposition doped layer N layer, crystal silicon chip turn-over, the first intrinsic layer I layer annealed, the first intrinsic layer I layer surface deposition doped layer P layer after the annealing process, in doped layer P layer and doped layer N layer surface deposition transparent conductive film layer, silk screen printing, annealing.
Preparation method two, crystal silicon chip making herbs into wool cleaning, deposit the first intrinsic layer I layer, the first intrinsic layer I layer annealed, silicon chip turn-over and deposit the second intrinsic layer I layer, the second intrinsic layer I layer surface deposition doped layer N layer, crystal silicon chip turn-over the first intrinsic layer I layer surface deposition doped layer P layer after the annealing process, in doped layer P layer and doped layer N layer surface deposition transparent conductive film layer, silk screen printing, annealing.
Preparation method three, crystal silicon chip making herbs into wool cleaning, deposit the first intrinsic layer I layer, silicon chip turn-over and deposit the second intrinsic layer I layer, at the second intrinsic layer I layer surface deposition doped layer N layer, the first intrinsic layer I layer is annealed, crystal silicon chip turn-over the first intrinsic layer I layer surface deposition doped layer P layer after the annealing process, in doped layer P layer and doped layer N layer surface deposition transparent conductive film layer, silk screen printing, annealing.
Preparation method four, crystal silicon chip making herbs into wool cleaning, deposit the second intrinsic layer I layer, crystal silicon chip turn-over deposits the first intrinsic layer I layer, anneal to the first intrinsic layer I layer, the first intrinsic layer I layer surface deposition doped layer P layer after the annealing process, crystal silicon chip turn-over at the second intrinsic layer I layer surface deposition doped layer N layer, in doped layer P layer and doped layer N layer surface deposition transparent conductive film layer, silk screen printing, annealing.
A kind of heterojunction solar battery that the embodiment of the present invention provides, comprise: the preparation method that heterojunction solar battery adopts the embodiment of the present invention to provide is prepared from, as shown in Figure 7, comprising: crystal silicon chip 71, first intrinsic layer I layer 72, second intrinsic layer I layer 73, doped layer P layer 74, doped layer N layer 75, nesa coating 76 and electrode 77.
The heterojunction solar battery that the embodiment of the present invention provides, the preparation method adopting the embodiment of the present invention to provide is prepared from, and also namely on crystal silicon chip first side surface, deposits the first intrinsic layer I layer, carries out annealing in process to the first intrinsic layer I layer, at the first intrinsic layer I layer deposited on silicon doped layer P layer of annealed process, also namely after the first intrinsic layer I layer deposition, before doped layer P layer deposition, annealing in process is carried out to the first intrinsic layer I layer, with in prior art after the first intrinsic layer I layer deposits, annealing in process is not carried out before doped layer P layer deposition, only have and just annealing in process is carried out to the intrinsic layer I layer of heterojunction solar battery after screen printing, boron atoms permeating in doped layer P layer is caused to be compared, by after the first intrinsic layer I layer deposition, before doped layer P layer deposition, annealing in process is carried out to the first intrinsic layer I layer, first intrinsic layer I layer is fully annealed, promote the migration of hydrogen atom in the first intrinsic layer I layer, reduce defect state density, promote passivation effect, improve open circuit voltage, make can take low temperature sintering technology during silk screen printing simultaneously, avoid the diffusion of boron atom in doped layer P layer, thus lifting battery conversion efficiency, improve battery performance.
In sum, a kind of heterojunction solar battery that the embodiment of the present invention provides and preparation method thereof, surface passivation method, crystal silicon chip first side surface deposits the first intrinsic layer I layer, carries out annealing in process to the first intrinsic layer I layer; At the first intrinsic layer I layer deposited on silicon doped layer P layer of annealed process, also namely after the first intrinsic layer I layer deposition, before doped layer P layer deposition, annealing in process is carried out to the first intrinsic layer I layer, first intrinsic layer I layer is fully annealed, promote the migration of hydrogen atom in the first intrinsic layer I layer, reduce defect state density, promote passivation effect, improve open circuit voltage, make can take low temperature sintering technology during silk screen printing simultaneously, avoid the diffusion of boron atom in doped layer P layer, thus lifting battery conversion efficiency, improve battery performance.
Those skilled in the art should understand, embodiments of the invention can be provided as method, system or computer program.Therefore, the present invention can adopt the form of complete hardware embodiment, completely software implementation or the embodiment in conjunction with software and hardware aspect.And the present invention can adopt in one or more form wherein including the upper computer program implemented of computer-usable storage medium (including but not limited to magnetic disc store and optical memory etc.) of computer usable program code.
The present invention describes with reference to according to the flow chart of the method for the embodiment of the present invention, equipment (system) and computer program and/or block diagram.Should understand can by the combination of the flow process in each flow process in computer program instructions realization flow figure and/or block diagram and/or square frame and flow chart and/or block diagram and/or square frame.These computer program instructions can being provided to the processor of all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing device to produce a machine, making the instruction performed by the processor of computer or other programmable data processing device produce device for realizing the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
These computer program instructions also can be stored in can in the computer-readable memory that works in a specific way of vectoring computer or other programmable data processing device, the instruction making to be stored in this computer-readable memory produces the manufacture comprising command device, and this command device realizes the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
These computer program instructions also can be loaded in computer or other programmable data processing device, make on computer or other programmable devices, to perform sequence of operations step to produce computer implemented process, thus the instruction performed on computer or other programmable devices is provided for the step realizing the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (12)
1. a surface passivation method for heterojunction solar battery, is characterized in that, comprising:
Crystal silicon chip first side surface deposits the first intrinsic layer I layer, annealing in process is carried out to described first intrinsic layer I layer;
At the first intrinsic layer I layer deposited on silicon doped layer P layer of annealed process.
2. surface passivation method according to claim 1, is characterized in that, before crystal silicon chip first side surface deposits the first intrinsic layer I layer, the method also comprises:
Described crystal silicon chip second side surface deposits the second intrinsic layer I layer;
Dopant deposition layer N layer on described second intrinsic layer I layer;
Wherein, described crystal silicon chip first side surface is relative with the second side surface.
3. surface passivation method according to claim 1, is characterized in that, after carrying out annealing in process to described first intrinsic layer I layer, before the first intrinsic layer I layer deposited on silicon doped layer P layer of annealed process, the method also comprises:
Described crystal silicon chip second side surface deposits the second intrinsic layer I layer;
Dopant deposition layer N layer on described second intrinsic layer I layer;
Wherein, described crystal silicon chip first side surface is relative with the second side surface.
4. surface passivation method according to claim 1, is characterized in that, after crystal silicon chip first side surface deposits the first intrinsic layer I layer, before carrying out annealing in process to described first intrinsic layer I layer, the method also comprises:
Described crystal silicon chip second side surface deposits the second intrinsic layer I layer;
Dopant deposition layer N layer on described second intrinsic layer I layer;
Wherein, described crystal silicon chip first side surface is relative with the second side surface.
5. surface passivation method according to claim 1, is characterized in that, before described crystal silicon chip first side surface deposits the first intrinsic layer I layer, the method also comprises:
Described crystal silicon chip second side surface deposits the second intrinsic layer I layer;
After the first intrinsic layer I layer deposited on silicon doped layer P layer of annealed process, the method also comprises: dopant deposition layer N layer on described second intrinsic layer I layer;
Wherein, described crystal silicon chip first side surface is relative with the second side surface.
6. the surface passivation method according to any one of claim 1-5, is characterized in that, the temperature that described first intrinsic layer I layer carries out annealing in process is more than or equal to 150 DEG C and is less than or equal to 300 DEG C.
7. surface passivation method according to claim 6, is characterized in that, the temperature that described first intrinsic layer I layer carries out annealing in process is more than or equal to 180 DEG C and is less than or equal to 220 DEG C.
8. surface passivation method according to claim 6, is characterized in that, the time that described first intrinsic layer I layer carries out annealing in process is more than or equal to 15 minutes and is less than or equal to 60 minutes.
9. surface passivation method according to claim 8, is characterized in that, the time that described first intrinsic layer I layer carries out annealing in process is more than or equal to 20 minutes and is less than or equal to 40 minutes.
10. surface passivation method according to claim 9, is characterized in that, carries out annealing in process, comprising described first intrinsic layer I layer: under vacuum condition or inert gas conditions or atmospheric conditions, carry out annealing in process to described first intrinsic layer I layer.
The preparation method of 11. 1 kinds of heterojunction solar batteries, it is characterized in that, comprise: adopt surface passivation method according to any one of claim 1-10 to carry out annealing in process to the first intrinsic layer I layer in heterojunction solar battery, and carrying out the first intrinsic layer I layer deposited on silicon doped layer P layer after annealing in process.
12. 1 kinds of heterojunction solar batteries, is characterized in that, described heterojunction solar battery adopts preparation method as claimed in claim 11 to be prepared from.
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