CN114639742A - Two-junction solar cell and preparation method thereof - Google Patents
Two-junction solar cell and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 7
- 239000010408 film Substances 0.000 claims abstract description 106
- 239000004065 semiconductor Substances 0.000 claims abstract description 85
- 230000005641 tunneling Effects 0.000 claims abstract description 52
- 239000010409 thin film Substances 0.000 claims abstract description 51
- 238000002161 passivation Methods 0.000 claims abstract description 48
- 229910052751 metal Inorganic materials 0.000 claims abstract description 47
- 239000002184 metal Substances 0.000 claims abstract description 47
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000009792 diffusion process Methods 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims description 248
- 238000004519 manufacturing process Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 13
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 12
- 229910052796 boron Inorganic materials 0.000 claims description 12
- 239000000203 mixture Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 238000004140 cleaning Methods 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 239000005388 borosilicate glass Substances 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- 238000007650 screen-printing Methods 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 230000000593 degrading effect Effects 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical group 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 238000000227 grinding Methods 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 239000002356 single layer Substances 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- 238000004590 computer program Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 238000004804 winding Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
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- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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Abstract
The embodiment of the invention provides a two-junction solar cell and a preparation method thereof, the cell is prepared on the basis of an N-type crystalline silicon substrate, crystalline silicon solar cell units comprising a diffusion P-type layer, a first tunneling film layer, a first P-type semiconductor layer, a first passivation layer and a first transparent conductive film layer are sequentially prepared on the front surface from inside to outside, and the two solar cell units are connected in series through a first metal electrode, and the whole solar cell is connected with an external circuit through a second metal electrode and a third metal electrode. Because the thin-film solar cell unit can utilize sunlight which cannot be absorbed by the crystalline silicon solar cell, the combination of the thin-film solar cell unit and the crystalline silicon solar cell unit can effectively improve the overall solar energy conversion efficiency, thereby solving the problem of low conversion efficiency of the solar cell adopting a unijunction tunneling oxide layer passivation metal structure.
Description
Technical Field
The invention relates to the technical field of photovoltaics, in particular to a two-junction solar cell and a preparation method thereof.
Background
Crystalline silicon solar cells are the most mature and widely used solar cells in technology, have a percentage in the photovoltaic market of over 90%, and will dominate for a considerable time in the future. Meanwhile, because the crystalline silicon solar cell is only sensitive to light within the visible wavelength range of 300-1100nm, photo-generated current can be generated and output to an external circuit, which indicates that the crystalline silicon solar cell cannot be used for light within the wavelength range of less than 300nm or more than 1100nm, and therefore the conversion efficiency of the solar cell adopting the single-junction tunneling oxide layer passivation metal structure is low.
Disclosure of Invention
In view of the above, the present invention provides a two-junction solar cell and a method for manufacturing the same, so as to solve the problem of low conversion efficiency of a solar cell using a single-junction tunneling oxide passivation metal structure.
In order to solve the above problems, the present invention discloses a two-junction solar cell, comprising an N-type crystalline silicon substrate, the crystalline silicon substrate comprising a front surface and a back surface, wherein:
a diffusion P-type layer, a first tunneling film layer, a first P-type semiconductor layer, a first passivation layer, a first transparent conductive film layer, a first N-type semiconductor layer, a second tunneling film layer, a second P-type semiconductor layer, a second transparent conductive film layer and a first anti-reflection layer are sequentially prepared on the front surface from inside to outside;
a first metal electrode is prepared between the first P-type semiconductor layer and the first transparent conductive film layer, a second metal electrode is prepared on the second transparent conductive film layer, and the second metal electrode penetrates through the first anti-reflection layer outwards;
a third tunneling film layer, a second N-type semiconductor layer, a second passivation layer and a second anti-reflection layer are sequentially prepared on the back surface from inside to outside;
and a third metal electrode connected with the second N-type semiconductor layer is prepared on the second N-type semiconductor layer, and the third metal electrode penetrates through the second passivation layer and the second anti-reflection layer outwards.
Optionally, the dopant of the diffused P-type layer is boron, and the highest doping concentration of the dopant is 1018～1020cm-3Boron concentration of 1017cm-3The depth of the diffusion junction is 0.2-0.8 μm.
Optionally, the first tunneling thin film layer is a mixture film, an oxide film, a nitride film or an oxynitride film of group IVA elements, or a metal oxide film;
the thickness of the first tunneling thin film layer is 1-5 nm.
Optionally, the first P-type semiconductor layer and the second P-type semiconductor layer are polycrystalline boron-doped films or amorphous boron-doped films of group IVA elements, or are compound strongly conductive P-type semiconductor films of group IIA elements or group VIA elements;
the thickness of the first P-type semiconductor layer or the second P-type semiconductor layer is 15-150 nm.
Optionally, the first passivation layer includes a stack of one or more of an aluminum oxide film, a silicon oxide film, an intrinsic film, and a P-type heavily doped amorphous group IVA element mixture film;
the thickness of the first passivation layer is 3-5 nm.
Optionally, the first N-type semiconductor layer and the second N-type semiconductor layer are polycrystalline doped films or amorphous phosphorus-doped films based on group IVA element mixtures, or are compound strongly conductive polar N-type semiconductor films of group IIA elements or group VIA elements;
the thickness of the first N-type semiconductor layer and the second N-type semiconductor layer is 15-150 nm.
Optionally, the second passivation layer includes a single-layer film or a stack of multiple films of a silicon nitride film, a silicon oxide film, an intrinsic film, and an N-type heavily-doped amorphous group IVA element film;
the thickness of the second passivation layer is 3-15 nm.
Optionally, the thicknesses of the first transparent conductive film layer and the second transparent conductive film layer are 60-100 nm.
There is also provided a method of making the two junction solar cell described above, the indexing method comprising the steps of:
cleaning and texturing two sides of the N-type crystalline silicon substrate;
carrying out boron diffusion treatment on the front surface of the N-type crystalline silicon substrate to form a diffusion P-type layer;
carrying out back side wrapping and expanding treatment on the borosilicate glass on the front side and the back side of the N-type crystalline silicon substrate;
respectively performing tunneling layer growth operation on the front surface and the back surface of the N-type crystalline silicon substrate to obtain the first tunneling thin film layer and the third tunneling thin film layer;
preparing the first P-type semiconductor layer on the first tunneling thin film layer, and preparing the second N-type semiconductor layer on the third tunneling thin film layer;
depositing and degrading the N-type crystalline silicon substrate to obtain a first passivation layer and a second passivation layer;
preparing a second anti-reflection layer on the second passivation layer;
preparing the first transparent conductive film layer on the first passivation layer;
preparing the first metal electrode and the second metal electrode on the first transparent conductive grinding layer in a screen printing mode, preparing the third metal electrode on the second anti-reflection layer, wherein the first metal electrode penetrates through the first passivation layer and then is in deep contact with the first P-type semiconductor layer;
and sequentially preparing the first N-type semiconductor layer, the second tunneling thin film layer, the second P-type semiconductor layer, the second transparent conductive film layer and the first anti-reflection layer on the first transparent conductive film layer.
According to the technical scheme, the two-junction solar cell and the preparation method thereof are provided, the cell is prepared on the basis of an N-type crystalline silicon substrate, crystalline silicon solar cell units comprising a diffusion P-type layer, a first tunneling film layer, a first P-type semiconductor layer, a first passivation layer and a first transparent conductive film layer are sequentially prepared on the front surface from inside to outside, the two solar cell units are connected in series through a first metal electrode, and the whole solar cell is connected with an external circuit through a second metal electrode and a third metal electrode. Because the thin-film solar cell unit can utilize sunlight which cannot be absorbed by the crystalline silicon solar cell, the combination of the thin-film solar cell unit and the crystalline silicon solar cell unit can effectively improve the overall solar energy conversion efficiency, thereby solving the problem of low conversion efficiency of the solar cell adopting a unijunction tunneling oxide layer passivation metal structure.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a cross-sectional view of a two-junction solar cell according to an embodiment of the present application;
FIG. 2 is a flow chart of a method of making an embodiment of the present application;
fig. 2a is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2b is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2c is a cross-sectional view of a two junction solar cell of an embodiment of the present application during fabrication;
fig. 2d is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2e is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2f is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2g is a cross-sectional view of a two junction solar cell of an embodiment of the present application during fabrication;
fig. 2h is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2i is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2j is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2k is a cross-sectional view of a two junction solar cell of an embodiment of the present application during fabrication;
FIG. 2l is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2m is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2n is a cross-sectional view of a two junction solar cell of an embodiment of the present application during fabrication;
fig. 2o is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
Fig. 1 is a cross-sectional view of a two-junction solar cell according to an embodiment of the present disclosure.
Referring to fig. 1, the two-junction solar cell provided in this embodiment is a power generation element of a solar module, and the cell is prepared based on an N-type crystalline silicon substrate 1, which includes a front surface and a back surface, where the front surface and the back surface are opposite concepts, that is, one surface facing sunlight is used as the front surface of the crystalline silicon substrate, and the other surface is used as the back surface.
The front surface of the N-type crystalline silicon substrate is sequentially provided with a diffusion P-type layer 1', a first tunneling thin film layer 2, a first P-type semiconductor layer 3, a first passivation layer 5, a first transparent conductive film layer 9, a first N-type semiconductor layer 10, a second tunneling thin film layer 11, a second P-type semiconductor layer 12, a second transparent conductive film layer 13 and a first anti-reflection layer 14 from inside to outside.
A first metal electrode 7 is prepared between the first P-type semiconductor layer 3 and the first transparent conductive film layer 9, and a second metal electrode 14 is prepared on the second transparent conductive film layer, and the second metal electrode penetrates the first anti-reflection layer outwards.
And a third tunneling thin film layer 2', a second N-type semiconductor layer 4, a second passivation layer 6 and a second anti-reflection layer 15 are sequentially prepared on the back surface of the N-type crystalline silicon substrate from inside to outside. And a third metal electrode 8 connected with the second N-type semiconductor layer is prepared on the second N-type semiconductor layer, and the third metal electrode penetrates through the second passivation layer and the second anti-reflection layer outwards.
The second metal electrode and the third metal electrode form an external electrode of the cell and are used for being connected with an external circuit so as to output a circuit generated by the solar cell to an external circuit. Or the solar cells are connected through the second metal electrode and the third metal electrode when the solar cells are connected in series and parallel.
Wherein the dopant of the diffusion P-type layer is boron, the highest doping concentration of the dopant is 1018-1020 cm < -3 >, and the diffusion junction depth at the boron concentration of 1017cm < -3 > is 0.2-0.8 mu m.
The first tunneling thin film layer is a thin film, an oxide thin film, a nitride thin film or an oxynitride thin film of IVA group elements, or a mixture thin film of a plurality of IVA group elements, or a metal oxide thin film; the thickness of the first tunneling thin film layer is 1-5 nm.
The first P-type semiconductor layer and the second P-type semiconductor layer are polycrystalline boron-doped films or amorphous boron-doped films of IVA group elements or P-type semiconductor films with strong conductivity of compounds of IIA group elements or VIA group elements; the thickness of the first P-type semiconductor layer or the second P-type semiconductor layer is 15-150 nm. The thicknesses of the first P-type semiconductor layer and the second P-type semiconductor layer may be the same or different.
The first passivation layer is an aluminum oxide film, a silicon oxide film, an intrinsic film, a P-type heavily doped amorphous IVA group element mixture film, or a laminated film obtained by laminating one or more films. The thickness of the first passivation layer is 3-5 nm.
The first N-type semiconductor layer and the second N-type semiconductor layer are polycrystal doped films or amorphous phosphorus-doped films based on a group IVA element mixture, or are compound strong-conductivity N-type semiconductor films of group IIA elements or group VIA elements; the thickness of the first N-type semiconductor layer and the second N-type semiconductor layer is 15-150 nm. The thicknesses of the two N-type semiconductor layers may be the same or different.
The second passivation layer is a silicon nitride film layer, a silicon oxide film, an intrinsic film or an N-type heavily-doped amorphous IVA group element film, and can also be a laminated film comprising the films. The thickness of the second passivation layer is 3-15 nm. The thickness of the first transparent conductive film layer and the second transparent conductive film layer is 60-100 nm.
According to the technical scheme, the two-junction solar cell is prepared on the basis of the N-type crystalline silicon substrate, crystalline silicon solar cell units comprising diffusion P-type layers, first tunneling thin layers, first P-type semiconductor layers, first passivation layers and first transparent conductive film layers are sequentially prepared on the front surface from inside to outside, thin-film solar cell units comprising the first N-type semiconductor layers, the second tunneling thin layers, the second P-type semiconductor layers and the second transparent conductive film layers are further included, the two solar cell units are connected in series through the first metal electrode, and the whole solar cell is connected with an external circuit through the second metal electrode and the third metal electrode. Because the thin-film solar cell unit can utilize sunlight which cannot be absorbed by the crystalline silicon solar cell, the combination of the thin-film solar cell unit and the crystalline silicon solar cell unit can effectively improve the overall solar energy conversion efficiency, thereby solving the problem of low conversion efficiency of the solar cell adopting a unijunction tunneling oxide layer passivation metal structure.
Example two
Fig. 2 is a flow chart of a method of manufacturing according to an embodiment of the present application.
Referring to fig. 1, the present embodiment provides a method for preparing a two-junction solar cell provided in the above embodiments, which specifically includes the following steps:
and S1, cleaning and texturing both sides of the N-type crystalline silicon substrate.
The N-type crystal silicon substrate 1 has resistivity of 0.5-3 Ω cm and size of 158.78 × 158.75mm2Cleaning two sides of a monocrystalline silicon wafer, removing a damaged layer, and texturing to form random pyramid structures on the front and back of the monocrystalline silicon wafer, as shown in fig. 2 a.
And S2, performing boron diffusion treatment on the front surface of the N-type crystalline silicon substrate to form a diffusion P-type layer.
B diffusion is carried out on the front surface of the N-type crystal silicon substrate after texturing by utilizing a boron diffusion furnace to form a P-type layer 1', so that a pn junction is obtained, and as shown in figure 2b, the highest doping concentration of the P-type layer is 1020cm-3Boron concentration of 1017cm-3The depth of the diffusion junction at this point was 0.5. mu.m.
And S3, performing back side wrap-around processing on the borosilicate glass on the front side and the back side of the N-type crystal silicon substrate.
The borosilicate glass on both sides of the N-type crystalline silicon substrate is removed by a cleaning machine, and back side wrap-around processing is performed, the effect of which is shown in fig. 2 c.
S4, preparing a first tunneling thin film layer and a third tunneling thin film layer.
The ultraviolet ozone treatment on the surface of the front surface and the back surface of the silicon wafer is realized by utilizing a turnover mechanism at the blanking section of the cleaning machine table, the growth of an ultrathin tunneling oxide layer is realized, a first tunneling thin film layer 2 is obtained on the front surface, a third tunneling thin film layer 2' is obtained on the back surface, and as shown in fig. 2d, the thicknesses of the two tunneling thin film layers are 1-3 nm. Two tunneling thin film layers are continuous at the edge of the crystalline silicon substrate.
And S5, preparing a first P-type semiconductor layer and a second N-type semiconductor layer.
Depositing boron-doped amorphous silicon on the front surface of the first tunneling thin film layer and the third tunneling thin film layer by using an anti-winding plating carrier plate type reactive magnetron sputtering device, and depositing phosphorus-doped amorphous silicon on the back surface of the first tunneling thin film layer and the third tunneling thin film layer, wherein the thicknesses of the amorphous silicon are respectively 70nm and 120nm, and the doping concentrations of the amorphous silicon are respectively 6 multiplied by 1020/cm3And 1021/cm3(ii) a And then, carrying out high-temperature annealing treatment at 890 ℃ for 20min on the cell piece through a tubular annealing furnace, so that a first P-type semiconductor layer 3 is formed on the first tunneling thin film layer doped on the front surface, and a second N-type semiconductor layer 4 is formed on the third tunneling thin film layer doped on the back surface, wherein the structure of the second N-type semiconductor layer is shown in fig. 2 e.
And S6, depositing and degrading to obtain a first passivation layer and a second passivation layer.
After the preparation of the first P-type semiconductor layer and the second N-type semiconductor layer is completed, a 3nm aluminum oxide film is deposited on the front surface of the first P-type semiconductor layer and the second N-type semiconductor layer by using an atomic layer deposition device to form a first passivation layer 5, and a 3nm silicon oxide film is deposited on the back surface of the first P-type semiconductor layer and the second N-type semiconductor layer to form a second passivation layer 6, wherein the structure of the second passivation layer is shown in fig. 2 f.
And S7, preparing a second anti-reflection layer on the second passivation layer.
After the preparation of the continuous passivation layer is completed, a silicon nitride and silicon oxide laminated film is deposited on the back surface of the material through the tubular PECVC, so that a second anti-reflection layer 15 is formed, the thickness of the second anti-reflection layer can be actually regulated and controlled according to the characteristics of the single-sided or double-sided battery, and the structure of the second anti-reflection layer is shown in FIG. 2 g.
And S8, preparing a first transparent conductive film layer on the first passivation layer.
An 80nm Indium Tin Oxide (ITO) transparent conductive film is deposited on the first passivation layer through an anti-winding plating carrier plate type reactive magnetron sputtering device to serve as a first transparent conductive film layer 9, the structure of the first transparent conductive film layer is shown in figure 2h, and the square resistance of the first transparent conductive film layer is 20 omega/square.
And S9, preparing a first metal electrode and a third metal electrode.
Preparing the first metal electrode 7 and the third metal electrode 8 on the first transparent conductive abrasive layer by means of screen printing, as shown in fig. 2 i; the first metal electrode needs to be ensured to be capable of burning through the ITO film layer 9 and the alumina film layer 5, and to be in contact with the surface of the boron-doped polycrystalline silicon 3 with a certain depth, the height of a grid line exposed outside the ITO 9 is less than 5nm, and the exposed part of the electrode is a silver electrode.
S10, preparing a first N-type semiconductor layer, the second tunneling film layer, a second P-type semiconductor layer, the second transparent conductive film layer and the first anti-reflection layer in sequence.
Depositing a phosphorus-doped hydrogenated amorphous silicon film on the front surface of the cell by using an anti-winding plating carrier plate type plasma enhanced chemical vapor deposition device to form a first N-type semiconductor layer 10, as shown in FIG. 2j, wherein the thickness of the first N-type semiconductor layer is 20nm, and the phosphorus doping concentration is 3 x 1021/cm3The deposition temperature is 200-220 ℃.
Depositing an intrinsic hydrogenated amorphous silicon film on the front surface of the cell by using the winding-proof plated carrier plate type plasma enhanced chemical vapor deposition equipment to form a second tunneling film layer 11, wherein the thickness of the second tunneling film layer is 5nm, and the deposition temperature is 200-220 ℃, as shown in fig. 2 k;
depositing a boron-doped hydrogenated amorphous silicon film on the front surface of the cell by using an anti-winding plating carrier plate type plasma enhanced chemical vapor deposition device to form a second P-type semiconductor layer 12, as shown in FIG. 2l, wherein the thickness of the second P-type semiconductor layer is 20nm, and the boron doping concentration is 8 x 1020/cm3The deposition temperature is 200-220 ℃;
and depositing an ITO film, namely a second transparent conductive film layer 13, on the front surface of the battery piece by using the winding-proof plating carrier plate type reactive magnetron sputtering equipment, wherein the thickness of the second transparent conductive film layer is 100nm, the sheet resistance is 40 omega/square, and the deposition temperature is room temperature, as shown in figure 2 m.
Finally, the front surface of the cell is subjected to low-temperature silver paste electrode printing by using a screen printing mode to obtain a second metal electrode 14, and as shown in fig. 2o, the curing temperature is lower than 180 ℃.
Optionally, the back edge of the cell may be trimmed by laser scanning (see fig. 2n) to expose the bare silicon wafer, which may be an optional process according to actual conditions.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and so forth) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The technical solutions provided by the present invention are described in detail above, and the principle and the implementation of the present invention are explained in this document by applying specific examples, and the descriptions of the above examples are only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (9)
1. A two-junction solar cell comprising an N-type crystalline silicon substrate, the crystalline silicon substrate comprising a front side and a back side, wherein:
a diffusion P-type layer, a first tunneling film layer, a first P-type semiconductor layer, a first passivation layer, a first transparent conductive film layer, a first N-type semiconductor layer, a second tunneling film layer, a second P-type semiconductor layer, a second transparent conductive film layer and a first anti-reflection layer are sequentially prepared on the front surface from inside to outside;
a first metal electrode is prepared between the first P-type semiconductor layer and the first transparent conductive film layer, a second metal electrode is prepared on the second transparent conductive film layer, and the second metal electrode penetrates through the first anti-reflection layer outwards;
a third tunneling film layer, a second N-type semiconductor layer, a second passivation layer and a second anti-reflection layer are sequentially prepared on the back surface from inside to outside;
and a third metal electrode connected with the second N-type semiconductor layer is prepared on the second N-type semiconductor layer, and the third metal electrode penetrates through the second passivation layer and the second anti-reflection layer outwards.
2. The two-junction solar cell of claim 1, wherein the dopant of the diffused P-type layer is boron and the dopant has a maximum doping concentration of 1018～1020cm-3Boron concentration of 1017cm-3The diffusion junction depth is 0.2-0.8 μm.
3. The two-junction solar cell of claim 1, wherein the first tunneling thin film layer is a mixture thin film, an oxide thin film, a nitride thin film, or an oxynitride thin film of a group IVA element, or is a metal oxide thin film;
the thickness of the first tunneling thin film layer is 1-5 nm.
4. The two-junction solar cell of claim 1, wherein the first and second P-type semiconductor layers are polycrystalline boron-doped or amorphous boron-doped films of group IVA elements, or are compound strongly conductive polarity P-type semiconductor films of group IIA or group VIA elements;
the thickness of the first P-type semiconductor layer or the second P-type semiconductor layer is 15-150 nm.
5. The two-junction solar cell of claim 1, wherein the first passivation layer comprises a stack of one or more layers of an aluminum oxide film, a silicon oxide film, an intrinsic film, and a P-type heavily doped amorphous group IVA elemental mixture film;
the thickness of the first passivation layer is 3-5 nm.
6. The two-junction solar cell of claim 1, wherein the first N-type semiconductor layer and the second N-type semiconductor layer are polycrystalline doped thin films or amorphous phosphorus doped thin films based on a group IVA element mixture, or compound strongly conductive polar N-type semiconductor thin films of a group IIA element or a group VIA element;
the thickness of the first N-type semiconductor layer and the second N-type semiconductor layer is 15-150 nm.
7. The two-junction solar cell of claim 1, wherein the second passivation layer comprises a single layer or a stack of layers of a silicon nitride film, a silicon oxide film, an intrinsic film, and a heavily N-doped amorphous group IVA element film;
the thickness of the second passivation layer is 3-15 nm.
8. The two-junction solar cell of claim 1, wherein the first transparent conductive film layer and the second transparent conductive film layer have a thickness of 60 to 100 nm.
9. A method for manufacturing a two-junction solar cell according to any of claims 1 to 8, wherein the index method comprises the steps of:
cleaning and texturing two sides of the N-type crystalline silicon substrate;
carrying out boron diffusion treatment on the front surface of the N-type crystalline silicon substrate to form a diffusion P-type layer;
carrying out back side wrapping and expanding treatment on the borosilicate glass on the front side and the back side of the N-type crystalline silicon substrate;
respectively performing tunneling layer growth operation on the front surface and the back surface of the N-type crystalline silicon substrate to obtain the first tunneling thin film layer and the third tunneling thin film layer;
preparing the first P-type semiconductor layer on the first tunneling thin film layer, and preparing the second N-type semiconductor layer on the third tunneling thin film layer;
depositing and degrading the N-type crystalline silicon substrate to obtain a first passivation layer and a second passivation layer;
preparing a second anti-reflection layer on the second passivation layer;
preparing the first transparent conductive film layer on the first passivation layer;
preparing the first metal electrode and the second metal electrode on the first transparent conductive grinding layer in a screen printing mode, preparing the third metal electrode on the second anti-reflection layer, wherein the first metal electrode penetrates through the first passivation layer and then is in deep contact with the first P-type semiconductor layer;
and sequentially preparing the first N-type semiconductor layer, the second tunneling film layer, the second P-type semiconductor layer, the second transparent conductive film layer and the first anti-reflection layer on the first transparent conductive film layer.
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