CN215299262U - Two-junction solar cell - Google Patents

Two-junction solar cell Download PDF

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CN215299262U
CN215299262U CN202022820213.2U CN202022820213U CN215299262U CN 215299262 U CN215299262 U CN 215299262U CN 202022820213 U CN202022820213 U CN 202022820213U CN 215299262 U CN215299262 U CN 215299262U
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layer
type semiconductor
solar cell
film
semiconductor layer
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王洪喆
刘勇
朴松源
李家栋
潘强强
杨刘
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Yidao New Energy Technology Co ltd
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Das Solar Co Ltd
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    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/544—Solar cells from Group III-V materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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Abstract

The embodiment of the application provides a two-junction solar cell, this battery forms based on N type crystal silicon substrate preparation, it is including diffusion P type layer to prepare in proper order on the front from inside to outside, first tunneling thin layer, first P type semiconductor layer, a first passivation layer, the crystalline silicon solar cell unit of first transparent conductive film layer, still include by first N type semiconductor layer, second tunneling thin layer, the thin film solar cell unit that second P type semiconductor layer and second transparent conductive film layer constitute, two kinds of solar cell units establish ties through first metal electrode, and whole solar cell passes through second metal electrode and third metal electrode realization and is connected with external circuit. Because the thin-film solar cell unit can utilize sunlight which cannot be absorbed by the crystalline silicon solar cell, the combination of the thin-film solar cell unit and the crystalline silicon solar cell unit can effectively improve the overall solar energy conversion efficiency, thereby solving the problem of low conversion efficiency of the solar cell adopting a unijunction tunneling oxide layer passivation metal structure.

Description

Two-junction solar cell
Technical Field
The application relates to the field of photovoltaic technology, in particular to a two-junction solar cell.
Background
Crystalline silicon solar cells are the most mature and widely used solar cells in technology, have a percentage in the photovoltaic market of over 90%, and will dominate for a considerable time in the future. Meanwhile, because the crystalline silicon solar cell is only sensitive to light within the visible wavelength range of 300-1100nm, photo-generated current can be generated and output to an external circuit, which indicates that the crystalline silicon solar cell cannot be used for light within the wavelength range of less than 300nm or more than 1100nm, and therefore the conversion efficiency of the solar cell adopting the single-junction tunneling oxide layer passivation metal structure is low.
SUMMERY OF THE UTILITY MODEL
In view of the above, the present application provides a two-junction solar cell to solve the problem of low conversion efficiency of a solar cell using a single junction tunnel oxide layer to passivate a metal structure.
In order to solve the above problem, the present application discloses a two-junction solar cell, comprising an N-type crystalline silicon substrate, the crystalline silicon substrate comprising a front side and a back side, wherein:
a diffusion P-type layer, a first tunneling film layer, a first P-type semiconductor layer, a first passivation layer, a first transparent conductive film layer, a first N-type semiconductor layer, a second tunneling film layer, a second P-type semiconductor layer, a second transparent conductive film layer and a first anti-reflection layer are sequentially prepared on the front surface from inside to outside;
a first metal electrode is prepared between the first P-type semiconductor layer and the first transparent conductive film layer, a second metal electrode is prepared on the second transparent conductive film layer, and the second metal electrode penetrates through the first anti-reflection layer outwards;
a third tunneling film layer, a second N-type semiconductor layer, a second passivation layer and a second anti-reflection layer are sequentially prepared on the back surface from inside to outside;
and a third metal electrode connected with the second N-type semiconductor layer is prepared on the second N-type semiconductor layer, and the third metal electrode penetrates through the second passivation layer and the second anti-reflection layer outwards.
Optionally, the dopant of the diffused P-type layer is boron, and the highest doping concentration of the dopant is 1018～1020cm-3Boron concentration of 1017cm-3The depth of the diffusion junction is 0.2-0.8 μm.
Optionally, the first tunneling thin film layer is a mixture film, an oxide film, a nitride film or an oxynitride film of group IVA elements, or a metal oxide film;
the thickness of the first tunneling thin film layer is 1-5 nm.
Optionally, the first P-type semiconductor layer and the second P-type semiconductor layer are polycrystalline boron-doped films or amorphous boron-doped films of group IVA elements, or are compound strongly conductive P-type semiconductor films of group IIA elements or group VIA elements;
the thickness of the first P-type semiconductor layer or the second P-type semiconductor layer is 15-150 nm.
Optionally, the first passivation layer includes a stack of one or more of an aluminum oxide film, a silicon oxide film, an intrinsic film, and a P-type heavily doped amorphous group IVA element mixture film;
the thickness of the first passivation layer is 3-5 nm.
Optionally, the first N-type semiconductor layer and the second N-type semiconductor layer are polycrystalline doped films or amorphous phosphorus-doped films based on group IVA element mixtures, or compound strongly conductive polar N-type semiconductor films of group IIA elements or group VIA elements;
the thickness of the first N-type semiconductor layer and the second N-type semiconductor layer is 15-150 nm.
Optionally, the second passivation layer includes a single-layer film or a stack of multiple films of a silicon nitride film, a silicon oxide film, an intrinsic film, and an N-type heavily-doped amorphous group IVA element film;
the thickness of the second passivation layer is 3-15 nm.
Optionally, the thicknesses of the first transparent conductive film layer and the second transparent conductive film layer are 60-100 nm.
According to the technical scheme, the two-junction solar cell is prepared on the basis of the N-type crystalline silicon substrate, crystalline silicon solar cell units comprising a diffusion P-type layer, a first tunneling thin layer, a first P-type semiconductor layer, a first passivation layer and a first transparent conductive film layer are sequentially prepared on the front surface from inside to outside, the two-junction solar cell further comprises a thin-film solar cell unit consisting of the first N-type semiconductor layer, a second tunneling thin layer, a second P-type semiconductor layer and a second transparent conductive film layer, the two solar cell units are connected in series through a first metal electrode, and the whole solar cell is connected with an external circuit through the second metal electrode and a third metal electrode. Because the thin-film solar cell unit can utilize sunlight which cannot be absorbed by the crystalline silicon solar cell, the combination of the thin-film solar cell unit and the crystalline silicon solar cell unit can effectively improve the overall solar energy conversion efficiency, thereby solving the problem of low conversion efficiency of the solar cell adopting a unijunction tunneling oxide layer passivation metal structure.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a cross-sectional view of a two-junction solar cell according to an embodiment of the present application;
FIG. 2 is a flow chart of a method of making an embodiment of the present application;
fig. 2a is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2b is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2c is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2d is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2e is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2f is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2g is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2h is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2i is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2j is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2k is a cross-sectional view of a two junction solar cell of an embodiment of the present application during fabrication;
FIG. 2l is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2m is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2n is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication;
fig. 2o is a cross-sectional view of a two-junction solar cell of an embodiment of the present application during fabrication.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Example one
Fig. 1 is a cross-sectional view of a two-junction solar cell according to an embodiment of the present disclosure.
Referring to fig. 1, the two-junction solar cell provided in this embodiment is a power generation element of a solar module, and the cell is prepared based on an N-type crystalline silicon substrate 1, which includes a front surface and a back surface, where the front surface and the back surface are opposite concepts, that is, one surface facing sunlight is used as the front surface of the crystalline silicon substrate, and the other surface is used as the back surface.
The front surface of the N-type crystalline silicon substrate is sequentially provided with a diffusion P-type layer 1', a first tunneling thin film layer 2, a first P-type semiconductor layer 3, a first passivation layer 5, a first transparent conductive film layer 9, a first N-type semiconductor layer 10, a second tunneling thin film layer 11, a second P-type semiconductor layer 12, a second transparent conductive film layer 13 and a first anti-reflection layer 14 from inside to outside.
A first metal electrode 7 is prepared between the first P-type semiconductor layer 3 and the first transparent conductive film layer 9, and a second metal electrode 14 is prepared on the second transparent conductive film layer and penetrates the first anti-reflection layer outwards.
And a third tunneling thin film layer 2', a second N-type semiconductor layer 4, a second passivation layer 6 and a second anti-reflection layer 15 are sequentially prepared on the back surface of the N-type crystalline silicon substrate from inside to outside. And a third metal electrode 8 connected with the second N-type semiconductor layer is prepared on the second N-type semiconductor layer, and the third metal electrode penetrates through the second passivation layer and the second anti-reflection layer outwards.
The second metal electrode and the third metal electrode form an external electrode of the cell and are used for being connected with an external circuit so as to output a circuit generated by the solar cell to an external circuit. Or the solar cells are connected through the second metal electrode and the third metal electrode when the solar cells are connected in series and parallel.
Wherein the dopant of the diffusion P-type layer is boron, the highest doping concentration of the dopant is 1018-1020 cm < -3 >, and the diffusion junction depth at the boron concentration of 1017cm < -3 > is 0.2-0.8 mu m.
The first tunneling thin film layer is a thin film, an oxide thin film, a nitride thin film or an oxynitride thin film of IVA group elements, or a mixture thin film of a plurality of IVA group elements, or a metal oxide thin film; the thickness of the first tunneling thin film layer is 1-5 nm.
The first P-type semiconductor layer and the second P-type semiconductor layer are polycrystalline boron-doped films or amorphous boron-doped films of IVA group elements, or are P-type semiconductor films with strong conductivity of compounds of IIA group elements or VIA group elements; the thickness of the first P-type semiconductor layer or the second P-type semiconductor layer is 15-150 nm. The thicknesses of the first P-type semiconductor layer and the second P-type semiconductor layer may be the same or different.
The first passivation layer is an aluminum oxide film, a silicon oxide film, an intrinsic film, a P-type heavily doped amorphous IVA group element mixture film, or a laminated film obtained by laminating one or more films. The thickness of the first passivation layer is 3-5 nm.
The first N-type semiconductor layer and the second N-type semiconductor layer are polycrystal doped films or amorphous phosphorus-doped films based on a group IVA element mixture, or are compound strong-conductivity N-type semiconductor films of group IIA elements or group VIA elements; the thickness of the first N-type semiconductor layer and the second N-type semiconductor layer is 15-150 nm. The thicknesses of the two N-type semiconductor layers may be the same or different.
The second passivation layer is a silicon nitride film layer, a silicon oxide film, an intrinsic film or an N-type heavily-doped amorphous IVA group element film, and can also be a laminated film comprising the films. The thickness of the second passivation layer is 3-15 nm. The thickness of the first transparent conductive film layer and the second transparent conductive film layer is 60-100 nm.
According to the technical scheme, the two-junction solar cell is prepared on the basis of the N-type crystalline silicon substrate, crystalline silicon solar cell units comprising a diffusion P-type layer, a first tunneling thin film layer, a first P-type semiconductor layer, a first passivation layer and a first transparent conductive film layer are sequentially prepared on the front surface from inside to outside, the two-junction solar cell further comprises a thin-film solar cell unit consisting of a first N-type semiconductor layer, a second tunneling thin film layer, a second P-type semiconductor layer and a second transparent conductive film layer, the two solar cell units are connected in series through a first metal electrode, and the whole solar cell is connected with an external circuit through a second metal electrode and a third metal electrode. Because the thin-film solar cell unit can utilize sunlight which cannot be absorbed by the crystalline silicon solar cell, the combination of the thin-film solar cell unit and the crystalline silicon solar cell unit can effectively improve the overall solar energy conversion efficiency, thereby solving the problem of low conversion efficiency of the solar cell adopting a unijunction tunneling oxide layer passivation metal structure.
Example two
Fig. 2 is a flow chart of a method of making an embodiment of the present application.
Referring to fig. 1, the present embodiment provides a method for preparing a two-junction solar cell provided in the above embodiments, which specifically includes the following steps:
and S1, cleaning and texturing both sides of the N-type crystalline silicon substrate.
The N-type crystal silicon substrate 1 has resistivity of 0.5-3 Ω cm and size of 158.78 × 158.75mm2Cleaning two sides of a monocrystalline silicon wafer, removing a damaged layer, and texturing to form random pyramid structures on the front and back of the monocrystalline silicon wafer, as shown in fig. 2 a.
And S2, performing boron diffusion treatment on the front surface of the N-type crystalline silicon substrate to form a diffusion P-type layer.
B diffusion is carried out on the front surface of the N-type crystal silicon substrate after texturing by utilizing a boron diffusion furnace to form a P-type layer 1', so that a pn junction is obtained, and as shown in figure 2b, the highest doping concentration of the P-type layer is 1020cm-3Boron concentration of 1017cm-3The depth of the diffusion junction at this point was 0.5. mu.m.
And S3, performing back side wrap-around processing on the borosilicate glass on the front side and the back side of the N-type crystal silicon substrate.
The borosilicate glass on both sides of the N-type crystalline silicon substrate is removed by a cleaning machine, and back side wrap-around processing is performed, the effect of which is shown in fig. 2 c.
S4, preparing a first tunneling thin film layer and a third tunneling thin film layer.
The ultraviolet ozone treatment on the surface of the front surface and the back surface of the silicon wafer is realized by utilizing a turnover mechanism at the blanking section of the cleaning machine table, the growth of an ultrathin tunneling oxide layer is realized, a first tunneling thin film layer 2 is obtained on the front surface, a third tunneling thin film layer 2' is obtained on the back surface, and as shown in fig. 2d, the thicknesses of the two tunneling thin film layers are 1-3 nm. Two tunneling thin film layers are continuous at the edge of the crystalline silicon substrate.
And S5, preparing a first P-type semiconductor layer and a second N-type semiconductor layer.
Depositing boron-doped amorphous silicon on the front surface of the first tunneling thin film layer and the third tunneling thin film layer by using an anti-winding plating carrier plate type reactive magnetron sputtering device, and depositing phosphorus-doped amorphous silicon on the back surface of the first tunneling thin film layer and the third tunneling thin film layer, wherein the thicknesses of the amorphous silicon are respectively 70nm and 120nm, and the doping concentrations of the amorphous silicon are respectively 6 multiplied by 1020/cm3And 1021/cm3(ii) a And then, carrying out high-temperature annealing treatment at 890 ℃ for 20min on the cell piece through a tubular annealing furnace, so that a first P-type semiconductor layer 3 is formed on the first tunneling thin film layer doped on the front surface, and a second N-type semiconductor layer 4 is formed on the third tunneling thin film layer doped on the back surface, wherein the structure of the second N-type semiconductor layer is shown in fig. 2 e.
And S6, depositing and degrading to obtain a first passivation layer and a second passivation layer.
After the preparation of the first P-type semiconductor layer and the second N-type semiconductor layer is completed, a 3nm aluminum oxide film is deposited on the front surface of the first P-type semiconductor layer and the second N-type semiconductor layer by using an atomic layer deposition device to form a first passivation layer 5, and a 3nm silicon oxide film is deposited on the back surface of the first P-type semiconductor layer and the second N-type semiconductor layer to form a second passivation layer 6, wherein the structure of the second passivation layer is shown in fig. 2 f.
And S7, preparing a second anti-reflection layer on the second passivation layer.
After the preparation of the continuous passivation layer is completed, a silicon nitride and silicon oxide laminated film is deposited on the back surface of the material through the tubular PECVC, so that a second anti-reflection layer 15 is formed, the thickness of the second anti-reflection layer can be actually regulated and controlled according to the characteristics of the single-sided or double-sided battery, and the structure of the second anti-reflection layer is shown in FIG. 2 g.
And S8, preparing a first transparent conductive film layer on the first passivation layer.
An 80nm Indium Tin Oxide (ITO) transparent conductive film is deposited on the first passivation layer through an anti-winding plating carrier plate type reactive magnetron sputtering device to serve as a first transparent conductive film layer 9, the structure of the first transparent conductive film layer is shown in figure 2h, and the square resistance of the first transparent conductive film layer is 20 omega/square.
And S9, preparing a first metal electrode and a third metal electrode.
Preparing the first metal electrode 7 and the third metal electrode 8 on the first transparent conductive abrasive layer by means of screen printing, as shown in fig. 2 i; the first metal electrode needs to be ensured to be capable of burning through the ITO film layer 9 and the alumina film layer 5, and to be in contact with the surface of the boron-doped polycrystalline silicon 3 with a certain depth, the height of a grid line exposed outside the ITO 9 is less than 5nm, and the exposed part of the electrode is a silver electrode.
S10, preparing a first N-type semiconductor layer, the second tunneling film layer, a second P-type semiconductor layer, the second transparent conductive film layer and the first anti-reflection layer in sequence.
Depositing a phosphorus-doped hydrogenated amorphous silicon film on the front surface of the cell by using an anti-winding plating carrier plate type plasma enhanced chemical vapor deposition device to form a first N-type semiconductor layer 10, as shown in FIG. 2j, wherein the thickness of the first N-type semiconductor layer is 20nm, and the phosphorus doping concentration is 3 x 1021/cm3The deposition temperature is 200-220 ℃.
Depositing an intrinsic hydrogenated amorphous silicon film on the front surface of the cell by using the winding-proof plated carrier plate type plasma enhanced chemical vapor deposition equipment to form a second tunneling film layer 11, wherein the thickness of the second tunneling film layer is 5nm, and the deposition temperature is 200-220 ℃, as shown in fig. 2 k;
depositing a boron-doped hydrogenated amorphous silicon film on the front surface of the cell by using an anti-winding plating carrier plate type plasma enhanced chemical vapor deposition device to form a second P-type semiconductor layer 12, as shown in FIG. 2l, wherein the thickness of the second P-type semiconductor layer is 20nm, and the boron doping concentration is 8 x 1020/cm3The deposition temperature is 200-220 ℃;
and depositing an ITO film, namely a second transparent conductive film layer 13, on the front surface of the battery piece by using the winding-proof plating carrier plate type reactive magnetron sputtering equipment, wherein the thickness of the second transparent conductive film layer is 100nm, the sheet resistance is 40 omega/square, and the deposition temperature is room temperature, as shown in figure 2 m.
Finally, the front surface of the cell is subjected to low-temperature silver paste electrode printing by using a screen printing mode to obtain a second metal electrode 14, and as shown in fig. 2o, the curing temperature is lower than 180 ℃.
Optionally, the back edge of the cell can be trimmed by laser scanning (see fig. 2n) to expose the bare silicon wafer, which can be selected according to actual conditions.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one of skill in the art, embodiments of the present application may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present application have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the true scope of the embodiments of the application.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The technical solutions provided by the present application are introduced in detail, and specific examples are applied in the description to explain the principles and embodiments of the present application, and the descriptions of the above examples are only used to help understanding the method and the core ideas of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (7)

1. A two-junction solar cell comprising an N-type crystalline silicon substrate, the crystalline silicon substrate comprising a front side and a back side, wherein:
a diffusion P-type layer, a first tunneling film layer, a first P-type semiconductor layer, a first passivation layer, a first transparent conductive film layer, a first N-type semiconductor layer, a second tunneling film layer, a second P-type semiconductor layer, a second transparent conductive film layer and a first anti-reflection layer are sequentially prepared on the front surface from inside to outside;
a first metal electrode is prepared between the first P-type semiconductor layer and the first transparent conductive film layer, a second metal electrode is prepared on the second transparent conductive film layer, and the second metal electrode penetrates through the first anti-reflection layer outwards;
a third tunneling film layer, a second N-type semiconductor layer, a second passivation layer and a second anti-reflection layer are sequentially prepared on the reverse side from inside to outside;
and a third metal electrode connected with the second N-type semiconductor layer is prepared on the second N-type semiconductor layer, and the third metal electrode penetrates through the second passivation layer and the second anti-reflection layer outwards.
2. The two-junction solar cell of claim 1, wherein the first tunneling thin film layer is a mixture thin film, an oxide thin film, a nitride thin film, or an oxynitride thin film of a group IVA element, or is a metal oxide thin film;
the thickness of the first tunneling thin film layer is 1-5 nm.
3. The two-junction solar cell of claim 1, wherein the first and second P-type semiconductor layers are polycrystalline boron-doped films or amorphous boron-doped films of group IVA elements, or compound strongly conductive polar P-type semiconductor films of group IIA or group VIA elements;
the thickness of the first P-type semiconductor layer or the second P-type semiconductor layer is 15-150 nm.
4. The two-junction solar cell of claim 1, wherein the first passivation layer comprises a stack of one or more layers of an aluminum oxide film, a silicon oxide film, an intrinsic film, and a P-type heavily doped amorphous group IVA elemental mixture film;
the thickness of the first passivation layer is 3-5 nm.
5. The two-junction solar cell of claim 1, wherein the first N-type semiconductor layer and the second N-type semiconductor layer are polycrystalline doped thin films or amorphous phosphorus doped thin films based on a group IVA element mixture, or compound strongly conductive polar N-type semiconductor thin films of a group IIA element or a group VIA element;
the thickness of the first N-type semiconductor layer and the second N-type semiconductor layer is 15-150 nm.
6. The two-junction solar cell of claim 1, wherein the second passivation layer comprises a single layer or a stack of layers of a silicon nitride film, a silicon oxide film, an intrinsic film, and a heavily N-doped amorphous group IVA element film;
the thickness of the second passivation layer is 3-15 nm.
7. The two-junction solar cell of claim 1, wherein the first transparent conductive film layer and the second transparent conductive film layer have a thickness of 60 to 100 nm.
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