CN113675300A - Preparation method of heterojunction battery - Google Patents
Preparation method of heterojunction battery Download PDFInfo
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- CN113675300A CN113675300A CN202110969906.4A CN202110969906A CN113675300A CN 113675300 A CN113675300 A CN 113675300A CN 202110969906 A CN202110969906 A CN 202110969906A CN 113675300 A CN113675300 A CN 113675300A
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
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- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
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- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02366—Special surface textures of the substrate or of a layer on the substrate, e.g. textured ITO/glass substrate or superstrate, textured polymer layer on glass substrate
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Abstract
A method of making a heterojunction battery, comprising: providing a semiconductor substrate layer; performing corrosion treatment on at least the back surface of the semiconductor substrate layer to enable the back surface of the semiconductor substrate layer to be smooth; performing corrosion treatment on at least the back surface of the semiconductor substrate layer, and then performing diffusion annealing treatment to form a first doping layer and a second doping layer in the semiconductor substrate layer with partial thickness respectively, wherein the surface of the first doping layer is positioned on the front surface of the semiconductor substrate layer, and the surface of the second doping layer is positioned on the back surface of the semiconductor substrate layer; after the diffusion annealing treatment is carried out, removing the first doping layer by adopting a single-sided etching process; and after the first doping layer is removed, performing texturing treatment on the front surface of the semiconductor substrate layer to enable the front surface of the semiconductor substrate layer to be an antireflection suede surface. The method avoids the tailing of the photoelectric conversion efficiency distribution of the heterojunction cell and reduces the cost.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a preparation method of a heterojunction battery.
Background
Solar cells (Solar cells) are devices that absorb sunlight and directly convert Solar radiation energy into electrical energy by the photoelectric effect. The solar cell is a clean energy cell and is widely applied to life and production. The HeteroJunction (HeteroJunction with intrinsic thin layer for short) cell is an important solar cell, and the structure of the HeteroJunction cell is that an N-type silicon substrate is used as the center, P-type amorphous silicon and N-type amorphous silicon are respectively formed on two sides of the HeteroJunction cell, then a layer of intrinsic amorphous silicon thin film is added between the P-type amorphous silicon and the N-type silicon substrate, and after the process measures are taken, the performance of a PN junction is improved, so that the conversion efficiency of the HeteroJunction cell is improved. In addition, the heterojunction cell has the characteristics of good temperature coefficient, double-sided power generation, low process temperature, high conversion efficiency and the like, and is a solar cell technology with great market competitiveness.
At present, the silicon wafers of the heterojunction battery have uneven quality, and the efficiency distribution of the battery is seriously trailing. The texturing thinning amount is large, and the silicon wafer cost is large.
Disclosure of Invention
The invention aims to solve the technical problems of trailing distribution of photoelectric conversion efficiency and higher cost of a heterojunction battery in the prior art.
In order to solve the above technical problems, the present invention provides a method for manufacturing a heterojunction battery, comprising: providing a semiconductor substrate layer; performing corrosion treatment on at least the back surface of the semiconductor substrate layer to enable the back surface of the semiconductor substrate layer to be smooth; performing corrosion treatment on at least the back surface of the semiconductor substrate layer, and then performing diffusion annealing treatment to form a first doping layer and a second doping layer in the semiconductor substrate layer with partial thickness respectively, wherein the surface of the first doping layer is positioned on the front surface of the semiconductor substrate layer, and the surface of the second doping layer is positioned on the back surface of the semiconductor substrate layer; after the diffusion annealing treatment is carried out, removing the first doping layer by adopting a single-sided etching process; and after the first doping layer is removed, performing texturing treatment on the front surface of the semiconductor substrate layer to enable the front surface of the semiconductor substrate layer to be an antireflection suede surface.
Optionally, the corrosion treatment is performed by using an alkali solution, wherein the alkali solution comprises a KOH solution or a NaOH solution, the mass percentage concentration of the alkali solution is 1% -20%, the temperature is 50-90 ℃, and the corrosion treatment time is 50-1000 seconds.
Optionally, the etching treatment further employs an alkali polishing additive, which includes tetramethylammonium hydroxide, alkyl glycoside, pyrazine, or polyethylene glycol.
Optionally, the alkali polishing additive has a mass percentage concentration of 1-10%.
Optionally, during the diffusion annealing treatment, a first oxide layer located on a surface of the first doping layer on a side facing away from the semiconductor substrate layer and a second oxide layer located on a surface of the second doping layer on a side facing away from the semiconductor substrate layer are further formed; the first oxide layer is also removed in the process of removing the first doped layer by adopting a single-sided etching process; the preparation method of the heterojunction battery further comprises the following steps: and removing the second oxide layer after the texturing treatment is carried out on the front surface of the semiconductor substrate layer.
Optionally, the second oxide layer is removed by a chain type cleaning mode, and in the process of removing the second doped layer by the chain type cleaning mode, the antireflection suede surface is positioned above the liquid level of the etching liquid adopted by the chain type cleaning.
Optionally, the method further includes: removing the second doped layer during the removing of the second oxide layer.
Optionally, the solid solubility of the first oxide layer to the impurities in the semiconductor substrate layer is greater than the solid solubility of the first doping layer to the impurities in the semiconductor substrate layer, and the solid solubility of the second oxide layer to the impurities in the semiconductor substrate layer is greater than the solid solubility of the second doping layer to the impurities in the semiconductor substrate layer.
Optionally, the thickness of the first oxide layer is 0.05 μm to 3 μm, and the thickness of the second oxide layer is 0.05 μm to 3 μm.
Optionally, the method further includes: after the front surface of the semiconductor substrate layer is subjected to texturing treatment, a first doped semiconductor layer is formed on one side of the front surface of the semiconductor substrate layer; after removing the second oxide layer, forming a second doped semiconductor layer on one side of the back surface of the semiconductor substrate layer; wherein the conductivity type of the second doped semiconductor layer is opposite to the conductivity type of the first doped semiconductor layer.
Optionally, the method further includes: forming a first intrinsic semiconductor layer on the surface of the front side of the semiconductor substrate layer after the texturing treatment and before the first doped semiconductor layer is formed; and after removing the second oxide layer and before forming the second doped semiconductor layer, forming a second intrinsic semiconductor layer on the back side of the semiconductor substrate layer.
Optionally, the diffusion annealing treatment is performed in a diffusion furnace, and a gas source adopted by the diffusion annealing treatment is a phosphorus-containing gas source; the first doped layer and the second doped layer contain phosphorus ions.
Optionally, the phosphorus-containing gas source comprises POCl3And O2。
Optionally, the phosphorus-containing gas source further comprises water vapor.
Optionally, the phosphorus-containing gas source further comprises H2。
Optionally, the temperature adopted by the diffusion annealing treatment is 600-1200 ℃; the time for the diffusion annealing treatment is 10min-120 min.
Optionally, the temperature adopted by the diffusion annealing treatment is 800-900 ℃.
Optionally, the diffusion annealing is performedO for physical adoption2The flow rate is 400sccm-1000 sccm.
Optionally, POCl used for the diffusion annealing treatment3The flow rate is 400sccm-1000 sccm.
Optionally, H is adopted in the diffusion annealing treatment2The flow rate is 400sccm-1000 sccm.
Optionally, the step of removing the first doped layer by using a single-sided etching process includes: and removing the first doped layer by adopting a chain type cleaning mode, wherein the second doped layer is exposed above the liquid level of the etching liquid by adopting the chain type cleaning mode in the process of removing the first doped layer by adopting the chain type cleaning mode.
Optionally, the conductivity type of the first doping layer is the same as the conductivity type of the semiconductor substrate layer before the diffusion annealing treatment is performed; and the conductivity type of the second doping layer is the same as that of the semiconductor substrate layer before the diffusion annealing treatment.
Optionally, before the diffusion annealing treatment is performed, the conductivity type of the semiconductor substrate layer is N-type, the conductivity type of the first doped layer is N-type, and the conductivity type of the second doped layer is N-type.
Optionally, the concentration of the doping ions in the first doping layer is 1E19atom/cm3-8E21 atom/cm3(ii) a The concentration of doped ions in the second doped layer is 1E19atom/cm3-8E21 atom/cm3。
Optionally, the texturing treatment adopts an alkaline texturing solution, the alkaline texturing solution comprises a KOH solution or a NaOH solution, the mass percentage concentration of the alkaline texturing solution is 1% -5%, the reaction temperature is 50-85 ℃, and the reaction time is 200s, 300s, 400s, 500s, 600s, 700s, 800s or 900 s.
Optionally, the texturing treatment further adopts a texturing additive and a selective corrosive agent, the texturing additive comprises hydrolyzed polyacrylonitrile sodium salt, polyamino acid or alkyl ammonium chloride, and the selective corrosive agent comprises tetramethyl sodium hydroxide.
Optionally, the reflectivity of the back side of the semiconductor substrate layer is 35% to 60%.
Optionally, after removing the second oxide layer, the thickness of the semiconductor substrate layer is 50 μm to 170 μm.
The technical method of the invention has the following beneficial effects:
in the preparation method of the heterojunction cell provided by the technical scheme of the invention, the amount of sunlight received by the front surface of the heterojunction cell is larger than that received by the back surface of the heterojunction cell. Firstly, the front side of the semiconductor substrate layer is an anti-reflection suede, the reflection quantity of sunlight incident from the front side of the heterojunction cell is reduced, and therefore more sunlight incident from the front side of the heterojunction cell can enter the semiconductor substrate layer. Secondly, before the front side of the semiconductor substrate layer is subjected to texturing treatment, corrosion treatment is carried out to enable the back side of the semiconductor substrate layer to be smooth, so that sunlight entering the semiconductor substrate layer from the front side of the heterojunction cell is easily reflected by the back side of the semiconductor substrate layer to return to the semiconductor substrate layer again, the optical path of the sunlight entering from the front side of the heterojunction cell in the semiconductor substrate layer is increased, and carriers in the semiconductor substrate layer are increased. Secondly, the single-sided texturing can reduce the overall thinning amount of the semiconductor substrate layer, so that the thickness of the semiconductor substrate layer after texturing is relatively large, and the sunlight absorption amount of the semiconductor substrate layer is improved. And thirdly, after the etching treatment, performing diffusion annealing treatment to form a first doping layer and a second doping layer on two sides of the semiconductor substrate layer with partial thickness respectively, wherein the diffusion annealing treatment is suitable for outwards migrating impurities in the semiconductor substrate layer, so that the content of the impurities in the semiconductor substrate layer is reduced. In conclusion, the internal defects of the semiconductor substrate layer are reduced, the probability that the current carriers are captured by the defect traps is further reduced, and the photoelectric conversion efficiency of the heterojunction cell is improved.
Furthermore, since the single-sided texturing can reduce the amount of thinning of the entire semiconductor substrate layer, the thickness of the substrate original sheet used in the case where the final design value of the thickness of the semiconductor substrate layer is the same can be reduced, which leads to a reduction in cost.
In addition, the first doping layer is removed by adopting a single-sided etching process, so that the step of removing the first doping layer is simple, and the process efficiency is improved.
Further, in the process of performing the diffusion annealing treatment, a first oxide layer located on a surface of the first doping layer on a side opposite to the semiconductor substrate layer and a second oxide layer located on a surface of the second doping layer on a side opposite to the semiconductor substrate layer are also formed. The first oxide layer is also removed in the process of removing the first doping layer by adopting a single-sided etching process, and the second oxide layer can also play a role in protecting the back surface of the semiconductor substrate layer in the process of performing texturing treatment on the front surface of the semiconductor substrate layer.
Furthermore, the solid solubility of the first oxidation layer to impurities in the semiconductor substrate layer is greater than that of the first doping layer to impurities in the semiconductor substrate layer, the solid solubility of the second oxidation layer to impurities in the semiconductor substrate layer is greater than that of the second doping layer to impurities in the semiconductor substrate layer, so that in the process of diffusion annealing treatment, the impurities in the semiconductor substrate layer are mainly diffused into the first oxidation layer after being adsorbed by the first doping layer, the impurities in the semiconductor substrate layer are mainly diffused into the second oxidation layer after being adsorbed by the second doping layer, the content of the impurities in the first doping layer and the second doping layer is reduced, the impurity concentrations in the semiconductor substrate layer, the first doping layer and the first oxidation layer form an increasing gradient, and the impurity concentrations in the semiconductor substrate layer, the second doping layer and the second oxidation layer form an increasing gradient, therefore, the impurity in the semiconductor substrate layer is removed more effectively. The first doping layer and the first oxidation layer are removed before the texturing treatment, the second oxidation layer is removed after the texturing treatment, and impurities in the first oxidation layer and the second oxidation layer are also removed. Since the second oxide layer has a greater solid solubility for impurities in the semiconductor substrate layer than the second doped layer, the second doped layer has a relatively low impurity content and can be selectively retained or removed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart of the heterojunction cell fabrication process in example 1 of the present invention;
fig. 2 to 9 are schematic structural views of a heterojunction cell fabrication process in example 1 of the present invention;
fig. 10 to 11 are schematic structural views of a heterojunction cell fabrication process in example 2 of the present invention;
reference numerals:
100. a semiconductor substrate layer; 111. a first doped layer; 112. a second doped layer; 131. a first oxide layer; 132. a second oxide layer; 141. a first doped semiconductor layer; 142. a second doped semiconductor layer; 141', a first doped semiconductor layer; 142' and a second doped semiconductor layer.
Detailed Description
Example 1:
an embodiment of the present invention provides a method for manufacturing a heterojunction battery, please refer to fig. 1, which includes the following steps:
s1, providing a semiconductor substrate layer;
s2, performing corrosion treatment on at least the back surface of the semiconductor substrate layer to enable at least the back surface of the semiconductor substrate layer to be smooth;
s3, after at least the back surface of the semiconductor substrate layer is subjected to corrosion treatment, performing diffusion annealing treatment to form a first doping layer and a second doping layer in the semiconductor substrate layer with partial thickness respectively, wherein the surface of the first doping layer is positioned on the front surface of the semiconductor substrate layer, and the surface of the second doping layer is positioned on the back surface of the semiconductor substrate layer;
s4, removing the first doped layer by adopting a single-sided etching process after the diffusion annealing treatment is carried out;
and S5, after the first doping layer is removed, performing texturing treatment on the front surface of the semiconductor substrate layer to enable the front surface of the semiconductor substrate layer to be an anti-reflection textured surface.
The process of forming a semiconductor substrate layer in one embodiment of the invention is described in detail below with reference to fig. 2-9.
Referring to fig. 2, a semiconductor substrate layer 100 is provided.
The material of the semiconductor substrate layer 100 comprises monocrystalline silicon. In other embodiments, the material of the semiconductor substrate layer is other semiconductor materials, such as silicon or silicon germanium. The material of the semiconductor substrate layer may also be other semiconductor materials.
In this embodiment, the conductivity type of the semiconductor substrate layer 100 is N-type, and may be an N-type silicon wafer, for example, which is suitable for the preparation of a heterojunction battery.
Referring to fig. 3, a surface pre-cleaning process is preferably performed on the semiconductor substrate layer 100.
The effects of the surface pre-cleaning treatment include: organic matters and metal impurity pollutants on the surface of the semiconductor substrate layer 100 are removed.
Specifically, the surface pre-cleaning treatment may be performed not only to clean the front surface of the semiconductor substrate layer 100 but also to clean the back surface of the semiconductor substrate layer 100. The solution adopted for the surface pre-cleaning treatment comprises: a mixed solution of hydrochloric acid and hydrogen peroxide.
Referring to fig. 4, at least the back side of the semiconductor substrate layer 100 is etched to render at least the back side of the semiconductor substrate layer smooth.
After the surface pre-cleaning treatment, the back surface of the semiconductor substrate layer 100 is subjected to etching treatment. The back side of the semiconductor substrate layer 100 is etched to make the back side of the semiconductor substrate layer 100 smooth. Correspondingly, the back surface of the subsequently formed semiconductor substrate layer is smooth.
In this embodiment, the front surface of the semiconductor substrate layer 100 is etched as well as the back surface of the semiconductor substrate layer 100, so that both the front surface and the back surface of the semiconductor substrate layer 100 are smooth after the etching.
The corrosion treatment adopts alkali liquor. The alkali solution comprises KOH solution or NaOH solution, the mass percentage concentration of the alkali solution is 1% -20%, such as 3%, 5%, 10%, 14% or 18%, and the temperature of the alkali solution is 50-90 ℃.
The concentration of the alkali liquor adopted in the corrosion treatment is higher than that of the alkali liquor adopted in the subsequent texturing treatment, so that the isotropy of etching in the corrosion treatment is realized, and the reflectivity of a smooth surface on the back surface of the semiconductor substrate layer is favorably improved. In the corrosion treatment, the temperature of the KOH solution is not more than 90 ℃, so that the etching rate is easy to control, the etching degrees of different areas are relatively consistent, the flatness of the formed smooth surface is relatively high, and in the corrosion treatment, the temperature of the KOH solution is not less than 50 ℃, so that the etching rate is relatively high.
In one embodiment, the time of the etching treatment is 50 seconds to 1000 seconds, such as 50 seconds, 80 seconds, 100 seconds, 200 seconds, 300 seconds, 400 seconds, 500 seconds, 600 seconds, 700 seconds, or 800 seconds. The time of the corrosion treatment is not suitable to be too long or too short, and if the time of the corrosion treatment is too long, the consumed thickness of the semiconductor substrate layer is increased; the etching process is performed for a time too short, and the reflectivity of the back surface of the semiconductor substrate layer is affected.
Further, the corrosion treatment also adopts an alkali polishing additive, the alkali polishing additive comprises tetramethylammonium hydroxide, alkyl glycoside, pyrazine or polyethylene glycol, and the mass percentage concentration of the alkali polishing additive is 1-10%. The role of the alkali polishing additive includes: the isotropic corrosion to the semiconductor substrate layer 100 is strengthened, the surface bulge of the semiconductor substrate layer 100 is eliminated, and the surface of the semiconductor substrate layer 100 is smoother.
Typically, the impurities within the semiconductor substrate layer 100 include metal impurities, limited by the formation mechanism of the silicon wafer.
Referring to fig. 5, after performing an etching process on at least the back surface of the semiconductor substrate layer 100, performing a diffusion annealing process on the semiconductor substrate layer 100 to form a first doped layer 111 and a second doped layer 112 in the semiconductor substrate layer 100 with a partial thickness, wherein the surface of the first doped layer 111 is located on the front surface of the semiconductor substrate layer 100, and the surface of the second doped layer 112 is located on the back surface of the semiconductor substrate layer 100.
The diffusion annealing process is adapted to migrate impurities inside the semiconductor substrate layer 100 outward. In particular, the diffusion annealing process is adapted to migrate impurities inside the semiconductor substrate layer 100 into said first and second doped layers 111, 112.
Through diffusion annealing treatment, the solubility of the first doping layer 111 and the second doping layer 112 to impurities is increased, and the impurities in the semiconductor substrate layer 100 are transferred to the first doping layer 111 and the second doping layer 112 through the diffusion annealing treatment, so that the content of the impurities in the semiconductor substrate layer 100 is reduced, and further the internal defects of the subsequently formed semiconductor substrate layer are reduced.
In this embodiment, the conductivity type of the first doping layer 111 is the same as the conductivity type of the semiconductor substrate layer 100 before the diffusion annealing treatment; the conductivity type of the second doped layer 112 is the same as the conductivity type of the semiconductor substrate layer 100 prior to the diffusion annealing process. Preferably, the first doped layer 111 and the second doped layer 112 are both N-type, and the doping element is phosphorus.
In one embodiment, the concentration of dopant ions in first doped layer 111 is 1E19atom/cm3-8E21atom/cm3E.g. 1E19atom/cm3、1E20atom/cm3、1E21atom/cm3. The concentration of doping ions in the second doping layer 112 is 1E19atom/cm3-8E21atom/cm3E.g. 1E19atom/cm3、1E20atom/cm3、1E21atom/cm3。
In this embodiment, during the diffusion annealing process, a first oxide layer 131 located on a surface of the first doped layer 111 facing away from the semiconductor substrate layer 100 and a second oxide layer 132 located on a surface of the second doped layer 112 facing away from the semiconductor substrate layer 100 are also formed. When the material of the semiconductor substrate layer 100 is silicon, the material of the first oxide layer 131 and the second oxide layer 132 is SiO2。
Further, the solid solubility of the first oxide layer 131 to the impurities in the semiconductor substrate layer 100 is greater than the solid solubility of the first doped layer 111 to the impurities in the semiconductor substrate layer 100, and the solid solubility of the second oxide layer 132 to the impurities in the semiconductor substrate layer 100 is greater than the solid solubility of the second doped layer 112 to the impurities in the semiconductor substrate layer 100. In the process of performing the diffusion annealing treatment, the impurities in the semiconductor substrate layer 100 are adsorbed by the first doping layer 111 and then mainly diffused into the first oxidation layer 131, the impurities in the semiconductor substrate layer 100 are adsorbed by the second doping layer 112 and then mainly diffused into the second oxidation layer 132, so that the content of the impurities in the first doping layer 111 and the second doping layer 112 is reduced, the impurity concentrations in the semiconductor substrate layer 100, the first doping layer 111 and the first oxidation layer 131 form an increasing gradient, the impurity concentrations in the semiconductor substrate layer 100, the second doping layer 112 and the second oxidation layer 132 form an increasing gradient, and therefore the effect of removing the impurities in the semiconductor substrate layer 100 is better.
The solid solubility means: the maximum content of solute in solid solution, that is, the limit solubility of impurities (solute) in a solvent (first oxide layer 131, second oxide layer 132, first doped layer 111, or second doped layer 112).
In this embodiment, the first oxide layer 131 and the first doped layer 111 both have a gettering function, and the second oxide layer 132 and the second doped layer 112 both have a gettering function.
In one embodiment, the diffusion annealing process is performed in a diffusion furnace, the diffusion furnace comprising a tubular diffusion furnace or a chain diffusion furnace; the gas source adopted for the diffusion annealing treatment is a phosphorus-containing gas source; the first doped layer 111 and the second doped layer 112 contain phosphorus ions therein. The source of phosphorus-containing gas comprises oxygen (O)2) And phosphorus oxychloride (POCl)3)。
In one embodiment, the diffusion annealing treatment is carried out at a temperature of 600 ℃ to 1200 ℃, e.g., 750 ℃ to 1100 ℃, preferably 800 ℃ to 900 ℃, e.g., 800 ℃, 850 ℃ or 900 ℃; the diffusion annealing treatment is carried out for 10min-120min, such as 10min, 30 min, 1 hr, 1.5 hr or 2 hr, preferably 10min-60 min. The temperature adopted in the diffusion annealing treatment needs to effectively dope the doping ions in the gas source into the surface region of the semiconductor substrate layer on one hand, and also needs to ensure that the impurities in the semiconductor substrate layer are transferred into the first doping layer 111 and the second doping layer 112 on the other hand; secondly, the temperature adopted by the diffusion annealing treatment needs to be better controlled in the doping thickness, and the cost is lower.
In one embodiment, the diffusion annealing process uses oxygen (O)2) Phosphorus oxychloride (POCl) with the flow rate of 400sccm-1000sccm3) The flow rate is 400sccm-1000 sccm. During the diffusion annealing treatment, at a certain temperature, for example, 600 ℃ to 1200 ℃, due to POCl3And O2Reaction to form P2O5And Cl2At high temperature P2O5Reacting with the surface of the semiconductor substrate layer to generate oxide and P, diffusing the P into the semiconductor substrate layer, and when the semiconductor substrate layer is made of silicon, the oxide is SiO doped with P2. Therefore, in the process of performing the diffusion annealing treatment, the surface of the semiconductor substrate layer 100 is oxidized to form the first oxide layer 131 and the second oxide layer 132, and finally the first oxide layer 131 is located on the surface of the first doped layer 111 facing away from the semiconductor substrate layer 100, and the second oxide layer 132 is located on the surface of the second doped layer 112 facing away from the semiconductor substrate layer 100.
In one embodiment, the phosphorus-containing gas source comprises O2、POCl3And water vapor, and further comprising a carrier gas comprising nitrogen. The addition of water vapor facilitates the thickness of the first oxide layer 131 and the second oxide layer 132 to be increased.
In another embodiment, the phosphorus-containing gas source comprises O2、POCl3And H2Further comprising a carrier gas comprising nitrogen (N)2)。H2Is advantageous in that the thickness of the first oxide layer 131 and the second oxide layer 132 is increased, H2The flow rate is 400sccm-1000 sccm. The nitrogen also plays roles of dilution, purging, protection and the like in the cavity.
In one embodiment, the thickness of first doped layer 111 is 0.1 μm to 0.5 μm, such as 0.1 μm, 0.2 μm, 0.3 μm, or 0.5 μm; the thickness of second doped layer 112 is 0.1 μm-0.3 μm, such as 0.1 μm, 0.2 μm, 0.3 μm, or 0.5 μm. The thicknesses of the first doping layer 111 and the second doping layer 112 are both greater than or equal to 0.1 μm, so that the first doping layer 111 and the second doping layer 112 have more space for absorbing impurities, and the thicknesses of the first doping layer 111 and the second doping layer 112 are both less than or equal to 0.5 μm, so that the situation that too many impurities enter the semiconductor substrate layer 100 to generate negative effects can be avoided.
In this embodiment, the material of the first oxide layer 131 and the second oxide layer 132 includes phosphosilicate glass (PSG).
The first oxide layer 131 has a thickness of 0.05 μm to 3 μm and the second oxide layer 132 has a thickness of 0.05 μm to 3 μm, for example 0.05 μm, 1 μm, 2 μm, 2.5 μm or 3 μm. The second oxide layer 132 has a relatively large thickness, so the second oxide layer 132 can protect the backside of the semiconductor substrate layer better in the subsequent texturing process.
Referring to fig. 6, after the diffusion annealing process is performed, the first doping layer 111 is removed by using a single-sided etching process. At the same time of removing first doping layer 111, impurities contained therein are also removed. The first oxide layer 131 is also removed during the removal of the first doped layer using a single-sided etching process.
The step of removing the first doped layer by adopting a single-sided etching process comprises the following steps: the first doped layer 111 is removed by using a chain cleaning method. Meanwhile, in the process of removing the first doping layer 111 by adopting the chain cleaning mode, the second doping layer 112 is exposed above the liquid level of the etching liquid for the chain cleaning. Specifically, in the process of removing the first doping layer 111 by using the chain cleaning method, both the second doping layer 112 and the second oxide layer 132 are exposed above the liquid level of the etching solution for the chain cleaning.
In the in-process of carrying out the chain cleaning, place the semiconductor substrate layer on a plurality of gyro wheels of arranging side by side, the front of semiconductor substrate layer is towards the gyro wheel and sets up with the gyro wheel is relative, the gyro wheel rotates around the center pin of gyro wheel, the liquid level of the etching solution that the chain cleaning adopted is less than the top of gyro wheel, consequently the gyro wheel makes the gyro wheel surface adhere to there is the sculpture liquid level at rotatory in-process, the etching solution on gyro wheel surface contacts first oxide layer, get rid of first oxide layer and expose first doping layer, then the etching solution on gyro wheel surface contacts first doping layer and gets rid of first doping layer.
The chain cleaning method improves the efficiency of removing the first doping layer 111, the adopted etching solution is a mixed solution of hydrofluoric acid and HCl, the mass percentage concentration of the hydrofluoric acid is 2% -5%, such as 2%, 3%, 4% or 5%, and the mass percentage concentration of the HCl is 5% -8%, such as 5%, 6%, 7% or 8%.
Referring to fig. 7, after the first doping layer 111 and the first oxide layer 131 are removed, a texturing process may be performed on the front surface of the semiconductor substrate layer 100 with higher purity, so that the front surface of the semiconductor substrate layer 100 is an anti-reflection textured surface.
The antireflection suede is pyramid-shaped. Specifically, a trough-type texturing tank is used, in which an alkaline texturing solution is provided, and the semiconductor substrate layer 100 is immersed in the alkaline texturing solution in the trough-type texturing tank. The alkaline texturing solution comprises KOH solution or NaOH solution, the mass percentage concentration of the alkaline texturing solution is 1% -5%, for example, 1%, 2%, 3%, 4% or 5%, the reaction temperature is 50-85 ℃, for example, 50 ℃, 60 ℃, 70 ℃, 80 ℃ or 85 ℃, and the reaction time is 200s, 300s, 400s, 500s, 600s, 700s, 800s or 900 s. The height of the pyramidal structure of the antireflection texture is 0.5 μm to 5 μm, and the bottom side length of the pyramidal structure is 0.5 μm to 8 μm, preferably 0.5 μm, 1 μm, 1.5 μm, 2 μm.
Furthermore, the wool making treatment also adopts a wool making additive and a selective corrosive agent, wherein the wool making additive comprises hydrolyzed polyacrylonitrile sodium salt, polyamino acid or alkyl ammonium chloride, and the selective corrosive agent comprises tetramethyl sodium hydroxide. The mass percentage concentration of the texturing additive is 1-10%. The mass percentage concentration of the selective corrosive agent is 0.1-3%.
The effects of the texturing additive include: the corrosion effect on the texturing surface is increased, and the corrosion degree on the second oxide layer is less than that on the texturing surface.
The effects of the selective etchant include: reducing corrosion of the second oxide layer.
In this embodiment, the method further includes: and after the texturing treatment is carried out, carrying out smoothing treatment on the antireflection suede.
When the front surface of the semiconductor substrate layer 100 is subjected to texturing, the second oxide layer 132 can protect the smooth surface formed on the back surface of the semiconductor substrate layer 100 to a certain extent, so that the smooth surface on the back surface of the semiconductor substrate layer 100 is prevented from being damaged in the texturing process, and the reflectivity of the smooth surface on the back surface of the semiconductor substrate layer 100 is ensured.
Referring to fig. 8, after the front surface of the semiconductor substrate layer 100 is subjected to a texturing process, the second oxide layer 132 is removed. Specifically, the second oxide layer 132 is removed in a chain type cleaning manner, and in the process of removing the second doped layer 132 in the chain type cleaning manner, the antireflection suede is located above the liquid level of the etching liquid adopted in the chain type cleaning.
In this embodiment, the second oxide layer 132 is removed and the second doped layer 112 remains. In this way, second oxide layer 132 containing more impurities is removed, and the impurities in second doped layer 112 are less, leaving second doped layer 112 less of an impact on the purity of semiconductor substrate layer 100 and enabling the thickness of semiconductor substrate layer 100 to be relatively large. Due to the back side being smooth, the sunlight is easily reflected by the back side back into the second doped layer 112 and the semiconductor substrate layer 100 again, which further increases the optical path of the sunlight incident from the front side of the heterojunction cell in the semiconductor substrate layer, so that the total amount of photogenerated carriers in the semiconductor substrate layer and the second doped layer 112 is increased. After removing the second oxide layer 132, the thickness of the semiconductor substrate layer 100 is 50 μm to 170 μm, such as 60 μm, 80 μm, 100 μm, 120 μm, 150 μm or 170 μm, and the thickness of the semiconductor substrate layer 100 is relatively large, so that the optical path of sunlight incident from the front side into the semiconductor substrate layer 100 after being reflected by the back side is large. By increasing the optical path of light propagating in the heterojunction cell, the acting time of the light in the layer structure is prolonged, the absorption rate of sunlight can be effectively improved, the solar cell can convert more electric energy, and the photoelectric conversion efficiency is improved.
Referring to fig. 9, after performing a texturing process on the front surface of the semiconductor substrate layer 100, a first doped semiconductor layer 141 is formed on the front surface side of the semiconductor substrate layer 100; after removing the second oxide layer, forming a second doped semiconductor layer 142 on the back side of the semiconductor substrate layer 100; wherein the conductivity type of the second doped semiconductor layer 142 is opposite to the conductivity type of the first doped semiconductor layer 141.
In this embodiment, the conductivity type of the first doped semiconductor layer 141 is an N-type, and the conductivity type of the second doped semiconductor layer 142 is a P-type.
In this embodiment, the method further includes: forming a first intrinsic semiconductor layer (not specifically shown in the figure) on the surface of the front side of the semiconductor substrate layer after the texturing treatment and before the first doped semiconductor layer is formed; after removing the second oxide layer and before forming the second doped semiconductor layer, a second intrinsic semiconductor layer (not specifically shown) is formed on the back side of the semiconductor substrate layer. By forming the first intrinsic semiconductor layer and the second intrinsic semiconductor layer, dangling bonds of the semiconductor substrate layer can be effectively hydrogenated and surface defects are reduced, so that minority carrier lifetime is prolonged, open-circuit voltage is increased, and cell efficiency is improved finally.
In this embodiment, the second doped layer 112 is located between the semiconductor substrate layer 100 and the second doped semiconductor layer 142, and more particularly, the second doped layer 112 is located between the semiconductor substrate layer 100 and the second intrinsic semiconductor layer.
In this embodiment, the method further includes: forming a first transparent conductive film (not specifically shown in the figure) on a side of the first doped semiconductor layer 141 facing away from the semiconductor substrate layer 100; forming a second transparent conductive film (not specifically shown in the figure) on a side of the second doped semiconductor layer 142 away from the semiconductor substrate layer 100; forming a first gate line electrode (not specifically shown in the figure) on one side of the first transparent conductive film, which is far away from the semiconductor substrate layer 100; a second gate line electrode (not specifically shown) is formed on a side of the second transparent conductive film facing away from the semiconductor substrate layer 100.
The reflectivity of the back side of the semiconductor substrate layer 100 is 35% -60%, such as 35%, 40%, 45%, 50%, 55%, or 60%. The reflectivity of the back side of the semiconductor substrate layer 100, especially in the 400nm-500nm and 1050nm-1200nm wave bands, enhances the light utilization rate, thereby improving the Internal Quantum Efficiency (IQE) and further improving the short-circuit current.
In this embodiment, the amount of sunlight received by the front side of the heterojunction cell is greater than the amount of sunlight received by the back side of the heterojunction cell. Firstly, the front side of the semiconductor substrate layer is an anti-reflection suede, the reflection quantity of sunlight incident from the front side of the heterojunction cell is reduced, and therefore more sunlight incident from the front side of the heterojunction cell can enter the semiconductor substrate layer. And secondly, before the front surface of the semiconductor substrate layer is subjected to texturing treatment, performing corrosion treatment to enable the back surface of the semiconductor substrate layer to be smooth, so that sunlight entering the semiconductor substrate layer from the front surface of the heterojunction cell is easily reflected by the back surface of the semiconductor substrate layer to return to the semiconductor substrate layer again, the optical path of the sunlight entering from the front surface of the heterojunction cell in the semiconductor substrate layer is increased, and carriers in the semiconductor substrate layer are increased. Secondly, the single-sided texturing can reduce the overall thinning amount of the semiconductor substrate layer, so that the thickness of the semiconductor substrate layer after texturing is relatively large, and the sunlight absorption amount of the semiconductor substrate layer is improved. And thirdly, after the etching treatment, performing diffusion annealing treatment to form a first doping layer and a second doping layer on two sides of the semiconductor substrate layer with partial thickness respectively, wherein the diffusion annealing treatment outwards migrates the impurities in the semiconductor substrate layer so as to reduce the content of the impurities in the semiconductor substrate layer. In conclusion, the preparation method of the heterojunction cell reduces the internal defects of the semiconductor substrate layer, further reduces the probability of capturing the current carriers by the defect traps, and improves the photoelectric conversion efficiency of the heterojunction cell. In addition, the first doping layer is removed by adopting a single-sided etching process, so that the step of removing the first doping layer is simple, and the process efficiency is improved.
In this embodiment, the single-sided texturing can reduce the overall thinning amount of the semiconductor substrate layer, and the single-sided texturing can reduce the overall thinning amount by 50% to 70%.
Example 2:
another embodiment of the present invention further provides a method for manufacturing a heterojunction battery, which is described in detail below with reference to fig. 10 to 11.
Referring to fig. 10, fig. 10 is a schematic diagram based on fig. 7, and compared with embodiment 1, in this embodiment, the second doping layer 112 is removed on the basis of removing the second oxide layer 132.
In this embodiment, the second doping layer 112 is removed in the process of removing the second oxide layer 132. Specifically, after the rounding process is performed, the second oxide layer 132 and the second doping layer 112 are removed.
The process for removing the second oxide layer 132 and the second doped layer 112 adopts a wet etching process, specifically, the second oxide layer 132 and the second doped layer 112 are removed by adopting a chain cleaning manner, the chain cleaning manner improves the efficiency of removing the second oxide layer 132 and the second doped layer 112, the adopted etching solution is a mixed solution of hydrofluoric acid (HF) and hydrochloric acid (HCl), the mass percentage concentration of the hydrofluoric acid (HF) is 2% -5%, such as 2%, 3%, 4% or 5%, and the mass percentage concentration of the hydrochloric acid (HCl) is 5% -8%, such as 5%, 6%, 7% or 8%. In the process of removing the protective layer 122 and the second doping layer 112 by adopting a chain cleaning mode, the antireflection suede is positioned above the liquid level of the etching liquid, so that the antireflection suede cannot be immersed in the etching liquid.
Referring to fig. 11, after the texturing process is performed on the front surface of the semiconductor substrate layer 100, a first doped semiconductor layer 141' is formed on the front surface side of the semiconductor substrate layer 100; forming a second doped semiconductor layer 142' on the back side of the semiconductor substrate layer 100 after removing the second oxide layer 132 and the second doped layer 112; wherein the conductivity type of the second doped semiconductor layer 142 'is opposite to the conductivity type of the first doped semiconductor layer 141'.
In this embodiment, the method further includes: after the texturing process is performed and before the first doped semiconductor layer 141' is formed, a first intrinsic semiconductor layer (not specifically shown) is formed on the surface of the front surface side of the semiconductor substrate layer 100; after removing the second oxide layer 132 and the second doping layer 112, and before forming the second doped semiconductor layer 142', a second intrinsic semiconductor layer (not specifically shown) is formed on the back side of the semiconductor substrate layer 100.
In this embodiment, the method further includes: the first transparent conductive film, the second transparent conductive film, the first gate line electrode and the second gate line electrode are formed, and regarding the formation process of these structures, reference is made to the contents of the foregoing embodiments, and details are not described.
In this embodiment, since the second doped layer 112 is also removed, the impurities in the second doped layer 112 are also removed, which is beneficial to maintain better purity of the semiconductor substrate layer 100.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (10)
1. A method of fabricating a heterojunction battery, comprising:
providing a semiconductor substrate layer;
performing corrosion treatment on at least the back surface of the semiconductor substrate layer to enable the back surface of the semiconductor substrate layer to be smooth;
performing corrosion treatment on at least the back surface of the semiconductor substrate layer, and then performing diffusion annealing treatment to form a first doping layer and a second doping layer in the semiconductor substrate layer with partial thickness respectively, wherein the surface of the first doping layer is positioned on the front surface of the semiconductor substrate layer, and the surface of the second doping layer is positioned on the back surface of the semiconductor substrate layer;
after the diffusion annealing treatment is carried out, removing the first doping layer by adopting a single-sided etching process;
and after the first doping layer is removed, performing texturing treatment on the front surface of the semiconductor substrate layer to enable the front surface of the semiconductor substrate layer to be an antireflection suede surface.
2. The preparation method of the heterojunction battery according to claim 1, wherein the corrosion treatment adopts an alkali solution, the alkali solution comprises a KOH solution or a NaOH solution, the concentration of the alkali solution in percentage by mass is 1% -20%, the temperature is 50 ℃ -90 ℃, and the time of the corrosion treatment is 50 seconds-1000 seconds;
preferably, the corrosion treatment further employs an alkali polishing additive, the alkali polishing additive including tetramethylammonium hydroxide, alkyl glycoside, pyrazine or polyethylene glycol;
preferably, the alkali polishing additive has a mass percentage concentration of 1-10%.
3. The method according to claim 1, wherein during the diffusion annealing treatment, a first oxide layer on a surface of the first doped layer on a side facing away from the semiconductor substrate layer and a second oxide layer on a surface of the second doped layer on a side facing away from the semiconductor substrate layer are further formed; the first oxide layer is also removed in the process of removing the first doped layer by adopting a single-sided etching process;
the preparation method of the heterojunction battery further comprises the following steps: removing the second oxide layer after the texturing treatment is carried out on the front side of the semiconductor substrate layer;
preferably, the second oxide layer is removed in a chain type cleaning mode, and in the process of removing the second doped layer in the chain type cleaning mode, the antireflection suede surface is positioned above the liquid level of the etching liquid adopted in the chain type cleaning;
preferably, the method further comprises the following steps: removing the second doping layer in the process of removing the second oxide layer;
preferably, the solid solubility of the first oxide layer to the impurities in the semiconductor substrate layer is greater than the solid solubility of the first doping layer to the impurities in the semiconductor substrate layer, and the solid solubility of the second oxide layer to the impurities in the semiconductor substrate layer is greater than the solid solubility of the second doping layer to the impurities in the semiconductor substrate layer;
preferably, the thickness of the first oxide layer is 0.05 μm to 3 μm, and the thickness of the second oxide layer is 0.05 μm to 3 μm.
4. The method of manufacturing a heterojunction battery according to claim 3, further comprising: after the front surface of the semiconductor substrate layer is subjected to texturing treatment, a first doped semiconductor layer is formed on one side of the front surface of the semiconductor substrate layer; after removing the second oxide layer, forming a second doped semiconductor layer on one side of the back surface of the semiconductor substrate layer; wherein the conductivity type of the second doped semiconductor layer is opposite to the conductivity type of the first doped semiconductor layer;
preferably, the method further comprises the following steps: forming a first intrinsic semiconductor layer on the surface of the front side of the semiconductor substrate layer after the texturing treatment and before the first doped semiconductor layer is formed; and after removing the second oxide layer and before forming the second doped semiconductor layer, forming a second intrinsic semiconductor layer on the back side of the semiconductor substrate layer.
5. The method for preparing the heterojunction cell according to claim 1 or 3, wherein the diffusion annealing treatment is performed in a diffusion furnace, and a gas source used in the diffusion annealing treatment is a phosphorus-containing gas source; the first doping layer and the second doping layer contain phosphorus ions;
preferably, the phosphorus-containing gas source comprises POCl3And O2；
Preferably, the phosphorus-containing gas source further comprises water vapor;
preferably, the phosphorus-containing gas source further comprises H2；
Preferably, the temperature adopted by the diffusion annealing treatment is 600-1200 ℃; the time for the diffusion annealing treatment is 10min-120 min;
preferably, the temperature adopted by the diffusion annealing treatment is 800-900 ℃;
preferably, O is used for the diffusion annealing treatment2The flow rate is 400sccm-1000 sccm;
preferably, the POCl adopted by the diffusion annealing treatment3The flow rate is 400sccm-1000 sccm;
preferably, the diffusion annealing treatment uses H2The flow rate is 400sccm-1000 sccm.
6. The method of claim 1, wherein the step of removing the first doped layer using a single-sided etching process comprises: and removing the first doped layer by adopting a chain type cleaning mode, wherein the second doped layer is exposed above the liquid level of the etching liquid by adopting the chain type cleaning mode in the process of removing the first doped layer by adopting the chain type cleaning mode.
7. The method of manufacturing a heterojunction cell according to claim 1, wherein the conductivity type of the first doped layer is the same as the conductivity type of the semiconductor substrate layer before the diffusion annealing treatment is performed; the conductivity type of the second doping layer is the same as that of the semiconductor substrate layer before the diffusion annealing treatment is carried out;
preferably, before the diffusion annealing treatment, the conductivity type of the semiconductor substrate layer is N-type, the conductivity type of the first doping layer is N-type, and the conductivity type of the second doping layer is N-type;
preferably, the concentration of doping ions in the first doping layer is 1E19atom/cm3-8E21atom/cm3(ii) a The concentration of doped ions in the second doped layer is 1E19atom/cm3-8E21atom/cm3。
8. The method for preparing a heterojunction battery according to claim 1, wherein the texturing treatment adopts an alkaline texturing solution, the alkaline texturing solution comprises a KOH solution or a NaOH solution, the mass percentage concentration of the alkaline texturing solution is 1-5%, the reaction temperature is 50-85 ℃, and the reaction time is 200s, 300s, 400s, 500s, 600s, 700s, 800s or 900 s;
preferably, the wool making treatment further adopts a wool making additive and a selective corrosive agent, wherein the wool making additive comprises hydrolyzed polyacrylonitrile sodium salt, polyamino acid or alkyl ammonium chloride, and the selective corrosive agent comprises tetramethyl sodium hydroxide.
9. The method of claim 1, wherein the back side of the semiconductor substrate layer has a reflectivity of 35% to 60%.
10. The method of claim 3, wherein the thickness of the semiconductor substrate layer after removing the second oxide layer is 50 μm to 170 μm.
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| CN114566568A (en) * | 2022-02-28 | 2022-05-31 | 安徽华晟新能源科技有限公司 | Processing method of semiconductor substrate layer and preparation method of solar cell |
| CN116053358A (en) * | 2023-02-09 | 2023-05-02 | 安徽华晟新能源科技有限公司 | Preparation method of heterojunction battery |
| CN116525717A (en) * | 2023-05-09 | 2023-08-01 | 安徽华晟新能源科技有限公司 | Method for forming semiconductor substrate layer and method for preparing heterojunction battery |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114566568A (en) * | 2022-02-28 | 2022-05-31 | 安徽华晟新能源科技有限公司 | Processing method of semiconductor substrate layer and preparation method of solar cell |
| CN116053358A (en) * | 2023-02-09 | 2023-05-02 | 安徽华晟新能源科技有限公司 | Preparation method of heterojunction battery |
| CN116053358B (en) * | 2023-02-09 | 2024-06-11 | 安徽华晟新能源科技有限公司 | Preparation method of heterojunction battery |
| WO2024164741A1 (en) * | 2023-02-09 | 2024-08-15 | 安徽华晟新能源科技有限公司 | Manufacturing method for heterojunction cell |
| CN116525717A (en) * | 2023-05-09 | 2023-08-01 | 安徽华晟新能源科技有限公司 | Method for forming semiconductor substrate layer and method for preparing heterojunction battery |
| CN116525717B (en) * | 2023-05-09 | 2024-07-09 | 安徽华晟新能源科技有限公司 | Method for forming semiconductor substrate layer and method for preparing heterojunction battery |
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