CN116230798A - High-efficiency heterojunction solar cell and manufacturing method thereof - Google Patents
High-efficiency heterojunction solar cell and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims abstract description 120
- 239000004065 semiconductor Substances 0.000 claims abstract description 85
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 56
- 238000002161 passivation Methods 0.000 claims abstract description 48
- 238000003475 lamination Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 23
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 61
- 229910000077 silane Inorganic materials 0.000 claims description 61
- 238000000034 method Methods 0.000 claims description 54
- 238000000151 deposition Methods 0.000 claims description 48
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 31
- 229910052739 hydrogen Inorganic materials 0.000 claims description 31
- 239000001257 hydrogen Substances 0.000 claims description 31
- 239000012495 reaction gas Substances 0.000 claims description 31
- 239000007789 gas Substances 0.000 claims description 27
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 27
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 26
- 239000005922 Phosphane Substances 0.000 claims description 23
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 23
- 229910000064 phosphane Inorganic materials 0.000 claims description 23
- 230000008021 deposition Effects 0.000 claims description 17
- 239000001569 carbon dioxide Substances 0.000 claims description 16
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 16
- -1 diborane Chemical compound 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 26
- 229910052710 silicon Inorganic materials 0.000 description 26
- 239000010703 silicon Substances 0.000 description 26
- 238000006243 chemical reaction Methods 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 239000002131 composite material Substances 0.000 description 6
- 150000002431 hydrogen Chemical class 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
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Abstract
The invention relates to a manufacturing method of a high-efficiency heterojunction solar cell, which comprises the following steps of forming a first semiconductor film layer with N-type doping or P-type doping on a first passivation layer of a semiconductor substrate subjected to passivation treatment, wherein the specific steps are as follows, step A, forming a first microcrystalline silicon lamination on the first passivation layer of the semiconductor substrate subjected to passivation treatment; and step B, forming a first amorphous silicon layer on the first microcrystalline silicon lamination. The invention aims to provide a high-efficiency heterojunction solar cell and a manufacturing method thereof, wherein the influence of short-circuit current, open-circuit voltage and filling factor of the cell can be simultaneously improved by adopting an N-type semiconductor film layer or/and a P-type semiconductor film layer compounded by a microcrystalline silicon laminated layer and an amorphous silicon layer, and the cell efficiency can be obviously improved.
Description
Technical Field
The invention relates to a high-efficiency heterojunction solar cell and a manufacturing method thereof.
Background
The heterojunction solar cell has the advantages of simple preparation process steps, low process temperature, high power generation quantity, high stability, no attenuation and low cost, and along with continuous technical progress and policy promotion of industry, the heterojunction solar cell has the advantages of cost performance and is possible to replace a crystalline silicon solar cell to become a next generation mainstream photovoltaic cell.
The traditional heterojunction solar cell uses an N-type monocrystalline silicon wafer as a substrate, intrinsic I-layer amorphous silicon passivates the surface of crystalline silicon, a boron-doped P-type amorphous silicon film is used as an emitting layer, and a phosphorus-doped N-type amorphous silicon film forms a back field; the method is used as a core process technology and is very important to the efficiency of the heterojunction solar cell; compared with the doped amorphous silicon film, the doped microcrystalline silicon film has the advantages of higher doping efficiency, high conductivity, low light absorption and the like, and is expected to further improve the battery efficiency when being applied to a heterojunction battery. However, the higher barrier height of the microcrystalline silicon layer from the TCO film reduces the open circuit voltage of the cell and also increases the series resistance of the cell, which can lead to a decrease in cell conversion efficiency.
Disclosure of Invention
The invention aims to provide a high-efficiency heterojunction solar cell and a manufacturing method thereof, wherein the influence of short-circuit current, open-circuit voltage and filling factor of the cell can be simultaneously improved by adopting an N-type semiconductor film layer or/and a P-type semiconductor film layer compounded by a microcrystalline silicon laminated layer and an amorphous silicon layer, and the cell efficiency can be obviously improved.
The aim of the invention is realized by the following technical scheme:
a high-efficiency heterojunction solar cell comprises a semiconductor substrate, a first passivation layer arranged on a first main surface of the semiconductor substrate and a first semiconductor film layer which is arranged on the first passivation layer and has N-type doping or P-type doping; the first semiconductor film layer comprises a first microcrystalline silicon lamination layer arranged on the first passivation layer and a first amorphous silicon layer which is arranged on the first microcrystalline silicon lamination layer and has the same conductive type doping as the first microcrystalline silicon lamination layer.
A method for manufacturing high-efficiency heterojunction solar cell comprises forming a first semiconductor film layer with N-type doping or P-type doping on a first passivation layer of a passivated semiconductor substrate,
step A, forming a first microcrystalline silicon stack on a first passivation layer of a passivated semiconductor substrate;
and step B, forming a first amorphous silicon layer on the first microcrystalline silicon lamination.
Compared with the prior art, the invention has the advantages that:
by designing the doped semiconductor film layer into a composite layer structure, on one hand, the microcrystalline silicon lamination is utilized to improve the optical band gap and doping efficiency of the film, so that the battery obtains high short circuit current and open circuit voltage; on one hand, good contact is formed between the thin doped amorphous silicon layer and the conductive film layer, so that the series resistance is reduced, the filling factor of the battery is improved, and the battery can obtain high conversion efficiency.
Drawings
Fig. 1 is a schematic structural diagram of an embodiment of a high-efficiency heterojunction solar cell provided by the invention.
Fig. 2 is a schematic structural diagram of an embodiment of a high-efficiency heterojunction solar cell provided by the invention.
Fig. 3 is a schematic structural diagram of an embodiment of a high-efficiency heterojunction solar cell provided by the invention.
Fig. 4 is a flowchart of a method for fabricating a high-efficiency heterojunction solar cell according to the present invention.
Fig. 5 is a schematic structural diagram of an embodiment of a high-efficiency heterojunction solar cell provided by the invention.
Detailed Description
A high-efficiency heterojunction solar cell comprises a semiconductor substrate, a first passivation layer arranged on a first main surface of the semiconductor substrate and a first semiconductor film layer which is arranged on the first passivation layer and has N-type doping or P-type doping; the first semiconductor film layer comprises a first microcrystalline silicon lamination layer arranged on the first passivation layer and a first amorphous silicon layer which is arranged on the first microcrystalline silicon lamination layer and has the same conductive type doping as the first microcrystalline silicon lamination layer.
The first microcrystalline silicon lamination comprises a first microcrystalline silicon seed layer, a first microcrystalline silicon oxide layer with N-type doping or P-type doping and a first microcrystalline silicon layer with the same conductive type doping as the first microcrystalline silicon oxide layer, which are sequentially arranged from bottom to top by taking the first passivation layer as a substrate.
When the first semiconductor film layer is doped in an N type, the thickness of the first microcrystalline silicon seed layer is 1-4nm, the thickness of the first microcrystalline silicon oxide layer is 4-8nm, the thickness of the first microcrystalline silicon layer is 1-4nm, and the thickness of the first amorphous silicon layer is 1-4nm;
when the first semiconductor film layer is doped in a P type, the thickness of the first microcrystalline silicon seed layer is 1-4nm, the thickness of the first microcrystalline silicon oxide layer is 2-6nm, the thickness of the first microcrystalline silicon layer is 8-20nm, and the thickness of the first amorphous silicon layer is 1-4nm.
In a specific scheme, the high-efficiency heterojunction solar cell further comprises a second passivation layer arranged on the second main surface of the semiconductor substrate and a second semiconductor film layer which is arranged on the second passivation layer and has different conduction type doping from the first semiconductor film layer; the second semiconductor film layer comprises a second microcrystalline silicon lamination layer arranged on the second passivation layer and a second amorphous silicon layer which is arranged on the second microcrystalline silicon lamination layer and has the same conductive type doping as the second microcrystalline silicon lamination layer.
In a specific aspect, the first passivation layer is only disposed on a portion of the first main surface of the semiconductor substrate; a second passivation layer and a second semiconductor film layer which is arranged on the second passivation layer and has different conduction type doping with the first semiconductor film layer are arranged on the first main surface which is not covered by the first passivation layer; the second semiconductor film layer comprises a second microcrystalline silicon lamination layer arranged on the second passivation layer and a second amorphous silicon layer which is arranged on the second microcrystalline silicon lamination layer and has the same conductive type doping as the second microcrystalline silicon lamination layer.
A method for manufacturing high-efficiency heterojunction solar cell comprises forming a first semiconductor film layer with N-type doping or P-type doping on a first passivation layer of a passivation-treated semiconductor substrate,
step A, forming a first microcrystalline silicon stack on a first passivation layer of a passivated semiconductor substrate;
and step B, forming a first amorphous silicon layer on the first microcrystalline silicon lamination.
The specific procedure of the step A is that a1, a first microcrystalline silicon seed layer is deposited on a first passivation layer of a semiconductor substrate after passivation treatment; a2, depositing a first microcrystalline silicon oxide layer with N-type doping or P-type doping on the first microcrystalline silicon seed layer; a3, depositing a first microcrystalline silicon layer with the same conductive type doping as the first microcrystalline silicon oxide layer on the first microcrystalline silicon oxide layer.
The specific method of the procedure a1 is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane and hydrogen is introduced, and the pressure of the reaction gas is 100-300Pa, so as to deposit a first microcrystalline silicon seed layer.
When the N-type doped first semiconductor film layer is prepared, the specific method of the step a2 is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane, phosphane, hydrogen and carbon dioxide is introduced, the pressure of the reaction gas is 150-500Pa, the ratio of the phosphane to the silane is 1-10%, and the ratio of the carbon dioxide to the silane is 50-100%, so as to deposit the N-type first microcrystalline silicon oxide layer;
when the P-type doped first semiconductor film layer is prepared, the specific method of the step a2 is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane, diborane, hydrogen and carbon dioxide is introduced, the pressure of the reaction gas is 150-500Pa, the ratio of diborane to silane is 0.5% -4%, and the ratio of carbon dioxide to silane is 50% -100%, so as to deposit the P-type first microcrystalline silicon oxide layer.
When preparing the N-type doped first semiconductor film layerThe specific method of the procedure a3 is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane, phosphane and hydrogen is introduced, the pressure of the reaction gas is 150-500Pa, and the deposition power density is 0.08-0.3W/cm 2 The ratio of the phosphane to the silane is 1-10 percent so as to deposit an N-type first microcrystalline silicon layer;
when preparing the P-type doped first semiconductor film layer, the specific method of the procedure a3 is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane, diborane and hydrogen is introduced, the pressure of the reaction gas is 150-500Pa, and the deposition power density is 0.1-0.5W/cm 2 The diborane to silane ratio is 0.5% -4% to deposit a P-type first microcrystalline silicon layer.
When preparing the N-type doped first semiconductor film, the specific method in the step B is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane, phosphane and hydrogen is introduced, the pressure of the reaction gas is 30-150Pa, and the deposition power density is 0.01-0.02W/cm 2 The ratio of phosphane to silane is 1% -10% to deposit an N-type first amorphous silicon layer;
when preparing the P-type doped first semiconductor film layer, the specific method in the step B is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane, diborane and hydrogen is introduced, the pressure of the reaction gas is 30-150Pa, and the deposition power density is 0.01-0.02W/cm 2 The ratio of diborane to silane is 1% -10% to deposit a P-type first amorphous silicon layer.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following detailed description of the present invention will be made with reference to the accompanying drawings and examples. It should be understood that the detailed description is presented by way of example only and is not intended to limit the invention.
As shown in fig. 1, the high-efficiency heterojunction solar cell provided by the invention comprises: the N-type silicon wafer 10 is sequentially arranged on a first intrinsic amorphous silicon layer 20 (namely a first passivation layer), an N-type semiconductor film layer 30 (namely a first semiconductor film layer), a front transparent conductive layer 60-1, a front metal grid line 70-1, a second intrinsic amorphous silicon layer 40 (namely a second passivation layer), a P-type semiconductor film layer 50 (namely a second semiconductor film layer), a back transparent conductive layer 60-2 and a back metal grid line 70-2 on the back of the silicon wafer 10. The N-type semiconductor film layer 30 and/or the P-type semiconductor film layer 50 are of a multi-layer composite structure, and the N-type semiconductor film layer 30 includes an N-sided microcrystalline silicon seed layer 31, an N-type microcrystalline silicon oxide layer 32, an N-type microcrystalline silicon layer 33, and an N-type amorphous silicon layer 34; the P-type semiconductor film 50 includes a P-side microcrystalline silicon seed layer 51, a P-type microcrystalline silicon oxide layer 52, a P-type microcrystalline silicon layer 53, and a P-type amorphous silicon layer 54.
The N-type silicon wafer is a monocrystalline silicon wafer or a polycrystalline silicon wafer.
The thickness of the N-face microcrystalline silicon seed layer 31 is 1-4nm; the thickness of the N-type microcrystalline silicon oxide layer 32 is 4-8nm; the thickness 33 of the N-type microcrystalline silicon layer is 1-4nm; the thickness of the N-type amorphous silicon layer 34 is 1-4nm.
The thickness of the P-surface microcrystalline silicon seed layer 51 is 1-4nm; the thickness of the P-type microcrystalline silicon oxide layer 52 is 2-6nm; the thickness 53 of the P-type microcrystalline silicon layer is 8-20nm; the thickness of the P-type amorphous silicon layer 54 is 1-4nm.
In another embodiment, as shown in fig. 5, a back contact heterojunction solar cell (HBC) includes an N-type monocrystalline silicon wafer 80, a third intrinsic amorphous silicon layer 97 and an anti-reflection layer 98 sequentially stacked on the front surface of the silicon wafer 80, a P-region intrinsic amorphous silicon layer 81 (i.e. a first passivation layer), a P-region semiconductor film (i.e. a first semiconductor film layer including a P-region microcrystalline silicon seed layer 82, a P-type microcrystalline silicon oxide layer 83, a P-type microcrystalline silicon layer 84, a P-type amorphous silicon layer 85), a P-region transparent conductive film layer 93, a P-region metal gate line 94, and an N-region intrinsic amorphous silicon layer 87 (i.e. a second passivation layer), an N-region semiconductor film layer (i.e. a second semiconductor film layer including an N-region microcrystalline silicon seed layer 88, an N-type microcrystalline silicon layer 89, an N-type microcrystalline silicon layer 90, an N-type amorphous silicon layer 91), an N-region transparent conductive layer 92, and an N-region metal gate line 95 sequentially stacked on the surface of the N-region of the back surface of the silicon wafer. At the junction between the N region and the P region, the N region intrinsic amorphous silicon layer 87 (i.e., the second passivation layer) and the N region semiconductor film layer are stacked on the P region semiconductor film layer through the insulating film layer 86, and an insulating trench 96 is provided between the P region transparent conductive film layer 93 and the N region transparent conductive layer 92 for separation.
As shown in fig. 1 and 4, the method for manufacturing the high-efficiency heterojunction solar cell comprises the following steps:
s01, providing an N-type silicon wafer which is subjected to texturing and cleaning;
s02, depositing a second intrinsic amorphous silicon layer on the back surface of the silicon wafer by PECVD;
s03, depositing a first intrinsic amorphous silicon layer on the front side of the silicon wafer by PECVD;
s04, depositing an N-type semiconductor film layer on the first intrinsic amorphous silicon layer on the front surface of the silicon wafer through PECVD; specifically, an N-type doped layer is deposited or an N-face seed layer, an N-type microcrystalline silicon oxide layer, an N-type microcrystalline silicon layer and an N-type amorphous silicon layer are sequentially deposited to form an N-type semiconductor film layer 30 with a multi-layer composite structure;
s05, depositing a P-type semiconductor film layer on the second intrinsic amorphous silicon layer on the back of the silicon wafer by PECVD; specifically, a P-type doped layer is deposited or a P-face microcrystalline silicon seed layer, a P-type microcrystalline silicon oxide layer, a P-type microcrystalline silicon layer and a P-type amorphous silicon layer are sequentially deposited to form a P-type semiconductor film layer 50 with a multilayer composite structure;
s06, depositing a front transparent conducting layer 60-1 on the front side of the silicon wafer and depositing a back transparent conducting layer 60-2 on the back side of the silicon wafer by PVD magnetron sputtering;
s07, manufacturing a front metal grid line 70-1 and a back metal grid line 70-2 on the front side and the back side of the silicon wafer respectively;
the process of depositing the N-face microcrystalline silicon seed layer in the step S04 and the process of depositing the P-face microcrystalline silicon seed layer in the step S05 are to introduce mixed gas of silane and hydrogen, and the pressure of the reaction gas is 100-300Pa.
The process of depositing the N-type microcrystalline silicon oxide layer in the step S04 comprises the steps of introducing mixed gas of silane, phosphane, hydrogen and carbon dioxide, wherein the pressure of the reaction gas is 150-500Pa, the ratio of the phosphane to the silane is 1% -10%, and the ratio of the carbon dioxide to the silane is 50% -100%.
The process for depositing the N-type microcrystalline silicon layer in the step S04 comprises the steps of introducing mixed gas of silane, phosphane and hydrogen, wherein the pressure of the reaction gas is 150-500Pa, and the deposition power density is 0.08-0.3W/cm 2 The ratio of phosphane to silane is 1% -10%;
the process for depositing the N-type amorphous silicon layer in the step S04 comprises the steps of introducing mixed gas of silane, phosphane and hydrogen, wherein the pressure of the reaction gas is 30-150Pa, and the deposition power density is 0.01-0.02W/cm 2 The ratio of phosphane to silane is 1% -10%.
The PECVD preset film forming temperature in the step S04 is 150-250 ℃.
The process of depositing the P-type microcrystalline silicon oxide layer in the step S05 comprises the steps of presetting the PECVD film forming temperature to be 150-250 ℃, then introducing mixed gas of silane, diborane, hydrogen and carbon dioxide, wherein the pressure of the reaction gas is 150-500Pa, the ratio of diborane to silane is 0.5% -4%, and the ratio of carbon dioxide to silane is 50% -100%.
The process for depositing the P-type microcrystalline silicon layer in the step S05 comprises the steps of presetting the PECVD film forming temperature to be 150-250 ℃, then introducing mixed gas of silane, diborane and hydrogen, wherein the pressure of the reaction gas is 150-500Pa, and the deposition power density is 0.1-0.5W/cm 2 The ratio of diborane to silane is 0.5% -4%.
The process for depositing the P-type amorphous silicon layer in the step S05 is to introduce mixed gas of silane, diborane and hydrogen, the pressure of the reaction gas is 30-150Pa, and the deposition power density is 0.01-0.02W/cm 2 The ratio of diborane to silane is 1% -10%.
Example 1
The manufacturing method of the high-efficiency heterojunction solar cell (shown in figure 1) comprises the following specific processes:
s01, providing an N-type silicon wafer 10 which is subjected to texturing and cleaning; the specific process is that the surface of the N-type silicon wafer 10 is formed with pyramid suede by a velvet making and cleaning mode, and the surface is kept clean; the N-type silicon wafer 10 is a monocrystalline silicon wafer.
S02, depositing a second intrinsic amorphous silicon layer 40 on the back surface of the silicon wafer 10 after the treatment of S01 by PECVD; the specific process is that silane and hydrogen are introduced into a reaction cavity; the preset film forming temperature is 150-250 ℃; the pressure of the reaction gas is 30-150Pa; the deposition thickness is 5-10nm.
S03, depositing a first intrinsic amorphous silicon layer 20 on the front surface of the silicon wafer 10 processed by the S02 through PECVD; the specific process is that silane and hydrogen are introduced into a reaction cavity; the preset film forming temperature is 150-250 ℃; the pressure of the reaction gas is 30-150Pa; the deposition thickness is 4-7nm.
S04, sequentially depositing an N-face microcrystalline silicon seed layer 31, an N-type microcrystalline silicon oxide layer 32, an N-type microcrystalline silicon layer 33 and an N-type amorphous silicon layer 34 on the first intrinsic amorphous silicon layer 20 on the front face of the silicon wafer 10 after the treatment of S03 by PECVD to form a multi-layer composite structure N-type doped layer; the specific process is that the preset film forming temperature is 150-250 ℃; firstly, introducing mixed gas of silane and hydrogen into a reaction cavity, wherein the pressure of the reaction gas is 100-300Pa, and depositing a first layer serving as an N-face microcrystalline silicon seed layer 31, and the thickness of the first layer is 1-4nm; then, introducing mixed gas of silane, phosphane, hydrogen and carbon dioxide into a reaction cavity, wherein the ratio of the phosphane to the silane is 1-10%, the ratio of the carbon dioxide to the silane is 50-100%, the pressure of the reaction gas is 150-500Pa, and depositing a second layer of N-type microcrystalline silicon oxide layer 32 with the thickness of 4-8nm; finally, introducing mixed gas of silane, phosphane and hydrogen into the reaction cavity, wherein the ratio of the phosphane to the silane is 1-10%, the pressure of the reaction gas is 150-500Pa, and the third layer is deposited as an N-type microcrystalline silicon layer 33, and the thickness of the N-type microcrystalline silicon layer is 1-4nm; depositing a fourth layer which is an N-type amorphous silicon layer 34, wherein the thickness of the fourth layer is 1-4nm;
s05, depositing a P-surface microcrystalline silicon seed layer 51, a P-type microcrystalline silicon oxide layer 52, a P-type microcrystalline silicon layer 53 and a P-type amorphous silicon layer 54 on the second intrinsic amorphous silicon layer on the back surface of the silicon wafer 10 after the treatment of S04 by PECVD to form a P-type doped layer with a multilayer composite structure; the specific process is that the preset film forming temperature is 150-250 ℃; firstly, introducing mixed gas of silane and hydrogen into a reaction cavity, wherein the pressure of the reaction gas is 100-300Pa, and depositing a first layer serving as a P-plane microcrystalline silicon seed layer 51, wherein the thickness of the first layer is 1-4nm; then, introducing mixed gas of silane, diborane, hydrogen and carbon dioxide into a reaction cavity, wherein the ratio of diborane to silane is 0.5% -4%, the ratio of carbon dioxide to silane is 50% -100%, the pressure of reaction gas is 150-500Pa, and the second layer is a P-type microcrystalline silicon oxide layer 52, and the thickness of the second layer is 2-6nm; finally, introducing mixed gas of silane, diborane and hydrogen into a reaction cavity, wherein the ratio of diborane to silane is 0.5% -4%, the pressure of the reaction gas is 150-500Pa, and the third layer is a P-type microcrystalline silicon layer 53, and the thickness of the third layer is 8-20nm; depositing a fourth layer which is a P-type amorphous silicon layer 54 with the thickness of 1-4nm;
s06, depositing a front transparent conductive layer 60-1 (ITO) on the front surface of the silicon wafer 10 processed by the S05 through PVD magnetron sputtering, and depositing a back transparent conductive layer 60-2 (ITO) on the back surface of the silicon wafer 10 processed by the S05 through PVD magnetron sputtering; the deposition thickness is 90-110nm.
S07, manufacturing a front metal grid line 70-1 (silver grid) on the front transparent conductive layer 60-1 of the silicon wafer 10 after the treatment of S06 through screen printing, and manufacturing a back metal grid line 70-2 (silver grid) on the back transparent conductive layer 60-2 of the silicon wafer 10 through screen printing.
Example 2
The specific process differs from that of example 1 only in the method for fabricating a high-efficiency heterojunction solar cell (as shown in fig. 2):
s05, depositing a P-type semiconductor film layer 50 on the second intrinsic amorphous silicon layer 40 on the back of the silicon wafer after the treatment of S04 by PECVD; the specific process is that diborane, silane and hydrogen are introduced into a reaction cavity; the preset film forming temperature is 150-250 ℃; the pressure of the reaction gas is 30-150Pa; the deposition thickness is 6-14nm.
Example 3
The specific process differs from that of example 1 only in the method for fabricating a high-efficiency heterojunction solar cell (as shown in fig. 3):
s04, depositing an N-type semiconductor film layer 30 on the first intrinsic amorphous silicon layer 20 on the front surface of the silicon wafer after the treatment of S03 through PECVD; the specific process is that phosphane, silane and hydrogen are introduced into a reaction cavity; the preset film forming temperature is 150-250 ℃; the pressure of the reaction gas is 30-150Pa; the deposition thickness is 4-7nm.
Table 1 shows the efficiency comparison of the heterojunction solar cell provided by the present invention and the conventional heterojunction solar cell, and the results show that the heterojunction solar cell provided by the present invention is more excellent in electrical performance, and is specifically shown as follows:
Claims (11)
1. the utility model provides a high-efficient heterojunction solar cell which characterized in that: the semiconductor device comprises a semiconductor substrate, a first passivation layer arranged on a first main surface of the semiconductor substrate, and a first semiconductor film layer which is arranged on the first passivation layer and has N-type doping or P-type doping; the first semiconductor film layer comprises a first microcrystalline silicon lamination layer arranged on the first passivation layer and a first amorphous silicon layer which is arranged on the first microcrystalline silicon lamination layer and has the same conductive type doping as the first microcrystalline silicon lamination layer.
2. The high efficiency heterojunction solar cell of claim 1, wherein: the first microcrystalline silicon lamination comprises a first microcrystalline silicon seed layer, a first microcrystalline silicon oxide layer with N-type doping or P-type doping and a first microcrystalline silicon layer with the same conductive type doping as the first microcrystalline silicon oxide layer, which are sequentially arranged from bottom to top by taking the first passivation layer as a substrate.
3. The high efficiency heterojunction solar cell of claim 2, wherein: when the first semiconductor film layer is doped in an N type, the thickness of the first microcrystalline silicon seed layer is 1-4nm, the thickness of the first microcrystalline silicon oxide layer is 4-8nm, the thickness of the first microcrystalline silicon layer is 1-4nm, and the thickness of the first amorphous silicon layer is 1-4nm;
when the first semiconductor film layer is doped in a P type, the thickness of the first microcrystalline silicon seed layer is 1-4nm, the thickness of the first microcrystalline silicon oxide layer is 2-6nm, the thickness of the first microcrystalline silicon layer is 8-20nm, and the thickness of the first amorphous silicon layer is 1-4nm.
4. A high efficiency heterojunction solar cell as claimed in any one of claims 1 to 3, wherein: the semiconductor device further comprises a second passivation layer arranged on the second main surface of the semiconductor substrate and a second semiconductor film layer which is arranged on the second passivation layer and doped with different conductive types from the first semiconductor film layer; the second semiconductor film layer comprises a second microcrystalline silicon lamination layer arranged on the second passivation layer and a second amorphous silicon layer which is arranged on the second microcrystalline silicon lamination layer and has the same conductive type doping as the second microcrystalline silicon lamination layer.
5. A high efficiency heterojunction solar cell as claimed in claims 1-3, wherein: the first passivation layer is only arranged on a part of the first main surface of the semiconductor substrate; a second passivation layer and a second semiconductor film layer which is arranged on the second passivation layer and has different conduction type doping with the first semiconductor film layer are arranged on the first main surface which is not covered by the first passivation layer; the second semiconductor film layer comprises a second microcrystalline silicon lamination layer arranged on the second passivation layer and a second amorphous silicon layer which is arranged on the second microcrystalline silicon lamination layer and has the same conductive type doping as the second microcrystalline silicon lamination layer.
6. The method for manufacturing a high-efficiency heterojunction solar cell as claimed in any one of claims 1 to 5, wherein: it comprises forming a first semiconductor film layer with N-type doping or P-type doping on a first passivation layer of a passivation-treated semiconductor substrate,
step A, forming a first microcrystalline silicon stack on a first passivation layer of a passivated semiconductor substrate;
and step B, forming a first amorphous silicon layer on the first microcrystalline silicon lamination.
7. The method for manufacturing the high-efficiency heterojunction solar cell as claimed in claim 6, wherein: the specific procedure of the step A is that a1, a first microcrystalline silicon seed layer is deposited on a first passivation layer of a semiconductor substrate after passivation treatment; a2, depositing a first microcrystalline silicon oxide layer with N-type doping or P-type doping on the first microcrystalline silicon seed layer; a3, depositing a first microcrystalline silicon layer with the same conductive type doping as the first microcrystalline silicon oxide layer on the first microcrystalline silicon oxide layer.
8. The method for manufacturing the high-efficiency heterojunction solar cell as claimed in claim 7, wherein: the specific method of the procedure a1 is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane and hydrogen is introduced, and the pressure of the reaction gas is 100-300Pa, so as to deposit a first microcrystalline silicon seed layer.
9. The method for manufacturing the high-efficiency heterojunction solar cell as claimed in claim 7, wherein: when the N-type doped first semiconductor film layer is prepared, the specific method of the step a2 is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane, phosphane, hydrogen and carbon dioxide is introduced, the pressure of the reaction gas is 150-500Pa, the ratio of the phosphane to the silane is 1-10%, and the ratio of the carbon dioxide to the silane is 50-100%, so as to deposit the N-type first microcrystalline silicon oxide layer;
when the P-type doped first semiconductor film layer is prepared, the specific method of the step a2 is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane, diborane, hydrogen and carbon dioxide is introduced, the pressure of the reaction gas is 150-500Pa, the ratio of diborane to silane is 0.5% -4%, and the ratio of carbon dioxide to silane is 50% -100%, so as to deposit the P-type first microcrystalline silicon oxide layer.
10. The method for manufacturing the high-efficiency heterojunction solar cell as claimed in claim 7, wherein: when preparing the N-type doped first semiconductor film layer, the specific method of the step a3 is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane, phosphane and hydrogen is introduced, the pressure of the reaction gas is 150-500Pa, and the deposition power density is 0.08-0.3W/cm 2 The ratio of the phosphane to the silane is 1-10 percent so as to deposit an N-type first microcrystalline silicon layer;
when preparing the P-type doped first semiconductor film layer, the specific method of the procedure a3 is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane, diborane and hydrogen is introduced, the pressure of the reaction gas is 150-500Pa, and the deposition power density is 0.1-0.5W/cm 2 The diborane to silane ratio is 0.5% -4% to deposit a P-type first microcrystalline silicon layer.
11. The method for manufacturing the high-efficiency heterojunction solar cell as claimed in claim 7, wherein: when makingWhen preparing the N-type doped first semiconductor film layer, the specific method in the step B is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane, phosphane and hydrogen is introduced, the pressure of the reaction gas is 30-150Pa, and the deposition power density is 0.01-0.02W/cm 2 The ratio of phosphane to silane is 1% -10% to deposit an N-type first amorphous silicon layer;
when preparing the P-type doped first semiconductor film layer, the specific method in the step B is that the PECVD film forming temperature is preset to be 150-250 ℃, then the mixed gas of silane, diborane and hydrogen is introduced, the pressure of the reaction gas is 30-150Pa, and the deposition power density is 0.01-0.02W/cm 2 The ratio of diborane to silane is 1% -10% to deposit a P-type first amorphous silicon layer.
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| CN117241600A (en) * | 2023-11-14 | 2023-12-15 | 无锡华晟光伏科技有限公司 | Three-junction laminated battery and preparation method thereof |
| CN117577697A (en) * | 2024-01-16 | 2024-02-20 | 金阳(泉州)新能源科技有限公司 | Back contact battery with specific front passivation structure and preparation method and application thereof |
| CN117577697B (en) * | 2024-01-16 | 2024-05-03 | 金阳(泉州)新能源科技有限公司 | Back contact battery with specific front passivation structure and preparation method and application thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117241600A (en) * | 2023-11-14 | 2023-12-15 | 无锡华晟光伏科技有限公司 | Three-junction laminated battery and preparation method thereof |
| CN117577697A (en) * | 2024-01-16 | 2024-02-20 | 金阳(泉州)新能源科技有限公司 | Back contact battery with specific front passivation structure and preparation method and application thereof |
| CN117577697B (en) * | 2024-01-16 | 2024-05-03 | 金阳(泉州)新能源科技有限公司 | Back contact battery with specific front passivation structure and preparation method and application thereof |
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