CN111463306A - Novel heterojunction battery and preparation method thereof - Google Patents
Novel heterojunction battery and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a novel heterojunction battery, comprising: the solar cell comprises a silicon layer substrate, a first intrinsic amorphous silicon layer, a second intrinsic amorphous silicon layer, a first doping layer, a first TCO layer and a first metal grid line, wherein the first doping layer, the first TCO layer and the first metal grid line are sequentially arranged on the front surface of the first intrinsic amorphous silicon layer; the first doping layer comprises a heavily doped layer and a lightly doped layer, and the heavily doped layer and the lightly doped layer are alternately arranged on the front side of the first intrinsic amorphous silicon layer; the heavily doped layer is a heavily doped n-type amorphous silicon layer, and the lightly doped layer comprises a lightly doped n-type amorphous silicon layer and a first silicon nitride layer arranged on the lightly doped n-type amorphous silicon layer; the second doping layer, the second TCO layer and the second metal grid line are sequentially arranged on the back surface of the second intrinsic amorphous silicon layer; the second doped layer is a doped p-type amorphous silicon layer. Therefore, the heterojunction structure battery prepared by adopting the structure of the invention not only can improve the performance of the heterojunction battery, but also can greatly reduce the manufacturing cost of the heterojunction battery.
Description
Technical Field
The invention belongs to the field of solar cell manufacturing, and relates to a novel heterojunction cell and a preparation method thereof.
Background
The essence of the rapid development of the photovoltaic industry chain in recent years is that the technology drives cost reduction and efficiency improvement. At present, the single crystal trend is established, the efficiency improvement progress of the p-type battery is slowed down, and the efficiency of the n-type battery has great improvement potential. Looking forward to the future, we consider the most promising change in the photovoltaic industry to be the switch from p-type cells to n-type cells in the cell segment, where the heterojunction cell becomes the next major tuyere of the industry due to its high efficiency and cost reduction potential. The heterojunction solar cell combines the advantages of a crystalline silicon cell and a thin film cell, has the advantages of simple structure, good temperature characteristic, double-sided power generation and the like, and is one of hot spot directions of a silicon-based solar cell with high conversion efficiency. In 1989, the japan sanyo opened the development of heterojunction cells, and china made a preliminary search for heterojunction cells since 2011 and tried to introduce import equipment for enterprises such as peng, seon, and china electric power. In 2015-2018, mass production pilot lines are established in advance by enterprises such as jin energy, Zhongzhi, Jun stone, Han energy and Tongwei, but cost factors are prevented and mass production is not realized.
The heterojunction solar cell takes an n-type monocrystalline silicon wafer as a substrate, an intrinsic amorphous silicon film and an n-type amorphous silicon layer are sequentially deposited on the front surface of the n-type monocrystalline silicon wafer subjected to texturing cleaning to form a front surface field, and the intrinsic amorphous silicon film and the p-type amorphous silicon layer are sequentially deposited on the back surface of the n-type monocrystalline silicon wafer to form a p-n heterojunction. Depositing transparent conductive oxide films (TCO) on two sides of the doped amorphous silicon thin film, and finally forming metal electrodes on the top layers of the two sides through screen printing to form the heterojunction solar cell with the symmetrical structure. The heterojunction solar cell keeps the core advantage of high efficiency due to the large forbidden bandwidth of the heterostructure, but at present, some technical difficulties, such as light absorption loss of a window layer material, grid line contact loss, high cost and the like, still exist.
In order to solve the problems, the invention provides a novel heterojunction battery, wherein a selective doping mode is adopted for a double-sided doped amorphous silicon layer of the battery, amorphous silicon is divided into a contact area (local heavy doping) and a passivation area according to functions, and a silicon nitride layer and TCO (transparent conducting oxide) stacking mode is adopted; the heterojunction solar cell prepared by the structure can improve the performance of the heterojunction solar cell, can greatly reduce the manufacturing cost of the heterojunction solar cell, and has a far-reaching market development prospect.
Disclosure of Invention
In view of the above, the invention provides a novel heterojunction battery and a preparation method thereof, and the battery prepared by the invention can not only improve the performance of the heterojunction battery, but also greatly reduce the manufacturing cost of the heterojunction battery.
In order to achieve the purpose, the invention adopts the following technical scheme:
a novel heterojunction battery comprising: the silicon wafer comprises a silicon substrate, a first intrinsic amorphous silicon layer arranged on the front surface of the silicon substrate and a second intrinsic amorphous silicon layer arranged on the back surface of the silicon substrate, and is characterized by further comprising:
the first doping layer, the first TCO layer and the first metal grid line are sequentially arranged on the front surface of the first intrinsic amorphous silicon layer;
the first doping layer comprises a shallow doping layer, and the shallow doping layer comprises a shallow n-type amorphous silicon layer;
the second doping layer, the second TCO layer and the second metal grid line are sequentially arranged on the back surface of the second intrinsic amorphous silicon layer;
the second doped layer comprises a doped p-type amorphous silicon layer.
Preferably, the first doped layer further comprises: a heavily doped layer; the heavily doped layers and the lightly doped layers are alternately arranged on the front side of the first intrinsic amorphous silicon layer and are both in contact with the first intrinsic amorphous silicon layer; the heavily doped layer is a heavily doped n-type amorphous silicon layer;
the shallow doped layer further comprises: the first silicon nitride layer is arranged on the front surface of the lightly doped n-type amorphous silicon layer.
According to the invention, the doping layer is partitioned into a contact area and a passivation area according to functions, the n-type amorphous silicon has a field passivation effect, so that the contact area adopts local heavy doping, the series resistance generated when the n-type amorphous silicon is in contact with a metal grid line is reduced, the FF is improved, the passivation area adopts shallow doping, a front surface field is formed, and the passivation effect is enhanced; the number of the heavy doping layers and the light doping layers can be set according to actual needs, and the number of the heavy doping layers is at least 1.
Preferably, the second doped layer further comprises: and the doped p-type amorphous silicon layer and the second silicon nitride layer are alternately arranged on the back surface of the second intrinsic amorphous silicon layer and are both in contact with the second intrinsic amorphous silicon layer.
The p-type amorphous silicon can affect the relative position of a Fermi level and a band gap center due to boron doping, the defect density is increased, and therefore the minority carrier lifetime is reduced, partial doping is only carried out on a p surface in a contact area, and the rest is not doped, so that a better passivation effect is guaranteed, the contact resistance of a metal area can be guaranteed, the UOC and the FF reach the maximum balance, the number of the p-type amorphous silicon doped layer and the number of the second silicon nitride doped layer can be set according to the actual situation, and the number of the p-type amorphous silicon doped layers is at least 1.
The novel heterojunction battery structure provided by the invention comprises but is not limited to the structure, and the front surface of the battery structure can be an n surface or a p surface; the heterojunction structure may comprise only n-face or p-face; the silicon nitride layer in the cell structure can be designed as a laminated film for optical matching.
Preferably, the thickness of the lightly doped n-type amorphous silicon layer is 5-10nm, and the doping concentration is less than or equal to 3 percent; the thickness of the heavily doped n-type amorphous silicon layer is 5-10nm, the width of each heavily doped n-type amorphous silicon layer is 20-100 mu m, and the doping concentration is 4-10%.
Preferably, the thickness of the doped p-type amorphous silicon layer is 8-10nm, each width is 20-100 μm, and the doping concentration is 3-10%.
Preferably, the thicknesses of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are both 5-10 nm; the thickness of the first TCO layer and the second TCO layer is 10-50 nm.
Preferably, the first silicon nitride layer and the second silicon nitride layer have a thickness of 40 to 70nm and a refractive index of 2.1 to 2.6.
The silicon nitride layer is used as a window material to replace a part of thickness TCO layer, and the layered laminated film structure design can reduce optical loss, greatly reduce the cost of TCO material, optimize efficiency and greatly reduce the production cost of heterojunction cells.
Preferably, the first metal grid line corresponds to the position of the heavily doped layer.
Preferably, the second metal gate line corresponds to the doped p-type amorphous silicon layer.
Preferably, the silicon layer substrate is an n-type monocrystalline silicon wafer.
The preparation method of the novel heterojunction battery comprises the following steps:
s1: texturing and cleaning the silicon layer substrate to form a double-sided textured structure;
s2: depositing a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on the front surface and the back surface of the silicon layer substrate respectively; depositing a lightly doped n-type amorphous silicon layer on the front surface of the first intrinsic amorphous layer;
s3: depositing a first silicon nitride layer on the front surface of the lightly doped n-type amorphous silicon layer;
s4: etching the first silicon nitride layer subjected to the step S3 in a mask mode by using a 3-10% HF solution in a partition mode, removing the first silicon nitride layer in the area which is not subjected to mask protection by etching, removing the mask glue by using a 1-5% KOH solution, and depositing a heavily-doped n-type amorphous silicon layer in the etched area;
s5: performing first TCO layer deposition on the front side of the lightly doped n-type amorphous silicon layer after S2 is completed, or performing first TCO layer deposition on the front sides of the heavily doped n-type amorphous silicon layer and the first silicon nitride layer after S4 is completed;
s6: depositing a second silicon nitride layer or a doped p-type amorphous silicon layer on the back of the second intrinsic amorphous silicon layer where the step of S5 is completed;
s7: etching the back surface of the second silicon nitride layer deposited in the step S6 in a mask mode by using a 3-10% HF solution in a partition mode, removing the second silicon nitride layer in the area which is not subjected to mask protection by etching, removing the mask glue by using a 1-5% KOH solution, and depositing a doped p-type amorphous silicon layer in the etched area;
s8: performing second TCO layer deposition on the back of the doped p-type amorphous silicon layer after the step S6, or performing second TCO layer deposition on the back of the doped p-type amorphous silicon layer and the back of the second silicon nitride layer after the step S7;
s9: and respectively carrying out metal grid line printing on the front surface of the first TCO layer and the back surface of the second TCO layer after the step S8 is finished, and thus obtaining the novel heterojunction battery.
In the preparation process, HF can not corrode the n-type lightly doped amorphous silicon layer and the second intrinsic amorphous silicon layer, but the mask needs to be removed by KOH, and the n-type lightly doped amorphous silicon layer and the p-surface intrinsic amorphous silicon layer can be removed in the process of removing the mask by KOH, so that the heavily doped layer only comprises the heavily doped n-type amorphous silicon layer.
Compared with the prior art, the invention has the following beneficial effects: after the structure is adopted, the battery double-sided doped amorphous silicon layer adopts a selective doping mode, amorphous silicon is divided into a contact region (local heavy doping) and a passivation region according to functions, the passivation region has higher passivation performance through a process regulation and control mode, and the contact resistance of a grid line can be reduced due to heavy doping in the contact region; the TCO adopts a silicon nitride and TCO laminated mode, a silicon nitride film with a certain thickness is firstly deposited on the doped amorphous silicon film, then TCO layer deposition is carried out, optical absorption can be improved, and the silicon nitride material replaces the TCO with a certain thickness, so that the production cost of the heterojunction cell can be greatly reduced. Therefore, the heterojunction structure battery prepared by adopting the structure of the invention not only can improve the performance of the heterojunction battery, but also can greatly reduce the manufacturing cost of the heterojunction battery.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic diagram of the structure of a novel heterojunction cell of the present invention;
fig. 2 is a schematic structural diagram of a novel heterojunction cell according to example 4 of the present invention;
fig. 3 is a schematic structural view of a novel heterojunction cell according to example 5 of the present invention;
fig. 4 is a schematic structural view of a comparative example heterojunction cell of the present invention.
Wherein in the figure:
1. a first metal gate line; 2. a first TCO layer; 3. a first silicon nitride layer; 4. heavily doped n-type amorphous silicon layer; 5. a lightly doped n-type amorphous silicon layer; 6. a first intrinsic amorphous silicon layer; 7. a silicon layer substrate; 8. a second intrinsic amorphous silicon layer; 9. doping a p-type amorphous silicon layer; 10. a second silicon nitride layer; 11. a second TCO layer; 12. and a second metal gate line.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 2, a novel heterojunction cell comprises: a silicon layer substrate 7, a first intrinsic amorphous silicon layer 6 disposed on the front surface of the silicon layer substrate 7, and a second intrinsic amorphous silicon layer 8 disposed on the back surface of the silicon layer substrate 7, further comprising:
the first doping layer, the first TCO layer 2 and the first metal grid line 1 are sequentially arranged on the front surface of the first intrinsic amorphous silicon layer 6; the first doping layer comprises a heavily doped layer and a lightly doped layer, the heavily doped layer and the lightly doped layer are alternately arranged on the front side of the first intrinsic amorphous silicon layer 6 and are both in contact with the first intrinsic amorphous silicon layer; the heavily doped layer is a heavily doped n-type amorphous silicon layer 4, and the lightly doped layer comprises a lightly doped n-type amorphous silicon layer 5 and a first silicon nitride layer 3 arranged on the front surface of the lightly doped n-type amorphous silicon layer;
the second doping layer, the second TCO layer 11 and the second metal grid line 12 are sequentially arranged on the back surface of the second intrinsic amorphous silicon layer 8; the second doped layer is a doped p-type amorphous silicon layer 9.
Further, another embodiment is included, as shown in fig. 3, the first doped layer is only a lightly doped n-type amorphous silicon layer 5, the second doped layer includes a doped p-type amorphous silicon layer 9 and a second silicon nitride layer 10, and the doped p-type amorphous silicon layer 9 and the second silicon nitride layer 10 are alternately disposed on the back surface of the second intrinsic amorphous silicon layer 8 and are both in contact with the second intrinsic amorphous silicon layer 8.
Further, another embodiment is included, as shown in fig. 1, in which the first doped layer includes a heavily doped layer and a lightly doped layer, and the second doped layer includes a doped p-type amorphous silicon layer 9 and a second silicon nitride layer 10.
Further, the first metal gate line 1 corresponds to the position of the heavily doped layer, and the second metal gate line 12 corresponds to the position of the doped p-type amorphous silicon layer 9.
Example 1
Referring to fig. 1, a novel heterojunction battery is prepared by the following steps:
s1, texturing and cleaning the N-type monocrystalline silicon wafer, texturing the silicon wafer and forming a clean surface, wherein the size of the textured surface is 3 microns;
s2, performing amorphous silicon film deposition on the preorder silicon wafer by using PECVD equipment, and sequentially depositing a first intrinsic amorphous silicon layer (with the thickness of 5nm) and a shallow n-type amorphous silicon layer (with the thickness of 5nm and the doping concentration of 1%) on the front surface; depositing a second intrinsic amorphous silicon layer (thickness 5nm) on the back surface;
s3, depositing a first silicon nitride layer with the deposition thickness of 40nm on the front surface of the lightly n-doped amorphous silicon layer which is subjected to the S2 step by using PECVD equipment; depositing a second silicon nitride layer on the back surface of the second intrinsic amorphous silicon layer, wherein the deposition thickness is 40 nm;
s4, selectively partitioning the first silicon carbide layer after the step S3 by using mask slurry (realized by a screen printing mode), carrying out partition corrosion on the first silicon carbide layer by using HF solution (with the concentration of 3%), wherein the partition corrosion area is 20 microns, removing the mask adhesive by using KOH solution (with the concentration of 2%) after the first silicon nitride layer of the area which is not protected by the mask is corroded and removed, and carrying out heavily-doped n-type amorphous silicon layer deposition on the corroded area; then depositing a first TCO layer on the front surfaces of the first silicon carbide layer and the heavily n-doped amorphous silicon layer, wherein the thickness is 10 nm;
s5, selectively partitioning the second silicon carbide layer after the step S4 by using mask slurry (realized by a screen printing mode), carrying out partition corrosion on the silicon wafer by using HF solution (with the concentration of 3%), wherein the partitioned corrosion region is 20 microns, removing the second silicon nitride layer in the region which is not protected by the mask by corrosion, removing the mask adhesive by using KOH solution (with the concentration of 2%), and depositing a doped p-type amorphous silicon layer (with the thickness of 8nm and the doping concentration of 3%) in the corroded region; then depositing a second TCO layer on the back surfaces of the second silicon nitride layer and the doped p-type amorphous silicon layer, wherein the thickness is 10 nm;
and S6, respectively printing metal grid lines on the front surface of the first TCO layer and the back surface of the second TCO layer after the step S5 is completed, and thus obtaining the novel heterojunction battery.
Example 2
A novel heterojunction battery comprises the following preparation process steps:
s1, texturing and cleaning the N-type monocrystalline silicon wafer, texturing the silicon wafer and forming a clean surface, wherein the size of the textured surface is 3 microns;
s2, performing amorphous silicon film deposition on the preorder silicon wafer by using PECVD equipment, and sequentially depositing a first intrinsic amorphous silicon layer (with the thickness of 10nm) and a shallow n-type amorphous silicon layer (with the thickness of 10nm and the doping concentration of 3%) on the front surface; depositing a second intrinsic amorphous silicon layer (thickness 10nm) on the back surface;
s3, depositing a first silicon nitride layer on the front surface of the lightly doped n-type amorphous silicon layer by using PECVD equipment, wherein the deposition thickness is 70 nm; depositing a second silicon nitride layer on the back surface of the second intrinsic amorphous silicon layer, wherein the deposition thickness is 70 nm;
s4, selectively partitioning the first silicon carbide layer after the step S3 by using mask slurry (realized by a screen printing mode), carrying out partition corrosion on the first silicon carbide layer by using HF solution (with the concentration of 10%), wherein the partition corrosion area is 100 mu m, removing the mask adhesive by using KOH solution (with the concentration of 2%) after the first silicon nitride layer of the area which is not protected by the mask is corroded and removed, and carrying out heavily-doped n-type amorphous silicon layer deposition on the corroded area; then depositing a first TCO layer on the front surfaces of the first silicon carbide layer and the heavily n-doped amorphous silicon layer, wherein the thickness is 50 nm;
s5, selectively partitioning the second silicon carbide layer after the step S4 by using mask slurry (realized by a screen printing mode), carrying out partition corrosion on the silicon wafer by using HF solution (with the concentration of 10%), wherein the partitioned corrosion region is 100 mu m, removing the second silicon nitride layer in the region which is not protected by the mask by corrosion, removing the mask adhesive by using KOH solution (with the concentration of 2%), and depositing a doped p-type amorphous silicon layer (with the thickness of 10nm and the doping concentration of 10%) in the corroded region; then depositing a second TCO layer on the back surfaces of the second silicon nitride layer and the doped p-type amorphous silicon layer, wherein the thickness is 50 nm;
and S6, respectively printing metal grid lines on the front surface of the first TCO layer and the back surface of the second TCO layer after the step S5 is completed, and thus obtaining the novel heterojunction battery.
Example 3
A novel heterojunction battery comprises the following preparation process steps:
s1, texturing and cleaning the N-type monocrystalline silicon wafer, texturing the silicon wafer and forming a clean surface, wherein the size of the textured surface is 3 microns;
s2, performing amorphous silicon film deposition on the preorder silicon wafer by using PECVD equipment, and sequentially depositing a first intrinsic amorphous silicon layer (with the thickness of 8nm) and a shallow n-type amorphous silicon layer (with the thickness of 8nm and the doping concentration of 2%) on the front surface; depositing a second intrinsic amorphous silicon layer (thickness 8nm) on the back surface;
s3, depositing a first silicon nitride layer with the deposition thickness of 70nm on the front surface of the shallow n-doped amorphous silicon layer which is subjected to the step S2 by using PECVD equipment; depositing a second silicon nitride layer on the back surface of the second intrinsic amorphous silicon layer, wherein the deposition thickness is 70 nm;
s4, selectively partitioning the first silicon carbide layer after the step S3 by using mask slurry (realized in a screen printing mode), carrying out partition corrosion on the silicon wafer by using HF solution (with the concentration of 5%), wherein the partition corrosion area is 50 microns, removing the mask adhesive by using KOH solution (with the concentration of 2%) after the first silicon nitride layer of the area which is not protected by the mask is corroded and removed, and carrying out heavily-doped n-type amorphous silicon layer deposition on the corroded area; then depositing a first TCO layer on the front surfaces of the first silicon carbide layer and the heavily n-doped amorphous silicon layer, wherein the thickness is 30 nm;
s5, selectively partitioning the second silicon carbide layer after the step S4 by using mask slurry (realized by a screen printing mode), carrying out partition corrosion on the silicon wafer by using HF solution (with the concentration of 5%), wherein the partition corrosion area is 50 μm, removing the mask adhesive by using KOH solution (with the concentration of 2%) after the second silicon nitride layer of the area which is not protected by the mask is corroded and removed, and depositing a doped p-type amorphous silicon layer (with the thickness of 10nm and the doping concentration of 5%) on the corroded area; then depositing a second TCO layer on the back surfaces of the second silicon nitride layer and the doped p-type amorphous silicon layer, wherein the thickness is 30 nm;
and S6, respectively carrying out metal grid line printing on the front surface of the first TCO layer and the front surface of the second TCO layer after the step S5 is completed to obtain a novel heterojunction battery, and carrying out electrical performance test, wherein the results are shown in Table 1.
Example 4
A cell with a heterojunction front surface adopting a patent technology structure (as shown in figure 2) is prepared by the following steps:
s1, texturing and cleaning the N-type monocrystalline silicon wafer, texturing the silicon wafer and forming a clean surface, wherein the size of the textured surface is 3 microns;
s2, performing amorphous silicon film deposition on the preorder silicon wafer by using PECVD equipment, and sequentially depositing a first intrinsic amorphous silicon layer (with the thickness of 8nm) and a shallow n-type amorphous silicon layer (with the thickness of 8nm and the doping concentration of 2%) on the front surface; depositing a second intrinsic amorphous silicon layer (with the thickness of 8nm) and a doped p-type amorphous silicon layer (with the thickness of 10nm and the doping concentration of 5%) on the back surface in sequence;
s3, depositing a first silicon nitride layer with the deposition thickness of 70nm on the front surface of the shallow n-doped amorphous silicon layer which is subjected to the step S2 by using PECVD equipment;
s4, depositing a second TCO layer on the back surface of the doped p-type amorphous silicon layer after the step S3 by using RPD equipment, wherein the deposition thickness is 100 nm;
s5, selectively partitioning the first silicon carbide layer by using mask slurry (realized by a screen printing mode), and performing partitioned corrosion on the first silicon carbide layer by using an HF solution (with the concentration of 5%), wherein the partitioned corrosion area is 50 μm; heavily doping n-type amorphous silicon in the corrosion area (the thickness is 10mm, the doping concentration is 4%), and depositing a first TCO layer on the front surfaces of the first silicon carbide layer and the heavily doped n-type amorphous silicon layer, wherein the deposition thickness is 30 nm;
s6, performing metal grid line printing (the front grid line printing position is a heavily n-doped amorphous silicon area) on the front side of the first TCO layer and the back side of the second TCO layer after the step S5 is completed by using a screen printing mode, and performing an electrical performance test after drying and curing, wherein the results are shown in Table 1.
Example 5
A cell with a heterojunction back adopting a patent technology structure (as shown in figure 3) is prepared by the following steps:
s1, texturing and cleaning the N-type monocrystalline silicon wafer, texturing the silicon wafer and forming a clean surface, wherein the size of the textured surface is 3 microns;
s2, performing amorphous silicon film deposition on the silicon wafer by using PECVD equipment, and sequentially depositing a first intrinsic amorphous silicon layer (with the thickness of 8nm) and a shallow n-type amorphous silicon layer (with the thickness of 8nm and the doping concentration of 2%) on the front surface; depositing a second intrinsic amorphous silicon layer (thickness 8nm) on the back surface;
s3, depositing a second silicon carbide layer on the back surface of the second intrinsic amorphous silicon layer by using PECVD equipment, wherein the deposition thickness is 70 nm;
s4, depositing a first TCO layer on the front surface of the lightly n-doped amorphous silicon layer by using RPD equipment, wherein the deposition thickness is 100 nm;
s5, selectively partitioning the back of the second silicon carbide layer by using mask slurry (realized in a screen printing mode), carrying out partition corrosion on the second silicon carbide layer by using HF solution (with the concentration of 5%), wherein the partition corrosion area is 50 mu m, carrying out p-type amorphous silicon doping on the corrosion area (with the thickness of 10mm and the doping concentration of 5%), and then carrying out second TCO layer deposition on the doped p-type amorphous silicon and the back of the second silicon carbide layer by using RPD equipment, wherein the deposition thickness is 30 nm;
s6, performing metal gate line printing (the back gate line printing position is a p-type doped amorphous silicon region) on the front side of the first TCO layer and the back side of the second TCO layer by screen printing, and performing electrical performance testing after drying and curing, the results are shown in table 1.
Comparative example
The preparation process of the conventional heterojunction structure battery comprises the following steps:
s1, texturing and cleaning the N-type monocrystalline silicon wafer, texturing the silicon wafer and forming a clean surface, wherein the size of the textured surface is 3 microns;
s2, performing amorphous silicon film deposition on the preorder silicon wafer by using PECVD equipment, and sequentially depositing a first intrinsic amorphous silicon layer (with the thickness of 8nm) and a shallow n-type amorphous silicon layer (with the thickness of 8nm and the doping concentration of 2%) on the front surface; depositing a second intrinsic amorphous silicon layer (with the thickness of 8nm) and a p-type doped amorphous silicon layer (with the thickness of 10nm and the doping concentration of 5%) on the back surface in sequence;
s3, performing a first TCO layer on the front surface of the lightly doped n-type amorphous silicon layer by using RPD equipment, wherein the deposition thickness is 100nm, and performing a second TCO layer on the back surface of the p-type doped amorphous silicon layer, wherein the deposition thickness is 30 nm;
s4, performing metal grid line printing on the front surface of the first TCO layer and the back surface of the second TCO layer by screen printing, drying and curing, and performing electrical performance testing, the results of which are shown in table 1.
Table 1 cell test performance results
| Grouping | Eta | Uoc | Isc | FF | TCO cost reduction |
| Comparative example | 0.00 | 0.000 | 0.000 | 0.0 | 0 |
| Example 4 | 0.16 | 0.000 | 0.020 | 0.40 | -30％ |
| Example 5 | 0.22 | 0.002 | 0.006 | 0.50 | -30％ |
| Example 3 | 0.29 | 0.002 | 0.002 | 0.20 | -60％ |
From the above, the comparative example is used as the B L standard, example 4 has an efficiency improved by 0.16% compared with the comparative example, the front surface adopts a patented structure, the metal contact area of amorphous silicon is heavily doped to effectively improve the FF of the cell, the front surface adopts a silicon nitride and TCO laminated film mode to improve the light utilization rate, thereby improving the Isc of the cell, the consumption of TCO material is reduced due to the introduction of the SiNx layer, the cost of TCO is reduced by 30% compared with example 1, example 5 has an efficiency improved by 0.22% compared with the comparative example, the back surface adopts a patented structure, p-type amorphous silicon is doped only in the metal contact area, the passivation effect is not affected, the Uoc and FF of the cell can be effectively improved, the consumption of TCO material is reduced due to the introduction of the SiNx layer, the cost is reduced by 30% compared with example 1, example 3 combines example 4 with example 5 first, the efficiency is improved by 0.29%, and the cost of TCO is directly reduced by 60%.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A novel heterojunction battery, comprising: the silicon wafer comprises a silicon substrate, a first intrinsic amorphous silicon layer arranged on the front surface of the silicon substrate and a second intrinsic amorphous silicon layer arranged on the back surface of the silicon substrate, and is characterized by further comprising:
the first doping layer, the first TCO layer and the first metal grid line are sequentially arranged on the front surface of the first intrinsic amorphous silicon layer;
the first doping layer comprises a shallow doping layer, and the shallow doping layer comprises a shallow n-type amorphous silicon layer;
the second doping layer, the second TCO layer and the second metal grid line are sequentially arranged on the back surface of the second intrinsic amorphous silicon layer;
the second doped layer comprises a doped p-type amorphous silicon layer.
2. A novel heterojunction cell as in claim 1 wherein said first doped layer further comprises: a heavily doped layer; the heavily doped layers and the lightly doped layers are alternately arranged on the front side of the first intrinsic amorphous silicon layer and are both in contact with the first intrinsic amorphous silicon layer; the heavily doped layer is a heavily doped n-type amorphous silicon layer;
the shallow doped layer further comprises: the first silicon nitride layer is arranged on the front surface of the lightly doped n-type amorphous silicon layer.
3. A novel heterojunction cell as claimed in claim 1 or 2, wherein said second doped layer further comprises: and the doped p-type amorphous silicon layer and the second silicon nitride layer are alternately arranged on the back surface of the second intrinsic amorphous silicon layer and are both in contact with the second intrinsic amorphous silicon layer.
4. The novel heterojunction cell of claim 3, wherein the thickness of the lightly doped n-type amorphous silicon layer is 5-10nm, and the doping concentration is less than or equal to 3%; the thickness of the heavily doped n-type amorphous silicon layer is 5-10nm, the width of each heavily doped n-type amorphous silicon layer is 20-100 mu m, and the doping concentration is 4-10%.
5. A novel heterojunction cell as claimed in claim 3 wherein said doped p-type amorphous silicon layer has a thickness of 8-10nm, a width of 20-100 μm each, and a doping concentration of 3-10%.
6. A novel heterojunction cell as claimed in any of claims 1 to 5 wherein the thickness of each of said first intrinsic amorphous silicon layer and said second intrinsic amorphous silicon layer is 5 to 10 nm; the thickness of the first TCO layer and the second TCO layer is 10-50 nm.
7. A novel heterojunction cell as claimed in claim 3 wherein said first silicon nitride layer and said second silicon nitride layer each have a thickness of 40-70nm and a refractive index of 2.1-2.6.
8. The novel heterojunction cell of claim 3 wherein said first metal grid line corresponds to said heavily doped layer.
9. A novel heterojunction cell as claimed in claim 3, wherein said second metal grid line corresponds to the position of said p-type doped amorphous silicon layer.
10. A preparation method of a novel heterojunction battery is characterized by comprising the following steps:
s1: texturing and cleaning the silicon layer substrate to form a double-sided textured structure;
s2: depositing a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on the front surface and the back surface of the silicon layer substrate respectively; depositing a lightly doped n-type amorphous silicon layer on the front surface of the first intrinsic amorphous layer;
s3: depositing a first silicon nitride layer on the front surface of the lightly doped n-type amorphous silicon layer;
s4: etching the first silicon nitride layer subjected to the step S3 in a mask mode by using a 3-10% HF solution in a partition mode, removing the first silicon nitride layer in the area which is not subjected to mask protection by etching, removing the mask glue by using a 1-5% KOH solution, and depositing a heavily-doped n-type amorphous silicon layer in the etched area;
s5: performing first TCO layer deposition on the front side of the lightly doped n-type amorphous silicon layer after S2 is completed, or performing first TCO layer deposition on the front sides of the heavily doped n-type amorphous silicon layer and the first silicon nitride layer after S4 is completed;
s6: depositing a second silicon nitride layer or a doped p-type amorphous silicon layer on the back of the second intrinsic amorphous silicon layer where the step of S5 is completed;
s7: etching the back surface of the second silicon nitride layer deposited in the step S6 in a mask mode by using a 3-10% HF solution in a partition mode, removing the second silicon nitride layer in the area which is not subjected to mask protection by etching, removing the mask glue by using a 1-5% KOH solution, and depositing a doped p-type amorphous silicon layer in the etched area;
s8: performing second TCO layer deposition on the back of the doped p-type amorphous silicon layer after the step S6, or performing second TCO layer deposition on the back of the doped p-type amorphous silicon layer and the back of the second silicon nitride layer after the step S7;
s9: and respectively carrying out metal grid line printing on the front surface of the first TCO layer and the back surface of the second TCO layer after the step S8 is finished, and thus obtaining the novel heterojunction battery.
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| CN113555469A (en) * | 2021-07-21 | 2021-10-26 | 苏州腾晖光伏技术有限公司 | Back passivation contact structure, preparation method thereof and solar cell |
| CN114335228A (en) * | 2021-12-30 | 2022-04-12 | 中威新能源(成都)有限公司 | Heterojunction solar cell, preparation method thereof and power generation device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113555469A (en) * | 2021-07-21 | 2021-10-26 | 苏州腾晖光伏技术有限公司 | Back passivation contact structure, preparation method thereof and solar cell |
| CN114335228A (en) * | 2021-12-30 | 2022-04-12 | 中威新能源(成都)有限公司 | Heterojunction solar cell, preparation method thereof and power generation device |
| WO2023124048A1 (en) * | 2021-12-30 | 2023-07-06 | 中威新能源(成都)有限公司 | Heterojunction solar cell, preparation method thereof and power generation apparatus |
| CN114335228B (en) * | 2021-12-30 | 2024-03-29 | 通威太阳能（成都）有限公司 | Heterojunction solar cell, preparation method thereof and power generation device |
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