CN105470347A - PERC (PowerEdge RAID Controller) battery manufacturing method - Google Patents
PERC (PowerEdge RAID Controller) battery manufacturing method Download PDFInfo
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- CN105470347A CN105470347A CN201510976235.9A CN201510976235A CN105470347A CN 105470347 A CN105470347 A CN 105470347A CN 201510976235 A CN201510976235 A CN 201510976235A CN 105470347 A CN105470347 A CN 105470347A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 56
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 38
- 239000010703 silicon Substances 0.000 claims abstract description 38
- 238000000137 annealing Methods 0.000 claims abstract description 16
- 238000004140 cleaning Methods 0.000 claims abstract description 5
- 101001073212 Arabidopsis thaliana Peroxidase 33 Proteins 0.000 claims description 45
- 101001123325 Homo sapiens Peroxisome proliferator-activated receptor gamma coactivator 1-beta Proteins 0.000 claims description 45
- 102100028961 Peroxisome proliferator-activated receptor gamma coactivator 1-beta Human genes 0.000 claims description 45
- 238000000151 deposition Methods 0.000 claims description 16
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 9
- 238000007650 screen-printing Methods 0.000 claims description 9
- 210000002268 wool Anatomy 0.000 claims description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 239000004332 silver Substances 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 239000002002 slurry Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 239000010408 film Substances 0.000 abstract description 48
- 238000006243 chemical reaction Methods 0.000 abstract description 9
- 239000010409 thin film Substances 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 2
- 229910052593 corundum Inorganic materials 0.000 abstract 2
- 230000001376 precipitating effect Effects 0.000 abstract 2
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 2
- 229910021419 crystalline silicon Inorganic materials 0.000 abstract 1
- 150000001875 compounds Chemical class 0.000 description 9
- 239000013078 crystal Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 206010042209 Stress Diseases 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The present invention discloses a PERC (PowerEdge RAID Controller) battery manufacturing method. The method comprises: cleaning a silicon wafer and performing surface texturing; performing diffusion to form a p-n junction; manufacturing a passive film on a front surface of the silicon wafer; covering a back surface of the silicon wafer with a mask stencil, and precipitating an Al2O3 thin film by using the mask stencil, and then precipitating an Si3N4 thin film after annealing, and taking down the mask stencil to obtain a slotted passive film pattern; and manufacturing a front electrode and a back electrode. In the method, the back surface of the silicon wafer is covered with the mask stencil, and the Al2O3 thin film is precipitated by using the mask stencil, and the Si3N4 thin film is precipitated after annealing, and the mask stencil is taken down, and the slotted passive film pattern is formed, so that backs of crystalline silicon batteries be in contact with one another locally, furthermore, damage caused by laser slotting can be avoided, combination is reduced, contact resistance is reduced and battery conversion efficiency is improved.
Description
Technical field
The invention belongs to photovoltaic apparatus manufacturing technology field, particularly relate to a kind of manufacture method of PERC battery.
Background technology
It is the single crystal silicon solar cell of 6% that U.S.'s Bell Laboratory in 1954 prepares first piece of conversion efficiency in the world, through scientist's continuous exploration of 60 years, solar cell achieves huge breakthrough, and most high conversion efficiency has reached 46% (light-focusing multi-junction GaAs).Although solar cell develops three generations, crystal silicon solar battery is occuping market main flow still, and how to reduce a great problem that material cost is still photovoltaic industry, therefore the Thickness Design of silicon solar cell is constantly thinning.But, when silicon wafer thickness is as thin as the diffusion length being less than silicon chip, the compound of cell backside will inevitably become the principal element of restriction battery conversion efficiency, and PERC battery (passsivatedemmiterandrearcell, passivation emitter local back contact battery) because of its good back of the body passivating technique, the loss in efficiency that back side compound causes can be reduced, improve open circuit voltage and the short circuit current of battery.
The local back contact of PERC battery of the prior art utilizes picosecond laser to realize back of the body passivating film fluting, lbg has accurate positioning, the advantages such as the little and technique of live width is simple, but also there is following drawback: the photon in laser can damage silicon chip back surface and passivating film, reduce the passivation effect of passivating film overlay area on the one hand, introduce compound, also the compound of no-coverage can be increased on the other hand, also may affect the contact between back electrode and silicon chip simultaneously and improve contact resistance, thus the open circuit voltage of battery and short circuit current are reduced, thus reduction battery conversion efficiency.
Summary of the invention
For solving the problem, the invention provides a kind of manufacture method of PERC battery, the local back contact of crystal silicon battery can be realized, the damage that lbg brings can be avoided again, thus reduce compound, reduce contact resistance, improve battery conversion efficiency.
The manufacture method of a kind of PERC battery provided by the invention, comprising:
Cleaning is carried out and surface wool manufacturing to silicon chip;
Diffuse to form p-n junction;
Passivating film is made in the front of described silicon chip;
At the back side mask film covering half tone of described silicon chip, and utilize described mask half tone depositing Al
2o
3film, deposits Si after annealing again
3n
4film, takes off described mask half tone, forms open flume type passivating film pattern;
Electrode and back electrode before making.
Preferably, in the manufacture method of above-mentioned PERC battery, described depositing Al
2o
3film is:
Utilize ald mode, arranging depositing temperature is 180 DEG C to 220 DEG C, and deposit thickness is the described Al of 4nm to 15nm
2o
3film.
Preferably, in the manufacture method of above-mentioned PERC battery, described deposition Si
3n
4film is:
Utilize plasma enhanced chemical vapor deposition mode, deposit thickness is the described Si of 80nm to 100nm
3n
4film.
Preferably, in the manufacture method of above-mentioned PERC battery, before described annealing, also comprise:
The time arranging described annealing is 20 minutes to 40 minutes, and temperature is 400 DEG C to 500 DEG C.
Preferably, in the manufacture method of above-mentioned PERC battery, described surface wool manufacturing is:
Wet chemical etch process is utilized to prepare 45 ° of positive pyramid mattes.
Preferably, in the manufacture method of above-mentioned PERC battery, described diffuse to form p-n junction after also comprise:
Etching technics is utilized to remove phosphorosilicate glass and the limit knot on surface.
Preferably, in the manufacture method of above-mentioned PERC battery, the described front at described silicon chip makes passivating film and is:
Utilize in the front of described silicon chip plasma enhanced chemical vapor deposition mode deposit ranges of indices of refraction between 2.04 to 2.11, the thickness Si that is 70nm to 80nm
3n
4film.
Preferably, in the manufacture method of above-mentioned PERC battery, before described making, electrode is:
Utilize screen printing mode to print silver paste, make described front electrode.
Preferably, in the manufacture method of above-mentioned PERC battery, described making back electrode is:
Utilize screen printing mode to print aluminum slurry, make described back electrode.
Preferably, in the manufacture method of above-mentioned PERC battery, also comprise after electrode and back electrode before described making:
Described front electrode and described back electrode are sintered.
Known by foregoing description, the manufacture method of above-mentioned PERC battery, due to the back side mask film covering half tone at described silicon chip, and utilizes described mask half tone depositing Al
2o
3film, deposits Si after annealing again
3n
4film, takes off described mask half tone, forms open flume type passivating film pattern, therefore can realize the local back contact of crystal silicon battery, can avoid again the damage that lbg brings, thus reduce compound, reduce contact resistance, improve battery conversion efficiency.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to the accompanying drawing provided.
The schematic diagram of the manufacture method of the first PERC battery that Fig. 1 provides for the embodiment of the present application;
The schematic diagram of the manufacture method of the second PERC battery that Fig. 2 provides for the embodiment of the present application.
Embodiment
Core concept of the present invention is the manufacture method providing a kind of PERC battery, can realize the local back contact of crystal silicon battery, can avoid again the damage that lbg brings, thus reduce compound, reduce contact resistance, improve battery conversion efficiency.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The manufacture method of the first PERC battery that the embodiment of the present application provides as shown in Figure 1, the schematic diagram of the manufacture method of the first PERC battery that Fig. 1 provides for the embodiment of the present application.The method comprises the steps:
S1: cleaning is carried out and surface wool manufacturing to silicon chip;
In this step, silicon chip surface is clean to utilize cleaning to ensure, and surface wool manufacturing can ensure that front side of silicon wafer has enough reflection preventing ability.
S2: diffuse to form p-n junction;
In this step, conventional diffusion technology can be adopted to spread.
S3: make passivating film in the front of described silicon chip;
In this step, form passivating film to protect front.
S4: at the back side mask film covering half tone of described silicon chip, and utilize described mask half tone depositing Al
2o
3film, deposits Si after annealing again
3n
4film, takes off described mask half tone, forms open flume type passivating film pattern;
In this step, mask half tone is utilized can directly to form the passivating film with open flume type pattern.
S5: electrode and back electrode before making.
After this step, just completed PERC battery.
Known by foregoing description, the manufacture method of the first PERC battery that above-described embodiment provides, due to the back side mask film covering half tone at described silicon chip, and utilizes described mask half tone depositing Al
2o
3film, deposits Si after annealing again
3n
4film, takes off described mask half tone, forms open flume type passivating film pattern, therefore can realize the local back contact of crystal silicon battery, can avoid again the damage that lbg brings, thus reduce compound, reduce contact resistance, improve battery conversion efficiency.
In order to enhanced deposition effect, in the step S4 of the manufacture method of the first PERC battery above-mentioned, utilize ald mode, arranging depositing temperature is 180 DEG C to 220 DEG C, and deposit thickness is the described Al of 4nm to 15nm
2o
3film, this temperature range is through the preferable temperature that test of many times draws, and this thickness is also preferred thickness, can obtain the better electrode of electrical property.It should be noted that, this is a preferred implementation, if if do not adopt this preferred implementation in the manufacture method of the first PERC battery in fact above-mentioned, also do not affect the enforcement of its overall plan.
Further, at deposition Si
3n
4during film, also can adopt following optimal way: utilize plasma enhanced chemical vapor deposition mode, deposit thickness is the described Si of 80nm to 100nm
3n
4film.This PECVD mode can the controlled and uniform film of deposit thickness, the electrical property of the electrode finally obtained can be strengthened, certain this mode is also a possibility, if do not adopt this mode also can not affect the concrete enforcement of the manufacture method of the first PERC battery above-mentioned.
In addition, in the manufacture method of the first PERC battery above-mentioned, before the anneal, can also comprise: the time arranging described annealing is 20 minutes to 40 minutes, and temperature is 400 DEG C to 500 DEG C.In depositing Al
2o
3after film, some atoms of this film inside deviate from original position, cause there are some residual stresss, reduce the electric conductivity of electrode, and after this step, add an annealing steps, just can eliminate these residual stresss, ensure that electrode has excellent electric conductivity, and above-mentioned annealing time scope and temperature range be through this Al preferably that test of many times obtains
2o
3the preferred version of Thin-film anneal, but, if if do not adopt this preferred version in the annealing process in the manufacture method of the first PERC battery above-mentioned, do not affect its specific implementation process yet.
Surface wool manufacturing process in above-mentioned four kinds of schemes can adopt following scheme: utilize wet chemical etch process to prepare 45 ° of positive pyramid mattes.This manufacture craft comparative maturity, the anti-reflective effect of the matte of formation is better.Certainly, if do not adopt in this way, the concrete enforcement of the manufacture method of the first PERC battery above-mentioned can't also be affected.
Further, after above-mentioned steps S2, can also comprise the steps: to utilize etching technics to remove phosphorosilicate glass and the limit knot on surface, this makes it possible to avoid producing harmful effect to subsequent step.
And above-mentioned steps S3 can be specially: utilize in the front of described silicon chip plasma enhanced chemical vapor deposition mode deposit ranges of indices of refraction between 2.04 to 2.11, the thickness Si that is 70nm to 80nm
3n
4film.It should be noted that, this is a preferred version in the manufacture method of the first PERC battery above-mentioned, if do not adopt this scheme also can't affect the enforcement of method.
As further preferred version, in above-mentioned steps S5, before described making, electrode can be specially: utilize screen printing mode to print silver paste, make described front electrode.This front electrode adopts silver paste effectively can reduce production cost, and screen printing mode also has the low advantage of cost, certainly this is one of preferred version, other modes can also be adopted, as evaporation or sputtering etc., do not limit here, and, if the first PERC battery production method above-mentioned does not adopt this mode, also concrete enforcement can't be affected.In addition, described making back electrode can be specially: utilize screen printing mode to print aluminum slurry, make described back electrode.This is also a kind of preferred production method of low cost, specifically repeats no more.
Can also comprise after electrode and back electrode before above-mentioned making: described front electrode and described back electrode are sintered, this makes it possible to form good ohmic contact, be conducive to follow-up use.Certainly, this is another preferred version, if the manufacture method of the first PERC battery above-mentioned does not adopt this step, also can't affect follow-up use.
Below the manufacture method of the second PERC battery that the embodiment of the present application provides is described.
The manufacture method of the second PERC battery that the embodiment of the present application provides as shown in Figure 2, the schematic diagram of the manufacture method of the second PERC battery that Fig. 2 provides for the embodiment of the present application.The method comprises the steps:
A1: silicon chip is cleaned and utilizes wet chemical etch process to prepare 45 ° of positive pyramid mattes;
In this step, ripe monocrystalline silicon wafer alkaline flocking technique can be adopted, form 45 degree of positive pyramid mattes.
A2: diffuse to form p-n junction, utilizes etching technics to remove phosphorosilicate glass and the limit knot on surface;
In this step, spread, for p-type silicon substrate in the side with described pyramid matte, n-type area is formed exactly on pyramid, diffusion technology ripe on manufacture of solar cells line can be adopted to realize, and spread rear sheet resistance and be about 95 Ω, junction depth is about 0.3um.
A3: utilize in the front of described silicon chip plasma enhanced chemical vapor deposition mode deposit ranges of indices of refraction between 2.04 to 2.11, the thickness Si that is 70nm to 80nm
3n
4film;
In this step, the Si of formation
3n
4film can adopt the plural layers of gradually changed refractive index, can reduce the light reflection on surface, can play again the effect of surface passivation.
A4: at the back side mask film covering half tone of described silicon chip, and utilize described mask half tone to utilize ald mode, arranging depositing temperature is 180 DEG C to 220 DEG C, and deposit thickness is the described Al of 4nm to 15nm
2o
3film, the time arranging annealing is 20 minutes to 40 minutes, and temperature is 400 DEG C and anneals to 500 DEG C, and then utilizes plasma enhanced chemical vapor deposition mode, and deposit thickness is the described Si of 80nm to 100nm
3n
4film, takes off described mask half tone, forms open flume type passivating film pattern;
In this step, the live width of web plate is relevant with electric conductivity with the doping content at the back side after formation battery with distance between centers of tracks, and such as live width is 50um, and distance between centers of tracks is 100um, and the thickness of web plate should be greater than the thickness of backside passivation film, about 1um.Should close contact between web plate and silicon chip, can not space be left, otherwise can shade be formed, " fluting " passivating film cannot be formed.
A5: utilize screen printing mode to print silver paste, make described front electrode, utilizes screen printing mode to print aluminum slurry, makes described back electrode, sinter described front electrode and described back electrode.
In this step, the modes such as evaporation, sputtering also can be adopted to prepare battery electrode.
Above-described embodiment is by the introducing of web plate mask technique, avoid the damage that cell backside passivating film lbg is introduced, effectively can reduce the compound of battery, improve open circuit voltage and short circuit current, the electrode contact performance of cell backside can be improved again, reduce the series resistance of battery, improve the output current of battery, in addition, mask half tone once drops into and can repeatedly use, the energy loss of laser ablation can be avoided, with low cost, technology is comparatively ripe, live width and the distance between centers of tracks of fluting do not limit by the parameter of experimental facilities laser, arbitrarily can change according to the doping of silicon chip and conductive capability, and do not need to increase additionally to increase main equipment, can be compatible with existing product line, be applicable to industrial large-scale application.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. a manufacture method for PERC battery, is characterized in that, comprising:
Cleaning is carried out and surface wool manufacturing to silicon chip;
Diffuse to form p-n junction;
Passivating film is made in the front of described silicon chip;
At the back side mask film covering half tone of described silicon chip, and utilize described mask half tone depositing Al
2o
3film, deposits Si after annealing again
3n
4film, takes off described mask half tone, forms open flume type passivating film pattern;
Electrode and back electrode before making.
2. the manufacture method of PERC battery according to claim 1, is characterized in that, described depositing Al
2o
3film is:
Utilize ald mode, arranging depositing temperature is 180 DEG C to 220 DEG C, and deposit thickness is the described Al of 4nm to 15nm
2o
3film.
3. the manufacture method of PERC battery according to claim 2, is characterized in that, described deposition Si
3n
4film is:
Utilize plasma enhanced chemical vapor deposition mode, deposit thickness is the described Si of 80nm to 100nm
3n
4film.
4. the manufacture method of PERC battery according to claim 3, is characterized in that, before described annealing, also comprises:
The time arranging described annealing is 20 minutes to 40 minutes, and temperature is 400 DEG C to 500 DEG C.
5. the manufacture method of the PERC battery according to any one of claim 1-4, is characterized in that, described surface wool manufacturing is:
Wet chemical etch process is utilized to prepare 45 ° of positive pyramid mattes.
6. the manufacture method of PERC battery according to claim 5, is characterized in that, described diffuse to form p-n junction after also comprise:
Etching technics is utilized to remove phosphorosilicate glass and the limit knot on surface.
7. the manufacture method of PERC battery according to claim 6, is characterized in that, the described front at described silicon chip makes passivating film and is:
Utilize in the front of described silicon chip plasma enhanced chemical vapor deposition mode deposit ranges of indices of refraction between 2.04 to 2.11, the thickness Si that is 70nm to 80nm
3n
4film.
8. the manufacture method of PERC battery according to claim 7, is characterized in that, before described making, electrode is:
Utilize screen printing mode to print silver paste, make described front electrode.
9. the manufacture method of PERC battery according to claim 8, is characterized in that, described making back electrode is:
Utilize screen printing mode to print aluminum slurry, make described back electrode.
10. the manufacture method of PERC battery according to claim 9, is characterized in that, also comprises before described making after electrode and back electrode:
Described front electrode and described back electrode are sintered.
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| CN201510976235.9A CN105470347A (en) | 2015-12-22 | 2015-12-22 | PERC (PowerEdge RAID Controller) battery manufacturing method |
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| CN201510976235.9A CN105470347A (en) | 2015-12-22 | 2015-12-22 | PERC (PowerEdge RAID Controller) battery manufacturing method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449876A (en) * | 2016-10-17 | 2017-02-22 | 无锡尚德太阳能电力有限公司 | Producing method of selective emitter double-faced PERC crystalline silicon solar cell |
| CN107662401A (en) * | 2016-07-31 | 2018-02-06 | 青岛瑞元鼎泰新能源科技有限公司 | A kind of equipment and technique for printing dereliction grid cell piece front electrode |
| CN109545908A (en) * | 2019-01-14 | 2019-03-29 | 浙江晶科能源有限公司 | A kind of solar cell inactivating mold and the equipment of solar battery production |
| WO2023061151A1 (en) * | 2021-10-13 | 2023-04-20 | 隆基绿能科技股份有限公司 | Solar cell preparation method and solar cell |
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| CN106449876B (en) * | 2016-10-17 | 2017-11-10 | 无锡尚德太阳能电力有限公司 | The preparation method of the two-sided PERC crystal silicon solar energy batteries of selective emitter |
| CN109545908A (en) * | 2019-01-14 | 2019-03-29 | 浙江晶科能源有限公司 | A kind of solar cell inactivating mold and the equipment of solar battery production |
| WO2023061151A1 (en) * | 2021-10-13 | 2023-04-20 | 隆基绿能科技股份有限公司 | Solar cell preparation method and solar cell |
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