CN114613865A - Solar cell and preparation method thereof - Google Patents
Solar cell and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
- H01L31/182—Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1872—Recrystallisation
Abstract
The application provides a solar cell and a preparation method thereof, wherein the solar cell comprises a silicon substrate, a front electrode and a back electrode which are respectively arranged on two sides of the silicon substrate, the silicon substrate is provided with a first part and a second part which are adjacent, the front of the first part is sequentially provided with a tunneling layer and a doped polycrystalline silicon layer in a stacking mode, the front electrode is in contact with the doped polycrystalline silicon layer, and the front of the second part is provided with a doped layer; the back surface of the silicon substrate is sequentially provided with an intrinsic amorphous silicon layer, a doped amorphous layer and a transparent conducting layer in a stacking mode, and the back surface electrode is arranged on the surface of one side, away from the silicon substrate, of the transparent conducting layer. The solar cell and the preparation method thereof can improve the passivation performance of the surface of the cell, reduce the composite loss and the contact resistance of the front electrode position, and simultaneously reduce the absorption loss of incident light, and the doped amorphous layer can also avoid the back high-temperature doping process, reduce the defects possibly caused by high temperature, and prolong the service life of the cell.
Description
Technical Field
The application relates to the technical field of solar power generation, in particular to a solar cell and a preparation method thereof.
Background
With the rapid development of the photovoltaic industry, the efficiency requirements of domestic and foreign markets for solar cells and photovoltaic modules are also continuously increased, which also prompts various manufacturers to actively develop and research high-efficiency cells. For the crystalline silicon battery, the improvement of battery performance and conversion efficiency through the innovation of battery structure and related process is a key issue of continuous attention in the industry.
It is considered in the industry that TOPCon cells and HJT cells are the main technological development routes of crystalline silicon solar cells in the post PERC era. The TOPCon (tunnel Oxide Passivated contact) cell is characterized in that an ultrathin tunneling Oxide layer and a doped polycrystalline silicon layer are prepared on the back surface of the cell to form a passivation contact structure together, so that the surface recombination and the metal recombination of the back surface can be greatly reduced, and the open-circuit voltage Voc and the conversion efficiency of the cell are greatly improved. The Heterojunction (HJT) cell is mainly characterized in that an intrinsic alpha-Si and H layer is deposited on the front surface and the back surface of an n-type silicon wafer, a p-type alpha-Si and H layer and an n-type alpha-Si and H layer are respectively deposited, and then metallization is carried out, so that the Heterojunction (HJT) cell has the advantages of high conversion efficiency, low light attenuation, low temperature coefficient and the like. The film layer structure on the surface of the heterojunction battery absorbs light relatively seriously, and the effective absorption of incident light is influenced; the tunnel layer and the doped polysilicon layer of the TOPCon cell are mostly arranged on the back surface of the cell, the recombination loss and the contact resistance of the front electrode position are large, and when the doped polysilicon layer is used for front passivation, the light absorption effect of the doped polysilicon layer can also influence the absorption and the conversion of incident light, so that the short-circuit current of the cell is reduced.
In view of the above, it is necessary to provide a novel solar cell and a method for manufacturing the same.
Disclosure of Invention
The application aims to provide a solar cell and a preparation method thereof, which can improve the surface passivation performance, reduce the light absorption loss, reduce the defects of the cell and ensure the service life of the cell.
In order to achieve the above object, the present application provides a solar cell, including a silicon substrate, a front electrode and a back electrode respectively disposed on two sides of the silicon substrate, wherein the silicon substrate has a first portion and a second portion adjacent to each other, a tunneling layer and a doped polysilicon layer are sequentially stacked on a front surface of the first portion, the front electrode contacts the doped polysilicon layer, and a doped layer is formed on a front surface of the second portion; the back surface of the silicon substrate is sequentially provided with an intrinsic amorphous silicon layer, a doped amorphous layer and a transparent conducting layer in a stacking mode, and the back surface electrode is arranged on the surface of one side, away from the silicon substrate, of the transparent conducting layer.
As a further development of the application, the front electrode does not extend beyond the doped polysilicon layer.
As a further improvement of the application, the thickness of the doped polycrystalline silicon layer is set to be 60-200 nm; the doping concentration of the doped polycrystalline silicon layer is set to be 1E 20-6E 20cm-3。
As a further improvement of the application, the doping concentration of the doping layer is set to be 5E 18-1E 20cm-3。
As a further improvement of the application, the tunneling layer is set to be a silicon oxide film or a silicon oxynitride film, and the thickness of the tunneling layer is set to be 0.5-3 nm.
As a further improvement of the present application, the solar cell further includes an anti-reflection layer disposed on the doped polysilicon layer and the doped layer, and the front electrode passes through the anti-reflection layer and contacts the doped polysilicon layer; the antireflection layer comprises a first antireflection layer and a second antireflection layer which are stacked, the first antireflection layer is a hydrogen-rich silicon nitride film, the thickness of the first antireflection layer is 3-30 nm, and the refractive index is 2.1-2.4; the second antireflection layer is provided as a silicon nitride film, a silicon oxynitride film, a silicon oxide film, or a composite film composed of at least two of these.
As a further improvement of the application, the thickness of the intrinsic amorphous silicon layer is set to be 5-10 nm.
As a further improvement of the present application, the intrinsic amorphous silicon layer includes a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer stacked on a surface of the first intrinsic amorphous silicon layer facing away from the silicon substrate, and a hydrogen content of the second intrinsic amorphous silicon layer is greater than a hydrogen content of the first intrinsic amorphous silicon layer.
As a further improvement of the application, the thickness of the first intrinsic amorphous silicon layer is set to be 1-3 nm, and the refractive index is set to be 4-4.3; the thickness of the second intrinsic amorphous silicon layer is set to be 3-8 nm, and the refractive index is set to be 3.8-4.1.
As a further improvement of the application, the thickness of the doped amorphous layer is set to be 5-10 nm; and the doping concentration of the doped amorphous layer is 1E 18-5E 20cm-3。
As a further improvement of the present application, the doped amorphous layer includes a first doped amorphous layer and a stacked layer, the first doped amorphous layer deviates from a second doped amorphous layer on one side surface of the silicon substrate, and the doping concentration of the second doped amorphous layer is greater than that of the first doped amorphous layer.
As a further improvement of the application, the thickness of the transparent conducting layer is set to be 70-120 nm.
As a further improvement of the present application, the silicon substrate is an N-type silicon wafer; the doping type of the doping layer is consistent with that of the doping polycrystalline silicon layer, and the doping elements of the doping layer and the doping polycrystalline silicon layer are phosphorus; the doped amorphous layer is a boron doped amorphous layer.
The application also provides a preparation method of the solar cell, which mainly comprises the following steps:
sequentially preparing a tunneling layer and a doped polycrystalline silicon layer on the front side of a silicon substrate, wherein the silicon substrate is provided with a first part and a second part which are adjacent;
removing the doped polycrystalline silicon layer and the tunneling layer on the surface of the second part;
preparing a doped layer on the front surface of the second part;
preparing an antireflection layer on the doping layer and the doped polycrystalline silicon layer;
preparing an intrinsic amorphous silicon layer, a doped amorphous layer and a transparent conducting layer on the back of a silicon substrate in sequence;
grooving in a set area of the antireflection layer;
preparing a front electrode at the grooving position of the antireflection layer;
and preparing a back electrode on the transparent conductive layer.
As a further improvement of the present application, the "notching" refers to removing the anti-reflective layer in a given area by laser etching, so that the doped polysilicon layer is exposed outwards.
As a further improvement of this application, positive electrode and back electrode all adopt low temperature solidification silver thick liquid printing, dry to obtain, and stoving temperature is between 150 ~ 250 ℃.
As a further improvement of the present application, the doped polysilicon layer is made by an ion implantation method; or the like, or a combination thereof,
depositing on the surface of the tunneling layer by adopting an LPCVD method or an HWCVD method, wherein the deposition temperature is set to be 500-700 ℃, and the reaction gas comprises SiH4、PH3、H2In which is SiH4、PH3The flow ratio of the two is set to be 1: 0.1-1: 0.001, SiH4、H2The flow ratio of the two is set to be 1: 10-1: 250.
As a further improvement of the application, the doping layer is prepared by adopting a thermal diffusion method or an ion implantation method, and the doping concentration of the doping layer is controlled to be 5E 18-1E 20cm-3(ii) a And when the preparation of the doped layer is finished, the doping concentration of the doped polycrystalline silicon layer is between 1E20 and 6E20cm-3。
As a further improvement of the present application, the preparation of the intrinsic amorphous silicon layer comprises sequentially depositing a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on the back surface of the silicon substrate, wherein the hydrogen content of the second intrinsic amorphous silicon layer is greater than that of the first intrinsic amorphous silicon layer; the thickness of the first intrinsic amorphous silicon layer is set to be 1-3 nm, and the refractive index is set to be 4-4.3; the thickness of the second intrinsic amorphous silicon layer is set to be 3-8 nm, and the refractive index is set to be 3.8-4.1.
As a further improvement of the application, the thickness of the doped amorphous layer is set to be 5-10 nm; the doping concentration of the doped amorphous layer is 1E 18-5E 20cm-3。
As a further improvement of the present application, the preparation of the doped amorphous layer comprises sequentially depositing a first doped amorphous layer and a second doped amorphous layer on the surface of the intrinsic amorphous silicon layer, wherein the doping concentration of the second doped amorphous layer is greater than that of the first doped amorphous layer; wherein the doping concentration of the first doped amorphous layer is 1E 18-1E 19cm-3(ii) a The doping concentration of the second doped amorphous layer is 1E 19-5E 20cm-3。
As a further improvement of the application, the transparent conducting layer is deposited by a magnetron sputtering method and is obtained by annealing treatment at the temperature of 180-220 ℃.
As a further improvement of the present application, the preparation method further comprises performing light injection or electrical injection treatment after the preparation of the front electrode and the back electrode is completed.
The beneficial effect of this application is: by adopting the solar cell and the preparation method thereof, the surface passivation performance is improved, the recombination loss and the contact resistance of the front electrode position are reduced, the absorption and the conversion of incident light rays are ensured, the back high-temperature doping process can be avoided by the doped amorphous layer, the defects possibly caused by high temperature are reduced, and the service life of the cell is prolonged.
Drawings
FIG. 1 is a schematic structural diagram of a preferred embodiment of a solar cell of the present application;
FIG. 2 is a schematic structural diagram of another preferred embodiment of a solar cell of the present application;
fig. 3 is a schematic main flow chart of a method for manufacturing a solar cell according to the present application.
100-solar cell; 1-a silicon substrate; 11-a doped layer; 2-a tunneling layer; 3-doping a polysilicon layer; 4-an anti-reflection layer; 41-a first anti-reflection layer; 42-a second anti-reflective layer; 5-intrinsic amorphous silicon layer; 51-a first intrinsic amorphous silicon layer; 52-a second intrinsic amorphous silicon layer; 6-doping an amorphous layer; 61-a first doped amorphous layer; 62-a second doped amorphous layer; 7-a transparent conductive layer; 81-front electrode; 82-back electrode.
Detailed Description
The present application will be described in detail below with reference to embodiments shown in the drawings. The present invention is not limited to the above embodiments, and structural, methodological, or functional changes made by one of ordinary skill in the art according to the present embodiments are included in the scope of the present invention.
Referring to fig. 1, a solar cell 100 provided by the present application includes a silicon substrate 1, where the silicon substrate 1 has a first portion and a second portion adjacent to each other, a tunneling layer 2 and a doped polysilicon layer 3 are sequentially stacked on a front surface of the first portion, and a doped layer 11 is formed on a front surface of the second portion; the front surface of the silicon substrate 1 is further provided with an antireflection layer 4 covering the doping layer 11 and the surface of the doped polycrystalline silicon layer 3. The solar cell 100 further comprises an intrinsic amorphous silicon layer 5, a doped amorphous layer 6, a transparent conductive layer 7, a front electrode 81 and a back electrode 82 which are respectively arranged on two sides of the silicon substrate 1, wherein the intrinsic amorphous silicon layer 5, the doped amorphous layer 6 and the transparent conductive layer 7 are sequentially stacked on the back surface of the silicon substrate 1. The front electrode 81 penetrates through the antireflection layer 4 and is in contact with the doped polysilicon layer 3; the rear electrode 82 is arranged on the surface of the transparent conductive layer 7 on the side facing away from the silicon substrate 1.
The first part and the second part respectively correspond to an electrode area and a non-electrode area on the front surface of the silicon substrate 1, and the doped polycrystalline silicon layer 3 is arranged in the electrode area on the front surface of the silicon substrate 1, and the doped layer 11 is adopted in the non-electrode area, so that the light absorption loss of the non-electrode area, namely a light receiving area, can be effectively reduced. Preferably, the front electrode 81 is disposed not to extend beyond the doped polysilicon layer 3, i.e., the front electrode 81 is not in contact with the doped layer 11. The pattern of the doped polysilicon layer 3 is matched with the front electrode 81, and in actual production, the set size of the doped polysilicon layer 3 is usually slightly larger than the size of the front electrode 81 in consideration of the process deviation and the width fluctuation of the front electrode 81 in the preparation process.
The silicon substrate 1 is an N-type silicon wafer, and the resistivity of the silicon substrate 1 is set to be 0.5-7 omega-cm, preferably 1-2 omega-cm. The front side of the silicon substrate 1 is usually subjected to alkali texturing to form a given pyramid textured structure, and the size of the textured structure is set to be 1-5 microns, preferably 2-3 microns.
The tunneling layer 2 is a silicon oxide film or a silicon oxynitride film or a composite film formed by the silicon oxide film and the silicon oxynitride film, the thickness of the tunneling layer 2 is set to be 1-3 nm, and the tunneling layer can be generally prepared by a chemical oxidation method, a thermal oxidation method or an ozone oxidation method. The thickness of the doped polycrystalline silicon layer 3 is set to be 60-200 nm, and preferably set to be 100-150 nm; the doping layer 11 and the doped polysilicon layer 3 have the same doping type and the doping elements of the doping layer 11 and the doped polysilicon layer 3 are phosphorus, the doping layer 11 and the doped polysilicon layer 3 can be regarded as an N + layer arranged on the front surface of the silicon substrate 1, and the solar cell 100 is a back junction cell.
The doping concentration of the doped polycrystalline silicon layer 3 is set to be 1E 20-6E 20cm-3The sheet resistance is 20-100 omega/sq; the doping concentration of the doping layer 11 is set to 5E 18-1E 20cm-3. The doped polysilicon layer 3 is a heavily doped region, and by the design, the contact resistance between the front electrode 81 and the doped polysilicon layer 3 can be further reduced.
The thickness of the intrinsic amorphous silicon layer 5 is set to be 5-10 nm; the doped amorphous layer 6 refers to a doped amorphous silicon film layer or a doped amorphous silicon oxide film layer. The doped amorphous layer 6 is a boron doped amorphous layer, the thickness of the doped amorphous layer 6 is 5-10 nm, and the doping concentration of the doped amorphous layer 6 is 1E 18-5E 20cm-3Preferably, the doping concentration of the doped amorphous layer 6 is 1E 19-1E 20cm-3. The thickness of the transparent conductive layer 7 is set to be 70-120 nm, preferably 90-100 nm, the transparent conductive layer 7 is generally referred to as a transparent conductive oxide film layer, and the transparent conductive layer 7 may be set to be an ITO film layer as an example.
Referring to fig. 2, in order to further improve film performance and battery efficiency, the antireflection layer 4 includes a first antireflection layer 41 and a second antireflection layer 42 which are stacked, the first antireflection layer 41 is a hydrogen-rich silicon nitride film, the thickness of the first antireflection layer is set to be 3 to 30nm, and the refractive index is set to be 2.1 to 2.4; the second antireflection layer 42 is provided as a silicon nitride film, a silicon oxynitride film, a silicon oxide film, or a composite film composed of at least two of them. Moreover, the antireflection layer 4 may also be provided with a gradual film structure, which is not described in detail herein.
The intrinsic amorphous silicon layer 5 comprises a first intrinsic amorphous silicon layer 51 and a second intrinsic amorphous silicon layer 52 stacked on the surface of the first intrinsic amorphous silicon layer 51 on the side away from the silicon substrate 1, and the hydrogen content of the second intrinsic amorphous silicon layer 52 is greater than that of the first intrinsic amorphous silicon layer 51. Specifically, the thickness of the first intrinsic amorphous silicon layer 51 is set to be 1-3 nm, and the refractive index is set to be 4-4.3; the thickness of the second intrinsic amorphous silicon layer 52 is set to be 3-8 nm, and the refractive index is set to be 3.8-4.1. Through the design, better passivation effect can be realized.
The doped amorphous layer 6 comprises a first doped amorphous layer 61 and a second doped amorphous layer 62 stacked on the surface of the first doped amorphous layer 61, which is far away from the silicon substrate 1, wherein the doping concentration of the second doped amorphous layer 62 is greater than that of the first doped amorphous layer 61. The inner low-concentration first doped amorphous layer 61 can effectively reduce recombination at the interface, and the outer high-concentration second doped amorphous layer 62 can form a good contact with the transparent conductive layer.
The solar cell 100 of the present application combines heterojunction cell design and polysilicon passivation technology to effectively control cell production cost and reduce the absorption of front side film layer structure to incident light. The solar cell 100 is designed by the boron-doped amorphous layer, a high-temperature boron diffusion process (950-1050 ℃) is not needed, and the crystal defects which are possibly generated in the high-temperature process are avoided. Furthermore, the front electrode 81 and the back electrode 82 are both prepared by low-temperature solidified silver paste, and high-temperature sintering is not needed; the front electrode 81 may be formed by electroplating a metal material such as copper or nickel.
In particular, the silicon substrate 1 may also be a P-type silicon wafer, the doped polysilicon layer 3 is also set as a phosphorus-doped polysilicon layer, the doped layer 11 is also doped with phosphorus, and corresponding PN junctions are formed between the doped layer 11, the doped polysilicon layer 3 and the silicon substrate 1. The doped amorphous layer 6 is likewise provided as a boron-doped amorphous layer, which serves as a back P + layer and is not described in more detail here.
Referring to fig. 3, the method for manufacturing the solar cell 100 includes:
providing a silicon substrate 1 and carrying out surface treatment on the silicon substrate 1, wherein the silicon substrate 1 is provided with a first part and a second part which are adjacent;
sequentially preparing a tunneling layer 2 and a doped polycrystalline silicon layer 3 on the front side of a silicon substrate 1;
removing the doped polysilicon layer 3 and the tunneling layer 2 on the surface of the second part to expose the silicon substrate 1 of the second part outwards;
preparing and forming a doped layer 11 on the front surface of the second part by adopting a thermal diffusion method or an ion implantation method;
preparing an antireflection layer 4 on the doping layer 11 and the doped polysilicon layer 3;
back cleaning;
preparing an intrinsic amorphous silicon layer 5, a doped amorphous layer 6 and a transparent conducting layer 7 on the back of a silicon substrate 1 in sequence;
grooving in a given area of the antireflection layer 4;
preparing a front electrode 81 at the grooving position of the antireflection layer 4, so that the front electrode 81 penetrates through the antireflection layer 4 and is in contact with the doped polysilicon layer 3;
a back electrode 82 is prepared on the transparent conductive layer 7.
The surface treatment step comprises the steps of firstly carrying out double-sided alkaline texturing on the silicon substrate 1 by using KOH or NaOH or TMAH aqueous solution, and controlling the pyramid height on the surface of the silicon substrate 1 to be 1-5 microns, preferably 2-3 microns. In actual production, a given texturing additive can be added into the solution to improve the texture quality of the silicon substrate 1.
The doped polycrystalline silicon layer 3 is prepared by adopting an ion implantation method; or is obtained by depositing on the surface of the tunneling layer 2 by an LPCVD method or an HWCVD method,the deposition temperature is set to be 500-700 ℃, and the reaction gas comprises SiH4、PH3、H2In which is SiH4、PH3The flow ratio of the two is set to be 1: 0.1-1: 0.001, SiH4、H2The flow ratio of the two is set to be 1: 10-1: 250.
The step of removing the doped polycrystalline silicon layer 3 and the tunneling layer 2 on the surface of the second part comprises the steps of preparing a layer of mask on the doped polycrystalline silicon layer 3 of the first part, and then carrying out secondary texturing on the silicon substrate 1 to enable the front surface of the second part to form a pyramid-shaped crystalline silicon textured surface again.
When the doped layer 11 is prepared, the doping concentration of the doped layer 11 is controlled to be 5E 18-1E 20cm-3(ii) a Moreover, the preparation process of the doped layer 11 is performed for all regions of the front surface of the silicon substrate 1, that is, in the preparation process of the doped layer 11, the doping concentration of the doped polysilicon layer 3 is increased, but the final doping concentration of the doped polysilicon layer 3 is between 1E20 and 6E20cm-3。
The antireflection layer 4 is usually deposited by a PECVD method, and the antireflection layer 4 with a given thickness and refractive index can be obtained by adjusting the process conditions such as the reaction gas flow rate, the deposition temperature and the like. Before the antireflection layer 4 is prepared, the front surface of the silicon substrate 1 needs to be cleaned, and the surface phosphosilicate glass layer needs to be removed.
The back cleaning step can adopt HF and HNO3The mixed solution or the alkali solution of (1) polishes and cleans the back surface of the silicon substrate 1.
The intrinsic amorphous silicon layer 5 and the doped amorphous layer 6 are also prepared by adopting a PECVD method. The preparation of the intrinsic amorphous silicon layer 5 comprises the steps of depositing a first intrinsic amorphous silicon layer 51 and a second intrinsic amorphous silicon layer 52 on the back surface of the silicon substrate 1 in sequence, wherein the hydrogen content of the second intrinsic amorphous silicon layer 52 is greater than that of the first intrinsic amorphous silicon layer 51; the preparation of the doped amorphous layer 6 includes depositing a first doped amorphous layer 61 and a second doped amorphous layer 62 on the surface of the second intrinsic amorphous silicon layer 52 in sequence, wherein the doping concentration of the second doped amorphous layer 62 is greater than that of the first doped amorphous layer 61.
Specifically, silane is used as a gas source in the deposition process of the first intrinsic amorphous silicon layer 51, no hydrogen is introduced, the thickness of the first intrinsic amorphous silicon layer 51 is set to be 1-3 nm, and the refractive index is set to be 4-4.3; the second intrinsic amorphous silicon layer 52 uses silane with high hydrogen dilution ratio as a gas source, and the gas flow ratio is set to SiH4:H2The thickness of the second intrinsic amorphous silicon layer 52 is set to be 3 to 8nm, and the refractive index is set to be 3.8 to 4.1. The doping concentration of the first doped amorphous layer 61 is 1E 18-5E 19cm-3(ii) a The doping concentration of the second doped amorphous layer 62 is 1E 19-5E 20cm-3。
The transparent conducting layer 7 is deposited by adopting a magnetron sputtering method and is obtained by annealing at the temperature of 180-220 ℃, and the annealing temperature is preferably 190-210 ℃.
The "grooving" refers to removing the antireflection layer 4 in a given area by laser etching, so that the doped polysilicon layer 3 is exposed outwards. The antireflection layer 4 can be designed according to the optical effect optimization without considering the burn-through contact problem of the front electrode 81, and the requirement on front metallization is lower. The notching process may preferably employ a laser beam having a shorter wavelength, such as 355nm, to better control the laser beam from etching through the doped polysilicon layer 3.
The front electrode 81 and the back electrode 82 are obtained by printing and drying low-temperature cured silver paste, and the printing position of the front electrode 81 corresponds to the slotting position, so that the low-temperature cured paste is directly contacted with the doped polycrystalline silicon layer 3; the temperature of the drying is usually set to be 150-250 ℃.
In addition, the preparation method further includes performing light injection or electrical injection treatment on the silicon substrate 1 after the preparation of the front electrode 81 and the back electrode 82 is completed, so that internal defects are reduced, and subsequent attenuation is reduced. To further illustrate the electrical performance of the solar cell 100 of the present application, refer to the following table:
| Group | Voc(mV) | Isc(A) | FF(％) | Rs(mΩ) | Rsh(Ω) | EFF(％) |
| example 1 | 726.8 | 9.906 | 83.27 | 1.03 | 2439.8 | 24.35％ |
| Example 2 | 728.8 | 9.912 | 83.31 | 0.92 | 2357.9 | 24.44％ |
| Comparative example 1 | 712.9 | 9.932 | 82.86 | 1.21 | 2427.1 | 23.83％ |
| Comparative example 2 | 737.9 | 9.774 | 83.36 | 0.89 | 2327.1 | 24.42％ |
The difference between the embodiment 1 and the embodiment 2 is that: POCl was used as the doping layer 11 in example 13The gas source is diffused, and the doped polycrystalline silicon layer 3 is grown by adopting an LPCVD method; the doped layer 11 and the doped polysilicon layer 3 in the embodiment 2 are both manufactured by an ion implantation method. Here, comparative example 1 is a TOPCon cell made using an N-type silicon wafer of the same specification; the comparative example 2 is an HJT cell fabricated using an N-type silicon wafer of the same specification, and the structure of the back film layer of the HJT cell is the same as that of the solar cell 100 of the present application. It can be seen that the open-circuit voltage, the fill factor and the conversion efficiency of the solar cell 100 are significantly improved compared to the conventional TOPCon cell; compared with the existing HJT battery, the open-circuit voltage is slightly reduced, but the short-circuit current is improved, and the conversion efficiency of the two is basically equivalent.
In summary, the solar cell 100 and the preparation method thereof improve the passivation performance of the cell surface, reduce the recombination loss and the contact resistance under the front electrode, and ensure the absorption of the incident light on the front of the cell; by reducing high temperature treatment steps, particularly boron diffusion high temperature processes, defects which may evolve in the silicon substrate 1 are reduced, the performance of the battery is improved, and the service life of the battery is prolonged.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above list of details is only for the concrete description of the feasible embodiments of the present application, they are not intended to limit the scope of the present application, and all equivalent embodiments or modifications that do not depart from the technical spirit of the present application are intended to be included within the scope of the present application.
Claims (23)
1. The utility model provides a solar cell, includes the silicon substrate, establishes respectively the front electrode and the back electrode of silicon substrate both sides, the silicon substrate has adjacent first portion and second part, its characterized in that: the front surface of the first part is sequentially provided with a tunneling layer and a doped polycrystalline silicon layer in a stacking mode, the front surface electrode is in contact with the doped polycrystalline silicon layer, and the front surface of the second part is provided with a doped layer; the back surface of the silicon substrate is sequentially provided with an intrinsic amorphous silicon layer, a doped amorphous layer and a transparent conducting layer in a stacking mode, and the back surface electrode is arranged on the surface of one side, away from the silicon substrate, of the transparent conducting layer.
2. The solar cell of claim 1, wherein: the front electrode does not extend beyond the doped polysilicon layer.
3. The solar cell of claim 1, wherein: the thickness of the doped polycrystalline silicon layer is set to be 60-200 nm; the doping concentration of the doped polysilicon layer is set to be 1E 20-6E 20cm-3。
4. The solar cell of claim 1, wherein: the doping concentration of the doping layer is set to be 5E 18-1E 20cm-3。
5. The solar cell of claim 1, wherein: the tunneling layer is set to be a silicon oxide film or a silicon oxynitride film, and the thickness of the tunneling layer is set to be 0.5-3 nm.
6. The solar cell of claim 1, wherein: the solar cell also comprises an antireflection layer arranged on the doped polycrystalline silicon layer and the doped layer, and the front electrode penetrates through the antireflection layer and is in contact with the doped polycrystalline silicon layer; the antireflection layer comprises a first antireflection layer and a second antireflection layer which are stacked, the first antireflection layer is a hydrogen-rich silicon nitride film, the thickness of the first antireflection layer is 3-30 nm, and the refractive index is 2.1-2.4; the second antireflection layer is provided as a silicon nitride film, a silicon oxynitride film, a silicon oxide film, or a composite film composed of at least two of them.
7. The solar cell of claim 1, wherein: the thickness of the intrinsic amorphous silicon layer is set to be 5-10 nm.
8. The solar cell of claim 1, wherein: the intrinsic amorphous silicon layer comprises a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer which is stacked on the surface of one side, away from the silicon substrate, of the first intrinsic amorphous silicon layer, and the hydrogen content of the second intrinsic amorphous silicon layer is larger than that of the first intrinsic amorphous silicon layer.
9. The solar cell of claim 8, wherein: the thickness of the first intrinsic amorphous silicon layer is set to be 1-3 nm, and the refractive index is set to be 4-4.3; the thickness of the second intrinsic amorphous silicon layer is set to be 3-8 nm, and the refractive index is set to be 3.8-4.1.
10. The solar cell of claim 1, wherein: the thickness of the doped amorphous layer is set to be 5-10 nm; and the doping concentration of the doped amorphous layer is 1E 18-5E 20cm-3。
11. The solar cell of claim 1, wherein: the doped amorphous layer comprises a first doped amorphous layer and a second doped amorphous layer which is arranged on the surface of one side, away from the silicon substrate, of the first doped amorphous layer in a stacking mode, and the doping concentration of the second doped amorphous layer is larger than that of the first doped amorphous layer.
12. The solar cell of claim 1, wherein: the thickness of the transparent conducting layer is set to be 70-120 nm.
13. The solar cell of claim 1, wherein: the silicon substrate is an N-type silicon wafer; the doping type of the doping layer is consistent with that of the doping polycrystalline silicon layer, and the doping elements of the doping layer and the doping polycrystalline silicon layer are phosphorus; the doped amorphous layer is a boron doped amorphous layer.
14. A method for manufacturing a solar cell is characterized in that:
sequentially preparing a tunneling layer and a doped polycrystalline silicon layer on the front side of a silicon substrate, wherein the silicon substrate is provided with a first part and a second part which are adjacent;
removing the doped polycrystalline silicon layer and the tunneling layer on the surface of the second part;
preparing a doped layer on the front surface of the second part;
preparing an antireflection layer on the doping layer and the doped polycrystalline silicon layer;
preparing an intrinsic amorphous silicon layer, a doped amorphous layer and a transparent conducting layer on the back of a silicon substrate in sequence;
grooving in a set area of the antireflection layer;
preparing a front electrode at the grooving position of the antireflection layer;
and preparing a back electrode on the transparent conductive layer.
15. The method of claim 14, wherein: the grooving refers to removing the antireflection layer in a set area by laser etching so that the doped polysilicon layer is exposed outwards.
16. The method of claim 14, wherein: the front electrode and the back electrode are obtained by adopting low-temperature curing silver paste printing and drying, and the drying temperature is 150-250 ℃.
17. The method of claim 14, wherein: the doped polycrystalline silicon layer is prepared by adopting an ion implantation method; or the like, or, alternatively,
depositing on the surface of the tunneling layer by adopting an LPCVD method or an HWCVD method, wherein the deposition temperature is set to be 500-700 ℃, and the reaction gas comprises SiH4、PH3、H2In which is SiH4、PH3The flow ratio of the two is set to be 1: 0.1-1: 0.001, SiH4、H2The flow ratio of the two is set to be 1: 10-1: 250.
18. The method of claim 14, wherein: the doping layer is prepared by adopting a thermal diffusion method or an ion implantation method, and the doping concentration of the doping layer is controlled to be 5E 18-1E 20cm-3(ii) a And when the preparation of the doped layer is finished, the doping concentration of the doped polycrystalline silicon layer is between 1E20 and 6E20cm-3。
19. The method of claim 14, wherein: the preparation of the intrinsic amorphous silicon layer comprises the steps of depositing a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer in sequence on the back surface of the silicon substrate, wherein the hydrogen content of the second intrinsic amorphous silicon layer is larger than that of the first intrinsic amorphous silicon layer; the thickness of the first intrinsic amorphous silicon layer is set to be 1-3 nm, and the refractive index is set to be 4-4.3; the thickness of the second intrinsic amorphous silicon layer is set to be 3-8 nm, and the refractive index is set to be 3.8-4.1.
20. The method of claim 14, wherein: the thickness of the doped amorphous layer is set to5-10 nm; the doping concentration of the doped amorphous layer is 1E 18-5E 20cm-3。
21. The production method according to claim 14 or 20, characterized in that: the preparation of the doped amorphous layer comprises the steps of depositing a first doped amorphous layer and a second doped amorphous layer on the surface of the intrinsic amorphous silicon layer in sequence, wherein the doping concentration of the second doped amorphous layer is greater than that of the first doped amorphous layer; wherein the doping concentration of the first doped amorphous layer is 1E 18-1E 19cm-3(ii) a The doping concentration of the second doped amorphous layer is 1E 19-5E 20cm-3。
22. The method of claim 14, wherein: the transparent conducting layer is deposited by a magnetron sputtering method and is obtained by annealing treatment at the temperature of 180-220 ℃.
23. The method of claim 14, wherein: the preparation method also comprises the step of carrying out light injection or electric injection treatment after the preparation of the front electrode and the back electrode is finished.
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