CN111640826A - Preparation method of battery conducting by utilizing selective contact - Google Patents

Abstract

The invention discloses a battery preparation method utilizing selective contact conduction, comprising the steps of: 1) selecting p-type doped or n-type doped crystalline silicon wafers; 2) respectively plating silicon oxide layers on the front and back sides of the silicon wafers ; 3) Phosphorus or boron doped amorphous silicon is plated on the front and back of the silicon wafer, and then annealed and crystallized at high temperature to form doped polysilicon; 4) TCO layers are respectively plated on the front and back of the silicon wafer; 5) On the front and back of the silicon wafer Re-coat the insulating protective layer on the reverse side; 6) Print the silver wire for collecting current on the front and back of the silicon wafer, and the silver wire penetrates the insulating protective layer after sintering to realize contact with the TCO layer. The invention realizes full coverage passivation and effectively avoids the problem of minority carrier recombination affecting conversion efficiency, and silicon oxide passivation realizes high-temperature sintering to effectively ensure the conductivity and adhesion of the silver paste without the problem of absorbing light. Type equipment coating integrates multiple processes into one equipment, which greatly improves work efficiency and reduces equipment investment costs and floor space.

Description

A kind of battery preparation method using selective contact conduction

technical field

The invention relates to the technical field of solar cells, in particular to a cell preparation method utilizing selective contact conduction.

Background technique

Photovoltaic power generation has become a technology that can replace fossil energy, which relies on the continuous reduction of production costs and the improvement of photoelectric conversion efficiency in recent years. According to the material of photovoltaic cells, solar cells can be roughly divided into two categories: one is crystalline silicon solar cells, including monocrystalline silicon solar cells and polycrystalline silicon solar cells; the other is thin film solar cells, mainly including amorphous silicon solar cells , cadmium telluride solar cells and copper indium gallium selenide solar cells. At present, crystalline silicon solar cells with high-purity silicon as the main raw material are the mainstream products, accounting for more than 80%.

In a crystalline silicon solar power generation system, one of the core steps to realize photoelectric conversion is the process of processing crystalline silicon into a cell that realizes photoelectric conversion. Therefore, the photoelectric conversion efficiency of the cell has also become a reflection of the technical level of the crystalline silicon solar power generation system. key indicators.

To improve cell efficiency, establishing passivated contacts is the key. Due to the rapid movement of photo-generated carriers inside the silicon wafer, once they contact the surface, they will recombine and cannot be collected into current to generate electricity. If a special protective film is coated on the surface, such as silicon oxide, silicon nitride, aluminum oxide, amorphous silicon, etc., due to the saturation of chemical bonds on the surface of crystalline silicon and the charge field formed between the film and crystalline silicon, they can effectively prevent Recombination of minority carriers on the surface. The recently developed PERC cell replaces the aluminum back contact with aluminum oxide passivation on the basis of the conventional cell, and then partially opens the window to introduce the conductive contact. The full name of PERC technology is Passivated Emitter Rear Cell technology. Through this kind of back passivation, the battery efficiency can be increased by 1~2% compared with the absolute value of conventional batteries. The preparation of PERC cells has the advantage of being highly compatible with the existing cell production line. Compared with the traditional process, PERC cells only need to add two additional equipment (alumina deposition and laser equipment) to the original conventional production line. Upgrading is relatively low cost, so it has become the mainstream direction of high-efficiency solar cells.

However, since a PERC cell requires a windowed contact, the part of the windowed contact will still lead to minority carrier recombination. And the front silver paste also needs to burn through the silicon nitride layer to make contact with the emitter surface. This contact also causes minority carrier recombination to affect the conversion efficiency.

In order to further improve the efficiency, the new theoretical simulation of the battery requires the full coverage of the passivation layer, and the carriers reach the conductive layer covering the passivation layer through the tunnel penetration effect. HIT battery is a new battery designed based on this concept. The HIT cell is covered with a thin layer of amorphous silicon (3~5 nm) on the front and back of the silicon wafer, and then phosphorous-doped amorphous silicon and boron-doped amorphous silicon are respectively plated on the surface of the amorphous silicon. Due to the excellent passivation performance of amorphous silicon, the conversion efficiency of HIT cells has been greatly improved. Panasonic Corporation of Japan reported a conversion efficiency of more than 25.6%, which is 3% higher than that of PERC cells. However, the amorphous silicon and doped amorphous silicon used in HIT cells have the problem of absorbing light, and only a very thin passivation layer can be placed to control the amount of light absorption, but the doped amorphous silicon is too thin, which will affect its lateral conduction and The ability of electricity to be sent to the silver grid line, therefore, a transparent conductive layer must be placed on its surface. Another disadvantage of amorphous silicon passivation is that it can only withstand low-temperature processes. When the temperature is above 250 °C, the passivation effect of amorphous silicon is immediately lost, which is not suitable for printing silver pastes that are maturely used in conventional batteries. Conventional silver paste needs to be sintered at 800°C to achieve good conductivity and adhesion. To this end, a low-temperature silver paste was specially developed for HIT batteries, but it currently faces the disadvantages of poor conductivity, high dosage, and small surface adhesion.

Another full-coverage passivation technology is polysilicon on the silicon oxide layer. The thickness of the silicon oxide layer is only about 1.5nm. Phosphorus or boron can be doped as needed, especially phosphorus-doped polysilicon on the silicon oxide. Allows electrons to pass through, while boron-doped polysilicon on silicon oxide allows holes to pass through. Such polysilicon selective passivation contact conduction (POLO) is the direction for the development of high-efficiency solar cells. However, it is still difficult to design a battery structure that utilizes selective contact conduction and can be mass-produced at low cost.

SUMMARY OF THE INVENTION

In order to solve the above-mentioned technical problems, the present invention provides a battery preparation method utilizing selective contact conduction, comprising the following steps:

1) Choose p-type doped or n-type doped crystalline silicon wafers as the basis, and the resistivity of p-type doped or n-type doped crystalline silicon wafers is 0.1~10Ω·cm;

2) Coating silicon oxide layers on the front and back surfaces of the silicon wafer in step 1), the coating method is any one of high temperature oxidation, plasma oxidation, PECVD deposition, and atomic layer deposition, and the coating thickness is 1-2 nm;

3) Coating doped amorphous silicon on the silicon oxide layers on the front and back surfaces of the silicon wafer in step 2), wherein one side is plated with phosphorus doped amorphous silicon, and the other side is plated with boron doped amorphous silicon, and the coating method is PVD, Any one of LPCVD and PECVD, preferably a PVD coating method, with a coating thickness of 3 to 20 nm; after coating, annealing and crystallization at a high temperature to form doped polysilicon, and the high-temperature annealing and crystallization temperature is 600-950 ° C. The two sides of the silicon wafer form p+POLO and n+POLO respectively;

4) Coating TCO layers on the front and back doped polysilicon of the silicon wafer in step 3), the coating method is PVD method, and the coating thickness is 30-200 nm; wherein, the TCO layer is any one of ITO, IWO, ICO, and AZO one or more;

5) Re-plating an insulating protective layer on the front and back TCO layers of the silicon wafer in step 4). The insulating protective layer is any one of SiN, SiO ₂ and SiON. The thickness of the insulating protective layer is determined according to the thickness of the TCO and needs to meet the The effect of anti-reflection, that is, the relative thickness of the TCO layer and the insulating protective layer reaches the lowest reflectivity (using the thin film optical effect, by adjusting the thickness and refractive index of the film, the light is not reflected after being irradiated on the surface), and at the same time, it is necessary to ensure that the TCO layer is There is sufficient thickness to meet the requirements of lateral conductivity;

6) The silver wire for collecting current is printed on the insulating protective layer on the front and back of the silicon wafer in step 5). After sintering, the silver wire penetrates the insulating protective layer to realize contact with the TCO layer. The width of the silver wire is 20~100 nm. And under the requirement of electrical conductivity, the narrower the better, the height of the silver wire is 10~20μm; the sintering temperature of the silver wire penetrating the insulating protective layer after sintering is 500~900℃.

After the above steps 1) to 6) are completed, the battery of the present invention utilizing selective contact conduction is formed. On the basis of the battery formed after the process of step 6) is completed, the photoelectric conversion efficiency and the anti-decay capability of the battery are further improved by means of annealing, illumination or electric injection.

Through the above technical solutions, the battery utilizing selective contact conduction provided by the present invention has the following advantages:

1) Compared with the PERC cell, the cell preparation process of the present invention achieves full coverage passivation, thus effectively avoiding the PERC cell due to the need to open the window to cause the minority carrier recombination and the front silver paste to burn through the silicon nitride layer in order to communicate with the emitter. The problem of minority carrier recombination affecting the conversion efficiency due to surface contact;

2) Compared with the HIT battery, the battery preparation process of the present invention uses silicon oxide passivation instead of amorphous silicon, and the silicon oxide passivation layer can withstand high temperature sintering without absorbing light;

3) Compared with the HIT battery, based on the silicon oxide passivation layer, the battery preparation process of the present invention replaces the low temperature silver paste sintering process with conventional high temperature silver paste sintering, which effectively ensures the conductivity of the silver paste and the adhesion on the insulating protective layer. focus;

4) The battery preparation process of the present invention is simple, and multiple processes can be integrated into one device by chain-type equipment coating, thereby greatly improving the preparation efficiency, reducing the equipment input cost and occupying space, and the production cost is low.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below.

Example 1:

The battery preparation method utilizing selective contact conduction provided by the present invention comprises the following steps:

1) Choose p-type doped or n-type doped crystalline silicon wafers as the basis, and the resistivity of p-type doped or n-type doped crystalline silicon wafers is 0.1~10Ω·cm;

2) Coating silicon oxide layers on the front and back surfaces of the silicon wafer in step 1), the coating method is any one of high temperature oxidation, plasma oxidation, PECVD deposition, and atomic layer deposition, and the coating thickness is 1-2 nm;

3) Coating doped amorphous silicon on the silicon oxide layers on the front and back surfaces of the silicon wafer in step 2), wherein one side is plated with phosphorus doped amorphous silicon, and the other side is plated with boron doped amorphous silicon, and the coating method is PVD, Any one of LPCVD and PECVD, preferably a PVD coating method, with a coating thickness of 3 to 20 nm; after coating, annealing and crystallization at a high temperature to form doped polysilicon, and the high-temperature annealing and crystallization temperature is 600-950 ° C. The two sides of the silicon wafer form p+POLO and n+POLO respectively;

4) Coating TCO layers on the front and back doped polysilicon of the silicon wafer in step 3), the coating method is PVD method, and the coating thickness is 30-200 nm; wherein, the TCO layer is any one of ITO, IWO, ICO, and AZO one or more;

5) Re-plating an insulating protective layer on the front and back TCO layers of the silicon wafer in step 4). The insulating protective layer is any one of SiN, SiO ₂ and SiON. The thickness of the insulating protective layer is determined according to the thickness of the TCO and needs to meet the The effect of anti-reflection, that is, the relative thickness of the TCO layer and the insulating protective layer reaches the lowest reflectivity, and at the same time, it is necessary to ensure that the TCO layer has sufficient thickness to meet the requirements of lateral conductivity;

6) The silver wire for collecting current is printed on the insulating protective layer on the front and back of the silicon wafer in step 5). After sintering, the silver wire penetrates the insulating protective layer to realize contact with the TCO layer. The width of the silver wire is 20~100 nm. And under the requirement of electrical conductivity, the narrower the better, the height of the silver wire is 10~20μm; the sintering temperature for the silver wire to penetrate the insulating protective layer after sintering is 500~900°C, and after sintering, the utilization selectivity of the present invention is formed. Contact conductive batteries.

Example 2:

Based on Example 1, on the basis of the battery formed after completing the process of step 6), the photoelectric conversion efficiency and the anti-decay capability of the battery are further improved by means of annealing, illumination or electric injection.

The above description of the disclosed embodiments enables any person skilled in the art to make or use the present invention. Various modifications to the above-described embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (8)

1. a battery preparation method utilizing selective contact conduction, is characterized in that, comprises the steps: 1) Choose p-type doped or n-type doped crystalline silicon wafers as the basis; 2) Coating silicon oxide layers on the front and back surfaces of the silicon wafer in step 1); 3) Coating doped amorphous silicon on the silicon oxide layers on the front and back surfaces of the silicon wafer in step 2) respectively, wherein one side is plated with phosphorus doped amorphous silicon, and the other side is plated with boron doped amorphous silicon. Annealing and crystallization to form doped polysilicon; 4) Plate TCO layers respectively on the front and back sides of the silicon wafer in step 3) doped polysilicon; 5) Re-plating an insulating protective layer on the front and back TCO layers of the silicon wafer in step 4); 6) The silver wire for collecting current is printed on the insulating protective layer on the front and back of the silicon wafer in step 5). After sintering, the silver wire penetrates the insulating protective layer to realize contact with the TCO layer. 2 . The method for preparing a battery utilizing selective contact conduction according to claim 1 , wherein in step 1), the resistivity of the p-type doped or n-type doped crystalline silicon wafer is 0.1. 3 . ~10Ω•cm. 3. The method for preparing a battery utilizing selective contact conduction according to claim 1, wherein in step 2), the coating method of the silicon oxide layer is high temperature oxidation, plasma oxidation, PECVD deposition, atomic layer deposition method Any of them, the coating thickness is 1~2 nm. 4. The method for preparing a battery utilizing selective contact conduction according to claim 1, wherein in step 3), the coating method for doped amorphous silicon is any one of PVD, LPCVD, and PECVD, The coating thickness is 3~20nm; the high temperature annealing and crystallization temperature is 600~950℃. 5. The method for preparing a battery utilizing selective contact conduction according to claim 1, wherein in step 4), the coating method of the TCO layer is the PVD method, and the coating thickness is 30-200 nm; the TCO layer is Any one or more of ITO, IWO, ICO, AZO. 6 . The method for preparing a battery utilizing selective contact conduction according to claim 1 , wherein, in step 5), the insulating protective layer is any one of SiN, SiO ₂ and SiON. 7 . 7. The method for preparing a battery utilizing selective contact conduction according to claim 1, wherein in step 6), the width of the silver wire is 20-100 nm, and the height is 10-20 μm; after the silver wire is sintered The sintering temperature for penetrating the insulating protective layer is 500~900°C. 8. The method for preparing a battery utilizing selective contact conduction according to any one of claims 1 to 7, wherein the battery formed after the process in step 6) is further enhanced by annealing, illumination or electric injection. Conversion efficiency and attenuation resistance.