CN111640826A - Preparation method of battery conducting by utilizing selective contact - Google Patents
Preparation method of battery conducting by utilizing selective contact Download PDFInfo
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- CN111640826A CN111640826A CN202010522946.XA CN202010522946A CN111640826A CN 111640826 A CN111640826 A CN 111640826A CN 202010522946 A CN202010522946 A CN 202010522946A CN 111640826 A CN111640826 A CN 111640826A
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- 238000002360 preparation method Methods 0.000 title description 10
- 239000010410 layer Substances 0.000 claims abstract description 46
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 29
- 238000007747 plating Methods 0.000 claims abstract description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 24
- 239000010703 silicon Substances 0.000 claims abstract description 24
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 24
- 239000011241 protective layer Substances 0.000 claims abstract description 20
- 229910052709 silver Inorganic materials 0.000 claims abstract description 18
- 239000004332 silver Substances 0.000 claims abstract description 18
- 238000000576 coating method Methods 0.000 claims abstract description 14
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 238000006243 chemical reaction Methods 0.000 claims abstract description 12
- 238000005245 sintering Methods 0.000 claims abstract description 12
- 238000000137 annealing Methods 0.000 claims abstract description 10
- 239000011248 coating agent Substances 0.000 claims abstract description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052796 boron Inorganic materials 0.000 claims abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 5
- 239000011574 phosphorus Substances 0.000 claims abstract description 5
- 238000005240 physical vapour deposition Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000007639 printing Methods 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 238000005286 illumination Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 238000002425 crystallisation Methods 0.000 claims 1
- 230000008025 crystallization Effects 0.000 claims 1
- 238000002161 passivation Methods 0.000 abstract description 17
- 239000000969 carrier Substances 0.000 abstract description 8
- 239000000853 adhesive Substances 0.000 abstract description 3
- 230000001070 adhesive effect Effects 0.000 abstract description 3
- 230000031700 light absorption Effects 0.000 abstract description 3
- 101001073212 Arabidopsis thaliana Peroxidase 33 Proteins 0.000 description 9
- 101001123325 Homo sapiens Peroxisome proliferator-activated receptor gamma coactivator 1-beta Proteins 0.000 description 9
- 102100028961 Peroxisome proliferator-activated receptor gamma coactivator 1-beta Human genes 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000010408 film Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000010248 power generation Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- LKJPSUCKSLORMF-UHFFFAOYSA-N Monolinuron Chemical compound CON(C)C(=O)NC1=CC=C(Cl)C=C1 LKJPSUCKSLORMF-UHFFFAOYSA-N 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000002310 reflectometry Methods 0.000 description 2
- MARUHZGHZWCEQU-UHFFFAOYSA-N 5-phenyl-2h-tetrazole Chemical compound C1=CC=CC=C1C1=NNN=N1 MARUHZGHZWCEQU-UHFFFAOYSA-N 0.000 description 1
- KTSFMFGEAAANTF-UHFFFAOYSA-N [Cu].[Se].[Se].[In] Chemical compound [Cu].[Se].[Se].[In] KTSFMFGEAAANTF-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/208—Particular post-treatment of the devices, e.g. annealing, short-circuit elimination
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
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- Computer Hardware Design (AREA)
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Abstract
The invention discloses a method for preparing a battery by utilizing selective contact conduction, which comprises the following steps: 1) selecting a p-type doped or n-type doped crystalline silicon wafer; 2) respectively plating silicon oxide layers on the front and back sides of the silicon wafer; 3) respectively plating phosphorus or boron doped amorphous silicon on the front and back sides of a silicon wafer, and annealing and crystallizing at high temperature after plating the film to form doped polycrystalline silicon; 4) plating TCO layers on the front side and the back side of the silicon wafer respectively; 5) plating insulating protective layers on the front and back sides of the silicon wafer; 6) and silver wires for collecting current are printed on the front side and the back side of the silicon wafer, and the silver wires penetrate through the insulating protective layer after being sintered so as to be in contact with the TCO layer. The invention realizes full-coverage passivation and effectively avoids the problem that minority carriers are compounded to influence conversion efficiency, and the silicon oxide passivation realizes high-temperature sintering and effectively ensures the conductivity and adhesive force of silver paste without light absorption problem, and can integrate a plurality of processes into one device by using chain type device coating, thereby greatly improving work efficiency and reducing device investment cost and occupied space.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a cell preparation method utilizing selective contact conduction.
Background
Photovoltaic power generation has become a technology that can replace fossil energy, relying on the ever-decreasing production costs and the increase in photoelectric conversion efficiency in recent years. Solar cells can be roughly classified into two types according to the material of the photovoltaic cell sheet: one is a crystalline silicon solar cell, including a monocrystalline silicon solar cell, a polycrystalline silicon solar cell; the other type is a thin film solar cell, which mainly comprises an amorphous silicon solar cell, a cadmium telluride solar cell, a copper indium gallium selenide solar cell and the like. At present, crystalline silicon solar cells using high-purity silicon materials as main raw materials are mainstream products, and account for more than 80%.
In a crystalline silicon solar power generation system, one of the most central steps for realizing photoelectric conversion is a process of processing crystalline silicon into a cell for realizing photoelectric conversion, so that the photoelectric conversion efficiency of the cell also becomes a key index for embodying the technical level of the crystalline silicon solar power generation system.
Improving cell efficiency and establishing passivation contacts is critical. Because photogenerated carriers move rapidly in the silicon wafer, once the photogenerated carriers contact the surface, the photogenerated carriers are recombined and cannot be collected into current to generate power. If a special protective film is plated on the surface, such as silicon oxide, silicon nitride, aluminum oxide, amorphous silicon and the like, because of saturation of surface crystalline silicon surface chemical bonds and a charge field formed between the film and crystalline silicon, the special protective film can effectively prevent minority carriers from being compounded on the surface. A recently developed PERC cell is based on a conventional cell and replaces the aluminum back contact with an aluminum oxide passivation and then locally opens the window to introduce the conductive contact. The PERC technology is called Emitter and back passivation Cell technology (Passivated Emitter reader Cell), and through the back passivation, the Cell efficiency can be improved by 1-2% compared with the absolute value of a conventional Cell. The preparation of the PERC battery has the advantage of high compatibility with the existing battery production line, and compared with the traditional process, the PERC battery can be upgraded on the original conventional production line only by adding two additional devices (alumina deposition and laser device), so that the cost is relatively low, and the PERC battery becomes the main flow direction of a high-efficiency solar battery.
However, due to the need for open contacts in a PERC cell, the fraction of open contacts still results in minority recombination. And the front silver paste also needs to burn through the silicon nitride layer to contact the surface of the emitter. This contact also causes minority recombination to affect conversion efficiency.
To further improve efficiency, new cell theory simulations require full coverage of the passivation layer, with carriers reaching the conductive layer overlying the passivation layer through tunneling. The HIT battery is a new battery designed based on this concept. The HIT battery is characterized in that a layer of thin amorphous silicon (3-5 nm) covers the front side and the back side of a silicon wafer, and then the surface of the amorphous silicon is plated with phosphorus-doped amorphous silicon and boron-doped amorphous silicon respectively. Due to the fact that amorphous silicon has excellent passivation performance, the conversion efficiency of the HIT battery is greatly improved, and the conversion efficiency of more than 25.6% is reported by Japan Songhua and is 3% higher than that of the PERC battery. However, amorphous silicon and doped amorphous silicon used for the HIT cell have a problem of light absorption, and only a very thin passivation layer can be placed to control the light absorption, but too thin doped amorphous silicon affects its ability to conduct electricity laterally and to transfer electricity to the silver grid lines, and therefore, a transparent conductive layer must be placed on its surface. Another disadvantage of amorphous silicon passivation is that it can only withstand low temperature processes, above 250 ℃, the amorphous silicon passivation effect is immediately lost, which is not applicable for printing silver pastes that are mature for use on conventional batteries. The conventional silver paste needs to be sintered at 800 ℃ to achieve good conductivity and adhesive force. Therefore, the low-temperature silver paste is specially developed for the HIT battery, but the defects of poor conductivity, large using amount and small surface adhesion are faced at present.
Another technique for full-coverage passivation is to coat Polysilicon (Polysilicon) on a silicon oxide layer, where the thickness of the silicon oxide layer is only about 1.5nm, and phosphorus or boron can be doped as required, especially phosphorus-doped Polysilicon can allow electrons to pass through on silicon oxide, and boron-doped Polysilicon can allow holes to pass through on silicon oxide. This polysilicon selective passivated contact conduction (POLO) is the direction of developing high efficiency solar cells. However, it is difficult to design a battery structure that conducts electricity by selective contact and can be mass-produced at low cost.
Disclosure of Invention
In order to solve the technical problem, the invention provides a method for preparing a battery by utilizing selective contact conduction, which comprises the following steps:
1) selecting a p-type doped or n-type doped crystalline silicon wafer as a basis, wherein the resistivity of the p-type doped or n-type doped crystalline silicon wafer is 0.1-10 omega-cm;
2) respectively plating silicon oxide layers on the front surface and the back surface of the silicon wafer in the step 1), wherein the plating method is any one of high-temperature oxidation, plasma oxidation, PECVD deposition and atomic layer deposition, and the plating thickness is 1-2 nm;
3) respectively plating doped amorphous silicon on the silicon oxide layers on the front surface and the back surface of the silicon wafer in the step 2), wherein one surface of the silicon oxide layer is plated with phosphorus doped amorphous silicon, the other surface of the silicon oxide layer is plated with boron doped amorphous silicon, the coating method is one of PVD, LPCVD and PECVD, preferably, the PVD coating method is adopted, and the coating thickness is 3-20 nm; annealing and crystallizing at high temperature after coating to form doped polysilicon, wherein the high-temperature annealing and crystallizing temperature is 600-950 ℃, and p + POLO and n + POLO are respectively formed on the two sides of the silicon wafer through the steps;
4) respectively plating TCO layers on the doped polycrystalline silicon on the front side and the back side of the silicon wafer in the step 3), wherein the plating method is a PVD method, and the plating thickness is 30-200 nm; wherein the TCO layer is any one or more of ITO, IWO, ICO and AZO;
5) plating insulating protective layers on the TCO layers on the front and back surfaces of the silicon wafer in the step 4), wherein the insulating protective layers are SiN and SiO2In any of SiON and the insulating protective layer, the thickness of the insulating protective layer is determined according to the thickness of the TCO, and the antireflection effect needs to be met, that is, the relative thicknesses of the TCO layer and the insulating protective layer reach the lowest reflectivity (the light is not reflected after being irradiated on the surface by adjusting the thickness and the refractive index of the film by using the optical effect of the film), and meanwhile, the TCO layer is ensured to have enough thickness to meet the requirement of transverse conductivity;
6) printing silver wires for collecting current on the front and back insulating protective layers of the silicon wafer in the step 5), wherein the silver wires penetrate through the insulating protective layers after being sintered to be in contact with the TCO layer, the width of each silver wire is 20-100 nm, the narrower the silver wire is under the condition of meeting the requirement of conductivity, the better the silver wire is, and the height of each silver wire is 10-20 microns; the sintering temperature of the silver wire penetrating through the insulating protective layer after sintering is 500-900 ℃.
After the processes of the steps 1) to 6) are completed, the battery which conducts electricity by utilizing selective contact is formed. And further improving the photoelectric conversion efficiency and the anti-attenuation capability of the battery by annealing, illumination or electrical injection on the basis of the battery formed after the process of the step 6).
Through the technical scheme, the battery conducting by utilizing selective contact provided by the invention has the following advantages:
1) compared with a PERC battery, the battery preparation process disclosed by the invention realizes full-coverage passivation, so that the problems that minority carriers are compounded due to windowing contact of the PERC battery and the conversion efficiency is influenced by minority carriers because the front silver paste burns through the silicon nitride layer and can be contacted with the surface of an emitter are effectively solved;
2) compared with an HIT cell, the cell preparation process disclosed by the invention has the advantages that amorphous silicon is replaced by silicon oxide passivation, and the silicon oxide passivation layer can bear high-temperature sintering and does not absorb light;
3) compared with an HIT battery, the battery preparation process disclosed by the invention has the advantages that based on a silicon oxide passivation layer, the conventional high-temperature silver paste sintering process is used for replacing a low-temperature silver paste sintering process, so that the conductivity of the silver paste and the adhesive force on an insulating protection layer are effectively ensured;
4) the battery preparation process disclosed by the invention is simple in process, and multiple processes can be integrated in one device by using chain type device coating, so that the preparation efficiency is greatly improved, the device input cost and the occupied space are reduced, and the production cost is low.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below.
Example 1:
the invention provides a preparation method of a battery conducting by utilizing selective contact, which comprises the following steps:
1) selecting a p-type doped or n-type doped crystalline silicon wafer as a basis, wherein the resistivity of the p-type doped or n-type doped crystalline silicon wafer is 0.1-10 omega-cm;
2) respectively plating silicon oxide layers on the front surface and the back surface of the silicon wafer in the step 1), wherein the plating method is any one of high-temperature oxidation, plasma oxidation, PECVD deposition and atomic layer deposition, and the plating thickness is 1-2 nm;
3) respectively plating doped amorphous silicon on the silicon oxide layers on the front surface and the back surface of the silicon wafer in the step 2), wherein one surface of the silicon oxide layer is plated with phosphorus doped amorphous silicon, the other surface of the silicon oxide layer is plated with boron doped amorphous silicon, the coating method is one of PVD, LPCVD and PECVD, preferably, the PVD coating method is adopted, and the coating thickness is 3-20 nm; annealing and crystallizing at high temperature after coating to form doped polysilicon, wherein the high-temperature annealing and crystallizing temperature is 600-950 ℃, and p + POLO and n + POLO are respectively formed on the two sides of the silicon wafer through the steps;
4) respectively plating TCO layers on the doped polycrystalline silicon on the front side and the back side of the silicon wafer in the step 3), wherein the plating method is a PVD method, and the plating thickness is 30-200 nm; wherein the TCO layer is any one or more of ITO, IWO, ICO and AZO;
5) plating insulating protective layers on the TCO layers on the front and back surfaces of the silicon wafer in the step 4), wherein the insulating protective layers are SiN and SiO2In SiON, the thickness of the insulating protection layer is determined according to the thickness of TCO, and the anti-reflection effect is required to be met, namely the relative thicknesses of the TCO layer and the insulating protection layer reach the lowest reflectivity, and meanwhile, the TCO layer is ensured to have enough thickness to meet the requirement of transverse conductivity;
6) printing silver wires for collecting current on the front and back side insulating protective layers of the silicon wafer in the step 5), wherein the silver wires penetrate through the insulating protective layers after being sintered to be in contact with the TCO layer, the width of each silver wire is 20-100 nm, the narrower the silver wire is under the condition of meeting the requirement of conductivity, the better the silver wire is, and the height of each silver wire is 10-20 microns; the sintering temperature of the silver wire penetrating through the insulating protective layer after sintering is 500-900 ℃, and the battery conducting by utilizing selective contact is formed after sintering.
Example 2:
based on the embodiment 1, the photoelectric conversion efficiency and the anti-attenuation capability of the battery are further improved by annealing, illumination or electric injection on the basis of the battery formed after the process of the step 6).
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to the above-described embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A method for preparing a battery conducting electricity by utilizing selective contact is characterized by comprising the following steps:
1) selecting a p-type doped or n-type doped crystalline silicon wafer as a basis;
2) respectively plating silicon oxide layers on the front and back surfaces of the silicon wafer in the step 1);
3) respectively plating doped amorphous silicon on the silicon oxide layers on the front and back surfaces of the silicon wafer in the step 2), wherein one surface is plated with phosphorus doped amorphous silicon, the other surface is plated with boron doped amorphous silicon, and annealing and crystallizing at high temperature after film plating to form doped polycrystalline silicon;
4) respectively plating TCO layers on the doped polycrystalline silicon on the front and back surfaces of the silicon wafer in the step 3);
5) plating insulating protective layers on the TCO layers on the front side and the back side of the silicon wafer in the step 4);
6) and (5) printing silver wires for collecting current on the insulating protective layers on the front side and the back side of the silicon wafer in the step 5), and enabling the silver wires to penetrate through the insulating protective layers after sintering so as to be in contact with the TCO layer.
2. The method for preparing a cell using selective contact conduction as claimed in claim 1, wherein the resistivity of the p-type doped or n-type doped crystalline silicon wafer in step 1) is 0.1-10 Ω.
3. The method for preparing a battery using selective contact conduction as claimed in claim 1, wherein in the step 2), the silicon oxide layer is coated by any one of high temperature oxidation, plasma oxidation, PECVD deposition and atomic layer deposition, and the thickness of the coating is 1-2 nm.
4. The method for preparing a battery using selective contact conduction according to claim 1, wherein in the step 3), the coating method of doping amorphous silicon is any one of PVD, LPCVD and PECVD, and the coating thickness is 3-20 nm; the high-temperature annealing crystallization temperature is 600-950 ℃.
5. The method for preparing a cell using selective contact conduction as claimed in claim 1, wherein in the step 4), the TCO layer is coated by PVD method, and the thickness of the coating is 30-200 nm; the TCO layer is any one or more of ITO, IWO, ICO and AZO.
6. The method for preparing a battery using selective contact for conduction according to claim 1, wherein in the step 5), the insulating protective layer is SiN or SiO2And SiON.
7. The method for preparing a battery using selective contact conduction as claimed in claim 1, wherein in step 6), the width of the silver wire is 20 to 100nm, and the height is 10 to 20 μm; the sintering temperature of the silver wire penetrating through the insulating protective layer after sintering is 500-900 ℃.
8. The method for preparing a battery using selective contact conduction according to any one of claims 1 to 7, wherein the battery formed after the step 6) is further subjected to annealing, illumination or electrical injection to improve photoelectric conversion efficiency and anti-attenuation capability.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112795872A (en) * | 2021-01-26 | 2021-05-14 | 常州比太科技有限公司 | Plating equipment for AZO + SiN laminated protective film of solar cell |
| CN113584464A (en) * | 2021-07-29 | 2021-11-02 | 通威太阳能（安徽）有限公司 | Quantitative winding plating method and adjustment method of coating equipment |
| CN115241327A (en) * | 2022-08-26 | 2022-10-25 | 共青城辟微自动化有限公司 | Crystalline silicon solar cell prepared through annealing crystallization and preparation method thereof |
| CN116053333A (en) * | 2022-08-31 | 2023-05-02 | 江苏杰太光电技术有限公司 | Preparation method of solar cell emitter |
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| CN107342332A (en) * | 2017-07-07 | 2017-11-10 | 常州亿晶光电科技有限公司 | Two-sided POLO batteries and preparation method thereof |
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| CN116053333A (en) * | 2022-08-31 | 2023-05-02 | 江苏杰太光电技术有限公司 | Preparation method of solar cell emitter |
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