CN116072738A - Solar cell and preparation method thereof - Google Patents

Solar cell and preparation method thereof Download PDF

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CN116072738A
CN116072738A CN202111282898.2A CN202111282898A CN116072738A CN 116072738 A CN116072738 A CN 116072738A CN 202111282898 A CN202111282898 A CN 202111282898A CN 116072738 A CN116072738 A CN 116072738A
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layer
electrode
forming
aluminum
solar cell
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钟观发
吴坚
蒋方丹
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Jiaxing Canadian Solar Technology Research Institute
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Jiaxing Canadian Solar Technology Research Institute
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
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    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation
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Abstract

The invention provides a solar cell and a preparation method thereof, wherein the solar cell comprises: the semiconductor device comprises a silicon substrate, a front passivation layer, a front anti-reflection layer, a front doped layer, a front electrode, a tunneling layer, a doped polysilicon layer, a back anti-reflection layer and a back electrode, wherein the front passivation layer is positioned in a non-grid line area on the front side of the silicon substrate, the front anti-reflection layer is positioned on the front side of the front passivation layer, the front doped layer is positioned in a grid line area on the front side of the silicon substrate, the front electrode is positioned on the front side of the front doped layer, the tunneling layer is positioned on the back side of the silicon substrate, the doped polysilicon layer is positioned on the back side of the tunneling layer, the back anti-reflection layer is positioned in a non-grid line area on the back side of the doped polysilicon layer, and the back electrode is positioned on the grid line area on the back side of the doped polysilicon layer. Compared with the prior art, the invention has the advantages that the compact chemical passivation layer is firstly arranged on the front surface of the silicon substrate, so that the surface dangling bond and the carrier recombination phenomenon can be effectively reduced; and an electric field passivation layer is arranged, the field passivation is realized through carried negative charges, and the double passivation effect is better.

Description

Solar cell and preparation method thereof
Technical Field
The method relates to the field of photovoltaics, in particular to a solar cell and a preparation method thereof.
Background
The TOPCON (tunnel oxide passivated contact cell) cell is a tunneling oxide passivation contact cell prepared based on a selective carrier principle, and specifically comprises the steps of preparing an ultrathin oxide layer on a silicon substrate, then depositing doped polysilicon, and forming a passivation structure by the ultrathin oxide layer and the doped polysilicon, so that surface recombination and metal lower contact recombination are effectively reduced.
At present, the efficiency of the Topcon battery with the P-type and N-type substrates is basically equal, and the N-type silicon wafer has higher service life, smaller sensitivity to metal impurities and no attenuation phenomenon caused by boron-oxygen recombination, and the pilot scale production mainly comprises an N-Topcon product. The existing preparation process of the topcon battery is complex, comprises multiple steps of high temperature and cleaning, and has great challenges for realizing high yield.
In view of the foregoing, there is a need for an improved solar cell and a method for manufacturing the same, which solve the above-mentioned problems.
Method content
The method aims at providing a solar cell and a preparation method thereof.
In order to solve one of the technical problems, the method adopts the following technical scheme:
a solar cell, comprising:
silicon-based;
the front passivation layer is positioned on the chemical passivation layer of the non-grid line area on the front side of the silicon substrate, and the electric field passivation layer is positioned on the front side of the chemical passivation layer;
the front anti-reflection layer is positioned on the front of the front passivation layer;
the front doped layer is positioned in the grid line area on the front side of the silicon substrate;
a front electrode positioned on the front surface of the front doped layer;
the tunneling layer is positioned on the back surface of the silicon substrate;
the doped polysilicon layer is positioned on the back surface of the tunneling layer;
the back anti-reflection layer is positioned in a non-grid line area on the back of the doped polysilicon layer;
and the back electrode is positioned in a grid line area at the back of the doped polysilicon layer.
Further, the chemical passivation layer comprises a silicon oxide layer or a silicon oxynitride layer or a laminated film of the silicon oxide layer and the silicon oxynitride layer, and the thickness of the passivation layer is 0.5-3 nm or 1-2 nm;
or, the chemical passivation layer is the same as the tunneling layer;
or forming the chemical passivation layer simultaneously with forming the tunneling layer.
Further, the front doped layer is an aluminum doped layer with the thickness of 0.1-10 μm.
Further, the front electrode is a printed aluminum electrode, or the front electrode comprises a printed aluminum+Ni/Cu/Ag electroplated layer, or the front electrode comprises a printed aluminum+Ag electroplated layer, or the front electrode comprises a printed silver main grid and a printed aluminum fine grid; or, the front electrode comprises a silver main grid formed by printing and a fine grid, wherein the fine grid comprises an aluminum+Ni/Cu/Ag electroplated layer formed by printing or an aluminum+Ag electroplated layer formed by printing;
and/or the back electrode comprises a Ni/Cu/Ag electroplated layer, wherein the Ni layer is 0.5-3 mu m, the Cu layer is 2-20 mu m, and the Ag layer is 0.5-3 mu m; alternatively, the back electrode includes an Ag plating layer.
A method of fabricating a solar cell, comprising:
forming a chemical passivation layer in a non-grid line area on the front surface of the P-type silicon wafer;
forming an electric field passivation layer on the front surface of the chemical passivation layer;
and forming a front doping layer and a front electrode positioned on the front surface of the front doping layer in a grid line area on the front surface of the P-type silicon wafer.
Further, the chemical passivation layer comprises a silicon oxide layer, a silicon oxynitride layer, or a laminated film of a silicon oxide layer and a silicon oxynitride layer; or, forming the chemical passivation layer by a chemical method and/or by a thermal oxidation method, wherein the chemical method is performed by HNO 3 /O 3 /H 2 SO 4 +H 2 O 2 And forming the chemical passivation layer.
Further, the thickness of the chemical passivation layer is 0.5 nm-3 nm or 1 nm-2 nm.
Further, deposition of Al by PECVD or ALD 2 O 3 As the electric field passivation layer, the deposition temperature is 180-400 ℃ and the thickness is 3-10 nm.
Further, the forming method of the front surface doping layer and the front surface electrode comprises the following steps: the grid line region comprises a main grid region and a fine grid region, wherein the main grid region and the fine grid region are printed with burning-through aluminum paste, and the burning-through aluminum paste is sintered at a low temperature of less than 600 ℃; or, the forming method of the front surface doping layer and the front surface electrode comprises the following steps: the grid line region comprises a main grid region and a fine grid region, non-burning-through silver paste is printed in the main grid region, burning-through aluminum paste is printed in the fine grid region, and the low-temperature sintering is carried out at the temperature of less than 600 ℃; or, the forming method of the front surface doping layer and the front surface electrode comprises the following steps: the grid line region comprises a main grid region and a fine grid region, windows are formed in the main grid region and the fine grid region, aluminum paste is printed in the windows, and the aluminum paste is sintered at a low temperature of less than 600 ℃; or, the forming method of the front surface doping layer and the front surface electrode comprises the following steps: the grid line region comprises a main grid region and a fine grid region, windows are formed in the fine grid region, aluminum paste is printed in the windows, and the aluminum paste is sintered at a low temperature of less than 600 ℃; and printing aluminum paste or non-burn-through silver paste on the main grid region.
Further, when the front electrode is an aluminum electrode, the method for forming the front electrode further includes: and electroplating a Ni/Cu/Ag metal electrode or an Ag metal electrode on the aluminum electrode.
Further, the preparation method of the solar cell further comprises the following steps:
forming a tunneling layer on the back surface of the silicon wafer;
forming a doped polysilicon layer on the back of the tunneling layer;
forming a back anti-reflection layer on the back of the doped polysilicon layer;
and windowing a grid line area on the back surface, and forming a back electrode in the windowing area.
Further, the tunneling layer comprises a silicon oxide layer or a silicon oxynitride layer or a laminated film of the silicon oxide layer and the silicon oxynitride layer, and the thickness of the tunneling layer is 0.5-3 nm or 1-2 nm; alternatively, the tunneling layer is formed by chemical means, i.e. by HNO, and/or by thermal oxidation means 3 /O 3 /H 2 SO 4 +H 2 O 2 Forming the tunneling layer; or, simultaneously forming the tunneling layer and the chemical passivation layer by a chemical method and/or by a thermal oxidation method, wherein the chemical method is performed by HNO 3 /O 3 /H 2 SO 4 +H 2 O 2 The tunneling layer and the chemical passivation layer are formed.
Further, the doped polysilicon layer is deposited on the back surface in a physical vapor deposition mode, and the doping concentration of the surface is 1E 19 ～1E 21 cm -3 The thickness of the doped polysilicon layer is 70 nm-500 nm or 90 nm-150 nm.
Further, forming the back electrode includes: the front electrode is contacted with the anode, the back electrode is contacted with the electroplating solution, and a Ni/Cu/Ag electrode or an Ag electrode is formed in the window area through photoinduction electroplating; or the front electrode is an aluminum electrode, a silicon wafer is used as a cathode to be contacted with electroplating liquid, and Ni/Cu/Ag metal electrodes or Ag metal electrodes are electroplated at the front electrode and the back window area.
The method has the beneficial effects that: compared with the prior art, the invention has the advantages that the compact chemical passivation layer is firstly arranged on the front surface of the silicon substrate, so that the surface dangling bond and the carrier recombination phenomenon can be effectively reduced; and an electric field passivation layer is arranged, the field passivation is realized through carried negative charges, and the double passivation effect is better.
Drawings
FIG. 1 is a schematic diagram of a topcon battery of the present invention;
FIG. 2 is an enlarged view of a portion of FIG. 1 at A;
fig. 3 is a partial enlarged view at B in fig. 1.
The solar cell comprises a 100-solar cell, a 1-silicon substrate, a 2-front passivation layer, a 21-chemical passivation layer, a 22-electric field passivation layer, a 3-front antireflection layer, a 4-front doped layer, a 5-front electrode, a 6-tunneling layer, a 7-doped polysilicon layer, an 8-back antireflection layer, a 9-back electrode, a 01-Ni layer, a 02-Cu layer and a 03-Ag layer.
Detailed Description
The method will be described in detail below with reference to specific embodiments shown in the drawings. However, these embodiments are not intended to limit the present method, and structural, methodological, or functional transformations by one of ordinary skill in the art based on these embodiments are included within the scope of the present method.
In each of the illustrations of the method, certain dimensions of the structure or portion may be exaggerated relative to other structures or portions for convenience of illustration, and thus serve only to illustrate the basic structure of the subject matter of the method.
Referring to fig. 1 to 3, a solar cell 100 according to a preferred embodiment of the invention includes a silicon substrate 1, a front passivation layer 2 located in a non-gate line region on the front side of the silicon substrate 1, a front anti-reflection layer 3 located on the front side of the front passivation layer 2, a front doped layer 4 located in a gate line region on the front side of the silicon substrate 1, a front electrode 5 located on the front side of the front doped layer 4, a tunneling layer 6 located on the back side of the silicon substrate 1, a doped polysilicon layer 7 located on the back side of the tunneling layer 6, a back anti-reflection layer 8 located in a non-gate line region on the back side of the doped polysilicon layer 7, and a back electrode 9 located in a gate line region on the back side of the doped polysilicon layer 7.
The silicon base 111 is P-type silicon, and has resistivity of 1 to 30 ohm/cm, preferably 3 to 21 ohm/cm; the front and back surfaces are textured by alkali liquor to form pyramid suede, and the pyramid size is 1-3 mu m, so that the light-capturing and light-limiting effects are good.
The front passivation layer 2 comprises a chemical passivation layer 21 positioned in a non-grid line area on the front side of the silicon substrate 1 and an electric field passivation layer 22 positioned on the front side of the chemical passivation layer 21, and through combination of chemical passivation and field passivation, surface dangling bonds and carrier recombination phenomena can be effectively reduced, and the passivation effect is better.
The chemical passivation layer 21 includes a silicon oxide layer, or a silicon oxynitride layer, or a laminated film of a silicon oxide layer and a silicon oxynitride layer, and has a thickness of 0.5nm to 3nm or 1nm to 2nm; the film is a compact film layer, and can effectively reduce surface dangling bonds and carrier recombination phenomena.
Preferably, the chemical passivation layer 21 is the same as the tunneling layer 6, and the chemical passivation layer 21 is formed simultaneously when the tunneling layer 6 is formed. On one hand, the oxide layers are simultaneously grown on the two sides of the silicon substrate 1, the whole film layer is uniform, and on the other hand, the chemical passivation layer 21 is compact, and the surface passivation effect is good.
The electric field passivation layer 22 is an Al2O3 layer deposited by PECVD or ALD, has a thickness of 3 nm-10 nm, has negative charges, and realizes field passivation.
The front anti-reflection layer 3 can be one or a plurality of laminated films of silicon nitride, silicon oxynitride and silicon oxide, and has the thickness of 60 nm-130 nm. Typically formed using PECVD deposition.
The front doped layer 4 is an aluminum doped layer, namely a P+ doped layer formed after aluminum and silicon are sintered, the thickness of the front doped layer 4 is 0.1-10 mu m, and the field passivation is provided to be beneficial to current collection. The sintering temperature of aluminum and silicon is not higher than 600 ℃, the procedures of boron expansion high-temperature sintering step, back etching, winding-removing plating cleaning and the like are omitted, and the improvement of the efficiency/yield of the battery is facilitated.
The front electrode 5 is a printed aluminum electrode, or the front electrode 5 comprises a printed aluminum+Ni/Cu/Ag electroplated layer, or the front electrode 5 comprises a printed aluminum+Ag electroplated layer, or the front electrode 5 comprises a printed silver main grid and a printed aluminum fine grid; or, the front electrode 5 includes a silver main grid formed by printing and a fine grid including an aluminum+ni/Cu/Ag plating layer formed by printing or an aluminum+ag plating layer formed by printing. The front electrode 5 can reduce the consumption of silver paste by more than 80% by printing aluminum paste and combining electroplating, thereby greatly reducing the production cost.
The front electrode 5 has a width of 20 to 60 μm and a height of 5 to 30 μm, and can achieve a higher aspect ratio and reduce the line resistivity.
The tunneling layer 6 may have a laminated film structure of silicon oxide, silicon oxynitride or both, and the thickness of the tunneling layer 6 is 0.5nm to 3nm, preferably 1nm to 2nm.
The doped polysilicon layer 7 is n+ poly-S and is positioned on the back surface of the tunneling layer 6, and the doping concentration is 1E 19 ～1E 21 cm -3 Preferably 1E 20 ～6E 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the doped polysilicon layer 7 is 70nm to 500nm, preferably 70nm to 500nm. After high temperature annealing treatment, part of phosphorus enters the silicon base 1 through the tunneling layer 6 to form an N+ layer on the back surfaceThe method comprises the steps of carrying out a first treatment on the surface of the And the tunneling layer 6, the doped polysilicon layer 7 and the silicon substrate 1 form a back passivation contact structure, so that the recombination under the back metal electrode is reduced.
The back antireflection layer 8 may be one or more laminated films of silicon nitride, silicon oxynitride and silicon oxide, and has a thickness of 60nm to 130nm. Typically deposited simultaneously with the front side anti-reflection layer 3 by PECVD.
A back electrode 9, wherein the back electrode 9 comprises a Ni/Cu/Ag electroplated layer, the Ni layer 01 is 0.5-3 mu m, the Cu layer 02 is 2-20 mu m, and the Ag layer 03 is 0.5-3 mu m; when the front electrode 5 includes a Ni/Cu/Ag plating layer, the thickness of each layer is the same as that of the back electrode 9. Alternatively, the back electrode 9 includes an Ag plating layer.
In the Ni/Cu/Ag electroplated layers contained in the back electrode 9 and the front electrode 5, the Ni layer 01 is used as a contact layer contacted with the silicon base 1, and after subsequent annealing treatment, nickel-silicon alloy is formed, so that the contact between nickel and silicon is enhanced, and the contact resistivity is reduced; meanwhile, the Ni layer 01 also serves as a barrier layer to prevent Cu from diffusing to the silicon base 1 on the inner side. The Cu layer 02 is used as an intermediate conductive layer of the electrode and is not in contact with the silicon base 1, so that the dosage of silver is further reduced, and the cost is reduced. The Ag layer 03 is used as a protective layer and a subsequent welding layer, so that copper oxidation is prevented, and better welding with tin can be realized.
The invention provides a method for manufacturing a solar cell, which can be used for manufacturing the solar cell 100.
The preparation method of the solar cell comprises the following steps: forming a chemical passivation layer 21 in a non-grid line area on the front surface of the P-type silicon wafer to realize surface passivation; forming an electric field passivation layer 22 on the front surface of the chemical passivation layer 21 to realize field passivation; and forming a front doping layer 4 and a front electrode 5 positioned on the front surface of the front doping layer 4 in a grid line area on the front surface of the P-type silicon wafer.
The chemical passivation layer 21 includes a silicon oxide layer, or a silicon oxynitride layer, or a laminated film of a silicon oxide layer and a silicon oxynitride layer, and has a thickness of 0.5nm to 3nm or 1nm to 2nm; the film is a compact film layer, and can effectively reduce surface dangling bonds and carrier recombination phenomena.
Specifically, the chemical passivation layer 21 is formed by a chemical method, for exampleBy HNO 3 /O 3 /H 2 SO 4 +H 2 O 2 The chemical passivation layer 21 is formed, or the chemical passivation layer 21 is formed by a thermal oxidation method (LPCVD), or the chemical passivation layer 21 is grown by a combination of a chemical method and a thermal oxygen method.
The electric field passivation layer 22 is deposited with Al by PECVD or ALD 2 O 3 Forming, the deposition temperature is 180-400 ℃, and the thickness is 3-10 nm.
The front anti-reflection layer 3 is formed by deposition on the front by PECVD, the deposition temperature is 300-550 ℃, the front anti-reflection film can be one or a plurality of laminated films of silicon nitride, silicon oxynitride and silicon oxide, and the thickness of the front anti-reflection layer 3 is 60-130 nm.
The grid line area comprises a main grid area and a fine grid area, correspondingly, the front electrode 5 also comprises a main grid and a fine grid, the fine grid is used for collecting current, the main grid is used for collecting current and collecting the current collected by the fine grid, and the current is output outwards through a welding strip. The inventors have further studied and found that forming the front side doped layer 4 in the fine gate region can significantly improve passivation effect and current collection even if the front side doped layer 4 is not formed in the main gate region.
Preferably, the front doped layer 4, at least part of the front electrode 5 is formed in the same step.
In one embodiment, the method for forming the front doped layer 4 and the front electrode 5 includes: and (3) printing burning-through aluminum paste in the main grid region and the fine grid region, sintering at a low temperature less than 600 ℃, penetrating the front passivation layer 2, diffusing the burning-through aluminum paste into the silicon substrate 1, and forming a P+ doped layer after sintering aluminum and silicon, wherein the thickness is 0.1-10 mu m. The main gate region and the fine gate region both form a front doped layer 4 and an aluminum gate, providing field passivation beneficial for current collection.
In another embodiment, the forming method of the front doped layer 4 and the front electrode 5 includes: printing non-burnt-through silver paste on a main grid region by adopting a main grid and fine grid split printing mode to form a silver main grid, so that the silver main grid is convenient to weld with a welding strip; and (3) printing burning-through aluminum paste in the fine grid region, and sintering at a low temperature of less than 600 ℃ to form a front doped layer 4 and an aluminum fine grid, so that current collection is facilitated.
In another embodiment, the forming method of the front doped layer 4 and the front electrode 5 includes: and opening windows in the main grid region and the fine grid region, printing aluminum paste in the window opening regions, and sintering at a low temperature of less than 600 ℃. At this time, the aluminum paste may be a burn-through type aluminum paste or a non-burn-through type aluminum paste, and the front doped layer 4 and the aluminum grid may be formed in the window area.
In another embodiment, the forming method of the front doped layer 4 and the front electrode 5 includes: and (3) windowing a fine grid region, and printing aluminum paste in the windowing region, wherein the aluminum paste can be burnt-through aluminum paste or non-burnt-through aluminum paste, and is sintered at a low temperature of less than 600 ℃ to form the front doped layer 4 and the aluminum fine grid in the fine grid region. Printing burning-through aluminum paste in a main grid region, and sintering at a low temperature of less than 600 ℃ to form a front doped layer 4 and an aluminum main grid; or printing non-burning-through aluminum paste on the main grid region to form an aluminum main grid; or printing non-burning-through silver paste on the main grid region to form the silver main grid. When the slurries forming the main grid and the fine grid are the same, the main grid and the fine grid can be printed simultaneously, and when the slurries forming the main grid and the fine grid are different, the main grid and the fine grid are printed separately.
In the embodiment, the sintering temperature of aluminum and silicon is not higher than 600 ℃, so that the processes of boron expansion high-temperature sintering, back etching, winding plating removal cleaning and the like are omitted, the process flow is simplified, and the improvement of the battery efficiency/yield is facilitated; and the reduction of the high temperature process is more beneficial to flaking and cost reduction.
Further, when the front electrode 5 is an aluminum electrode, the aluminum electrode includes an aluminum main grid or an aluminum fine grid, and the method for forming the front electrode 5 further includes: and electroplating a Ni/Cu/Ag metal electrode or an Ag metal electrode on the aluminum electrode.
Of course, the front doped layer 4 and at least part of the front electrode 5 can also be formed in two steps, wherein in the first step, a layer of aluminum paste is printed on the fine grid region or the fine grid region and the main grid region, and the front doped layer is formed by sintering at a low temperature of less than 600 ℃. When the burning-through type aluminum paste is adopted, the window does not need to be opened in the grid line area; the non-burning-through aluminum paste is adopted, and the window must be opened in the grid line area. And secondly, printing aluminum paste on the front diffusion layer to sinter to form an aluminum grid, printing silver paste to sinter to form a silver grid, or electroplating to form a Ni/Cu/Ag metal electrode, or electroplating to form an Ag metal electrode.
Based on all the above embodiments, the method for manufacturing a solar cell further includes the following steps: forming a tunneling layer 6 on the back surface of the silicon wafer; forming a doped polysilicon layer 7 on the back surface of the tunneling layer 6; forming a back anti-reflection layer 8 on the back of the doped polysilicon layer 7; a gate line region on the back surface is windowed, and a back electrode 9 is formed in the windowed region.
The tunneling layer 6 may have a laminated film structure of silicon oxide, silicon oxynitride or both, and the thickness of the tunneling layer 6 is 0.5nm to 3nm, preferably 1nm to 2nm. Specifically, the tunneling layer 6 is formed by chemical means, for example by HNO 3 /O 3 /H 2 SO 4 +H 2 O 2 The tunneling layer 6 is formed either by thermal oxidation (LPCVD) or a combination of chemical and thermo-oxidative methods.
Preferably, the chemical passivation layer 21 is the same as the tunneling layer 6, and the chemical passivation layer 21 is formed simultaneously when the tunneling layer 6 is formed. On one hand, the oxide layers are simultaneously grown on the two sides of the silicon substrate 1, the whole film layer is uniform, and on the other hand, the chemical passivation layer 21 is compact, and the surface passivation effect is good.
The doped polysilicon layer 7 is deposited on the back surface by physical vapor deposition or sputtering, and the doping concentration of the surface is 1E 19 ～1E 21 cm -3 The thickness of the doped polysilicon layer 7 is 70 nm-500 nm or 90 nm-150 nm. After the doped polysilicon is deposited, the polysilicon is annealed at high temperature, so that part of phosphorus enters the silicon substrate 1 through the tunneling layer 6, and an N+ layer is formed on the back surface.
And depositing a back anti-reflection layer 8 on a non-gate line area on the back of the doped polysilicon layer 7 by PECVD, wherein the deposition temperature is 300-550 ℃, and the back anti-reflection film can be one or more laminated films of silicon nitride, silicon oxynitride and silicon oxide, and the thickness of the back anti-reflection layer 8 is 60-130 nm.
Preferably, the front side anti-reflection layer 3 is deposited on the front side and the back side anti-reflection layer 8 is deposited on the back side simultaneously by PECVD.
The back electrode 9 of the present invention is formed by electroplating, and a back surface needs to be windowed before electroplating. Specifically, in the gate line region on the back, a short-wave nanometer or picosecond laser windowing (wavelength is less than or equal to 350 nm) is adopted to perform patterning windowing treatment on the back, the back anti-reflection layer 8 of the gate line region is removed, the laser windowing size is preferably 10-40 μm, and the laser damage depth cannot exceed that of the doped polysilicon layer 7.
The manner of forming the back electrode 9 includes, but is not limited to, the following:
method 1: the front electrode 5 of the battery is contacted with the anode, the back electrode is contacted with the plating solution, and the Ni/Cu/Ag electrode or the Ag electrode is formed in the windowing area by electroplating in a photoinduced electroplating mode under the illumination condition. In this scheme, only the back side is electroplated to form the metal electrode, and the front side main grid needs to be a silver electrode or has a silver layer on the surface, so that the subsequent welding of the battery can be performed.
Method 2: the front electrode 5 is an aluminum electrode, and is plated on both the front and back surfaces of the battery. The silicon chip is used as a cathode to be contacted with electroplating liquid, and a Ni/Cu/Ag metal electrode or an Ag metal electrode is electroplated on the basis of the front aluminum electrode, so that higher aspect ratio can be realized, and the line resistivity is reduced; and simultaneously, plating Ni/Cu/Ag metal electrodes or Ag metal electrodes on the back window area to form a back electrode 9.
Finally, the method for manufacturing the solar cell may further include a post-treatment process, the post-treatment process including: the low-temperature annealing is carried out at 150-350 ℃, and the main purpose is to form nickel-silicon alloy, strengthen the contact between nickel and silicon, reduce the contact resistivity and improve the tensile force of the grid line. And simultaneously, electric injection passivation or light injection passivation is carried out, so that the efficiency is improved.
The whole preparation method of the solar cell 100 is carried out at a low temperature less than 600 ℃, does not need high-temperature equipment, is mild in production adjustment, and is energy-saving and environment-friendly.
The method for producing a solar cell according to the present invention will be described in detail with reference to the following examples. The preparation method of the solar cell comprises the following steps:
s1, wool making: taking a P-type silicon wafer with the resistivity of 0.3-7Ω & cm, and texturing by alkali liquor to form pyramid suede, wherein the pyramid size is 1-3 μm.
S2, by chemistryMethods such as HNO 3 /O 3 /H 2 SO 4 +H 2 O 2 Or thermal oxidation LPCVD or a combination of chemical and thermal oxygen to grow a tunneling oxide layer, which may be a silicon oxide, silicon oxynitride or a laminated film structure of both, the tunneling layer 615 has a thickness of 0.5nm to 3nm, preferably 1nm to 2nm.
The chemical passivation layer 21 is grown on the front surface of the silicon wafer while the tunneling layer 6 is grown, namely, oxide film layers are grown on both sides simultaneously, so that the uniformity of the film layers is consistent, and the novel front-surface-reserved oxide film is just used as the chemical passivation layer 21, which is essentially different from the steps and cognition that the film layers are required to be produced on one side and the front-surface oxide layers are cleaned in the traditional process, and the technical prejudice is overcome.
S3, depositing a layer of doped polysilicon layer 7 on the back surface of the tunneling layer 6 in a sputtering mode, and after the deposition is finished, enabling part of phosphorus to enter the silicon substrate 1 through the tunneling layer 6 by high-temperature annealing treatment to form an N+ layer on the back surface.
S4, depositing Al on the front surface of the silicon substrate 1 by utilizing a PECVD or ALD mode 2 O 3 The front passivation layer 213 is deposited at 180-400 deg.c and 3-10 nm thick.
S5, depositing a front antireflection film and a back antireflection film on the front side and the back side respectively by PECVD, wherein the deposition temperature is 300-550 ℃, and the thickness of the antireflection film is 60-130 nm.
S6, preparing the front doping layer 4 and at least part of the front electrode 5 on the front surface at the same time. Specifically, one of the following two methods is adopted:
method 1: and printing non-burning-through silver paste on the main grid and burning-through aluminum paste on the fine grid in a main and auxiliary grid split printing mode, and performing low-temperature sintering at the temperature of less than 600 ℃ to form an aluminum Back Surface Field (BSF). Of course, the main grid can also be printed with burning-through type aluminum paste or non-burning-through type aluminum paste, and sintered at low temperature.
Method 2: patterning laser windowing is performed on a fine grid region on the front surface, then aluminum paste is printed in the windowing region in an overprinting mode, the aluminum paste can be burnt-through type or non-burnt-through type, then low-temperature sintering is performed to form an aluminum back field, and the main grid region can be printed with the aluminum paste to form an aluminum main grid or printed with non-burnt-through type silver paste to form a silver main grid.
S7, back windowing is carried out, the back is subjected to patterning windowing treatment by adopting short-wave nanometer or picosecond laser windowing (wavelength is less than or equal to 350 nm), the back anti-reflection layer 8 of the grid line area is removed, the laser windowing size is preferably 10-40 mu m, and the laser damage depth cannot exceed the doped polysilicon layer 7.
S8, forming the back electrode 9, wherein the method 1 for forming the back electrode 9 can be adopted, plating is only carried out on the back, and Ni/Cu/Ag or Ag grid lines are formed in the window area. The method 2 of forming the back electrode 9 may be used to plate both the front and back surfaces.
S9, annealing at low temperature, and simultaneously carrying out electric injection passivation or light injection passivation, wherein the low temperature annealing temperature is 150-350 ℃.
In summary, the front surface of the silicon substrate 1 is provided with the compact chemical passivation layer 21, so that the surface dangling bond and the carrier recombination phenomenon can be effectively reduced; an electric field passivation layer 22 is further arranged, and the field passivation is realized through the carried negative charge, so that the double passivation effect is better.
In view of cost, the P-topcon battery prepared by using the P-type silicon wafer is prepared by doping aluminum paste to form a P+ layer, so that a high-temperature process of boron diffusion and a plurality of cleaning steps are omitted, the process flow is simplified, and a base metal is adopted to replace most of silver electrodes in combination with an electroplating process, so that the consumption of silver paste is greatly reduced, and the preparation of the high-efficiency low-cost topcon battery is realized.
It should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is for clarity only, and that the skilled artisan should recognize that the embodiments may be combined as appropriate to form other embodiments that will be understood by those skilled in the art.
The above list of detailed descriptions is only specific to practical embodiments of the method, and they are not intended to limit the scope of the method, and all equivalent embodiments or modifications that do not depart from the spirit of the technology of the method are included in the scope of the method.
It should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is for clarity only, and that the skilled artisan should recognize that the embodiments may be combined as appropriate to form other embodiments that will be understood by those skilled in the art.
The above list of detailed descriptions is only specific to practical embodiments of the method, and they are not intended to limit the scope of the method, and all equivalent embodiments or modifications that do not depart from the spirit of the technology of the method are included in the scope of the method.

Claims (14)

1. A solar cell, comprising:
silicon-based;
the front passivation layer is positioned on the chemical passivation layer of the non-grid line area on the front side of the silicon substrate, and the electric field passivation layer is positioned on the front side of the chemical passivation layer;
the front anti-reflection layer is positioned on the front of the front passivation layer;
the front doped layer is positioned in the grid line area on the front side of the silicon substrate;
a front electrode positioned on the front surface of the front doped layer;
the tunneling layer is positioned on the back surface of the silicon substrate;
the doped polysilicon layer is positioned on the back surface of the tunneling layer;
the back anti-reflection layer is positioned in a non-grid line area on the back of the doped polysilicon layer;
and the back electrode is positioned in a grid line area at the back of the doped polysilicon layer.
2. The solar cell of claim 1, wherein: the chemical passivation layer comprises a silicon oxide layer or a silicon oxynitride layer or a laminated film of the silicon oxide layer and the silicon oxynitride layer, and the thickness of the passivation layer is 0.5-3 nm or 1-2 nm;
or, the chemical passivation layer is the same as the tunneling layer;
or forming the chemical passivation layer simultaneously with forming the tunneling layer.
3. The solar cell of claim 1, wherein: the front doped layer is an aluminum doped layer with the thickness of 0.1-10 mu m.
4. The solar cell of claim 1, wherein: the front electrode is a printed aluminum electrode, or the front electrode comprises a printed aluminum+Ni/Cu/Ag electroplated layer, or the front electrode comprises a printed aluminum+Ag electroplated layer, or the front electrode comprises a printed silver main grid and a printed aluminum fine grid; or, the front electrode comprises a silver main grid formed by printing and a fine grid, wherein the fine grid comprises an aluminum+Ni/Cu/Ag electroplated layer formed by printing or an aluminum+Ag electroplated layer formed by printing;
and/or the back electrode comprises a Ni/Cu/Ag electroplated layer, wherein the Ni layer is 0.5-3 mu m, the Cu layer is 2-20 mu m, and the Ag layer is 0.5-3 mu m; alternatively, the back electrode includes an Ag plating layer.
5. A preparation method of a solar cell is characterized by comprising the following steps: comprising the following steps:
forming a chemical passivation layer in a non-grid line area on the front surface of the P-type silicon wafer;
forming an electric field passivation layer on the front surface of the chemical passivation layer;
and forming a front doping layer and a front electrode positioned on the front surface of the front doping layer in a grid line area on the front surface of the P-type silicon wafer.
6. The method of manufacturing a solar cell according to claim 5, wherein: the chemical passivation layer comprises a silicon oxide layer or a silicon oxynitride layer or a laminated film of the silicon oxide layer and the silicon oxynitride layer; or by chemical means and/or by heatThe chemical passivation layer is formed by an oxidation method, wherein the chemical method is carried out by HNO 3 /O 3 /H 2 SO 4 +H 2 O 2 And forming the chemical passivation layer.
7. The method of manufacturing a solar cell according to claim 5, wherein: the thickness of the chemical passivation layer is 0.5 nm-3 nm or 1 nm-2 nm.
8. The method of manufacturing a solar cell according to claim 5, wherein: deposition of Al by PECVD or ALD 2 O 3 As the electric field passivation layer, the deposition temperature is 180-400 ℃ and the thickness is 3-10 nm.
9. The method of manufacturing a solar cell according to claim 5, wherein:
the forming method of the front doping layer and the front electrode comprises the following steps: the grid line region comprises a main grid region and a fine grid region, wherein the main grid region and the fine grid region are printed with burning-through aluminum paste, and the burning-through aluminum paste is sintered at a low temperature of less than 600 ℃;
or, the forming method of the front surface doping layer and the front surface electrode comprises the following steps: the grid line region comprises a main grid region and a fine grid region, non-burning-through silver paste is printed in the main grid region, burning-through aluminum paste is printed in the fine grid region, and the low-temperature sintering is carried out at the temperature of less than 600 ℃;
or, the forming method of the front surface doping layer and the front surface electrode comprises the following steps: the grid line region comprises a main grid region and a fine grid region, windows are formed in the main grid region and the fine grid region, aluminum paste is printed in the windows, and the aluminum paste is sintered at a low temperature of less than 600 ℃;
or, the forming method of the front surface doping layer and the front surface electrode comprises the following steps: the grid line region comprises a main grid region and a fine grid region, windows are formed in the fine grid region, aluminum paste is printed in the windows, and the aluminum paste is sintered at a low temperature of less than 600 ℃; and printing aluminum paste or non-burn-through silver paste on the main grid region.
10. The method of manufacturing a solar cell according to claim 9, wherein: when the front electrode is an aluminum electrode, the method for forming the front electrode further comprises the following steps: and electroplating a Ni/Cu/Ag metal electrode or an Ag metal electrode on the aluminum electrode.
11. The method of manufacturing a solar cell according to any one of claims 5 to 10, characterized in that: the method also comprises the following steps:
forming a tunneling layer on the back surface of the silicon wafer;
forming a doped polysilicon layer on the back of the tunneling layer;
forming a back anti-reflection layer on the back of the doped polysilicon layer;
and windowing a grid line area on the back surface, and forming a back electrode in the windowing area.
12. The method of manufacturing a solar cell according to claim 11, wherein:
the tunneling layer comprises a silicon oxide layer or a silicon oxynitride layer or a laminated film of the silicon oxide layer and the silicon oxynitride layer, and the thickness of the tunneling layer is 0.5-3 nm or 1-2 nm;
alternatively, the tunneling layer is formed by chemical means, i.e. by HNO, and/or by thermal oxidation means 3 /O 3 /H 2 SO 4 +H 2 O 2 Forming the tunneling layer;
or, simultaneously forming the tunneling layer and the chemical passivation layer by a chemical method and/or by a thermal oxidation method, wherein the chemical method is performed by HNO 3 /O 3 /H 2 SO 4 +H 2 O 2 The tunneling layer and the chemical passivation layer are formed.
13. The method of manufacturing a solar cell according to claim 11, wherein: depositing the doped polysilicon layer on the back surface in a physical vapor deposition mode, wherein the doping concentration of the surface is 1E 19 ～1E 21 cm -3 The thickness of the doped polysilicon layer is 70 nm-500 nm or 90 nm-150 nm.
14. The method of manufacturing a solar cell according to claim 11, wherein:
forming the back electrode includes: the front electrode is contacted with the anode, the back electrode is contacted with the electroplating solution, and a Ni/Cu/Ag electrode or an Ag electrode is formed in the window area through photoinduction electroplating;
or the front electrode is an aluminum electrode, a silicon wafer is used as a cathode to be contacted with electroplating liquid, and Ni/Cu/Ag metal electrodes or Ag metal electrodes are electroplated at the front electrode and the back window area.
CN202111282898.2A 2021-11-01 2021-11-01 Solar cell and preparation method thereof Pending CN116072738A (en)

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