CN114188431A

CN114188431A - Solar cell and preparation method thereof

Info

Publication number: CN114188431A
Application number: CN202111234260.1A
Authority: CN
Inventors: 李华; 童洪波; 张洪超; 刘继宇
Original assignee: Taizhou Longi Solar Technology Co Ltd
Current assignee: Taizhou Longi Solar Technology Co Ltd
Priority date: 2021-10-22
Filing date: 2021-10-22
Publication date: 2022-03-15
Anticipated expiration: 2041-10-22
Also published as: CN114188431B

Abstract

The application discloses a solar cell, which comprises a silicon substrate, a tunneling layer, a first doped polycrystalline silicon layer, a first dielectric layer and a first electrode; a tunneling layer, a first doped polycrystalline silicon layer and a first dielectric layer are sequentially stacked on the surface of one side of the silicon substrate; the first electrode comprises a first main grid electrode and a first fine grid electrode, and the first fine grid electrode is intersected with and electrically connected with the first main grid electrode; the first main gate electrode burns through the first dielectric layer and extends into the first doped polysilicon layer; a first metal nanoparticle having a crystalline state at a boundary of the first doped polysilicon layer and the first main gate electrode; a plurality of first openings penetrating through the first medium layer are formed in the first medium layer; the first fine gate electrode is electroplated on the first doped polysilicon layer exposed by the first opening. The application also provides a preparation method of the solar cell. The solar cell reduces the usage amount of the first main grid electrode slurry and also enhances the bonding strength of the first main grid electrode and the first fine grid electrode.

Description

Solar cell and preparation method thereof

Technical Field

The application relates to the technical field of solar cells, in particular to a solar cell and a preparation method thereof.

Background

The crystalline silicon solar cell is the solar cell with the highest market share at present due to high energy conversion efficiency. How to improve the conversion efficiency of crystalline silicon solar cells and modules and reduce the production cost thereof is the biggest problem in the industry. At present, in the large-scale silicon solar cell manufacturing, a screen printing mode is usually adopted to realize a metallization process of the silicon solar cell, but the screen printing precision is limited, the printed electrode has fluctuant shapes, the electrode is widened greatly after printing and sintering, and the formed grid has a low height-width ratio, so that the effective light receiving area of the light receiving surface of the silicon solar cell is reduced, and in addition, the series resistance of the silicon solar cell manufactured by the screen printing is large. With the expansion of the market and the productivity of the photovoltaic industry, the continuous and stable supply of silver paste becomes a serious test, and the rising silver price also has the problem of cost competitiveness. Therefore, studies on the use of the plating method have been actively conducted in recent years.

Since electroplating is difficult when a seed layer is not formed on the silicon wafer, it is required to form a conductive layer on the silicon wafer in advance to perform a subsequent electroplating process. The seed layer forming process is independently performed in a separate apparatus, for example, by sputtering or light-induced plating, but the sputtering seed layer requires additional sputtering equipment in the existing production line, the required pattern for sputtering also uses a mask step, the operation is complicated, the production cost is difficult to reduce, and the sputtering seed layer is generally not conductive enough to support the large current density generated by the silicon-based solar cell, and needs to be coated with other metals such as nickel and copper to enhance the conductivity.

Disclosure of Invention

In view of the above problems, the present application provides a solar cell and a method for manufacturing the same, which not only reduces the usage amount of the paste for the first main gate electrode, but also enhances the bonding strength between the first main gate electrode and the first fine gate electrode, and increases the current collection efficiency.

The application provides a solar cell, which comprises a silicon substrate, a tunneling layer, a first doped polycrystalline silicon layer, a first dielectric layer and a first electrode;

the tunneling layer, the first doped polycrystalline silicon layer and the first dielectric layer are sequentially stacked on the surface of one side of the silicon substrate;

the first electrode comprises a first main gate electrode and a first fine gate electrode, and the first fine gate electrode is intersected with and electrically connected with the first main gate electrode;

the first main gate electrode burns through the first dielectric layer and extends into the first doped polysilicon layer; a first metal nanoparticle having a crystalline state at a boundary of the first doped polysilicon layer and the first main gate electrode;

a plurality of first openings penetrating through the first medium layer are formed in the first medium layer; the first fine gate electrode is electroplated on the first doped polycrystalline silicon layer exposed from the first opening.

Further, the crystalline first metal nanoparticles include a metal that is the same as the metal material in the first main gate electrode;

the crystalline first metal nanoparticles are discretely distributed in an island shape at the junction of the first doped polycrystalline silicon layer and the first main gate electrode.

Further, the crystalline first metal nanoparticles comprise metallic silver.

Further, the first main gate electrode includes a first printed sintered layer and a first metal layer which are stacked,

the first printing sintering layer penetrates through the first medium layer and extends into the first doped polycrystalline silicon layer, and the junction of the first doped polycrystalline silicon layer and the first printing sintering layer is provided with the crystalline first metal nano-particles;

the first metal layer is arranged on the surface of one side, away from the first doped polycrystalline silicon layer, of the first printing sintering layer.

Further, the first main gate electrode further comprises a first auxiliary electrode located at an intersection of the first main gate electrode and the first fine gate electrode; the cross-sectional area of the first auxiliary electrode in the direction perpendicular to the silicon substrate is gradually reduced in the direction away from the first main gate electrode and close to the first fine gate electrode.

Further, the display device also comprises a second electrode with the polarity opposite to that of the first electrode, wherein the second electrode comprises a second main gate electrode and a second fine gate electrode, and the second fine gate electrode is intersected with and electrically connected with the second main gate electrode;

the second main gate electrode further comprises a second auxiliary electrode, and the second auxiliary electrode is positioned at the intersection of the second main gate electrode and the second fine gate electrode; the cross-sectional area of the second auxiliary electrode along the direction perpendicular to the silicon substrate is gradually reduced along the direction far away from the second main grid electrode and close to the second fine grid electrode.

Further, a doped layer is formed on the surface of one side, away from the tunneling layer, of the silicon substrate, and a second dielectric layer is arranged on the surface of the doped layer;

the second main gate electrode burns through the second dielectric layer and extends into the doped layer;

a second metal nanoparticle having a crystalline state at a boundary of the doped layer and the second main gate electrode; or a eutectic layer and a local back field are arranged at the boundary of the doped layer and the second main gate electrode.

Further, the second main gate electrode comprises metal aluminum or metal silver;

when the second main gate electrode comprises metal aluminum, a eutectic layer and a local back field are arranged at the boundary of the second main gate electrode and the doped layer;

when the second main gate electrode comprises metal silver, crystalline second metal nanoparticles are arranged at the junction of the second main gate electrode and the doped layer; the crystalline second metal nanoparticles are discretely distributed at the junction of the doping layer and the second main gate electrode in an island shape.

Further, the second main gate electrode includes a second printed sintered layer and a second metal layer which are stacked,

the second printing sintering layer penetrates through the second dielectric layer and extends into the doping layer, and second metal nano-particles in the crystalline state are arranged in the doping layer and at the junction of the second printing sintering layer and the doping layer;

the second metal layer is arranged on the surface of one side, away from the doped layer, of the second printing sintering layer.

Further, the first electrode and the second electrode are located on the same side of the silicon substrate.

Further, the second fine gate electrodes and the first fine gate electrodes are alternately parallel to each other;

the second main gate electrodes and the first main gate electrodes are alternately parallel to each other.

Further, on the surface of the silicon substrate, the tunneling layer comprises a plurality of tunneling units arranged at intervals,

the area between the adjacent tunneling units is a first area,

the first dielectric layer covers the surface of the first doped polycrystalline silicon layer, the side face of the first doped polycrystalline silicon layer in the first region, the side face of the tunneling unit and the surface of the silicon substrate.

Further, the second main gate electrode penetrates through the first dielectric layer in the first region and is connected with the silicon substrate.

Further, on the surface of the tunneling layer, the first doped polysilicon layer comprises a plurality of first doped polysilicon units arranged at intervals;

the region between the adjacent first doped polycrystalline silicon units is a second region;

a second doped polycrystalline silicon unit is arranged in the second area, and a plurality of second doped polycrystalline silicon units form a second doped polycrystalline silicon layer;

the first dielectric layer covers the surfaces of the first doped polycrystalline silicon unit and the second doped polycrystalline silicon unit;

the second main gate electrode penetrates through the first dielectric layer to be connected with the second doped polycrystalline silicon layer.

The application provides a preparation method of a solar cell, which comprises the following steps:

providing a silicon substrate;

arranging a tunneling layer on the surface of one side of the silicon substrate;

depositing a first doped polysilicon layer on one side of the tunneling layer, which is far away from the silicon substrate;

depositing a first dielectric layer on one side of the first doped polycrystalline silicon layer, which is far away from the tunneling layer;

printing first printing electrode slurry on one side of the first dielectric layer, which is far away from the first doped polycrystalline silicon layer, and sintering to enable the first printing electrode slurry to burn through the first dielectric layer, so as to form a first printing sintering layer connected with the first doped polycrystalline silicon layer, and form crystalline first metal nano-particles at the junction of the first doped polycrystalline silicon layer and the first printing sintering layer;

arranging a plurality of first openings penetrating through the first dielectric layer on the first dielectric layer;

electroplating and depositing metal on the surface of the first printing sintering layer to form a first metal layer, wherein the first printing sintering layer and the first metal layer form the first main gate electrode;

a metal is electrodeposited on a silicon substrate having a first opening.

Further, the method also comprises the steps of carrying out heat treatment on the deposited metal; the sintering temperature is 750-900 ℃, and the heat treatment temperature is 250-500 ℃.

Further, a second dielectric layer is deposited on the surface of one side, away from the tunneling layer, of the silicon substrate;

ablating the first doped polysilicon layer and the tunneling layer at intervals on the surface of the first doped polysilicon layer to expose the silicon substrate, thereby forming a first region;

the first dielectric layer is deposited on the surface of the first doped polycrystalline silicon layer, the side face of the first doped polycrystalline silicon layer in the first region, the side face of the tunneling unit and the surface of the silicon substrate.

Further, printing second printing electrode slurry on the surface of the first dielectric layer in the first region, forming a second printing sintering layer through sintering, wherein the second printing electrode slurry is sintered through the second dielectric layer to be connected with the doping layer, and forming a second metal nanoparticle or eutectic layer in a crystalline state and a local back surface field at the junction of the doping layer close to the second printing sintering layer;

electroplating and depositing metal on the surface of the second printing sintering layer to form a second metal layer;

the second printed sintered layer and the second metal layer constitute a second main gate electrode.

Furthermore, a plurality of second openings penetrating through the first dielectric layer are formed in the first dielectric layer, deposited metal is electroplated in the second openings, and second fine gate electrodes are formed through the heat treatment and are connected with the silicon substrate;

the second fine gate electrode intersects and is electrically connected with the second main gate electrode to form a second electrode.

Further, a first doped polysilicon unit and a second doped polysilicon unit are sequentially deposited at intervals on the surface of the tunneling layer,

the first doped polycrystalline silicon units form the first doped polycrystalline silicon layer;

the second doped polycrystalline silicon units form a second doped polycrystalline silicon layer;

the first dielectric layer is deposited on the surface of the first doped polysilicon unit and the surface of the second doped polysilicon unit.

Further, printing second printing electrode slurry on the surface of the first dielectric layer corresponding to the second doped polycrystalline silicon layer, and forming a second printing sintering layer through sintering, wherein the second printing electrode slurry is sintered through the first dielectric layer and is connected with the second doped polycrystalline silicon layer;

Furthermore, a plurality of second openings penetrating through the first dielectric layer are formed in the first dielectric layer, metal is electroplated in the second openings, and second fine gate electrodes are formed through the heat treatment and are connected with the second doped polycrystalline silicon layer;

The present application provides a solar cell in which the plurality of crystalline first metal nanoparticles have a relatively low resistance, and carriers (e.g., electrons) moving from the silicon substrate to the first conductivity type semiconductor region through the tunneling layer may move (contact) directly onto the first main gate electrode through the crystalline first metal nanoparticles, or may move onto the first electrode in a multi-step transition between the crystalline first metal nanoparticles and the crystalline first metal nanoparticles. The crystalline first metal nanoparticles can thus be used to help the carriers move more easily to the first electrode. And the crystalline first metal nanoparticles are positioned at the junction of the first doped polycrystalline silicon layer and the first main gate electrode, so that the performance of the tunneling layer is not damaged. The first fine gate electrode and the second fine gate electrode are both electroplated, and the tunneling layer cannot be damaged. And the electroplating process is adopted, a seed layer is not required to be additionally formed, the main gate is used as an electric contact point, the bonding force between the main gate and the polycrystalline silicon is better, and the improvement of the drawing force between the main gate and the solder strip is facilitated.

Drawings

The drawings are included to provide a further understanding of the application and are not to be construed as limiting the application. Wherein:

fig. 1 is a schematic structural diagram of a solar cell provided in the present application.

Fig. 2 is a schematic structural diagram of a solar cell provided in the present application.

Fig. 3 is a schematic structural diagram of a solar cell provided in the present application.

Fig. 4 is a schematic structural diagram of a light receiving surface or a backlight surface of a solar cell provided in the present application.

Fig. 5 is a schematic structural diagram of a light receiving surface or a backlight surface of a solar cell provided in the present application.

Fig. 6 is a schematic structural diagram of a light receiving surface or a backlight surface of a solar cell provided in the present application.

Description of the reference numerals

1-silicon substrate, 2-tunneling layer, 3-first doped polysilicon layer, 4-first dielectric layer, 5-first main gate electrode, 6-crystalline first metal nano-particle, 7-first fine gate electrode, 8-doping layer, 9-second dielectric layer, 10-antireflection layer, 11-second main gate electrode, 12-second fine gate electrode, 13-eutectic layer, 14-first connection point, 15-first connection gate line, 16-second connection point, 17-second connection gate line, 18-first auxiliary electrode, 19-local back field, and 20-second doped polysilicon layer.

Detailed Description

The following description of the exemplary embodiments of the present application, including various details of the embodiments of the present application to assist in understanding, should be taken as exemplary only. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present application. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness. The upper and lower positions in the present application depend on the incident direction of the light, and the incident position of the light is the upper position.

The present application provides three types of solar cells, specifically as follows.

First solar cell

As shown in fig. 1, the solar cell provided by the present application includes a silicon substrate 1, a first electrode and a second electrode, wherein a tunneling layer 2, a first doped polysilicon layer 3 and a first dielectric layer 4 are sequentially disposed on a back surface (back surface) of the silicon substrate 1, and a doped layer 8 and a second dielectric layer 9 are sequentially formed on a front surface (front surface) of the silicon substrate 1. The first electrode penetrates through the first dielectric layer 4 and extends into the first doped polysilicon layer 3, and crystalline first metal nanoparticles 6 are arranged at the junction between the first doped polysilicon layer 3 and the first electrode. The second electrode penetrates through the second dielectric layer 9 and extends into the doped layer 8, and a crystalline second metal nanoparticle or eutectic layer 13 and a local back field 19 are arranged at the boundary between the doped layer 8 and the second electrode.

Specifically, the first electrode includes a plurality of first main gate electrodes 5 and a plurality of first fine gate electrodes 7, and each first main gate electrode 5 intersects and is electrically connected to each first fine gate electrode 7. In the first doped polysilicon layer 3, at the interface with the first main gate electrode 5, there are crystalline first metal nanoparticles 6. In the first doped polysilicon layer 3, the interface with the first fine gate electrode 7 is free of crystalline first metal nanoparticles 6.

Specifically, the second electrode includes a plurality of second main gate electrodes 11 and a plurality of second fine gate electrodes 12, and each second main gate electrode 11 intersects and is electrically connected to each second fine gate electrode 12.

Further, when the second main gate electrode 11 includes silver metal, crystalline second metal nanoparticles are present at the boundary with the second main gate electrode 11 in the doped layer 8. Within said doped layer 8. The interface with the second fine gate electrode 12 is free of crystalline second metal nanoparticles.

Further, when the second main gate electrode 11 includes aluminum metal, the doped layer 8 has a eutectic layer 13 and a local back field 19 at the boundary with the second main gate electrode 11. In the doped layer 8, there is no eutectic layer 13 and no local back field 19 at the interface with the second fine gate electrode 12.

In the present application, the silicon substrate 1 may be made of a single crystal or polycrystalline semiconductor (e.g., single crystal or polycrystalline silicon). The front surface and/or the back surface of the silicon substrate 1 may have a pyramid shape of an irregular size. The textured structure of the front surface can reduce the reflectivity of light incident through the front surface of the silicon substrate 1. Therefore, light loss can be minimized, and the amount of light reaching the pn junction formed by the base region and the first doped polysilicon layer 3 or the doped layer 8 increases. The textured surface in fig. 1 has been illustrated as being formed in the front surface and the back surface of the silicon substrate 1, thus effectively preventing reflection of light incident through both surfaces. A textured structure may also be formed only in the front side of the silicon substrate 1, and a textured structure may not be formed in the back side of the silicon substrate 1. In this case, the back surface of the silicon substrate 1, on which the tunneling layer 2 is formed, may be formed to have a smaller surface roughness than the front surface thereof, so that the tunneling layer 2 is more stably and uniformly formed.

In the present application, the tunneling layer 2 may be disposed on the rear surface of the first doped polysilicon layer 3, and may be in direct contact with the first doped polysilicon layer 3. The tunneling layer 2 and the first doped polysilicon layer 3 formed thereon may be formed on the entire surface of the rear surface; or on a part of the surface of the rear surface. The tunneling layer 2 may create a tunneling effect and act as a barrier for electrons and holes. After the minority carriers are accumulated in a portion adjacent to the tunneling layer 2, only the majority carriers having energy of a specific level or more may pass through the tunneling layer 2. Majority carriers having energy of a certain level or more can easily pass through the tunneling layer 2 by a tunneling effect. Furthermore, the tunneling layer 2 may also serve as a diffusion barrier for preventing the dopant of the first doped polysilicon layer 3 from diffusing into the silicon substrate 1. The tunneling layer 2 may include various materials through which majority carriers can tunnel. For example, the tunneling layer 2 may include oxides, nitrides, semiconductors, and conductive polymers.

Specifically, the tunneling layer 2 may be formed of a silicon oxide layer including silicon oxide (SiOx). The silicon oxide layer has excellent passivation characteristics, and carriers can easily tunnel through the silicon oxide layer. In some embodiments, the tunneling layer 2 may be made of SiCx, or may be made of SiNx, hydrogenated SiNx, AlOx, SiON, or hydrogenated SiON. In order to sufficiently realize the tunneling effect, the thickness of the tunneling layer 2 may be 0.5nm to 2.5 nm. The tunneling layer 2 may be formed by, for example, an oxidation process, an LPCVD process, or a PECVD deposition process.

In the present application, the first doped polysilicon layer 3, which is spaced apart from the silicon substrate 1 as shown in fig. 1, and the first doped polysilicon layer 3 includes a doped polysilicon material formed on the rear surface of the tunneling layer 2, has better conductivity, and can smoothly generate tunneling of carriers in the tunneling layer 2 made of oxide, which can further improve the open circuit voltage Voc of the solar cell. The thickness of the first doped polysilicon layer 3 may be 50nm to 500 nm. The first doped polysilicon layer 3 may be formed by doping impurities into an amorphous silicon material or a polysilicon material by various methods such as deposition.

Specifically, the silicon substrate 1 may be doped with impurities of the first doped polysilicon layer 3 or the doped layer 8 at a low doping concentration. In this case, the silicon substrate 1 may have a lower doping concentration, a higher resistance, or a lower carrier concentration than one of the first doped polysilicon layer 3 and the doped layer 8, the first doped polysilicon layer 3 or the doped layer 8 having the same conductivity type as the silicon substrate 1.

Specifically, the doping layer 8 is disposed on an opposite surface of the silicon substrate 1, for example, a front surface of the silicon substrate 1 on which light is incident. The doping layer 8 may include impurities of a conductivity type opposite to that of the semiconductor substrate. The doping layer 8 may be formed as a doping region formed by doping an impurity in the doping layer 8 into a portion of the silicon substrate 1.

Specifically, for example, in the present application in which the first doped polysilicon layer 3 (the impurity in the first doped polysilicon layer 3 and the silicon substrate 1 is a p-type conductivity type) has the same conductivity type as the silicon substrate 1, a Back Surface Field (BSF) region may be formed, which has a higher doping concentration than the silicon substrate 1 and forms BSF. The doped layer 8 (the impurity in the doped layer 8 is of an n-type conductivity type) has a conductivity type opposite to that of the silicon substrate 1, and can form an emitter region of a pn junction, minimizing a path of light entering the pn junction region.

In the present application, each of the first and second

dielectric layers

4 and 9 may have a single-layer or multi-layer film structure, and the first dielectric layer 4 may be a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, MgF₂Film, MgF₂Film, TiO₂Film, and CeO₂One or more than two of the films. An antireflection layer 10 may also be disposed on a surface of the second dielectric layer 9 on a side away from the doped layer 8, where the antireflection layer 10 may be a silicon nitride layer.

Specifically, the first dielectric layer 4 may be a first passivation film, i.e., a silicon nitride film, may have a refractive index of 1.9 to 2.1, and may have a thickness of 30nm to 50 nm.

Specifically, the second dielectric layer 9 may be a second passivation film, and may have a double-layer structure in which an aluminum oxide film and a silicon nitride film are sequentially stacked on the doping layer 8. In this case, the aluminum oxide film may have a refractive index of 1.5 to 1.7 and a thickness of 5nm to 10 nm. The silicon nitride film may have a refractive index of 1.9 to 2.1 and a thickness of 70nm to 120 nm.

In the present application, the height of the first fine gate electrode 7 may be 15 micrometers or less, for example, less than 10 micrometers, the width is less than 35 micrometers, and the height difference between the first main gate electrode 5 and the first fine gate electrode 7 is 5 to 35 micrometers, so that the area and the amount of electrode arrangement can be reduced by depositing a metal electrode with low resistivity, and the production cost can be reduced.

In this application, the first main gate electrode 5 is burned through the first dielectric layer 4 and extends into the first doped polysilicon layer 3, and an opening burned out of the first dielectric layer 4 is a first sintering opening. A plurality of first openings penetrating through the first medium layer 4 are formed in the first medium layer 4; the first fine gate electrode 7 is electroplated on the first doped polysilicon layer exposed from the first opening, that is, a plurality of first windows (each first window comprises a first opening and a first sintering opening) are arranged on the first dielectric layer 4, the first fine gate electrode 7 penetrates through the first opening, and the first main gate electrode 5 penetrates through the first sintering opening and is connected with the first doped polysilicon layer 3.

In the present application, the first main gate electrode 5 and the first fine gate electrode 7 have a double-layer or multi-layer structure, and the number of layers of the first main gate electrode 5 is greater than the number of layers of the first fine gate electrode 7. The first fine gate electrode 7 may include aluminum, copper, silver, gold, and/or a combination of at least two or more of nickel, tungsten, titanium, and cobalt. The first main gate electrode 5 includes at least one of nickel (Ni), copper (Cu), silver (Ag), aluminum (Al), tin (Sn), zinc (Zn), indium (In), titanium (Ti), and gold (Au), and combinations thereof, including but not limited thereto.

Specifically, the first main gate electrode 5 includes a first printed sintered layer and a first metal layer, which are stacked, the first printed sintered layer penetrates through the first dielectric layer 4 and extends into the first doped polysilicon layer 3, and the first doped polysilicon layer 3 has the crystalline first metal nanoparticles 6 at the boundary with the first printed sintered layer; the first metal layer is arranged on the surface of the first printing sintering layer on the side away from the first doped polycrystalline silicon layer 3. The first metal layer may be a plurality of metal layers arranged in a stack. The first printing sintering layer is different from the metal contained in the first metal layer, for example, the metal in the first printing sintering layer is silver, and the metal in the first metal layer can be Ni/Cu/Sn, so that the high-cost silver consumption can be saved, and the cost of the electrode material can be reduced. The first fine gate electrode 7 may be a plurality of metal layers stacked. The first metal layer may be the same as the first fine gate electrode 7.

Specifically, the electrode paste forming the first printed sintered layer is silver paste or aluminum paste.

Specifically, the electrode paste for forming the first metal layer is silver paste, aluminum paste, silver-aluminum paste, copper paste or nickel paste.

Specifically, the electrode paste for forming the first fine gate electrode 7 is silver paste, aluminum paste, silver-aluminum paste, copper paste, or nickel paste.

In the present application, as shown in fig. 5, the first main gate electrode 5 includes a plurality of first connection points 14 and a plurality of first connection gate lines 15, and two adjacent first connection points 14 are connected by the first connection gate lines 15, that is, the first connection points 14 and the first connection gate lines 15 are sequentially connected and extend to form the first main gate electrode 5; the first main gate electrodes 5 are arranged in parallel at equal intervals.

In particular toThe width of the first connecting point 14 is larger than that of the first connecting grid line 15, the first connecting point 14 is discontinuously arranged in a point shape, and the single area is 0.5-10mm². The first connection point 14 is a welding point, and the cross section of the first connection point 14 may be a rectangle, a circle, an ellipse, or other geometric shapes. Specific dimensions of said first connection point 14 may be, for example, 1.2mm by 1mm, 0.7mm by 0.8mm, 1mm by 0.5 mm.

Specifically, the first thin gate electrodes 7 are arranged in parallel at equal intervals, the first thin gate electrode 7 includes a plurality of first thin gate lines spaced apart by the first main gate electrode 5, and both ends of the first thin gate lines are connected to the first main gate electrode 5, specifically, both ends of a part of the first thin gate lines are connected to the first connection gate line 15, and both ends of a part of the first thin gate lines are connected to the first connection point 14.

The first fine gate electrode 7 perpendicularly intersects the first main gate electrode 5.

In the present application, as shown in fig. 6, the first main gate electrode 5 further includes a first auxiliary electrode 18, the first auxiliary electrode 18 is located at the intersection of the first main gate electrode 5 and the first thin gate electrode 7, one end of the first auxiliary electrode 18 is connected to the first connection point 14 or the first connection gate line 15, and the other end thereof is connected to the first thin gate line; the first auxiliary electrode 18 is arranged to enhance the connection between the first fine grid electrode 7 and the first main grid electrode 5, so as to avoid or reduce the possibility that the first fine grid electrode 7 is disconnected by welding, and improve the performance and reliability of the solar cell.

Specifically, the shape of the first auxiliary electrode 18 may be an arc shape, a V shape, a U shape, and the like, including but not limited thereto. Preferably, the first auxiliary electrode 18 is arc-shaped, and the cross-sectional area of the first auxiliary electrode 18 in the direction perpendicular to the silicon substrate gradually decreases in the direction away from the first main gate electrode 5 and close to the first fine gate electrode 7; that is, the cross-sectional area of the first auxiliary electrode 18 in the direction perpendicular to the silicon substrate tends to decrease in the direction away from the first connection point 14 or the first connection gate line 15.

The plurality of said crystalline first metal nanoparticles 6 has a relatively low resistance compared to the first doped polysilicon layer 3 made of doped polysilicon. Since the crystalline first metal nanoparticles 6 are located at the interface with the first main gate electrode 5 within the first doped polysilicon layer 3, carriers (e.g., electrons) moving from the silicon substrate 1 through the tunneling layer 2 to the first doped polysilicon layer 3 may move (contact) directly to the first main gate electrode 5 through the crystalline first metal nanoparticles 6, or may move to the first electrode through multi-step transitions between the crystalline first metal nanoparticles 6 and the crystalline first metal nanoparticles 6 (through tunneling of a glass layer between the crystalline first metal nanoparticles 6 and the first main gate electrode 5). The crystalline first metal nanoparticles 6 can thus be used to help the carriers move more easily to the first electrode.

Specifically, in the preparation process of the first main gate electrode 5, a first printing electrode slurry is printed on the first dielectric layer 4, and by sintering, the first printing electrode slurry is burned through the first dielectric layer 4 to be in contact with the first doped polysilicon layer 3, a metal material in the first printing electrode slurry is dissolved into a glass frit, and is grown on the first doped polysilicon layer 3 through glass, and is recrystallized to form a crystalline first metal nanoparticle 6, so that the crystalline first metal nanoparticle 6 includes the same metal as the metal material in the first main gate electrode 5; if the first printed electrode paste comprises silver (Ag), for example, the crystalline first metal nanoparticles 6 may also comprise silver (Ag).

In addition, the morphology and distribution of the metal in the crystalline first metal nanoparticles 6 are different from those of the metal in the first printed sintering layer, for example, the metal in the crystalline first metal nanoparticles 6 is discretely distributed in island shapes at the interface with the first main gate electrode 5 in the first doped polysilicon layer 3 (i.e., at the interface with the first connection point 14, the first connection gate line 15, and the first auxiliary gate line in the first doped polysilicon layer 3), and the metal in the first printed sintering layer is combined with the glass body after heat treatment, and a plurality of holes generated by solvent evaporation in the first printed electrode paste are formed in the first printed sintering layer and are filled with the first metal layer deposited subsequently.

The plurality of crystalline first metal nanoparticles 6 are not located in the tunneling layer 2, so that the crystalline first metal nanoparticles 6 are prevented from damaging the tunneling layer 2 or the silicon substrate 1, and the performance of the solar cell is reduced.

In the present application, the height of the second fine gate electrode 12 may be 15 micrometers or less, for example, less than 10 micrometers, and the width is less than 35 micrometers, and the height difference between the second main gate electrode 11 and the second fine gate electrode 12 is 5-35 micrometers, so that the area and the amount of the electrode arrangement can be reduced by depositing a metal electrode with low resistivity, and the production cost can be reduced.

The second main gate electrode 11 is burned through the second dielectric layer 9 and extends into the doping layer 8, and an opening burned out of the second dielectric layer 9 is a second sintering opening. A plurality of second openings penetrating through the second medium layer 9 are further formed in the second medium layer 9; the second fine gate electrode 12 is electroplated on the doped layer 8 exposed from the second opening, that is, a plurality of second windows (each second window includes a second opening and a second sintering opening) are arranged on the second dielectric layer 9, the second fine gate electrode 12 penetrates through the second opening, and the second main gate electrode 11 penetrates through the second sintering openings and is connected with the doped layer 8.

In the present application, the second main gate electrode 11 and the second fine gate electrode 12 have a double-layer or multi-layer structure, and the number of layers of the second main gate electrode 11 is greater than the number of layers of the second fine gate electrode 12. The second fine gate electrode 12 may include aluminum, copper, silver, gold, and/or a combination of at least two or more of nickel, tungsten, titanium, and cobalt. The second main gate electrode 11 includes at least one of nickel (Ni), copper (Cu), silver (Ag), aluminum (Al), tin (Sn), zinc (Zn), indium (In), titanium (Ti), and gold (Au), and a combination thereof, including but not limited thereto.

Specifically, the second main gate electrode 11 includes a second printed sintering layer and a second metal layer, which are stacked, the second printed sintering layer penetrates through the second dielectric layer 9 and extends into the doping layer 8, and second metal nanoparticles in the crystalline state are arranged in the doping layer 8 at the boundary with the second printed sintering layer; the second metal layer is arranged on the surface of the second printed sintering layer on the side facing away from the doped layer 8. The second metal layer may be a plurality of metal layers arranged in a stack. The second printed sintering layer is different from the metal contained in the second metal layer, for example, the metal in the second printed sintering layer is silver, and the metal in the second metal layer can be Ni/Cu/Sn, so that the high-cost silver consumption can be saved, and the cost of the electrode material can be reduced. The second fine gate electrode 12 may be a plurality of metal layers stacked. The second metal layer may be the same as the second fine gate electrode 12.

Specifically, the electrode paste forming the second printed sintering layer is silver paste or aluminum paste.

Specifically, the electrode paste for forming the second metal layer is silver paste, aluminum paste, silver-aluminum paste, copper paste or nickel paste.

Specifically, the electrode paste for forming the second fine gate electrode 12 is silver paste, aluminum paste, silver-aluminum paste, copper paste or nickel paste.

In this application, as shown in fig. 5, the second main gate electrode 11 includes a plurality of second connection points 16 and a plurality of second connection gate lines 17, two adjacent second connection points 16 are connected by the second connection gate lines 17, that is, the second connection points 16 and the second connection gate lines 17 are sequentially connected and extend to form the second main gate electrode 11; the plurality of second main gate electrodes 11 are arranged in parallel at equal intervals.

Specifically, the width of the second connection point 16 is greater than the width of the second connection gate line 17, the second connection point 16 is discontinuously arranged in a point shape, and the single area is 0.5-10mm². The second connection point 16 is a welding point, and the cross section of the second connection point 16 may be a rectangle, a circle, an ellipse, or other geometric shapes. Specific dimensions of the second connection point 16 may be, for example, 1.2mm by 1mm, 0.7mm by 0.8mm, 1mm by 0.5 mm.

The second thin gate electrodes 12 are arranged in parallel at equal intervals, the second thin gate electrodes 12 include a plurality of second thin gate lines spaced apart by the second main gate electrodes 11, and two ends of each second thin gate line are connected to the second main gate electrodes 11, specifically, two ends of a part of the second thin gate lines are connected to the second connection gate line 17, and two ends of a part of the second thin gate lines are connected to the second connection point 16.

The second fine gate electrode 12 perpendicularly intersects the second main gate electrode 11.

In this application, the second main gate electrode 11 further includes a second auxiliary electrode, the second auxiliary electrode is located at the intersection of the second main gate electrode 11 and the second thin gate electrode 12, one end of the second auxiliary electrode is connected to the second connection point 16 or the second connection gate line 17, and the other end of the second auxiliary electrode is connected to the second thin gate line; the second auxiliary electrode can enhance the connection between the second fine grid electrode 12 and the second main grid electrode 11, avoid or reduce the possibility that the second fine grid electrode 12 is disconnected by welding, and improve the performance and reliability of the solar cell.

Specifically, the shape of the second auxiliary electrode may be an arc shape, a V shape, a U shape, and the like, including but not limited thereto. Preferably, the second auxiliary electrode is arc-shaped, and the cross-sectional area of the second auxiliary electrode along the direction perpendicular to the silicon substrate 1 gradually decreases along the direction away from the second main gate electrode 5 and close to the second fine gate electrode 12. I.e. the cross-sectional area of the second auxiliary electrode in a direction perpendicular to the silicon substrate 1, tends to decrease in a direction away from the second connection point 16 or the second connection gate line 17.

The projections of the first main gate electrode 5 and the second main gate electrode 11, and the projections of the first fine gate electrode 7 and the second fine gate electrode 12 in the thickness direction of the silicon substrate 1 are not overlapped, so that the first windowing and the second windowing are asymmetrically arranged, and the phenomenon that openings symmetrically arranged on two sides of the substrate in an opening process obviously reduce the mechanical strength of the silicon substrate 1 is avoided.

When the second main gate electrode 11 includes silver metal, crystalline second metal nanoparticles are present at the boundary with the second main gate electrode 11 in the doped layer 8. The plurality of the crystalline second metal nanoparticles has a relatively low resistance compared to the doped layer 8 made of doped polysilicon. Since the crystalline second metal nanoparticles are located at the interface with the second main gate electrode 11 within the doped layer 8, carriers (e.g., electrons) moving from the silicon substrate 1 to the doped layer 8 through the tunneling layer 2 may directly move (contact) to the second main gate electrode 11 through the crystalline second metal nanoparticles, or may move to the second electrode through multi-step transitions between the crystalline second metal nanoparticles and the crystalline second metal nanoparticles (tunneling through a glass layer between the crystalline second metal nanoparticles and the second main gate electrode 11). The crystalline second metal nanoparticles can be used to help carriers move more easily to the second electrode.

Specifically, in the preparation process of the second main gate electrode 11, a second printing electrode paste is printed on the second dielectric layer 9, and by sintering, the second printing electrode paste is burned through the second dielectric layer 9 to contact the doped layer 8, a metal material in the second printing electrode paste is dissolved in a glass frit, and is grown on the doped layer 8 through glass, and is recrystallized to form a crystalline second metal nanoparticle, so that the crystalline second metal nanoparticle includes the same metal as the metal material in the second main gate electrode 11; if the second printed electrode paste includes, for example, silver (Ag), the crystalline second metal nanoparticles may also include silver (Ag).

In addition, the morphology and distribution of the metal in the crystalline second metal nanoparticles are different from those in the second printed sintering layer, for example, the metal in the crystalline second metal nanoparticles is discretely distributed in island shape at the interface with the second main gate electrode 11 in the doping layer 8 (i.e., at the interface with the second connection point 16, the second connection gate line 17, and the second auxiliary gate line in the doping layer 8), and the metal in the second printed sintering layer is combined with the glass body after heat treatment, and a plurality of holes generated by solvent evaporation in the second printed electrode paste are formed in the second printed sintering layer and are filled with the second metal layer deposited later.

The second metal nanoparticles of the crystalline state are not located in the tunneling layer 2, so that the second metal nanoparticles of the crystalline state are prevented from damaging the tunneling layer 2 or the silicon substrate 1, and the performance of the solar cell is reduced.

Further, when the second main gate electrode 11 includes aluminum metal, the doped layer 8 has a eutectic layer 13 and a local back field 19 at the boundary with the second main gate electrode 11. The eutectic layer 13 has good conductivity, which is beneficial to forming firm ohmic contact, the local back field 19 can block the movement of electrons, reduce the recombination rate of the surface, reduce the light penetrating through the silicon substrate 1, and enhance the absorption of long wave.

Specifically, the p-type aluminum doping infiltration is formed during sintering, so that the p-type Si originally doped with boron forms a layer of p + -type Si with the thickness of several microns as a local back surface field 19, and the back surface recombination rate is reduced to improve the open-circuit voltage Voc of the battery; because of the difference of absorption coefficients of the silicon substrate 1, when the thickness is reduced, the absorption of the incident light by the second dielectric layer 9 is reduced, and the existence of the local back field 19 is helpful for the absorption of long-wave light which can reach the silicon substrate 1 with deeper depth, so the influence of the short-circuit current density is more obvious; the energy step difference between p and p + can also increase the open circuit voltage Voc, p + can form a low resistance ohmic contact and so the fill factor FF can also be improved.

In the present application, a first method for manufacturing a solar cell includes the following steps:

the method comprises the following steps: a silicon substrate 1 is provided.

Step two: a doped layer 8 is formed on one side surface (front surface or front surface) of the silicon substrate.

Step three: a tunneling layer 2 is provided on one side surface (back surface or rear surface) of the silicon substrate 1.

Step four: and depositing a first doped polysilicon layer 3 on one side of the tunneling layer 2 departing from the silicon substrate 1.

Step five: and depositing a first dielectric layer 4 on one side of the first doped polycrystalline silicon layer 3 departing from the tunneling layer 2.

Step six: printing first printing electrode slurry on one side of the first dielectric layer 4, which is far away from the first doped polycrystalline silicon layer 3, to form a first printing sintering layer, wherein the first printing electrode slurry is burnt through the first dielectric layer 4 to be connected with the first doped polycrystalline silicon layer 3, and crystalline first metal nano-particles 6 are formed at the junction of the first doped polycrystalline silicon layer 3 and the first printing sintering layer.

Step seven: and electroplating and depositing metal on the surface of the first printing sintering layer to form a first metal layer, wherein the first printing sintering layer and the first metal layer form the first main gate electrode 5.

Step eight: a plurality of first openings penetrating through the first dielectric layer 4 are formed in the first dielectric layer 4, metal is electroplated in the first openings to form first fine gate electrodes 7, each first fine gate electrode 7 is intersected with each first main gate electrode 5 and is electrically connected with the first main gate electrode 5, and the first fine gate electrodes 7 and the first main gate electrodes 5 form first electrodes.

Step nine: and depositing a second dielectric layer 9 on one side of the doped layer 8 departing from the silicon substrate 1.

Step ten: printing second printing electrode slurry on one side of the second dielectric layer 9, which is far away from the doped layer 8, forming a second printing sintering layer through sintering, wherein the second printing electrode slurry burns through the second dielectric layer 9 to be connected with the doped layer 8, and forming a second crystalline metal nanoparticle or eutectic layer 13 and a local back field 19 at the junction between the doped layer 8 and the second printing sintering layer.

Step eleven: and electroplating and depositing metal on the surface of the second printing sintering layer to form a second metal layer, wherein the second printing sintering layer and the second metal layer form the second main gate electrode 11.

Step twelve: a plurality of second openings penetrating through the second dielectric layer 9 are formed in the second dielectric layer 9, metal is electroplated in the second openings to form second fine gate electrodes 12, and each second fine gate electrode 12 is intersected with and electrically connected with each second main gate electrode 11 to form a second electrode.

Specifically, in the first step, the silicon substrate 1 may be obtained by cleaning, alkali texturing, and edge etching a silicon wafer, and a pyramid textured surface is formed on the front surface (front surface) of the silicon wafer after texturing.

Specifically, in the second step, boron on the front surface of the silicon substrate is diffused to form a doped layer;

the boron diffusion may be: the silicon substrate is diffused at a high temperature by a boron source, and a doped layer is formed on the front surface by the boron diffusion.

The boron source for boron diffusion can comprise boron tribromide, the diffusion temperature of boron diffusion ranges from 950 ℃ to 1000 ℃, and the diffusion time ranges from 1.5 to 2.5 hours.

Specifically, in step three, a tunneling layer 2 is grown on the back surface of the silicon substrate 1 by thermal oxidation.

Specifically, in the fourth step, silane and phosphine are introduced by LPCVD to deposit an amorphous silicon film doped with impurities on the side of the tunneling layer 2 away from the silicon substrate 1, and then the amorphous silicon film is annealed, wherein the annealing temperature is controlled to be 800-1000 ℃, and the annealing time is controlled to be 30 minutes, so that the amorphous silicon is crystallized into polycrystalline silicon, and a first doped polycrystalline silicon layer is formed.

When the first doped polycrystalline silicon layer is formed, an amorphous silicon film is formed on the doped layer, and the amorphous silicon film is removed, specifically, a chain type single-sided etching device is adopted, an HF solution is firstly adopted to remove an oxidation layer on the surface of the amorphous silicon film, and a KOH solution is adopted to etch and remove the amorphous silicon film wound on the front side.

Specifically, in the fifth step, a passivation film is deposited on one side of the first doped polysilicon layer 3 away from the tunneling layer 2 in a tubular PECVD manner to form a first dielectric layer 4.

Specifically, in the sixth step, a first printing electrode paste is printed on the first dielectric layer 4, the first printing electrode paste is burned through the first dielectric layer 4 to contact the first doped polysilicon layer 3, the metal material in the first printing electrode paste is dissolved into the glass frit, and the glass is grown on the first doped polysilicon layer 3 to recrystallize to form the crystalline first metal nanoparticle 6, so that the crystalline first metal nanoparticle 6 includes the same metal as the metal material in the first main gate electrode 5; if the first printed electrode paste comprises silver (Ag), for example, the crystalline first metal nanoparticles 6 may also comprise silver (Ag).

The first printing electrode paste may be silver paste or aluminum paste.

The sintering temperature is 750-900 ℃, and the heat treatment temperature is 250-500 ℃. For example, the sintering temperature may be 750 ℃, 800 ℃, 850 ℃ or 900 ℃.

Specifically, the step of forming the first opening in the first dielectric layer 4 and the step of forming the first main gate electrode 5 in the first dielectric layer 4 may not be sequentially performed, that is, the first opening may be formed first, and then the first main gate electrode 5 is formed, or the first main gate electrode 5 may be formed first, and then the first opening is formed in the first dielectric layer 4.

Specifically, in the eighth step, the deposited metal is further subjected to a heat treatment, and the temperature of the heat treatment may be 250 ℃, 300 ℃, 350 ℃, 400 ℃, 450 ℃ or 500 ℃.

Specifically, in the seventh step and the eighth step, the electrode paste used for forming the first metal layer is the same as the first fine gate electrode 7 paste. The first fine gate electrode 7 slurry may be silver slurry, aluminum slurry, silver-aluminum slurry, copper slurry or nickel slurry.

Specifically, in the ninth step, a passivation film is deposited on one side of the doping layer 8 away from the tunneling layer 2 in a tubular PECVD manner to form a second dielectric layer 9.

Further, before the step ten, depositing an antireflection layer 10 on a side of the second dielectric layer 9 facing away from the doped layer 8. When light is irradiated on the solar cell, the anti-reflection layer 10 may reduce reflection of light, enhancing utilization of light.

Further, in step ten, after the anti-reflection layer 10 is deposited on the second dielectric layer 9, the second main gate electrode 11 is burned through the anti-reflection layer 10 and the second dielectric layer 9 and extends into the doped layer 8 for connection.

Specifically, in step ten, when the second printing electrode paste includes metallic silver, after the second printing electrode paste is printed on the second dielectric layer 9, the second printing electrode paste burns through the second dielectric layer 9 to contact the doping layer 8, the metallic material in the second printing electrode paste is dissolved into the glass paste, and the glass grows on the doping layer 8, and recrystallization is performed to form crystalline second metallic nanoparticles, so that the crystalline second metallic nanoparticles include the same metallic silver (Ag) as the metallic material in the second main gate electrode 11.

In addition, the morphology and distribution of the metal in the crystalline second metal nanoparticles are different from those in the second printed sintering layer, for example, the metal in the crystalline second metal nanoparticles is discretely distributed in island shape at the interface with the second main gate electrode 11 in the doping layer 8 (i.e., at the interface with the second connection point 16, the second connection gate line 17, and the second auxiliary gate line in the doping layer 8), and the metal in the second printed sintering layer is combined with the glass body after heat treatment, and a plurality of holes generated by solvent evaporation in the second printed electrode paste are formed in the second printed sintering layer and are filled with the second metal layer deposited later. The second metal nanoparticles of the crystalline state are not located in the tunneling layer 2, so that the second metal nanoparticles of the crystalline state are prevented from damaging the tunneling layer 2 or the silicon substrate 1, and the performance of the solar cell is reduced.

Specifically, in step ten, when the second main gate electrode 11 includes aluminum metal, after printing a second printing electrode paste on the second dielectric layer 9, by sintering, the metal (e.g., Al) in the second printing electrode paste is a trivalent element and silicon is a tetravalent element, and aluminum diffuses into the doped layer 8 during the heat treatment process, so that the eutectic layer 13 and the local back field 19 are formed at the interface with the second main gate electrode 11. In the doped layer 8, there is no eutectic layer 13 and no local back field 19 at the interface with the second fine gate electrode 12. The eutectic layer 13 has good conductivity, which is beneficial to forming firm ohmic contact, the local back field 19 can block the movement of electrons, reduce the recombination rate of the surface, reduce the light penetrating through the silicon substrate 1, and enhance the absorption of long wave.

Specifically, the antireflection layer 10 is provided with a third opening penetrating through the second opening, and the second fine gate electrode 12 penetrates through the second opening and the third opening to be connected to the doping layer 8.

Specifically, in the twelfth step, the method further comprises performing heat treatment on the deposited metal, wherein the temperature of the heat treatment can be 250 ℃, 300 ℃, 350 ℃, 400 ℃, 450 ℃ or 500 ℃.

The second printed electrode paste may be a silver paste or an aluminum paste.

Specifically, in step eleven, step twelve, the electrode paste used for forming the second metal layer is the same as the second fine gate electrode 12 paste. The second fine gate electrode 12 slurry may be silver slurry, aluminum slurry, silver-aluminum slurry, copper slurry or nickel slurry.

Further specifically, the first fine gate electrode 7 paste may be the same as the second fine gate electrode 12 paste.

the method comprises the following steps: a silicon substrate 1 is provided.

Specifically, the silicon substrate 1 may be obtained by cleaning, alkali texturing, and edge etching a silicon wafer, and a pyramid textured surface is formed on the front surface (front surface) of the silicon wafer after texturing.

Step two: a doped layer 8 is formed on one side surface (front surface or front surface) of the silicon substrate 1.

Boron on the front side of the silicon substrate is diffused to form a doped layer;

Specifically, a tunneling layer 2 is grown on the back surface of the silicon substrate 1 by thermal oxidation.

Specifically, silane and phosphine are introduced by LPCVD to deposit an amorphous silicon film doped with impurities on one side of the tunneling layer 2, which is far away from the silicon substrate 1, and then the amorphous silicon film is annealed, wherein the annealing temperature is controlled to be 800-1000 ℃, and the annealing time is controlled to be 30 minutes, so that the amorphous silicon is crystallized into polycrystalline silicon to form a first doped polycrystalline silicon layer.

Specifically, a passivation film is deposited on one side of the first doped polysilicon layer 3 away from the tunneling layer 2 in a tubular PECVD mode to form a first dielectric layer 4.

Step six: printing first printing electrode slurry on one side of the first dielectric layer 4, which is far away from the first doped polycrystalline silicon layer 3, sintering to form a first printing sintering layer, wherein the first printing electrode slurry burns through the first dielectric layer 4 and extends into the first doped polycrystalline silicon layer 3, and crystalline first metal nano-particles 6 are formed at the junction of the first doped polycrystalline silicon layer 3 and the first printing sintering layer.

Specifically, a first printing electrode paste is printed on the first dielectric layer 4, the first printing electrode paste is burnt through the first dielectric layer 4 to contact the first doped polysilicon layer 3, a metal material in the first printing electrode paste is dissolved into a glass frit, and is recrystallized to form a crystalline first metal nanoparticle 6 by growing a glass on the first doped polysilicon layer 3, so that the crystalline first metal nanoparticle 6 includes the same metal as the metal material in the first main gate electrode 5; if the first printed electrode paste comprises silver (Ag), for example, the crystalline first metal nanoparticles 6 may also comprise silver (Ag).

The sintering temperature is 750 ℃ to 900 ℃, for example the sintering temperature may be 750 ℃, 800 ℃, 850 ℃ or 900 ℃.

The first printing electrode paste may be silver paste or aluminum paste.

Step eight: a plurality of first openings penetrating through the first dielectric layer 4 are formed in the first dielectric layer 4, metal is electroplated in the first openings, a first thin gate electrode 7 is formed through heat treatment, the first thin gate electrode 7 is connected with the first main gate electrode 5, and the first thin gate electrode 7 and the first main gate electrode 5 form a first electrode.

The temperature of the heat treatment is 250-500 ℃. For example, the temperature of the heat treatment may be 250 ℃, 300 ℃, 350 ℃, 400 ℃, 450 ℃ or 500 ℃.

The electrode paste used for forming the first metal layer is the same as the first fine gate electrode 7 paste. The first fine gate electrode 7 slurry may be silver slurry, aluminum slurry, silver-aluminum slurry, copper slurry or nickel slurry.

Further, after the ninth step and before the tenth step, depositing an antireflection layer 10 on a side of the second dielectric layer 9 facing away from the doped layer 8. When light is irradiated on the solar cell, the anti-reflection layer 10 may reduce reflection of light, enhancing utilization of light.

Step ten: and printing second printing electrode slurry on one side of the second dielectric layer 9, which is far away from the doped layer 8, sintering to form a second printing sintered layer, wherein the second printing electrode slurry is sintered through the second dielectric layer 9 and extends into the doped layer 8.

Further, after the anti-reflection layer 10 is deposited on the second dielectric layer 9, the second main gate electrode 11 burns through the anti-reflection layer 10 and the second dielectric layer 9 extends into the doped layer 8.

Specifically, when the second printing electrode paste includes metallic silver, after the second printing electrode paste is printed on the second dielectric layer 9, the second printing electrode paste burns through the second dielectric layer 9 to contact the doping layer 8, the metallic material in the second printing electrode paste is dissolved in the glass frit, and the glass grows on the doping layer 8 to recrystallize to form the crystalline second metallic nanoparticles, so that the crystalline second metallic nanoparticles include the same metallic silver (Ag) as the metallic material in the second main gate electrode 11.

Specifically, in step ten, when the second main gate electrode 11 includes aluminum metal, after printing a second printing electrode paste on the second dielectric layer 9, by sintering, the metal (e.g., Al) in the second printing electrode paste is a trivalent element and silicon is a tetravalent element, and aluminum diffuses into the doped layer 8 during the heat treatment process, so that the eutectic layer 13 and the local back field 19 are formed at the interface with the second main gate electrode 11. In the doped layer 8, there is no eutectic layer 13 and no local back field 19 at the interface with the second fine gate electrode 12.

The eutectic layer 13 has good conductivity, which is beneficial to forming firm ohmic contact, the local back field 19 can block the movement of electrons, reduce the recombination rate of the surface, reduce the light penetrating through the silicon substrate 1, and enhance the absorption of long wave.

Specifically, the sintering temperature is 750 ℃ to 900 ℃, for example, the sintering temperature may be 750 ℃, 800 ℃, 850 ℃ or 900 ℃.

The second printed electrode paste may be a silver paste or an aluminum paste.

Specifically, the temperature of the heat treatment is 250-500 ℃. For example, the temperature of the heat treatment may be 250 ℃, 300 ℃, 350 ℃, 400 ℃, 450 ℃ or 500 ℃.

Step twelve: and arranging a plurality of second openings penetrating through the second dielectric layer 9 on the second dielectric layer 9, electroplating metal in the second openings, forming second fine gate electrodes 12 through the heat treatment, and connecting the second fine gate electrodes 12 with the second main gate electrode 11 to form a second electrode.

Specifically, the electrode paste used for forming the second metal layer is the same as the second fine gate electrode 12 paste. The second fine gate electrode 12 slurry may be silver slurry, aluminum slurry, silver-aluminum slurry, copper slurry or nickel slurry.

Second solar cell

As shown in fig. 2, the solar cell provided by the present application includes a silicon substrate 1, a first electrode and a second electrode, and a second dielectric layer 9 is disposed on a front surface of the silicon substrate 1. The back surface of the silicon substrate 1 is sequentially provided with a tunneling layer 2, a first doped polycrystalline silicon layer 3 and a first dielectric layer 4 in a stacking mode, and the first electrode penetrates through the first dielectric layer 4 and extends into the first doped polycrystalline silicon layer 3. A first metal nanoparticle 6 in crystalline state is present in the first doped polysilicon layer 3 at the interface with the first electrode. The second electrode penetrates through the first medium layer 4 and is connected with the back surface of the silicon substrate 1.

Specifically, the first electrode includes a plurality of first main gate electrodes 5 and a plurality of first fine gate electrodes 7, and each first main gate electrode 5 intersects and is electrically connected to each first fine gate electrode 7. A first metal nanoparticle 6 in crystalline state is present in the first doped polysilicon layer 3 at the interface with the first main gate electrode 5. There are no crystalline first metal nanoparticles 6 at the interface with the first fine gate electrode 7 within the first doped polysilicon layer 3.

Specifically, the second electrode includes a second main gate electrode 11 and a second fine gate electrode 12, and the second main gate electrode 11 and the second fine gate electrode 12 intersect and are electrically connected.

Specifically, on the back surface of the silicon substrate 1, the tunneling layer 2 includes a plurality of tunneling units arranged at intervals, an area between adjacent tunneling units is a first area, and the first dielectric layer 4 covers the surface of the first doped polysilicon layer 3, the side surface of the first doped polysilicon layer 3 in the first area, the side surface of the tunneling unit, and the surface of the silicon substrate 1. The second main gate electrode 11 penetrates through the first dielectric layer 4 in the first region and is connected with the silicon substrate 1.

Further, when the second main gate electrode 11 includes silver metal, crystalline second metal nanoparticles are located at the interface with the second main gate electrode 11 in the silicon substrate 1. There are no crystalline second metal nanoparticles in the silicon substrate 1 at the interface with the second fine gate electrode 12.

Further, when the second main gate electrode 11 comprises aluminum metal, a eutectic layer 13 and a local back field 19 are provided in the silicon substrate 1 at the interface with the second main gate electrode 11. There is no eutectic layer 13 and no local back field 19 at the interface with the second fine gate electrode 12 within the silicon substrate 1.

Specifically, as shown in fig. 4, the first fine gate electrodes 7 are disposed at equal intervals, the first fine gate electrodes 7 include a plurality of first fine gate lines spaced apart by the first main gate electrodes 5 and the second main gate electrodes 11, and one end of each first fine gate line is connected to the first main gate electrode 5, and the other end of each first fine gate line is spaced apart by the second main gate electrode 11. The first fine gate electrode 7 perpendicularly intersects the first main gate electrode 5.

The plurality of second fine gate electrodes 12 are disposed at equal intervals, the second fine gate electrodes 12 include a plurality of second fine gate lines spaced apart by the first main gate electrode 5 and the second main gate electrode 11, and one end of each of the second fine gate lines is connected to the second main gate electrode 11, and the other end is spaced apart by the first main gate electrode 5. The second fine gate electrode 12 perpendicularly intersects the second main gate electrode 11.

The second fine gate electrodes 12 and the first fine gate electrodes 7 are alternately parallel to each other, that is, the first fine gate electrodes 7 and the second fine gate electrodes 12 are sequentially parallel to each other, and the second fine gate electrodes 12 are disposed between adjacent first fine gate electrodes 7. The second main gate electrodes 11 and the first main gate electrodes 5 are alternately parallel to each other, that is, the first main gate electrodes 5 and the second main gate electrodes 11 are sequentially parallel, and the second main gate electrodes 11 are disposed between adjacent first main gate electrodes 5.

In this embodiment, the tunneling layer 2, the first doped polysilicon layer 3, the first dielectric layer 4, the first electrode, and the crystalline first metal nanoparticles 6 may all refer to the description of the first solar cell, that is, the specific structures and materials of the tunneling layer 2, the first doped polysilicon layer 3, the first dielectric layer 4, the first electrode, and the crystalline first metal nanoparticles 6 of the solar cell may all refer to the contents described in the description of the first solar cell.

The material of the second electrode in this embodiment may be the same as or different from the material of the first electrode, and when the material of the second electrode is the same as that of the first electrode, the description may be made with reference to the material of the first electrode in the aforementioned first solar cell portion. When the materials of the second electrodes are different, the second printing electrode slurry is silver slurry or aluminum slurry. And the electrode slurry of the second metal layer is silver slurry, aluminum slurry, silver-aluminum slurry, copper slurry or nickel slurry. The electrode paste of the second fine gate electrode 12 is silver paste, aluminum paste, silver-aluminum paste, copper paste or nickel paste.

In the solar cell in the embodiment, since the front surface of the silicon substrate 1 is not provided with the second doped polysilicon layer and the second electrode, when light is irradiated on the solar cell, the light can be directly irradiated on the silicon substrate 1, so that the solar cell is simple in structure and high in light utilization rate. In addition, the first electrode and the second electrode are positioned on the same side of the silicon substrate 1, so that the using amount of electrode slurry can be greatly reduced, and the cost is low.

In the present application, a second method for manufacturing a solar cell includes the steps of:

the method comprises the following steps: a silicon substrate 1 is provided.

Step two: a second dielectric layer 9 is formed on one side surface (front surface or front surface) of the silicon substrate 1.

Step three: a tunneling layer 2 is disposed on one side surface of the silicon substrate 1.

Step six: printing first printing electrode slurry and second printing electrode slurry at intervals on one side of the first dielectric layer 4, which is far away from the first doped polycrystalline silicon layer 3, sintering to form a first printing sintering layer and a second printing sintering layer, wherein the first printing electrode slurry burns through the first dielectric layer 4 and extends into the first doped polycrystalline silicon layer 3, crystalline first metal nanoparticles 6 are formed at the junction of the first doped polycrystalline silicon layer 3 and the first printing sintering layer, and the second printing electrode slurry burns through the first dielectric layer 4 and is connected with the silicon substrate 1.

Step eight: and electroplating and depositing metal on the surface of the second printing sintering layer to form a second metal layer, wherein the second printing sintering layer and the second metal layer form the second main gate electrode 11.

Step nine: the method comprises the steps of arranging a plurality of first openings and second openings penetrating through the first dielectric layer 4 on the first dielectric layer 4, electroplating metal in the first openings and the second openings respectively, forming a first fine gate electrode 7 and a second fine gate electrode 12 through heat treatment, enabling the first fine gate electrode 7 to be intersected with and electrically connected with the first main gate electrode 5, enabling the first fine gate electrode 7 and the first main gate electrode 5 to form a first electrode, enabling the second fine gate electrode 12 to be intersected with and electrically connected with the second main gate electrode 11, and enabling the second fine gate electrode 12 and the second main gate electrode 11 to form a second electrode.

Step ten: and arranging a second dielectric layer 9 on the surface of one side of the silicon substrate 1, which is far away from the tunneling layer 2.

Specifically, in the first step, the silicon substrate 1 may be obtained by cleaning, alkali texturing and edge etching a silicon wafer, and a pyramid textured surface is formed on both sides of the silicon wafer after texturing.

Specifically, in the second step, the front surface of the silicon substrate is oxidized, and a silicon oxide layer is formed on the front surface of the silicon substrate, that is, the silicon oxide layer is a second dielectric layer.

Specifically, in step three, the tunneling layer 2 is grown on the back surface of the silicon substrate 1 by thermal oxidation.

Specifically, in step five, the first doped polysilicon layer 3 and the tunneling layer 2 are ablated at intervals on the surface of the first doped polysilicon layer 3 to expose the silicon substrate 1, so as to form a plurality of spaced first regions. And depositing a first dielectric layer on the surface of the first doped polycrystalline silicon layer, the side surface of the first doped polycrystalline silicon layer in the first region, the side surface of the tunneling layer and the surface of the silicon substrate.

Further, on the surface of the first doped polysilicon layer 3, the first doped polysilicon layer 3 and the tunneling layer 2 are ablated at intervals by using a laser technique to expose the silicon substrate 1, so that a plurality of spaced first regions are formed.

Specifically, in step six, printing a second printing electrode paste on the surface of the first dielectric layer 4 in the first region, and sintering to form a second printing sintered layer, wherein the second printing electrode paste is sintered through the second dielectric layer 9 to be connected with the silicon substrate 1.

Further, when the second main gate electrode 11 slurry includes silver metal, crystalline second metal nanoparticles are formed at the interface with the second main gate electrode 11 in the silicon substrate 1.

Further, when the second main gate electrode 11 slurry includes aluminum metal, a eutectic layer 13 and a local back field 19 are formed in the silicon substrate 1 at the interface with the second main gate electrode 11.

Specifically, in the eighth step, a plurality of second openings penetrating through the first dielectric layer 4 are formed in the first dielectric layer 4, metal is electroplated in the second openings, a second fine gate electrode 12 is formed through the heat treatment, and the second fine gate electrode 12 is connected with the silicon substrate 1; the second fine gate electrode 12 intersects and is electrically connected to the second main gate electrode 11 to form a second electrode.

the method comprises the following steps: a silicon substrate 1 is provided.

Specifically, the tunneling layer 2 is grown on the back surface of the silicon substrate 1 by thermal oxidation.

Specifically, on the surface of the first doped polysilicon layer 3, the first doped polysilicon layer 3 and the tunneling layer 2 are ablated at intervals to expose the silicon substrate 1, thereby forming a plurality of spaced first regions. And depositing a first dielectric layer on the surface of the first doped polycrystalline silicon layer, the side surface of the first doped polycrystalline silicon layer in the first region, the side surface of the tunneling layer and the surface of the silicon substrate.

Step six: printing first printing electrode slurry and second printing electrode slurry at intervals on one side of the first dielectric layer 4, which is far away from the first doped polycrystalline silicon layer 3, sintering to form a first printing sintering layer and a second printing sintering layer, wherein the first printing electrode slurry burns through the first dielectric layer 4 to enter the first doped polycrystalline silicon layer 3, crystalline first metal nano-particles 6 are formed at the junction of the first doped polycrystalline silicon layer 3 and the first printing sintering layer, and the second printing electrode slurry burns through the first dielectric layer 4 to be connected with the silicon substrate 1.

Specifically, a second printing electrode paste is printed on the surface of the first dielectric layer 4 in the first region, and is sintered to form a second printing sintered layer, wherein the second printing electrode paste is sintered through the second dielectric layer 9 to be connected with the silicon substrate 1.

Further, when the second printing electrode paste includes metallic silver, crystalline second metal nanoparticles are formed at the interface with the second printing sintering layer within the silicon substrate 1.

Further, when the second printing electrode paste includes aluminum metal, a eutectic layer 13 and a local back field 19 are formed in the silicon substrate 1 at the interface with the second printing sintering layer.

Step nine: the method comprises the steps of arranging a plurality of first openings and second openings penetrating through the first dielectric layer 4 on the first dielectric layer 4, electroplating metal in the first openings and the second openings respectively, forming first fine gate electrodes 7 and second fine gate electrodes 12 through heat treatment, enabling each first fine gate electrode 7 to be intersected with and electrically connected with each first main gate electrode 5, enabling the first fine gate electrodes 7 and the first main gate electrodes 5 to form first electrodes, enabling each second fine gate electrode 12 to be intersected with and electrically connected with each second main gate electrode 11, and enabling the second fine gate electrodes 12 and the second main gate electrodes 11 to form second electrodes.

Specifically, a plurality of second openings penetrating through the first dielectric layer 4 are arranged on the first dielectric layer 4, metal is electroplated in the second openings, a second fine gate electrode 12 is formed through the heat treatment, and the second fine gate electrode 12 is connected with the silicon substrate 1; each of the second fine gate electrodes 12 intersects and is electrically connected to each of the second main gate electrodes 11 to form a second electrode.

In this embodiment, the tunneling layer 2, the first doped polysilicon layer 3, the first dielectric layer 4, the first electrode, and the crystalline first metal nanoparticles 6 may all refer to the description of the first method for manufacturing a solar cell, that is, the materials, structures, and manufacturing methods of the tunneling layer 2, the first doped polysilicon layer 3, the first dielectric layer 4, the first electrode, and the crystalline first metal nanoparticles 6 of the solar cell may refer to the contents described in the first solar cell and the manufacturing method thereof.

Third solar cell

As shown in fig. 3, the present application provides a solar cell, a third solar cell, which is a variation of the second solar cell. The solar cell comprises a silicon substrate 1, a first electrode and a second electrode, wherein a second medium layer 9 is arranged on the front surface of the silicon substrate 1. The back surface of the silicon substrate 1 is sequentially provided with a tunneling layer 2, a first doped polycrystalline silicon layer 3 and a first dielectric layer 4 in a stacking mode, and the first electrode penetrates through the first dielectric layer 4 and extends into the first doped polycrystalline silicon layer 3; within the first doped polysilicon layer 3, at the interface with the first electrode, there are crystalline first metal nanoparticles 6.

Specifically, the first electrode comprises a plurality of first main gate electrodes 5 and a plurality of first fine gate electrodes 7, and each first main gate electrode 5 intersects and is connected with each first fine gate electrode 7; a first metal nanoparticle 6 in crystalline state is present in the first doped polysilicon layer 3 at the interface with the first main gate electrode 5.

Specifically, the second electrode includes second main gate electrodes 11 and second fine gate electrodes 12, and each of the second main gate electrodes 11 and each of the second fine gate electrodes 12 intersect and are connected.

On the surface of the tunneling layer 2, the first doped polysilicon layer 3 includes a plurality of first doped polysilicon units arranged at intervals; the region between the adjacent first doped polycrystalline silicon units is a second region; a second doped polysilicon unit is arranged in the second area, and a plurality of second doped polysilicon units form a second doped polysilicon layer 20; the first dielectric layer 4 covers the surfaces of the first doped polysilicon unit and the second doped polysilicon unit.

There is a region between the first doped polysilicon cell and the second doped polysilicon cell, i.e. the width of the second doped polysilicon layer 20 is smaller than the width of the second region, and the first doped polysilicon layer 3 is not in contact with the second doped polysilicon layer 20. The second doped polysilicon layer 20 is located in the middle of the second region.

The second main gate electrode 11 penetrates through the first dielectric layer 4 and is connected with the second doped polysilicon layer 20. The second doped polysilicon layer 20 has a conductivity type opposite to that of the first doped polysilicon layer 3, and the second main gate electrode 11 is different from the first main gate electrode 5.

Further, when the second main gate electrode 11 includes silver metal, crystalline second metal nanoparticles are formed at the boundary with the second main gate electrode 11 in the second doped polysilicon layer 20.

Further, when the second main gate electrode 11 includes aluminum metal, a eutectic layer 13 and a local back field 19 are formed in the second doped polysilicon layer 20 at the boundary with the second main gate electrode 11.

The material of the second electrode in this embodiment is the same as that of the second electrode in the aforementioned second solar cell, and reference may be made to the description of the aforementioned second solar cell section.

In this embodiment, the positional relationship between the second electrode and the first electrode on the surface of the first dielectric layer 4 is as shown in fig. 4, and the description of the second solar cell section can be referred to.

In the present application, a third method for manufacturing a solar cell includes the following steps:

the method comprises the following steps: a silicon substrate 1 is provided.

Step four: and sequentially depositing a first doped polycrystalline silicon unit and a second doped polycrystalline silicon unit at intervals on one side of the tunneling layer 2 departing from the silicon substrate 1, wherein the first doped polycrystalline silicon units form the first doped polycrystalline silicon layer 3, and the second doped polycrystalline silicon units form the second doped polycrystalline silicon layer 20.

Step five: a first dielectric layer 4 is deposited on the first doped polysilicon layer 3 and the second doped polysilicon layer 20 on the side away from the tunneling layer 2.

Step six: printing first printing electrode slurry on one side of the first dielectric layer 4, which is far away from the first doped polycrystalline silicon layer 3, sintering to form a first printing sintering layer, wherein the first printing electrode slurry is sintered through the first dielectric layer 4 and connected with the first doped polycrystalline silicon layer 3, and crystalline first metal nano-particles 6 are formed at the junction of the first doped polycrystalline silicon layer 3 and the first printing sintering layer.

Step eight: and printing second printing electrode slurry on one side of the first dielectric layer 4, which is far away from the second doped polycrystalline silicon layer 20, sintering to form a second printing sintered layer, wherein the second printing electrode slurry is sintered through the first dielectric layer 4 and extends into the second doped polycrystalline silicon layer 20 for connection.

Step nine: and electroplating and depositing metal on the surface of the second printing sintering layer to form a second metal layer, wherein the second printing sintering layer and the second metal layer form the second main gate electrode 11.

Step ten: a plurality of first openings and second openings penetrating through the first dielectric layer 4 are formed in the first dielectric layer 4, metal is electroplated in the first openings, metal is electroplated in the second openings, first fine gate electrodes 7 and second fine gate electrodes 12 are formed through heat treatment, each first fine gate electrode 7 is intersected with and electrically connected with each first main gate electrode 5, and each second fine gate electrode 12 is intersected with and electrically connected with each second main gate electrode 11.

Specifically, in step four, the plurality of first doped polysilicon cells are arranged at equal intervals; the second doped polysilicon units are arranged at equal intervals.

Specifically, in step five, the first dielectric layer 4 is deposited on the surface of the first doped polysilicon unit and the surface of the second doped polysilicon unit, that is, the first dielectric layer 4 covers the surfaces of the first doped polysilicon unit and the second doped polysilicon unit.

Specifically, in the sixth step, a first printing electrode paste is printed on the surface of the first dielectric layer 4 corresponding to the first doped polysilicon layer 3, and a first printing sintering layer is formed by sintering.

Specifically, in step eight, a second printing electrode paste is printed on the surface of the first dielectric layer 4 corresponding to the second doped polysilicon layer 20, and a second printing sintering layer is formed by sintering.

the method comprises the following steps: a silicon substrate 1 is provided.

Specifically, a plurality of first doped polysilicon units are arranged at equal intervals; the second doped polysilicon units are arranged at equal intervals.

Specifically, the first dielectric layer 4 is deposited on the surface of the first doped polysilicon unit and the surface of the second doped polysilicon unit, that is, the first dielectric layer 4 covers the surfaces of the first doped polysilicon unit and the second doped polysilicon unit.

Specifically, a first printing electrode paste is printed on the surface of the first dielectric layer 4 corresponding to the first doped polysilicon layer 3, and a first printing sintering layer is formed by sintering.

Step eight: and printing second printing electrode slurry on one side of the first dielectric layer 4, which is far away from the second doped polycrystalline silicon layer 20, sintering to form a second printing sintering layer, wherein the second printing electrode slurry is sintered through the first dielectric layer 4 and extends into the second doped polycrystalline silicon layer 20.

Step ten: arranging a plurality of first openings and second openings penetrating through the first dielectric layer 4 on the first dielectric layer 4, electroplating metal in the first openings, electroplating metal in the second openings, forming a first fine gate electrode 7 and a second fine gate electrode 12 through heat treatment, wherein the first fine gate electrode 7 is connected with the first main gate electrode 5, and the second fine gate electrode 12 is connected with the second main gate electrode 11.

Examples

The experimental methods used in the following examples are all conventional methods, unless otherwise specified.

Materials, reagents and the like used in the following examples are commercially available unless otherwise specified.

Example 1

The solar cell in this embodiment is a first solar cell, and includes the following steps:

the method comprises the following steps: a silicon substrate is provided.

The p-type crystalline silicon layer is obtained by cleaning, alkali texturing and edge etching of a silicon wafer, and a pyramid textured surface is formed on the front surface of the silicon wafer after texturing to obtain the p-type crystalline silicon layer.

Step two: formation of doped layer

Step three: forming a tunneling layer.

And in the second step, boron is diffused on the back surface (back surface) of the silicon substrate to form a back boron diffusion layer, then the back boron diffusion layer is removed, and a tunneling layer is grown on the back surface of the silicon substrate in a thermal oxidation mode, wherein the tunneling layer is a silicon oxide layer and has the thickness of 1 nm.

And the back boron diffusion layer is removed by using wet etching equipment.

Specifically, the back boron diffusion layer on the back can be removed through wet etching by using wet etching equipment, the wet etching equipment can realize single-side cleaning and etching, and the etching depth can be 1.5-3 microns.

Step four: forming a first doped polysilicon layer

And introducing silane and phosphine by adopting LPCVD (low pressure chemical vapor deposition) to deposit an in-situ phosphorus-doped amorphous silicon film on one side of the tunneling layer, which is far away from the silicon substrate, and annealing the amorphous silicon film, wherein the annealing temperature is controlled to be 800-1000 ℃, and the annealing time is controlled to be 30 minutes, so that the amorphous silicon is crystallized into polycrystalline silicon to form a first doped polycrystalline silicon layer. The thickness of the first doped polycrystalline silicon layer is 100 nm.

When the first doped polycrystalline silicon layer is formed, an amorphous silicon film is formed on the doped layer, and the amorphous silicon film is removed, specifically, a chain type single-sided etching device is adopted, an HF solution is firstly adopted to remove an oxidation layer on the surface of the amorphous silicon film on the front side, and a KOH solution is adopted to etch and remove the amorphous silicon film wound and plated on the front side.

Step five: a first dielectric layer is formed.

And depositing a silicon nitride film on one side of the first doped polycrystalline silicon layer, which is far away from the tunneling layer, by adopting a tubular PECVD mode to form a first dielectric layer, wherein the thickness of the first dielectric layer is 50 nm.

Step six: forming a first electrode

Printing first printing electrode slurry on one side of the first dielectric layer, which is far away from the first doped polycrystalline silicon layer, wherein the first printing electrode slurry is burnt through the first dielectric layer and connected with the first doped polycrystalline silicon layer through the sintering temperature of 900 ℃, and crystalline first metal nano-particles are formed at the junction of the first doped polycrystalline silicon layer and the first printing sintering layer. And electroplating and depositing electrode metal on the surface of the first printing sintering layer to form a first metal layer, wherein the first printing sintering layer and the first metal layer form the first main gate electrode.

And forming a plurality of first openings penetrating through the first dielectric layer on the first dielectric layer, electroplating first fine gate electrode metal in the first openings, and forming a first fine gate electrode through heat treatment at 250 ℃, wherein the first fine gate electrode is connected with the first doped polycrystalline silicon layer. The straight line where the first fine gate electrode is located is perpendicular to the straight line where the first main gate electrode is located, each first fine gate electrode is intersected with and electrically connected with each first main gate electrode, and the first fine gate electrode and the first main gate electrode form a first electrode.

The first main grid electrode comprises a plurality of first connecting points, a plurality of first connecting grid lines and a plurality of first auxiliary electrodes, the first connecting points and the first connecting grid lines are sequentially connected and extend, the first auxiliary electrodes are located at the connecting positions of the first main grid electrodes and the first thin grid electrodes, one end of each first auxiliary electrode is connected with the first connecting point or the first connecting grid line, and the other end of each first auxiliary electrode is connected with the first thin grid line. The first auxiliary electrode is arc-shaped, and the width of the first auxiliary electrode tends to decrease along the direction far away from the first connecting point or the first connecting grid line.

The first printing electrode slurry is Ag slurry.

The crystalline first metal nanoparticles include silver.

The first metal layer is formed to be Ni.

The first fine gate electrode is Ni.

The height of the first main gate electrode is 10 micrometers. The width was 100 microns.

The height of the first fine gate electrode is 5 micrometers. The width was 10 microns.

Step seven: forming a second dielectric layer

And depositing a silicon nitride film on the surface of one side of the doping layer, which is far away from the tunneling layer, in a tubular PECVD mode to form a second dielectric layer, wherein the thickness of the second dielectric layer is 50 nm.

Step eight: forming an anti-reflection layer

And depositing an anti-reflection layer on one side of the second dielectric layer, which is far away from the doped layer.

The anti-reflection layer is formed by combining an aluminum oxide layer and a silicon nitride layer, wherein the thickness of the aluminum oxide layer is 10nm, and the thickness of the silicon nitride layer is 60 nm.

Step nine: forming a second electrode

And printing second printing electrode slurry on the surface of one side of the anti-reflection layer, wherein the second printing electrode slurry is burnt through the anti-reflection layer and the second dielectric layer to extend into the doping layer to be connected through the sintering temperature of 900 ℃, and crystalline second metal nano particles are formed at the junction of the doping layer and the second printing sintering layer. And electroplating and depositing metal on the surface of the second printing sintering layer to form a second metal layer, wherein the second printing sintering layer and the second metal layer form the second main gate electrode.

And the anti-reflection layer is provided with a third opening penetrating through the anti-reflection layer, the second dielectric layer is provided with a plurality of second openings penetrating through the second dielectric layer, and the second openings are communicated with the third openings. Electroplating in the second opening and the third opening, and forming a second fine gate electrode through heat treatment at 250 ℃, wherein the second fine gate electrode is connected with the doped layer. The straight line where the second fine gate electrode is located is perpendicular to the straight line where the second main gate electrode is located, each second fine gate electrode is intersected with and electrically connected with each second main gate electrode, and the second fine gate electrode and the second main gate electrode form a second electrode.

The second printing electrode slurry is Ag slurry.

The crystalline second metal nanoparticles comprise silver.

And forming the second metal layer to be Ni.

The second fine gate electrode is Ni.

The height of the second main gate electrode is 10 micrometers. The width was 100 microns.

The height of the second fine gate electrode is 5 micrometers. The width is 10-microns.

Example 2

The solar cell in this embodiment is a second type of solar cell, and includes the following steps:

the method comprises the following steps: providing a silicon substrate (example 1 can be referred to for the specific process)

Step two: forming a second dielectric layer

And oxidizing the front surface of the silicon substrate, and forming a silicon oxide layer on the front surface of the silicon substrate, namely the silicon oxide layer is a second dielectric layer.

Step three: forming a tunneling layer (refer to example 1)

Step four: forming a first doped polysilicon layer (refer to example 1)

Step five: forming a first dielectric layer

And on the surface of the first doped polycrystalline silicon layer, the first doped polycrystalline silicon layer and the tunneling layer are ablated at intervals by laser to expose the silicon substrate, so that a plurality of spaced first regions are formed.

And depositing a first dielectric layer on the surface of the first doped polysilicon layer, the side surface of the first doped polysilicon layer in the first region, the side surface of the tunneling layer and the surface of the silicon substrate (the specific deposition process can refer to embodiment 1).

Step six: forming a first electrode and a second electrode

And printing first printing electrode slurry and second printing electrode slurry at intervals on one side of the first dielectric layer, which is far away from the first doped polycrystalline silicon layer, wherein the first printing electrode slurry is printed in the area, corresponding to the first dielectric layer, of the first doped polycrystalline silicon layer, and the second printing electrode slurry is printed in the area, corresponding to the first dielectric layer, of the first area. Then, the first printed sintered layer and the second printed sintered layer were formed by sintering at 800 ℃. The first printing electrode slurry burns through the first dielectric layer and extends into the first doped polycrystalline silicon layer, crystalline first metal nano particles are formed at the junction between the first doped polycrystalline silicon layer and the first printing sintering layer, the second printing electrode slurry burns through the first dielectric layer and extends into the silicon substrate, and a eutectic layer and a local back surface field are formed at the junction, close to the second printing sintering layer, in the silicon substrate.

And electroplating and depositing metal on the surface of the first printing sintering layer to form a first metal layer, wherein the first printing sintering layer and the first metal layer form the first main gate electrode.

And electroplating and depositing metal on the surface of the second printing sintering layer to form a second metal layer, wherein the second printing sintering layer and the second metal layer form the second main gate electrode.

The method comprises the steps of forming a plurality of first openings and second openings penetrating through a first dielectric layer on the first dielectric layer, electroplating metal in the first openings and the second openings respectively, forming first thin gate electrodes and second thin gate electrodes through heat treatment at 250 ℃, enabling each first thin gate electrode to be intersected with and electrically connected with each first main gate electrode, enabling the first thin gate electrodes and the first main gate electrodes to form first electrodes, enabling each second thin gate electrode to be intersected with and electrically connected with each second main gate electrode, and enabling the second thin gate electrodes and the second main gate electrodes to form second electrodes.

The first main gate electrode comprises a plurality of first connecting points and a plurality of first connecting grid lines, and two adjacent first connecting points are connected through the first connecting grid lines, namely the second connecting points are sequentially connected with the second connecting grid lines and extend to form the first main gate electrode; the first main grid electrodes are arranged in parallel at equal intervals.

The second main gate electrode comprises a plurality of second connection points and a plurality of second connection grid lines, and two adjacent second connection points are connected through the second connection grid lines, namely the second connection points are sequentially connected with the second connection grid lines and extend to form the second main gate electrode; the second main grid electrodes are arranged in parallel at equal intervals.

The second fine gate electrodes and the first fine gate electrodes are alternately parallel to each other. The second main gate electrodes and the first main gate electrodes are alternately parallel to each other.

The first thin gate electrodes are arranged at equal intervals, each first thin gate electrode comprises a plurality of first thin gate lines which are separated by the first main gate electrode and the second main gate electrode, one end of each first thin gate line is connected with the first main gate electrode, and the other end of each first thin gate line is separated by the second main gate electrode. The first fine gate electrode is perpendicularly intersected with the first main gate electrode.

The plurality of second thin gate electrodes are arranged at equal intervals, each second thin gate electrode comprises a plurality of second thin gate lines which are separated by the first main gate electrode and the second main gate electrode, one end of each second thin gate line is connected with the second main gate electrode, and the other end of each second thin gate line is separated by the first main gate electrode. The second fine gate electrode is perpendicularly intersected with the second main gate electrode.

The first printing electrode slurry is Ag slurry.

The crystalline first metal nanoparticles include silver.

And forming the first metal layer to be Cu.

The first fine gate electrode is Cu.

The height of the first main gate electrode is 30 micrometers. The width was 1000 microns.

The height of the first fine gate electrode is 15 micrometers. The width was 40 microns.

The second printing electrode slurry is Ag slurry.

And forming the second metal layer to be Cu.

The second fine gate electrode is Cu.

The height of the second main gate electrode is 30 micrometers, and the width of the second main gate electrode is 1000 micrometers.

The height of the second fine gate electrode is 15 microns, and the width of the second fine gate electrode is 40 microns.

Example 3

the method comprises the following steps: a silicon substrate is provided (example 1 may be referred to for a specific process).

Step two: forming a second dielectric layer

Step three: a tunneling layer is disposed on a side surface of the silicon substrate (the specific process can refer to example 1).

Step four: forming a first doped polysilicon layer and a second doped polysilicon layer

And sequentially depositing a first doped polycrystalline silicon unit and a second doped polycrystalline silicon unit at intervals on one side of the tunneling layer, which is far away from the silicon substrate.

The first doped polycrystalline silicon units form the first doped polycrystalline silicon layer; the plurality of second doped polysilicon cells form the second doped polysilicon layer.

The width of the first doped polycrystalline silicon layer is 600nm, and the width of the second doped polycrystalline silicon layer is 1200 nm.

The first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer are the same in height and are 250 nm.

Step five: formation of the first dielectric layer (see example 1 for details)

And depositing a first dielectric layer on the surfaces of one sides of the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer, which are far away from the tunneling layer. The first dielectric layer covers the surfaces of the first doped polysilicon unit and the second doped polysilicon unit.

Step six: formation of first electrode (see example 1 for details)

Printing first printing electrode slurry on one side of the first dielectric layer, which is far away from the first doped polycrystalline silicon layer, forming a first printing sintering layer through sintering at 900 ℃, wherein the first printing electrode slurry penetrates through the first dielectric layer and extends into the first doped polycrystalline silicon layer, and crystalline first metal nano-particles are formed at the junction of the first doped polycrystalline silicon layer and the first printing sintering layer. And electroplating and depositing metal on the surface of the first printing sintering layer to form a first metal layer, wherein the first printing sintering layer and the first metal layer form the first main gate electrode.

And arranging a plurality of first openings penetrating through the first dielectric layer on the first dielectric layer, wherein the first openings correspond to the first doped polycrystalline silicon units, electroplating first fine gate electrode slurry in the first openings, and forming first fine gate electrodes through heat treatment at 300 ℃. Each first fine gate electrode intersects and is electrically connected with each first main gate electrode.

The first printing electrode slurry is Ag slurry.

The crystalline first metal nanoparticles include silver.

And forming the first metal layer to be/Sn.

The first fine gate electrode is Sn.

Step seven: forming a second electrode

And printing second printing electrode slurry on the surface of one side of the first dielectric layer, which is far away from the second doped polycrystalline silicon layer, and sintering at 900 ℃ to form a second printing sintering layer, wherein the second printing electrode slurry is sintered through the first dielectric layer to be connected with the second doped polycrystalline silicon layer.

And arranging a plurality of second openings penetrating through the first dielectric layer on the first dielectric layer, wherein the second openings correspond to the second doped polysilicon units, electroplating second fine gate electrode slurry in the second openings, and forming second fine gate electrodes through heat treatment at 300 ℃. Each second fine gate electrode intersects and is electrically connected with each second main gate electrode.

The second printing electrode slurry is Ag slurry.

And forming the second metal layer to be Sn.

The second fine gate electrode is Sn.

The second main gate electrode has a height of 30 micrometers and a width of 100 micrometers.

In this embodiment, reference is made to example 2 for the arrangement of the first electrode and the second electrode on the surface of the first dielectric layer.

While embodiments of the present application have been described above in connection with specific embodiments thereof, the present application is not limited to the above-described embodiments and fields of application, which are intended to be illustrative, instructive, and not restrictive. Those skilled in the art, having the benefit of this disclosure, may effect numerous modifications thereto and changes may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A solar cell is characterized by comprising a silicon substrate, a tunneling layer, a first doped polycrystalline silicon layer, a first dielectric layer and a first electrode;

2. The solar cell of claim 1, wherein the crystalline first metal nanoparticles comprise a metal that is the same as the metal material in the first main gate electrode;

3. The solar cell of claim 1, wherein the crystalline first metal nanoparticles comprise metallic silver.

4. The solar cell of claim 1, wherein the first main gate electrode comprises a first printed frit layer and a first metal layer disposed in a stack,

5. The solar cell of claim 1, wherein the first main gate electrode further comprises a first auxiliary electrode at the intersection of the first main gate electrode and the first fine gate electrode; the cross-sectional area of the first auxiliary electrode in the direction perpendicular to the silicon substrate is gradually reduced in the direction away from the first main gate electrode and close to the first fine gate electrode.

6. The solar cell according to any one of claims 1 to 5, further comprising a second electrode of opposite polarity to the first electrode, the second electrode comprising a second main gate electrode and a second fine gate electrode, the second fine gate electrode intersecting and electrically connected to the second main gate electrode;

7. The solar cell of claim 6, wherein a doped layer is formed on a surface of the silicon substrate on a side facing away from the tunneling layer, and a second dielectric layer is disposed on a surface of the doped layer;

8. The solar cell of claim 7, wherein the second main gate electrode comprises metallic aluminum or metallic silver;

9. The solar cell of claim 7, wherein the second main gate electrode comprises a second printed sintered layer and a second metal layer arranged in a stack,

10. The solar cell of any of claim 6, wherein the first electrode and the second electrode are located on a same side of the silicon substrate.

11. The solar cell of claim 10, wherein the second fine gate electrode and the first fine gate electrode are alternately parallel to each other;

12. The solar cell of claim 10 or 11, wherein the tunneling layer comprises a plurality of tunneling units arranged at intervals on the surface of the silicon substrate,

the area between the adjacent tunneling units is a first area,

13. The solar cell of claim 12, wherein the second main gate electrode is connected to the silicon substrate through the first dielectric layer in the first region.

14. The solar cell of claim 10 or 11, wherein the first doped polysilicon layer comprises a plurality of first doped polysilicon cells spaced apart on a surface of the tunneling layer;

15. A preparation method of a solar cell is characterized by comprising the following steps:

providing a silicon substrate;

a metal is electrodeposited on a silicon substrate having a first opening.

16. The method of claim 15, further comprising heat treating the deposited metal; the sintering temperature is 750-900 ℃, and the heat treatment temperature is 250-500 ℃.

17. The method of claim 15 or 16, wherein a second dielectric layer is deposited on a surface of the silicon substrate on a side facing away from the tunneling layer;

18. The method of claim 17, wherein a second printed electrode paste is printed on the surface of the first dielectric layer in the first region, a second printed sintered layer is formed by the sintering, the second printed electrode paste is sintered through the second dielectric layer to connect with the doped layer, and a crystalline second metal nanoparticle or eutectic layer and a local back field are formed at the doped layer at the interface near the second printed sintered layer;

19. The method of claim 18, wherein a plurality of second openings are formed through the first dielectric layer on the first dielectric layer, a metal is electroplated and deposited in the second openings, a second fine gate electrode is formed by the thermal treatment, and the second fine gate electrode is connected with the silicon substrate;

20. The method of claim 15 or 16, wherein a first doped polysilicon cell and a second doped polysilicon cell are sequentially deposited at intervals on the surface of the tunneling layer,

21. The method of claim 20, wherein a second printing electrode paste is printed on the surface of the first dielectric layer corresponding to the second doped polysilicon layer and sintered to form a second printing sintered layer, the second printing electrode paste being sintered through the first dielectric layer to connect with the second doped polysilicon layer;

22. The method of claim 21, wherein a plurality of second openings are formed through the first dielectric layer on the first dielectric layer, metal is electroplated in the second openings, a second fine gate electrode is formed by the thermal treatment, and the second fine gate electrode is connected to the second doped polysilicon layer;