CN114188431B - Solar cell and preparation method thereof - Google Patents

Solar cell and preparation method thereof Download PDF

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Publication number
CN114188431B
CN114188431B CN202111234260.1A CN202111234260A CN114188431B CN 114188431 B CN114188431 B CN 114188431B CN 202111234260 A CN202111234260 A CN 202111234260A CN 114188431 B CN114188431 B CN 114188431B
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layer
gate electrode
doped polysilicon
electrode
metal
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CN114188431A (en
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李华
童洪波
张洪超
刘继宇
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Taizhou Longi Solar Technology Co Ltd
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Taizhou Longi Solar Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022433—Particular geometry of the grid contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System
    • H01L31/0288—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H01L31/182—Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/546—Polycrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The application discloses a solar cell, which comprises a silicon substrate, a tunneling layer, a first doped polysilicon layer, a first dielectric layer and a first electrode; a tunneling layer, a first doped polysilicon layer and a first dielectric layer are sequentially laminated on one side surface of the silicon substrate; the first electrode comprises a first main gate electrode and a first thin gate electrode, and the first thin gate electrode is intersected with and electrically connected with the first main gate electrode; the first main gate electrode burns through the first dielectric layer and extends into the first doped polysilicon layer; a first metal nano particle with a crystalline state at the junction of the first doped polysilicon layer and the first main gate electrode; a plurality of first openings penetrating through the first dielectric layer are formed in the first dielectric layer; the first thin gate electrode is electroplated on the first doped polysilicon layer exposed by the first opening. The application also provides a preparation method of the solar cell. The solar cell reduces the usage amount of the first main gate electrode slurry, and also enhances the bonding strength of the first main gate electrode and the first thin gate electrode.

Description

Solar cell and preparation method thereof
Technical Field
The application relates to the technical field of solar cells, in particular to a solar cell and a preparation method thereof.
Background
Crystalline silicon solar cells are currently the most popular solar cells in the market due to their high energy conversion efficiency. How to improve the conversion efficiency of crystalline silicon solar cells and components while reducing the production cost thereof is the biggest problem facing the industry. In the current large-scale silicon solar cell manufacturing, a screen printing mode is generally adopted to realize the metallization process of the silicon solar cell, but the screen printing precision is limited, the shape of a printed electrode is rough, the electrode is widened after printing and sintering, the formed grid is low in height and width, the effective light receiving area of a light receiving surface of the silicon solar cell is reduced, and in addition, the series resistance of the silicon solar cell manufactured by screen printing is large. With the expansion of the market and productivity of the photovoltaic industry, the continuous and stable supply of silver paste is a serious challenge, and the rising price of silver is also a cost competitive problem. Accordingly, studies on the use of plating methods have been actively conducted in recent years.
Because electroplating is difficult when the seed layer is not formed on the silicon wafer, it is required to form a conductive layer on the silicon wafer in advance for the subsequent electroplating process. The seed layer forming processes are separately performed in separate devices, for example, by sputtering or photo-induced plating, but the sputtering of the seed layer requires additional sputtering equipment in existing production lines, the sputtering of the desired pattern requires masking steps, the operation is complicated, it is difficult to reduce the production cost, and the sputtering of the seed layer is often not sufficiently conductive to carry the large current density generated by silicon-based solar cells, and it is necessary to be plated with other metals such as nickel and copper to enhance the conductivity.
Disclosure of Invention
In view of the above problems, the present application provides a solar cell and a method for manufacturing the same, in which the solar cell not only reduces the usage amount of the slurry of the first main gate electrode, but also enhances the bonding strength between the first main gate electrode and the first thin gate electrode, and increases the current collection efficiency.
The application provides a solar cell, which comprises a silicon substrate, a tunneling layer, a first doped polysilicon layer, a first dielectric layer and a first electrode;
the tunneling layer, the first doped polysilicon layer and the first dielectric layer are sequentially laminated on one side surface of the silicon substrate;
the first electrode comprises a first main gate electrode and a first thin gate electrode, and the first thin gate electrode is intersected with and electrically connected with the first main gate electrode;
the first main gate electrode burns through the first dielectric layer and stretches into the first doped polysilicon layer; a first metal nano particle with a crystalline state at the junction of the first doped polysilicon layer and the first main gate electrode;
a plurality of first openings penetrating through the first dielectric layer are formed in the first dielectric layer; the first thin gate electrode is electroplated on the first doped polysilicon layer exposed by the first opening.
Further, the crystalline first metal nanoparticles comprise the same metal as the metal material in the first main gate electrode;
the crystalline first metal nano particles are discretely distributed in island shapes at the junction of the first doped polysilicon layer and the first main gate electrode.
Further, the crystalline first metal nanoparticle comprises metallic silver.
Further, the first main gate electrode comprises a first printed sintered layer and a first metal layer which are stacked,
the first printed sintering layer penetrates through the first dielectric layer and stretches into the first doped polycrystalline silicon layer, and crystalline first metal nano particles are arranged at the junction of the first doped polycrystalline silicon layer and the first printed sintering layer;
the first metal layer is arranged on the surface of one side of the first printing sintering layer, which is away from the first doped polysilicon layer.
Further, the first main gate electrode further comprises a first auxiliary electrode, and the first auxiliary electrode is positioned at the intersection of the first main gate electrode and the first thin gate electrode; the first auxiliary electrode gradually decreases in cross-sectional area in a direction perpendicular to the silicon substrate in a direction away from the first main gate electrode and toward the first thin gate electrode.
Further, the semiconductor device further comprises a second electrode with the polarity opposite to that of the first electrode, wherein the second electrode comprises a second main gate electrode and a second thin gate electrode, and the second thin gate electrode is intersected with and electrically connected with the second main gate electrode;
the second main gate electrode further comprises a second auxiliary electrode, and the second auxiliary electrode is positioned at the intersection of the second main gate electrode and the second fine gate electrode; the second auxiliary electrode gradually decreases in cross-sectional area in a direction perpendicular to the silicon substrate in a direction away from the second main gate electrode and toward the second thin gate electrode.
Further, a doped layer is formed on the surface of one side, away from the tunneling layer, of the silicon substrate, and a second dielectric layer is arranged on the surface of the doped layer;
the second main gate electrode burns through the second dielectric layer and stretches into the doping layer;
a second metal nanoparticle having a crystalline state at the junction of the doped layer and the second main gate electrode; or a eutectic layer and a local back field are arranged at the junction of the doped layer and the second main gate electrode.
Further, the second main gate electrode comprises metal aluminum or metal silver;
when the second main gate electrode comprises metal aluminum, a eutectic layer and a local back field are arranged at the junction of the doped layer and the second main gate electrode;
When the second main gate electrode comprises metallic silver, second metal nano particles with crystalline state are arranged at the junction with the second main gate electrode in the doping layer; the crystalline second metal nano particles are discretely distributed at the junction of the doped layer and the second main gate electrode in an island shape.
Further, the second main gate electrode comprises a second printed sintered layer and a second metal layer which are stacked,
the second printed sintering layer penetrates through the second medium layer and stretches into the doping layer, and the junction between the second printed sintering layer and the second printed sintering layer in the doping layer is provided with the crystalline second metal nano particles;
the second metal layer is arranged on the surface of one side of the second printing sintering layer, which is away from the doped layer.
Further, the first electrode and the second electrode are positioned on the same side of the silicon substrate.
Further, the second thin gate electrodes and the first thin gate electrodes are alternately parallel to each other;
the second main gate electrode and the first main gate electrode are alternately parallel to each other.
Further, the tunneling layer comprises a plurality of tunneling units arranged at intervals on the surface of the silicon substrate,
The area between adjacent tunneling units is a first area,
the first dielectric layer covers the surface of the first doped polysilicon layer and the side surface of the first doped polysilicon layer, the side surface of the tunneling unit and the surface of the silicon substrate in the first region.
Further, the second main gate electrode penetrates through the first dielectric layer in the first area and is connected with the silicon substrate.
Further, on the surface of the tunneling layer, the first doped polysilicon layer includes a plurality of first doped polysilicon units arranged at intervals;
the area between the adjacent first doped polysilicon units is a second area;
a second doped polysilicon unit is arranged in the second region, and a plurality of second doped polysilicon units form a second doped polysilicon layer;
the first dielectric layer covers the surfaces of the first doped polysilicon unit and the second doped polysilicon unit;
the second main gate electrode penetrates through the first dielectric layer and is connected with the second doped polysilicon layer.
The application provides a preparation method of a solar cell, which comprises the following steps:
providing a silicon substrate;
providing a tunneling layer on one side surface of the silicon substrate;
Depositing a first doped polysilicon layer on a side of the tunneling layer facing away from the silicon substrate;
depositing a first dielectric layer on one side of the first doped polysilicon layer away from the tunneling layer;
printing a first printing electrode slurry on one side of the first medium layer, which is away from the first doped polysilicon layer, and sintering the first printing electrode slurry to enable the first printing electrode slurry to burn through the first medium layer to form a first printing sintering layer connected with the first doped polysilicon layer, and forming crystalline first metal nano particles at the junction of the first doped polysilicon layer and the first printing sintering layer;
a plurality of first openings penetrating through the first dielectric layer are formed in the first dielectric layer;
electroplating and depositing metal on the surface of the first printed sintering layer to form a first metal layer, wherein the first printed sintering layer and the first metal layer form the first main gate electrode;
a metal is electrodeposited on a silicon substrate having a first opening.
Further, the method also comprises the step of heat treating the deposited metal; the sintering temperature is 750-900 ℃, and the heat treatment temperature is 250-500 ℃.
Further, a second dielectric layer is deposited on the surface of one side of the silicon substrate away from the tunneling layer;
Ablating the first doped polysilicon layer and the tunneling layer at intervals on the surface of the first doped polysilicon layer to expose the silicon substrate, thereby forming a first region;
the first dielectric layer is deposited on the surface of the first doped polysilicon layer and the side surface of the first doped polysilicon layer, the side surface of the tunneling unit and the surface of the silicon substrate in the first region.
Further, printing second printing electrode slurry on the surface of the first dielectric layer in the first area, forming a second printing sintering layer through sintering, wherein the second printing electrode slurry is burnt through the second dielectric layer to be connected with a doped layer, and forming crystalline second metal nano particles or eutectic layers and a local back field at the junction of the doped layer close to the second printing sintering layer;
electroplating and depositing metal on the surface of the second printing sintering layer to form a second metal layer;
the second printed sintered layer and the second metal layer form a second main gate electrode.
Further, a plurality of second openings penetrating through the first dielectric layer are formed on the first dielectric layer, metal is electroplated and deposited in the second openings, a second thin gate electrode is formed through the heat treatment, and the second thin gate electrode is connected with the silicon substrate;
The second thin gate electrode intersects and is electrically connected with the second main gate electrode to form a second electrode.
Further, a first doped polysilicon unit and a second doped polysilicon unit are sequentially deposited on the surface of the tunneling layer at intervals,
a plurality of the first doped polysilicon units form the first doped polysilicon layer;
a plurality of the second doped polysilicon units form the second doped polysilicon layer;
the first dielectric layer is deposited on the surface of the first doped polysilicon unit and the surface of the second doped polysilicon unit.
Further, printing second printing electrode slurry on the surface of the first dielectric layer corresponding to the second doped polysilicon layer, and forming a second printing sintering layer through sintering, wherein the second printing electrode slurry is burnt through the first dielectric layer and connected with the second doped polysilicon layer;
electroplating and depositing metal on the surface of the second printing sintering layer to form a second metal layer;
the second printed sintered layer and the second metal layer form a second main gate electrode.
Further, a plurality of second openings penetrating through the first dielectric layer are formed on the first dielectric layer, metal is electroplated in the second openings, a second thin gate electrode is formed through the heat treatment, and the second thin gate electrode is connected with the second doped polysilicon layer;
The second thin gate electrode intersects and is electrically connected with the second main gate electrode to form a second electrode.
The present application provides a solar cell in which the plurality of crystalline first metal nanoparticles have a relatively low resistance, and carriers (e.g., electrons) moving from the silicon substrate to the first conductivity type semiconductor region through the tunneling layer may move (contact) directly onto the first main gate electrode through the crystalline first metal nanoparticles, or may transition in multiple steps between the crystalline first metal nanoparticles and the crystalline first metal nanoparticles, and move onto the first electrode. The crystalline first metal nanoparticles can therefore be used to help carriers to move more easily to the first electrode. And the crystalline first metal nano particles are positioned at the junction of the first doped polysilicon layer and the first main gate electrode, so that the performance of the tunneling layer is not damaged. The first thin gate electrode and the second thin gate electrode are both made by electroplating, and the tunneling layer is not damaged. And the electroplating process is adopted without forming a seed layer additionally, the main grid is used as a contact point, the binding force between the main grid and the polysilicon is better, and the drawing force between the main grid and the welding strip is improved.
Drawings
The drawings are included to provide a better understanding of the present application and are not to be construed as unduly limiting the present application. Wherein:
fig. 1 is a schematic structural diagram of a solar cell provided in the present application.
Fig. 2 is a schematic structural diagram of a solar cell provided in the present application.
Fig. 3 is a schematic structural diagram of a solar cell provided in the present application.
Fig. 4 is a schematic structural diagram of a light receiving surface or a backlight surface of the solar cell provided in the present application.
Fig. 5 is a schematic structural diagram of a light receiving surface or a backlight surface of the solar cell provided in the present application.
Fig. 6 is a schematic structural diagram of a light receiving surface or a backlight surface of the solar cell provided in the present application.
Description of the reference numerals
1-silicon substrate, 2-tunneling layer, 3-first doped polysilicon layer, 4-first dielectric layer, 5-first main gate electrode, 6-crystalline first metal nanoparticle, 7-first thin gate electrode, 8-doped layer, 9-second dielectric layer, 10-anti-reflection layer, 11-second main gate electrode, 12-second thin gate electrode, 13-eutectic layer, 14-first connection point, 15-first connection gate line, 16-second connection point, 17-second connection gate line, 18-first auxiliary electrode, 19-local back field, 20-second doped polysilicon layer.
Detailed Description
Exemplary embodiments of the present application are described below, including various details of embodiments of the present application to facilitate understanding, which should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present application. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness. The upper and lower positions in this application depend on the direction of incidence of the light, where the light is incident.
The present application provides three solar cells, in particular as follows.
First solar cell
As shown in fig. 1, the solar cell provided by the application includes a silicon substrate 1, a first electrode and a second electrode, a tunneling layer 2, a first doped polysilicon layer 3 and a first dielectric layer 4 are sequentially disposed on the back surface (rear surface) of the silicon substrate 1, and a doped layer 8 and a second dielectric layer 9 are sequentially formed on the front surface (front surface) of the silicon substrate 1. The first electrode penetrates through the first dielectric layer 4 and extends into the first doped polysilicon layer 3, and crystalline first metal nano particles 6 are arranged at the junction between the first doped polysilicon layer 3 and the first electrode. The second electrode penetrates through the second dielectric layer 9 and extends into the doped layer 8, and crystalline second metal nano particles or eutectic layers 13 and local back fields 19 are arranged at the junction between the doped layer 8 and the second electrode.
Specifically, the first electrode includes a plurality of first main gate electrodes 5 and a plurality of first thin gate electrodes 7, and each of the first main gate electrodes 5 intersects with and is electrically connected to each of the first thin gate electrodes 7. Inside the first doped polysilicon layer 3, the junction with the first main gate electrode 5 has crystalline first metal nanoparticles 6. Within the first doped polysilicon layer 3 there is no crystalline first metal nanoparticle 6 at the interface with the first thin gate electrode 7.
Specifically, the second electrode includes a plurality of second main gate electrodes 11 and a plurality of second thin gate electrodes 12, and each of the second main gate electrodes 11 intersects and is electrically connected to each of the second thin gate electrodes 12.
Further, when the second main gate electrode 11 includes silver metal, the junction with the second main gate electrode 11 in the doped layer 8 has crystalline second metal nanoparticles. Within the doped layer 8. The interface with the second fine gate electrode 12 is devoid of crystalline second metal nanoparticles.
Further, when the second main gate electrode 11 includes metal aluminum, a eutectic layer 13 and a local back field 19 are provided at the interface with the second main gate electrode 11 in the doped layer 8. Within the doped layer 8, there is no eutectic layer 13 and no local back field 19 at the interface with the second thin gate electrode 12.
In the present application, the silicon substrate 1 may be made of a single crystal or a polycrystalline semiconductor (e.g., single crystal or polycrystalline silicon). The front and/or back surface of the silicon substrate 1 may have an irregularly sized pyramid shape. The textured structure of the front surface can reduce the reflectivity of light incident through the front surface of the silicon substrate 1. Therefore, the light loss can be minimized, and the amount of light reaching the pn junction formed by the base region and the first doped polysilicon layer 3 or the doped layer 8 increases. The texturing in fig. 1 has been exemplified as being formed in the front and back surfaces of the silicon substrate 1, and thus reflection of light incident through both surfaces is effectively prevented. It is also possible to form a textured structure only in the front side of the silicon substrate 1, and to form no textured in the back side of the silicon substrate 1. In this case, the back surface of the silicon substrate 1, on which the tunneling layer 2 is formed, may be formed to have a smaller surface roughness than the front surface thereof, so that the tunneling layer 2 is formed more stably and more uniformly.
In the present application, the tunneling layer 2 may be disposed on the rear surface of the first doped polysilicon layer 3, and may be in direct contact with the first doped polysilicon layer 3. The tunneling layer 2 and the first doped polysilicon layer 3 formed thereon may be formed on the entire surface of the rear surface; or on a portion of the surface of the rear surface. The tunneling layer 2 may create a tunneling effect, acting as a kind of barrier for electrons and holes. After minority carriers are accumulated in a portion adjacent to the tunneling layer 2, only majority carriers having a certain level or higher of energy may pass through the tunneling layer 2. Majority carriers having energies of a certain level or higher can easily pass through the tunneling layer 2 by tunneling effect. Furthermore, the tunneling layer 2 serves as a diffusion barrier for preventing the dopant of the first doped polysilicon layer 3 from diffusing into the silicon substrate 1. The tunneling layer 2 may include various materials through which majority carriers can tunnel. For example, the tunneling layer 2 may include an oxide, a nitride, a semiconductor, and a conductive polymer.
Specifically, the tunneling layer 2 may be formed of a silicon oxide layer including silicon oxide (SiOx). The silicon oxide layer has excellent passivation characteristics and carriers can easily tunnel through the silicon oxide layer. In some embodiments, the tunneling layer 2 may be made of SiCx, or may be made of SiNx, hydrogenated SiNx, alOx, siON, or hydrogenated SiON. The thickness of the tunneling layer 2 may be 0.5nm to 2.5nm in order to sufficiently achieve the tunneling effect. The tunneling layer 2 may be formed by, for example, an oxidation process, an LPCVD process, or a PECVD deposition process.
In this application, the first doped polysilicon layer 3 is spaced apart from the silicon substrate 1 as shown in fig. 1, and the first doped polysilicon layer 3 includes a doped polysilicon material formed on the rear surface of the tunneling layer 2, has good conductivity, and can smoothly generate tunneling of carriers in the tunneling layer 2 made of oxide, and can further increase the open circuit voltage Voc of the solar cell. The thickness of the first doped polysilicon layer 3 may be 50nm to 500nm. The first doped polysilicon layer 3 may be formed by doping impurities into an amorphous silicon material or a polysilicon material by various methods such as deposition.
Specifically, the silicon substrate 1 may be doped with impurities of the first doped polysilicon layer 3 or the doped layer 8 at a low doping concentration. In this case, the silicon substrate 1 may have a lower doping concentration, a higher resistance, or a lower carrier concentration than one of the first doped polysilicon layer 3 and the doped layer 8, and the first doped polysilicon layer 3 or the doped layer 8 may have the same conductivity type as the silicon substrate 1.
Specifically, the doped layer 8 is provided on the opposite surface of the silicon substrate 1, for example, on the front surface of the silicon substrate 1 on which light is incident. The doped layer 8 may include impurities of opposite conductivity type to the semiconductor substrate. The doped layer 8 may be formed as a doped region formed by doping impurities in the doped layer 8 into a portion of the silicon substrate 1.
Specifically, for example, in the present application, the first doped polysilicon layer 3 (the impurity in the first doped polysilicon layer 3 and the silicon substrate 1 is of the p-type conductivity type) has the same conductivity type as the silicon substrate 1, and a Back Surface Field (BSF) region may be formed, which has a higher doping concentration than the silicon substrate 1 and forms a BSF. The doped layer 8 (the impurity in the doped layer 8 is of n-type conductivity type) has an opposite conductivity type to the silicon substrate 1, and an emitter region of a pn junction can be formed, minimizing the path of light entering the pn junction region.
In the present application, the first dielectric layer 4 and the second dielectric layer 9 may each have a single-layer or multi-layer film structure, and the first dielectric layer 4 may be a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or MgF 2 Film, mgF 2 Film, tiO 2 Film, and CeO 2 One or more of the films. An anti-reflection layer 10 may also be disposed on a surface of the second dielectric layer 9 facing away from the doped layer 8, and the anti-reflection layer 10 may be a silicon nitride layer.
Specifically, the first dielectric layer 4 may be a first passivation film, i.e., a silicon nitride film, may have a refractive index of 1.9 to 2.1, and may have a thickness of 30nm to 50 nm.
Specifically, the second dielectric layer 9 may be a second passivation film, and may be formed of a double layer structure having an aluminum oxide film and a silicon nitride film sequentially stacked on the doping layer 8. In this case, the aluminum oxide film may have a refractive index of 1.5 to 1.7 and a thickness of 5nm to 10 nm. The silicon nitride film may have a refractive index of 1.9 to 2.1 and a thickness of 70nm to 120 nm.
In this application, the height of the first thin gate electrode 7 may be 15 micrometers or less, for example, less than 10 micrometers, and the width is less than 35 micrometers, and the height difference between the first main gate electrode 5 and the first thin gate electrode 7 is 5-35 micrometers, so that the area and the amount of the electrode arrangement can be reduced by depositing the metal electrode with low resistivity, and the production cost can be reduced.
In this application, the first main gate electrode 5 burns through the first dielectric layer 4 and extends into the first doped polysilicon layer 3, and the opening burned out in the first dielectric layer 4 is a first sintering opening. A plurality of first openings penetrating through the first dielectric layer 4 are formed in the first dielectric layer 4; the first thin gate electrode 7 is electroplated on the first doped polysilicon layer exposed by the first opening, that is, a plurality of first windows (the first windows comprise first openings and first sintering openings) are formed in the first dielectric layer 4, the first thin gate electrode 7 penetrates through the first openings, and the first main gate electrode 5 penetrates through the first sintering openings and is connected with the first doped polysilicon layer 3.
In this application, the first main gate electrode 5 and the first thin gate electrode 7 have a double-layer or multi-layer structure, and the number of layers of the first main gate electrode 5 is greater than that of the first thin gate electrode 7. The first thin gate electrode 7 may include at least two or more of aluminum, copper, silver, gold, and/or nickel, tungsten, titanium, and cobalt. The first main gate electrode 5 includes therein at least one of nickel (Ni), copper (Cu), silver (Ag), aluminum (Al), tin (Sn), zinc (Zn), indium (In), titanium (Ti), and gold (Au), and combinations thereof, including but not limited thereto.
Specifically, the first main gate electrode 5 includes a first printed sintered layer and a first metal layer that are stacked, where the first printed sintered layer extends into the first doped polysilicon layer 3 through the first dielectric layer 4, and the junction between the first doped polysilicon layer 3 and the first printed sintered layer has the crystalline first metal nanoparticles 6; the first metal layer is arranged on the surface of one side of the first printing sintering layer, which faces away from the first doped polysilicon layer 3. The first metal layer may be a plurality of metal layers stacked. The first printed sintering layer is different from the metal contained in the first metal layer, for example, the metal in the first printed sintering layer is silver, and the metal in the first metal layer can be Ni/Cu/Sn, so that the high-cost silver consumption can be saved, and the cost of electrode materials is reduced. The first thin gate electrode 7 may be a plurality of metal layers stacked. The first metal layer may be the same as the first thin gate electrode 7.
Specifically, the electrode paste forming the first printed sintered layer is silver paste or aluminum paste.
Specifically, the electrode slurry for forming the first metal layer is silver slurry, aluminum slurry, silver-aluminum slurry, copper slurry or nickel slurry.
Specifically, the electrode paste forming the first thin gate electrode 7 is silver paste, aluminum paste, silver aluminum paste, copper paste or nickel paste.
In this application, as shown in fig. 5, the first main gate electrode 5 includes a plurality of first connection points 14 and a plurality of first connection gate lines 15, and two adjacent first connection points 14 are connected by the first connection gate lines 15, that is, the first connection points 14 are sequentially connected to and extend from the first connection gate lines 15, so as to form the first main gate electrode 5; a plurality of the first main gate electrodes 5 are arranged in parallel at equal intervals.
Specifically, the width of the first connection point 14 is larger than the width of the first connection gate line 15, the first connection points 14 are arranged discontinuously in a dot shape, and the single area is 0.5-10mm 2 . The first connection point 14 is a welding point, and the cross section of the first connection point 14 may be rectangular, circular, oval, or the like. The specific dimensions of the first connection point 14 may be, for example, 1.2mm by 1mm, 0.7mm by 0.8mm, 1mm by 0.5mm.
Specifically, a plurality of the first thin gate electrodes 7 are arranged in parallel at equal intervals, the first thin gate electrodes 7 comprise a plurality of first thin gate lines spaced apart by the first main gate electrodes 5, two ends of the first thin gate lines are connected with the first main gate electrodes 5, specifically, two ends of part of the first thin gate lines are connected with the first connecting gate lines 15, and two ends of part of the first thin gate lines are connected with the first connecting points 14.
The first thin gate electrode 7 perpendicularly intersects the first main gate electrode 5.
In this application, as shown in fig. 6, the first main gate electrode 5 further includes a first auxiliary electrode 18, where the first auxiliary electrode 18 is located at the intersection of the first main gate electrode 5 and the first thin gate electrode 7, and one end of the first auxiliary electrode 18 is connected to the first connection point 14 or the first connection gate line 15, and the other end is connected to the first thin gate line; the first auxiliary electrode 18 can strengthen the connection between the first thin gate electrode 7 and the first main gate electrode 5, avoid or reduce the possibility that the first thin gate electrode 7 is disconnected by welding, and improve the performance and reliability of the solar cell.
Specifically, the shape of the first auxiliary electrode 18 may be arc-shaped, V-shaped, U-shaped, etc., including but not limited to. Preferably, the first auxiliary electrode 18 has an arc shape, and the cross-sectional area of the first auxiliary electrode 18 in the direction perpendicular to the silicon substrate gradually decreases in the direction away from the first main gate electrode 5 and toward the first thin gate electrode 7; i.e. the cross-sectional area of the first auxiliary electrode 18 in the direction perpendicular to the silicon substrate tends to decrease in the direction away from the first connection point 14 or the first connection gate line 15.
The plurality of crystalline first metal nanoparticles 6 have a relatively low resistance compared to the first doped polysilicon layer 3 made of doped polysilicon. Since the crystalline first metal nanoparticles 6 are located within the first doped polysilicon layer 3 at the interface with the first main gate electrode 5, carriers (e.g., electrons) moving from the silicon substrate 1 through the tunneling layer 2 to the first doped polysilicon layer 3 may move (contact) directly to the first main gate electrode 5 through the crystalline first metal nanoparticles 6 or may move to the first electrode at a multi-step transition between the crystalline first metal nanoparticles 6 and the crystalline first metal nanoparticles 6 (through tunneling of a glass layer between the crystalline first metal nanoparticles 6 and the first main gate electrode 5). The crystalline first metal nanoparticles 6 may thus be used to help carriers to move more easily to the first electrode.
Specifically, in the preparation process of the first main gate electrode 5, a first printing electrode slurry is printed on the first dielectric layer 4, the first printing electrode slurry is burnt through the first dielectric layer 4 to be in contact with the first doped polysilicon layer 3 through sintering, a metal material in the first printing electrode slurry is dissolved into a glass frit, grows onto the first doped polysilicon layer 3 through glass, and is recrystallized to form crystalline first metal nano particles 6, so that the crystalline first metal nano particles 6 comprise the same metal as the metal material in the first main gate electrode 5; if the first printed electrode paste comprises, for example, silver (Ag), the crystalline first metal nanoparticles 6 may also comprise silver (Ag).
In addition, the morphology and distribution of the metal in the crystalline first metal nanoparticles 6 are different from those in the first printed sintered layer, for example, the metal in the crystalline first metal nanoparticles 6 is discretely distributed in island shape in the first doped polysilicon layer 3 at the interface with the first main gate electrode 5 (i.e. the interface with the first connection point 14, the first connection gate line 15 and the first auxiliary gate line in the first doped polysilicon layer 3), and the metal in the first printed sintered layer is bonded with the glass body after heat treatment, and many holes generated due to the volatilization of the solvent in the first printed electrode paste are formed in the first printed sintered layer, and these holes are filled with the subsequently deposited first metal layer.
The plurality of crystalline first metal nanoparticles 6 are not located in the tunneling layer 2, so that the crystalline first metal nanoparticles 6 do not damage the tunneling layer 2 or the silicon substrate 1, and the performance of the solar cell is reduced.
In this application, the height of the second fine gate electrode 12 may be 15 micrometers or less, for example, less than 10 micrometers, and the width is less than 35 micrometers, and the height difference between the second main gate electrode 11 and the second fine gate electrode 12 is 5-35 micrometers, so that the area and the amount of the electrode arrangement can be reduced by depositing the metal electrode with low resistivity, and the production cost can be reduced.
The second main gate electrode 11 burns through the second dielectric layer 9 and stretches into the doped layer 8, and an opening burnt out by the second dielectric layer 9 is a second sintering opening. A plurality of second openings penetrating through the second dielectric layer 9 are also formed in the second dielectric layer 9; the second fine gate electrode 12 is electroplated on the doped layer 8 exposed by the second opening, that is, a plurality of second windows (the second windows include a second opening and a second sintering opening) are provided on the second dielectric layer 9, the second fine gate electrode 12 penetrates through the second opening, and the second main gate electrode 11 penetrates through the second sintering opening and is connected with the doped layer 8.
In this application, the second main gate electrode 11 and the second thin gate electrode 12 have a double-layer or multi-layer structure, and the number of layers of the second main gate electrode 11 is greater than that of the second thin gate electrode 12. The second thin gate electrode 12 may include at least two or more of aluminum, copper, silver, gold, and/or nickel, tungsten, titanium, cobalt. The second main gate electrode 11 includes therein at least one of nickel (Ni), copper (Cu), silver (Ag), aluminum (Al), tin (Sn), zinc (Zn), indium (In), titanium (Ti), and gold (Au), and combinations thereof, including but not limited thereto.
Specifically, the second main gate electrode 11 includes a second printed sintered layer and a second metal layer that are stacked, where the second printed sintered layer extends into the doped layer 8 through the second dielectric layer 9, and in the doped layer 8, a junction with the second printed sintered layer has the crystalline second metal nanoparticles; the second metal layer is arranged on the surface of the second printed sintered layer facing away from the doped layer 8. The second metal layer may be a plurality of metal layers stacked. The second printed sintering layer is different from the metal contained in the second metal layer, for example, the metal in the second printed sintering layer is silver, and the metal in the second metal layer can be Ni/Cu/Sn, so that the arrangement can save the silver consumption with high cost and reduce the cost of electrode materials. The second thin gate electrode 12 may be a plurality of metal layers stacked. The second metal layer may be the same as the second thin gate electrode 12.
Specifically, the electrode paste forming the second printed sintered layer is silver paste or aluminum paste.
Specifically, the electrode slurry for forming the second metal layer is silver slurry, aluminum slurry, silver-aluminum slurry, copper slurry or nickel slurry.
Specifically, the electrode paste forming the second fine gate electrode 12 is silver paste, aluminum paste, silver aluminum paste, copper paste or nickel paste.
In this application, as shown in fig. 5, the second main gate electrode 11 includes a plurality of second connection points 16 and a plurality of second connection gate lines 17, and two adjacent second connection points 16 are connected by the second connection gate lines 17, that is, the second connection points 16 are sequentially connected to and extend from the second connection gate lines 17, so as to form the second main gate electrode 11; a plurality of the second main gate electrodes 11 are arranged in parallel at equal intervals.
Specifically, the width of the second connection point 16 is larger than the width of the second connection gate line 17, the second connection point 16 is discontinuously arranged in a dot shape, and the single area is 0.5-10mm 2 . The second connection point 16 is a welding point, and the cross section of the second connection point 16 may be rectangular, circular, oval, or the like. The specific dimensions of the second connection point 16 may be, for example, 1.2mm by 1mm, 0.7mm by 0.8mm, 1mm by 0.5mm.
The second thin gate electrodes 12 are arranged in parallel and at equal intervals, the second thin gate electrodes 12 include a plurality of second thin gate lines spaced apart by the second main gate electrode 11, and two ends of the second thin gate lines are connected with the second main gate electrode 11, specifically, two ends of part of the second thin gate lines are connected with the second connection gate line 17, and two ends of part of the second thin gate lines are connected with the second connection point 16.
The second thin gate electrode 12 perpendicularly intersects the second main gate electrode 11.
In this application, the second main gate electrode 11 further includes a second auxiliary electrode, where the second auxiliary electrode is located at the intersection of the second main gate electrode 11 and the second thin gate electrode 12, and one end of the second auxiliary electrode is connected to the second connection point 16 or the second connection gate line 17, and the other end of the second auxiliary electrode is connected to the second thin gate line; the arrangement of the second auxiliary electrode can strengthen the connection between the second thin gate electrode 12 and the second main gate electrode 11, avoid or reduce the possibility that the second thin gate electrode 12 is disconnected by welding, and improve the performance and reliability of the solar cell.
Specifically, the shape of the second auxiliary electrode may be arc-shaped, V-shaped, U-shaped, etc., including but not limited to. Preferably, the second auxiliary electrode has an arc shape, and the cross-sectional area of the second auxiliary electrode in the direction perpendicular to the silicon substrate 1 gradually decreases in the direction away from the second main gate electrode 5 toward the second thin gate electrode 12. I.e. the cross-sectional area of the second auxiliary electrode in a direction perpendicular to the silicon substrate 1 tends to decrease in a direction away from the second connection point 16 or the second connection gate line 17.
The projections of the first main gate electrode 5 and the second main gate electrode 11, and the first thin gate electrode 7 and the second thin gate electrode 12 in the thickness direction of the silicon substrate 1 are not coincident, so that the first window and the second window are asymmetrically arranged, and the mechanical strength of the silicon substrate 1 is obviously reduced by avoiding symmetrically arranging openings on two sides of a substrate in an opening process.
When the second main gate electrode 11 includes silver metal, crystalline second metal nanoparticles are provided at the interface with the second main gate electrode 11 in the doped layer 8. A plurality of the crystalline second metal nanoparticles have a relatively low resistance compared to the doped layer 8 made of doped polysilicon. Since the crystalline second metal nanoparticles are located within the doped layer 8 at the interface with the second main gate electrode 11, carriers (e.g., electrons) moving from the silicon substrate 1 through the tunneling layer 2 to the doped layer 8 may move (contact) directly to the second main gate electrode 11 through the crystalline second metal nanoparticles, or may move to the second electrode in a multi-step transition between the crystalline second metal nanoparticles and the crystalline second metal nanoparticles (through tunneling of a glass layer between the crystalline second metal nanoparticles and the second main gate electrode 11). The crystalline second metal nanoparticles can therefore be used to help carriers to move more easily to the second electrode.
Specifically, in the preparation process of the second main gate electrode 11, a second printing electrode slurry is printed on the second dielectric layer 9, the second printing electrode slurry is burned through the second dielectric layer 9 to contact with the doped layer 8 through sintering, a metal material in the second printing electrode slurry is dissolved into a glass frit, and is grown onto the doped layer 8 through glass, and is recrystallized to form crystalline second metal nano-particles, so that the crystalline second metal nano-particles comprise the same metal as the metal material in the second main gate electrode 11; if the second printed electrode paste comprises, for example, silver (Ag), the crystalline second metal nanoparticles may also comprise silver (Ag).
In addition, the morphology and distribution of the metal in the crystalline second metal nanoparticles are different from those in the second printed sintered layer, for example, the metal in the crystalline second metal nanoparticles is discretely distributed in island form in the doped layer 8 at the interface with the second main gate electrode 11 (i.e. the interface between the doped layer 8 and the second connection point 16, the second connection gate line 17 and the second auxiliary gate line), and the metal in the second printed sintered layer is bonded with the glass body after heat treatment, and a plurality of holes generated due to the volatilization of the solvent in the second printed electrode paste are formed in the second printed sintered layer, and these holes are filled with the subsequently deposited second metal layer.
The plurality of crystalline second metal nanoparticles are not located in the tunneling layer 2, so as to prevent the crystalline second metal nanoparticles from damaging the tunneling layer 2 or the silicon substrate 1, and reduce the performance of the solar cell.
Further, when the second main gate electrode 11 includes metal aluminum, a eutectic layer 13 and a local back field 19 are provided at the interface with the second main gate electrode 11 in the doped layer 8. The eutectic layer 13 has good conductivity, is favorable for forming firm ohmic contact, and the local back field 19 can block movement of electrons, reduce the recombination rate of the surface, reduce light penetration through the silicon substrate 1 and enhance absorption of long waves.
Specifically, the aluminum doped infiltration of p-type during sintering forms p+ -type Si that would otherwise be boron doped to form one layer of micron thick p+ -type Si as the local back field 19 to reduce the back surface recombination rate to increase the open circuit voltage Voc of the cell; because the absorption coefficient of the silicon substrate 1 is poor, when the thickness is reduced, the absorption of the second dielectric layer 9 to the incident light is reduced, and the existence of the local back surface field 19 helps the absorption of the long wave light which can reach the depth of the silicon substrate 1 and is deeper, so that the influence of the short circuit current density is more obvious; the energy level difference of p and p+ can also raise the open circuit voltage Voc, and p+ can form ohmic contact with low resistance so that the fill factor FF can also be improved.
In the application, the first preparation method of the solar cell comprises the following steps:
step one: a silicon substrate 1 is provided.
Step two: a doped layer 8 is formed on one side surface (front or front surface) of the silicon substrate.
Step three: a tunneling layer 2 is provided on one side surface (back surface or rear surface) of the silicon substrate 1.
Step four: a first doped polysilicon layer 3 is deposited on the side of the tunneling layer 2 facing away from the silicon substrate 1.
Step five: a first dielectric layer 4 is deposited on the side of the first doped polysilicon layer 3 facing away from the tunneling layer 2.
Step six: printing a first printing electrode slurry on one side of the first dielectric layer 4 away from the first doped polysilicon layer 3 to form a first printing sintering layer, wherein the first printing electrode slurry burns through the first dielectric layer 4 to be connected with the first doped polysilicon layer 3, and crystalline first metal nano particles 6 are formed at the junction between the first doped polysilicon layer 3 and the first printing sintering layer.
Step seven: and electroplating and depositing metal on the surface of the first printed sintering layer to form a first metal layer, wherein the first printed sintering layer and the first metal layer form the first main gate electrode 5.
Step eight: a plurality of first openings penetrating through the first dielectric layer 4 are formed on the first dielectric layer 4, metal is electroplated in the first openings to form first thin gate electrodes 7, each first thin gate electrode 7 is intersected with and electrically connected with each first main gate electrode 5, and the first thin gate electrodes 7 and the first main gate electrodes 5 form first electrodes.
Step nine: a second dielectric layer 9 is deposited on the side of the doped layer 8 facing away from the silicon substrate 1.
Step ten: printing second printing electrode slurry on one side of the second dielectric layer 9 away from the doped layer 8, forming a second printing sintered layer through sintering, wherein the second printing electrode slurry is burnt through the second dielectric layer 9 to be connected with the doped layer 8, and forming crystalline second metal nano particles or eutectic layers 13 and local back fields 19 at the junction between the doped layer 8 and the second printing sintered layer.
Step eleven: and electroplating and depositing metal on the surface of the second printed sintering layer to form a second metal layer, wherein the second printed sintering layer and the second metal layer form the second main gate electrode 11.
Step twelve: a plurality of second openings penetrating through the second dielectric layer 9 are formed on the second dielectric layer 9, metal is electroplated in the second openings to form second thin gate electrodes 12, and each second thin gate electrode 12 is intersected with and electrically connected with each second main gate electrode 11 to form a second electrode.
Specifically, in the first step, the silicon substrate 1 may be obtained by cleaning a silicon wafer, alkali texturing, and edge etching, where a pyramidal textured surface is formed on the front surface (front surface) of the silicon wafer after texturing.
Specifically, in the second step, boron on the front surface of the silicon substrate diffuses to form a doped layer;
the boron diffusion therein may be: the silicon substrate is diffused under high temperature conditions by a boron source, and a doped layer is formed on the front surface by the boron diffusion.
The boron source for boron diffusion may comprise boron tribromide, and the diffusion temperature of the boron diffusion may be in the range of 950-1000 ℃ and the diffusion time may be in the range of 1.5-2.5 hours.
Specifically, in step three, a tunneling layer 2 is grown on the back surface of the silicon substrate 1 by thermal oxidation.
Specifically, in the fourth step, silane and phosphine are introduced into the tunnel layer 2 by LPCVD to deposit an impurity doped amorphous silicon film on the side facing away from the silicon substrate 1, and then the amorphous silicon film is annealed, wherein the annealing temperature is controlled to be 800-1000 ℃, and the annealing time is controlled to be 30 minutes, so that the amorphous silicon is crystallized into polysilicon, and a first doped polysilicon layer is formed.
When the first doped polysilicon layer is formed, an amorphous silicon film is formed on the doped layer, the amorphous silicon film is removed, particularly, chain type single-sided etching equipment is adopted, HF solution is firstly adopted to remove an oxide layer on the surface of the amorphous silicon film, and KOH solution is adopted to etch and remove the amorphous silicon film which is wound and plated on the front surface.
Specifically, in the fifth step, a passivation film is deposited on the side of the first doped polysilicon layer 3 facing away from the tunneling layer 2 by using a tube PECVD method, so as to form a first dielectric layer 4.
Specifically, in the sixth step, a first printing electrode paste is printed on the first dielectric layer 4, the first printing electrode paste is burnt through the first dielectric layer 4 to be in contact with the first doped polysilicon layer 3, the metal material in the first printing electrode paste is dissolved into the glass frit, and the first metal nano-particles 6 are formed by recrystallization through the growth of the glass onto the first doped polysilicon layer 3, so that the crystalline first metal nano-particles 6 comprise the same metal as the metal material in the first main gate electrode 5; if the first printed electrode paste comprises, for example, silver (Ag), the crystalline first metal nanoparticles 6 may also comprise silver (Ag).
In addition, the morphology and distribution of the metal in the crystalline first metal nanoparticles 6 are different from those in the first printed sintered layer, for example, the metal in the crystalline first metal nanoparticles 6 is discretely distributed in island shape in the first doped polysilicon layer 3 at the interface with the first main gate electrode 5 (i.e. the interface with the first connection point 14, the first connection gate line 15 and the first auxiliary gate line in the first doped polysilicon layer 3), and the metal in the first printed sintered layer is bonded with the glass body after heat treatment, and many holes generated due to the volatilization of the solvent in the first printed electrode paste are formed in the first printed sintered layer, and these holes are filled with the subsequently deposited first metal layer.
The plurality of crystalline first metal nanoparticles 6 are not located in the tunneling layer 2, so that the crystalline first metal nanoparticles 6 do not damage the tunneling layer 2 or the silicon substrate 1, and the performance of the solar cell is reduced.
The first printed electrode paste may be silver paste or aluminum paste.
The sintering temperature is 750-900 ℃, and the heat treatment temperature is 250-500 ℃. For example, the sintering temperature may be 750 ℃, 800 ℃, 850 ℃ or 900 ℃.
Specifically, the step of forming the first opening on the first dielectric layer 4 and the step of forming the first main gate electrode 5 on the first dielectric layer 4 may be performed without any sequence, that is, the first opening may be formed first, then the first main gate electrode 5 may be formed, or the first main gate electrode 5 may be formed first, and then the first opening may be formed on the first dielectric layer 4.
Specifically, in step eight, the deposited metal is further subjected to a heat treatment, which may be at a temperature of 250 ℃, 300 ℃, 350 ℃, 400 ℃, 450 ℃ or 500 ℃.
Specifically, in step seven and step eight, the electrode paste used to form the first metal layer is the same as the first fine gate electrode 7 paste. The first thin gate electrode 7 paste may be silver paste, aluminum paste, silver aluminum paste, copper paste or nickel paste.
Specifically, in step nine, a passivation film is deposited on the doped layer 8 on the side facing away from the tunneling layer 2 by means of tube PECVD, so as to form a second dielectric layer 9.
Further, before step ten, an anti-reflection layer 10 is deposited on the side of the second dielectric layer 9 facing away from the doped layer 8. The anti-reflection layer 10 can reduce reflection of light when light is irradiated on the solar cell, enhancing utilization of light.
Further, in step ten, after the anti-reflection layer 10 is deposited on the second dielectric layer 9, the second main gate electrode 11 burns through the anti-reflection layer 10 and the second dielectric layer 9 extends into the doped layer 8 to connect.
Specifically, in step ten, when the second printing electrode paste includes metallic silver, after the second printing electrode paste is printed on the second dielectric layer 9, the second printing electrode paste burns through the second dielectric layer 9 to contact the doped layer 8, the metallic material in the second printing electrode paste is dissolved into the frit, and is recrystallized by growth of glass onto the doped layer 8 to form crystalline second metallic nanoparticles, so that the crystalline second metallic nanoparticles include metallic silver (Ag) identical to the metallic material in the second main gate electrode 11.
In addition, the morphology and distribution of the metal in the crystalline second metal nanoparticles are different from those in the second printed sintered layer, for example, the metal in the crystalline second metal nanoparticles is discretely distributed in island form in the doped layer 8 at the interface with the second main gate electrode 11 (i.e. the interface between the doped layer 8 and the second connection point 16, the second connection gate line 17 and the second auxiliary gate line), and the metal in the second printed sintered layer is bonded with the glass body after heat treatment, and a plurality of holes generated due to the volatilization of the solvent in the second printed electrode paste are formed in the second printed sintered layer, and these holes are filled with the subsequently deposited second metal layer. The plurality of crystalline second metal nanoparticles are not located in the tunneling layer 2, so as to prevent the crystalline second metal nanoparticles from damaging the tunneling layer 2 or the silicon substrate 1, and reduce the performance of the solar cell.
Specifically, in step ten, when the second main gate electrode 11 includes metal aluminum, after the second printing electrode paste is printed on the second dielectric layer 9, the metal (such as Al) in the second printing electrode paste is trivalent element, silicon is tetravalent element, and aluminum diffuses into the doped layer 8 during the heat treatment, and the eutectic layer 13 and the local back field 19 are formed at the interface with the second main gate electrode 11. Within the doped layer 8, there is no eutectic layer 13 and no local back field 19 at the interface with the second thin gate electrode 12. The eutectic layer 13 has good conductivity, is favorable for forming firm ohmic contact, and the local back field 19 can block movement of electrons, reduce the recombination rate of the surface, reduce light penetration through the silicon substrate 1 and enhance absorption of long waves.
Specifically, the anti-reflection layer 10 is provided with a third opening penetrating the second opening, and the second thin gate electrode 12 penetrates the second opening and the third opening to be connected with the doped layer 8.
The sintering temperature is 750-900 ℃, and the heat treatment temperature is 250-500 ℃. For example, the sintering temperature may be 750 ℃, 800 ℃, 850 ℃ or 900 ℃.
Specifically, in step twelve, the deposited metal is further comprised of a heat treatment, which may be at a temperature of 250 ℃, 300 ℃, 350 ℃, 400 ℃, 450 ℃ or 500 ℃.
The second printed electrode paste may be silver paste or aluminum paste.
Specifically, in step eleven, the electrode paste used to form the second metal layer is the same as the second fine gate electrode 12 paste. The second fine gate electrode 12 paste may be silver paste, aluminum paste, silver aluminum paste, copper paste, or nickel paste.
Further specifically, the first thin gate electrode 7 paste may be the same as the second thin gate electrode 12 paste.
In the application, the first preparation method of the solar cell comprises the following steps:
step one: a silicon substrate 1 is provided.
Specifically, the silicon substrate 1 may be obtained by cleaning a silicon wafer, alkali texturing and edge etching, and after texturing, a pyramid textured surface is formed on the front surface (front surface) of the silicon wafer.
Step two: a doped layer 8 is formed on one side surface (front or front surface) of the silicon substrate 1.
Boron on the front side of the silicon substrate diffuses to form a doped layer;
the boron diffusion therein may be: the silicon substrate is diffused under high temperature conditions by a boron source, and a doped layer is formed on the front surface by the boron diffusion.
The boron source for boron diffusion may comprise boron tribromide, and the diffusion temperature of the boron diffusion may be in the range of 950-1000 ℃ and the diffusion time may be in the range of 1.5-2.5 hours.
Step three: a tunneling layer 2 is provided on one side surface (back surface or rear surface) of the silicon substrate 1.
Specifically, a tunneling layer 2 is grown on the back surface of the silicon substrate 1 by thermal oxidation.
Step four: a first doped polysilicon layer 3 is deposited on the side of the tunneling layer 2 facing away from the silicon substrate 1.
Specifically, silane and phosphane are introduced into LPCVD, an impurity-doped amorphous silicon film is deposited on one side of the tunneling layer 2, which is far away from the silicon substrate 1, and then the amorphous silicon film is annealed, wherein the annealing temperature is controlled to be 800-1000 ℃, and the annealing time is controlled to be 30 minutes, so that the amorphous silicon is crystallized into polysilicon, and a first doped polysilicon layer is formed.
When the first doped polysilicon layer is formed, an amorphous silicon film is formed on the doped layer, the amorphous silicon film is removed, particularly, chain type single-sided etching equipment is adopted, HF solution is firstly adopted to remove an oxide layer on the surface of the amorphous silicon film, and KOH solution is adopted to etch and remove the amorphous silicon film which is wound and plated on the front surface.
Step five: a first dielectric layer 4 is deposited on the side of the first doped polysilicon layer 3 facing away from the tunneling layer 2.
Specifically, a passivation film is deposited on the side of the first doped polysilicon layer 3 facing away from the tunneling layer 2 by adopting a tubular PECVD method, so as to form a first dielectric layer 4.
Step six: printing a first printing electrode slurry on one side of the first medium layer 4, which is away from the first doped polysilicon layer 3, and sintering to form a first printing sintering layer, wherein the first printing electrode slurry burns through the first medium layer 4 and stretches into the first doped polysilicon layer 3, and crystalline first metal nano particles 6 are formed at the junction between the first doped polysilicon layer 3 and the first printing sintering layer.
Specifically, a first printing electrode slurry is printed on the first dielectric layer 4, the first printing electrode slurry burns through the first dielectric layer 4 to be in contact with the first doped polysilicon layer 3, the metal material in the first printing electrode slurry is dissolved into the glass frit, and the first metal nano-particles 6 are formed in a crystalline state through the growth of the glass onto the first doped polysilicon layer 3, so that the crystalline state first metal nano-particles 6 comprise the same metal as the metal material in the first main gate electrode 5; if the first printed electrode paste comprises, for example, silver (Ag), the crystalline first metal nanoparticles 6 may also comprise silver (Ag).
In addition, the morphology and distribution of the metal in the crystalline first metal nanoparticles 6 are different from those in the first printed sintered layer, for example, the metal in the crystalline first metal nanoparticles 6 is discretely distributed in island shape in the first doped polysilicon layer 3 at the interface with the first main gate electrode 5 (i.e. the interface with the first connection point 14, the first connection gate line 15 and the first auxiliary gate line in the first doped polysilicon layer 3), and the metal in the first printed sintered layer is bonded with the glass body after heat treatment, and many holes generated due to the volatilization of the solvent in the first printed electrode paste are formed in the first printed sintered layer, and these holes are filled with the subsequently deposited first metal layer.
The plurality of crystalline first metal nanoparticles 6 are not located in the tunneling layer 2, so that the crystalline first metal nanoparticles 6 do not damage the tunneling layer 2 or the silicon substrate 1, and the performance of the solar cell is reduced.
The sintering temperature is 750 ℃ to 900 ℃, for example, the sintering temperature can be 750 ℃, 800 ℃, 850 ℃ or 900 ℃.
The first printed electrode paste may be silver paste or aluminum paste.
Step seven: and electroplating and depositing metal on the surface of the first printed sintering layer to form a first metal layer, wherein the first printed sintering layer and the first metal layer form the first main gate electrode 5.
Step eight: a plurality of first openings penetrating through the first dielectric layer 4 are formed on the first dielectric layer 4, metal is electroplated in the first openings, a first thin gate electrode 7 is formed through heat treatment, the first thin gate electrode 7 is connected with the first main gate electrode 5, and the first thin gate electrode 7 and the first main gate electrode 5 form a first electrode.
The temperature of the heat treatment is 250-500 ℃. For example, the temperature of the heat treatment may be 250 ℃, 300 ℃, 350 ℃, 400 ℃, 450 ℃, or 500 ℃.
The electrode paste used to form the first metal layer is the same as the paste of the first fine gate electrode 7. The first thin gate electrode 7 paste may be silver paste, aluminum paste, silver aluminum paste, copper paste or nickel paste.
Step nine: a second dielectric layer 9 is deposited on the side of the doped layer 8 facing away from the silicon substrate 1.
Specifically, in step nine, a passivation film is deposited on the doped layer 8 on the side facing away from the tunneling layer 2 by means of tube PECVD, so as to form a second dielectric layer 9.
Further, step nine is followed by step ten by depositing an anti-reflection layer 10 on the side of the second dielectric layer 9 facing away from the doped layer 8. The anti-reflection layer 10 can reduce reflection of light when light is irradiated on the solar cell, enhancing utilization of light.
Step ten: printing second printing electrode slurry on one side of the second dielectric layer 9 away from the doped layer 8, and sintering to form a second printing sintering layer, wherein the second printing electrode slurry burns through the second dielectric layer 9 and stretches into the doped layer 8.
Further, after the anti-reflection layer 10 is deposited on the second dielectric layer 9, the second main gate electrode 11 burns through the anti-reflection layer 10 and the second dielectric layer 9 extends into the doped layer 8.
Specifically, when the second printing electrode paste includes metallic silver, after the second printing electrode paste is printed on the second dielectric layer 9, the second printing electrode paste burns through the second dielectric layer 9 to contact the doped layer 8, the metallic material in the second printing electrode paste is dissolved into the glass paste, and is recrystallized by growing the glass onto the doped layer 8 to form crystalline second metallic nanoparticles, so that the crystalline second metallic nanoparticles include metallic silver (Ag) identical to the metallic material in the second main gate electrode 11.
In addition, the morphology and distribution of the metal in the crystalline second metal nanoparticles are different from those in the second printed sintered layer, for example, the metal in the crystalline second metal nanoparticles is discretely distributed in island form in the doped layer 8 at the interface with the second main gate electrode 11 (i.e. the interface between the doped layer 8 and the second connection point 16, the second connection gate line 17 and the second auxiliary gate line), and the metal in the second printed sintered layer is bonded with the glass body after heat treatment, and a plurality of holes generated due to the volatilization of the solvent in the second printed electrode paste are formed in the second printed sintered layer, and these holes are filled with the subsequently deposited second metal layer. The plurality of crystalline second metal nanoparticles are not located in the tunneling layer 2, so as to prevent the crystalline second metal nanoparticles from damaging the tunneling layer 2 or the silicon substrate 1, and reduce the performance of the solar cell.
Specifically, in step ten, when the second main gate electrode 11 includes metal aluminum, after the second printing electrode paste is printed on the second dielectric layer 9, the metal (such as Al) in the second printing electrode paste is trivalent element, silicon is tetravalent element, and aluminum diffuses into the doped layer 8 during the heat treatment, and the eutectic layer 13 and the local back field 19 are formed at the interface with the second main gate electrode 11. Within the doped layer 8, there is no eutectic layer 13 and no local back field 19 at the interface with the second thin gate electrode 12.
The eutectic layer 13 has good conductivity, is favorable for forming firm ohmic contact, and the local back field 19 can block movement of electrons, reduce the recombination rate of the surface, reduce light penetration through the silicon substrate 1 and enhance absorption of long waves.
Specifically, the anti-reflection layer 10 is provided with a third opening penetrating the second opening, and the second thin gate electrode 12 penetrates the second opening and the third opening to be connected with the doped layer 8.
In particular, the sintering temperature is 750 ℃ to 900 ℃, for example, the sintering temperature may be 750 ℃, 800 ℃, 850 ℃ or 900 ℃.
The second printed electrode paste may be silver paste or aluminum paste.
Step eleven: and electroplating and depositing metal on the surface of the second printed sintering layer to form a second metal layer, wherein the second printed sintering layer and the second metal layer form the second main gate electrode 11.
Specifically, the temperature of the heat treatment is 250 ℃ to 500 ℃. For example, the temperature of the heat treatment may be 250 ℃, 300 ℃, 350 ℃, 400 ℃, 450 ℃, or 500 ℃.
Step twelve: a plurality of second openings penetrating through the second dielectric layer 9 are arranged on the second dielectric layer 9, metal is electroplated in the second openings, a second thin gate electrode 12 is formed through the heat treatment, and the second thin gate electrode 12 is connected with the second main gate electrode 11 to form a second electrode.
Specifically, the electrode paste used to form the second metal layer is the same as the second fine gate electrode 12 paste. The second fine gate electrode 12 paste may be silver paste, aluminum paste, silver aluminum paste, copper paste, or nickel paste.
Further specifically, the first thin gate electrode 7 paste may be the same as the second thin gate electrode 12 paste.
Second solar cell
As shown in fig. 2, the solar cell provided by the application comprises a silicon substrate 1, a first electrode and a second electrode, wherein a second dielectric layer 9 is arranged on the front surface of the silicon substrate 1. The tunneling layer 2, the first doped polysilicon layer 3 and the first dielectric layer 4 are sequentially stacked on the back surface of the silicon substrate 1, and the first electrode penetrates through the first dielectric layer 4 and stretches into the first doped polysilicon layer 3. There are crystalline first metal nanoparticles 6 within the first doped polysilicon layer 3 at the interface with the first electrode. The second electrode penetrates through the first dielectric layer 4 and is connected with the back surface of the silicon substrate 1.
Specifically, the first electrode includes a plurality of first main gate electrodes 5 and a plurality of first thin gate electrodes 7, and each of the first main gate electrodes 5 intersects with and is electrically connected to each of the first thin gate electrodes 7. A first metal nanoparticle 6 having a crystalline state is provided in the first doped polysilicon layer 3 at the interface with the first main gate electrode 5. There are no crystalline first metal nanoparticles 6 within the first doped polysilicon layer 3 at the interface with the first thin gate electrode 7.
Specifically, the second electrode includes a second main gate electrode 11 and a second thin gate electrode 12, and the second main gate electrode 11 and the second thin gate electrode 12 intersect and are electrically connected.
Specifically, on the back surface of the silicon substrate 1, the tunneling layer 2 includes a plurality of tunneling units disposed at intervals, the area between adjacent tunneling units is a first area, and the first dielectric layer 4 covers the surface of the first doped polysilicon layer 3 and the side surface of the first doped polysilicon layer 3, the side surface of the tunneling units and the surface of the silicon substrate 1 in the first area. The second main gate electrode 11 penetrates through the first dielectric layer 4 in the first region and is connected with the silicon substrate 1.
Further, when the second main gate electrode 11 includes silver metal, the interface with the second main gate electrode 11 in the silicon substrate 1 has crystalline second metal nanoparticles. There are no crystalline second metal nanoparticles within the silicon substrate 1 at the interface with the second thin gate electrode 12.
Further, when the second main gate electrode 11 includes metal aluminum, a eutectic layer 13 and a local back field 19 are provided at the interface with the second main gate electrode 11 in the silicon substrate 1. In the silicon substrate 1, there is no eutectic layer 13 and no local back field 19 at the interface with the second thin gate electrode 12.
Specifically, as shown in fig. 4, a plurality of the first thin gate electrodes 7 are disposed at equal intervals, the first thin gate electrodes 7 include a plurality of first thin gate lines spaced apart by the first and second main gate electrodes 5 and 11, and one ends of the first thin gate lines are connected to the first main gate electrode 5 and the other ends are spaced apart by the second main gate electrode 11. The first thin gate electrode 7 perpendicularly intersects the first main gate electrode 5.
The second thin gate electrodes 12 are disposed at equal intervals, the second thin gate electrodes 12 include a plurality of second thin gate lines spaced apart by the first and second main gate electrodes 5 and 11, and one ends of the second thin gate lines are connected to the second main gate electrodes 11 and the other ends are spaced apart by the first main gate electrodes 5. The second thin gate electrode 12 perpendicularly intersects the second main gate electrode 11.
The second thin gate electrodes 12 and the first thin gate electrodes 7 are alternately parallel to each other, that is, the first thin gate electrodes 7 and the second thin gate electrodes 12 are sequentially parallel, and the second thin gate electrodes 12 are disposed between adjacent first thin gate electrodes 7. The second main gate electrodes 11 and the first main gate electrodes 5 are alternately parallel to each other, that is, the first main gate electrodes 5 and the second main gate electrodes 11 are sequentially parallel, and the second main gate electrodes 11 are disposed between adjacent first main gate electrodes 5.
The tunneling layer 2, the first doped polysilicon layer 3, the first dielectric layer 4, the first electrode and the crystalline first metal nanoparticles 6 in this embodiment may refer to the description of the first solar cell, that is, the specific structures and materials of the tunneling layer 2, the first doped polysilicon layer 3, the first dielectric layer 4, the first electrode and the crystalline first metal nanoparticles 6 of the solar cell may refer to those described in the first solar cell section.
The material of the second electrode in this embodiment may be the same as that of the first electrode or may be different from that of the first electrode, and when the material of the second electrode is the same as that of the first electrode, the material of the first electrode in the foregoing first solar cell portion may be referred to. When the materials of the second electrodes are different, the second printing electrode slurry is silver slurry or aluminum slurry. The electrode slurry of the second metal layer is silver slurry, aluminum slurry, silver-aluminum slurry, copper slurry or nickel slurry. The electrode paste of the second fine gate electrode 12 is silver paste, aluminum paste, silver aluminum paste, copper paste or nickel paste.
In the solar cell of this embodiment, since the second doped polysilicon layer and the second electrode are not disposed on the front surface of the silicon substrate 1, when light irradiates the solar cell, the light can directly irradiate the silicon substrate 1, so that the solar cell has a simple structure and a high light utilization rate. In addition, as the first electrode and the second electrode are positioned on the same side of the silicon substrate 1, the consumption of electrode slurry can be greatly reduced, and the cost is lower.
In the present application, the second method for manufacturing a solar cell includes the steps of:
step one: a silicon substrate 1 is provided.
Step two: a second dielectric layer 9 is formed on one side surface (front or front surface) of the silicon substrate 1.
Step three: a tunneling layer 2 is provided on one side surface of the silicon substrate 1.
Step four: a first doped polysilicon layer 3 is deposited on the side of the tunneling layer 2 facing away from the silicon substrate 1.
Step five: a first dielectric layer 4 is deposited on the side of the first doped polysilicon layer 3 facing away from the tunneling layer 2.
Step six: and a first printing electrode slurry and a second printing electrode slurry are printed on one side of the first medium layer 4, which is away from the first doped polysilicon layer 3, at intervals, a first printing sintering layer and a second printing sintering layer are formed by sintering, the first printing electrode slurry is burnt through the first medium layer 4 to extend into the first doped polysilicon layer 3, crystalline first metal nano particles 6 are formed at the junction between the first doped polysilicon layer 3 and the first printing sintering layer, and the second printing electrode slurry is burnt through the first medium layer 4 to be connected with the silicon substrate 1.
Step seven: and electroplating and depositing metal on the surface of the first printed sintering layer to form a first metal layer, wherein the first printed sintering layer and the first metal layer form the first main gate electrode 5.
Step eight: and electroplating and depositing metal on the surface of the second printed sintering layer to form a second metal layer, wherein the second printed sintering layer and the second metal layer form the second main gate electrode 11.
Step nine: a plurality of first openings and second openings penetrating through the first dielectric layer 4 are formed in the first dielectric layer 4, metal is respectively electroplated in the first openings and the second openings, a first thin gate electrode 7 and a second thin gate electrode 12 are formed through heat treatment, the first thin gate electrode 7 is intersected with and electrically connected with the first main gate electrode 5, the first thin gate electrode 7 and the first main gate electrode 5 form a first electrode, the second thin gate electrode 12 is intersected with and electrically connected with the second main gate electrode 11, and the second thin gate electrode 12 and the second main gate electrode 11 form a second electrode.
Step ten: a second dielectric layer 9 is arranged on the surface of the side of the silicon substrate 1 facing away from the tunneling layer 2.
Specifically, in the first step, the silicon substrate 1 may be obtained by cleaning a silicon wafer, alkali texturing and edge etching, and pyramid texturing is formed on both sides of the silicon wafer after texturing.
Specifically, in the second step, oxidizing the front surface of the silicon substrate, and forming a silicon oxide layer on the front surface of the silicon substrate, i.e. the silicon oxide layer is a second dielectric layer.
Specifically, in the third step, the tunneling layer 2 is formed on the back surface of the silicon substrate 1 by thermal oxidation.
Specifically, in step five, the first doped polysilicon layer 3 and the tunneling layer 2 are ablated at intervals on the surface of the first doped polysilicon layer 3 to expose the silicon substrate 1, thereby forming a plurality of first regions at intervals. And depositing a first dielectric layer on the surface of the first doped polysilicon layer and the side surface of the first doped polysilicon layer, the side surface of the tunneling layer and the surface of the silicon substrate in the first region.
Further, on the surface of the first doped polysilicon layer 3, the first doped polysilicon layer 3 and the tunneling layer 2 are ablated at intervals by using a laser technology to expose the silicon substrate 1, so as to form a plurality of first regions at intervals.
Specifically, in step six, a second printed electrode paste is printed on the surface of the first dielectric layer 4 in the first area, and sintered to form a second printed sintered layer, and the second printed electrode paste is sintered through the second dielectric layer 9 to be connected with the silicon substrate 1.
Further, when the second main gate electrode 11 paste includes silver metal, crystalline second metal nanoparticles are formed at the interface with the second main gate electrode 11 in the silicon substrate 1.
Further, when the second main gate electrode 11 slurry includes metal aluminum, a eutectic layer 13 and a local back surface field 19 are formed at the junction with the second main gate electrode 11 in the silicon substrate 1.
Specifically, in the eighth step, a plurality of second openings penetrating the first dielectric layer 4 are provided on the first dielectric layer 4, metal is electroplated in the second openings, a second thin gate electrode 12 is formed through the heat treatment, and the second thin gate electrode 12 is connected with the silicon substrate 1; the second thin gate electrode 12 intersects and is electrically connected to the second main gate electrode 11 to form a second electrode.
In the present application, the second method for manufacturing a solar cell includes the steps of:
step one: a silicon substrate 1 is provided.
Step two: a second dielectric layer 9 is formed on one side surface (front or front surface) of the silicon substrate 1.
Step three: a tunneling layer 2 is provided on one side surface of the silicon substrate 1.
Specifically, the tunneling layer 2 is formed on the back surface of the silicon substrate 1 by thermal oxidation.
Step four: a first doped polysilicon layer 3 is deposited on the side of the tunneling layer 2 facing away from the silicon substrate 1.
Step five: a first dielectric layer 4 is deposited on the side of the first doped polysilicon layer 3 facing away from the tunneling layer 2.
Specifically, on the surface of the first doped polysilicon layer 3, the first doped polysilicon layer 3 and the tunneling layer 2 are ablated at intervals to expose the silicon substrate 1, thereby forming a plurality of first regions at intervals. And depositing a first dielectric layer on the surface of the first doped polysilicon layer and the side surface of the first doped polysilicon layer, the side surface of the tunneling layer and the surface of the silicon substrate in the first region.
Further, on the surface of the first doped polysilicon layer 3, the first doped polysilicon layer 3 and the tunneling layer 2 are ablated at intervals by using a laser technology to expose the silicon substrate 1, so as to form a plurality of first regions at intervals.
Step six: and a first printing electrode slurry and a second printing electrode slurry are printed at intervals on one side of the first medium layer 4, which is away from the first doped polysilicon layer 3, and sintered to form a first printing sintered layer and a second printing sintered layer, wherein the first printing electrode slurry burns through the first medium layer 4 to enter the first doped polysilicon layer 3, crystalline first metal nano particles 6 are formed at the junction between the first doped polysilicon layer 3 and the first printing sintered layer, and the second printing electrode slurry burns through the first medium layer 4 to be connected with the silicon substrate 1.
Specifically, a second printed electrode paste is printed on the surface of the first dielectric layer 4 in the first area, and sintered to form a second printed sintering layer, and the second printed electrode paste burns through the second dielectric layer 9 to be connected with the silicon substrate 1.
Further, when metallic silver is included in the second printed electrode paste, crystalline second metallic nanoparticles are formed in the silicon substrate 1 at the interface with the second printed sintered layer.
Further, when metallic aluminum is included in the second printed electrode paste, a eutectic layer 13 and a local back field 19 are formed in the silicon substrate 1 at the interface with the second printed sintered layer.
Step seven: and electroplating and depositing metal on the surface of the first printed sintering layer to form a first metal layer, wherein the first printed sintering layer and the first metal layer form the first main gate electrode 5.
Step eight: and electroplating and depositing metal on the surface of the second printed sintering layer to form a second metal layer, wherein the second printed sintering layer and the second metal layer form the second main gate electrode 11.
Step nine: a plurality of first openings and second openings penetrating through the first dielectric layer 4 are formed in the first dielectric layer 4, metal is respectively electroplated in the first openings and the second openings, a first thin gate electrode 7 and a second thin gate electrode 12 are formed through heat treatment, each first thin gate electrode 7 is intersected with and electrically connected with each first main gate electrode 5, the first thin gate electrode 7 and the first main gate electrode 5 form a first electrode, each second thin gate electrode 12 is intersected with and electrically connected with each second main gate electrode 11, and the second thin gate electrode 12 and the second main gate electrode 11 form a second electrode.
Specifically, a plurality of second openings penetrating through the first dielectric layer 4 are formed on the first dielectric layer 4, metal is electroplated in the second openings, a second thin gate electrode 12 is formed through the heat treatment, and the second thin gate electrode 12 is connected with the silicon substrate 1; each of the second fine gate electrodes 12 crosses and is electrically connected to each of the second main gate electrodes 11 to form a second electrode.
Step ten: a second dielectric layer 9 is arranged on the surface of the side of the silicon substrate 1 facing away from the tunneling layer 2.
The tunneling layer 2, the first doped polysilicon layer 3, the first dielectric layer 4, the first electrode and the crystalline first metal nanoparticles 6 in this embodiment may refer to the description of the preparation method of the first solar cell, that is, the materials, structures and preparation methods of the tunneling layer 2, the first doped polysilicon layer 3, the first dielectric layer 4, the first electrode and the crystalline first metal nanoparticles 6 of the solar cell may refer to those described in the first solar cell and the preparation method thereof.
Third solar cell
As shown in fig. 3, the solar cell provided herein, the third solar cell, is a variation of the second solar cell. The solar cell comprises a silicon substrate 1, a first electrode and a second electrode, wherein a second dielectric layer 9 is arranged on the front surface of the silicon substrate 1. The tunneling layer 2, the first doped polysilicon layer 3 and the first dielectric layer 4 are sequentially stacked on the back surface of the silicon substrate 1, and the first electrode penetrates through the first dielectric layer 4 and stretches into the first doped polysilicon layer 3; inside the first doped polysilicon layer 3, the junction with the first electrode has crystalline first metal nanoparticles 6.
Specifically, the first electrode includes a plurality of first main gate electrodes 5 and a plurality of first thin gate electrodes 7, and each of the first main gate electrodes 5 intersects with and is connected to each of the first thin gate electrodes 7; a first metal nanoparticle 6 having a crystalline state is provided in the first doped polysilicon layer 3 at the interface with the first main gate electrode 5.
Specifically, the second electrodes include second main gate electrodes 11 and second thin gate electrodes 12, and each of the second main gate electrodes 11 and each of the second thin gate electrodes 12 intersect and are connected.
On the surface of the tunneling layer 2, the first doped polysilicon layer 3 includes a plurality of first doped polysilicon units arranged at intervals; the area between the adjacent first doped polysilicon units is a second area; a second doped polysilicon unit is arranged in the second region, and a plurality of the second doped polysilicon units form a second doped polysilicon layer 20; the first dielectric layer 4 covers the surfaces of the first doped polysilicon unit and the second doped polysilicon unit.
A region is provided between the first doped polysilicon unit and the second doped polysilicon unit, that is, the width of the second doped polysilicon layer 20 is smaller than the width of the second region, and the first doped polysilicon layer 3 is not in contact with the second doped polysilicon layer 20. The second doped polysilicon layer 20 is located in the middle of the second region.
The second main gate electrode 11 penetrates through the first dielectric layer 4 and is connected with the second doped polysilicon layer 20. The second doped polysilicon layer 20 is of opposite conductivity type to the first doped polysilicon layer 3, and the second main gate electrode 11 is different from the first main gate electrode 5.
Further, when the second main gate electrode 11 includes silver metal, crystalline second metal nanoparticles are formed at the interface with the second main gate electrode 11 within the second doped polysilicon layer 20.
Further, when the second main gate electrode 11 includes metal aluminum, a eutectic layer 13 and a local back field 19 are formed at the interface with the second main gate electrode 11 in the second doped polysilicon layer 20.
The tunneling layer 2, the first doped polysilicon layer 3, the first dielectric layer 4, the first electrode and the crystalline first metal nanoparticles 6 in this embodiment may refer to the description of the first solar cell, that is, the specific structures and materials of the tunneling layer 2, the first doped polysilicon layer 3, the first dielectric layer 4, the first electrode and the crystalline first metal nanoparticles 6 of the solar cell may refer to those described in the first solar cell section.
The material of the second electrode in this embodiment is the same as that of the second electrode in the second solar cell, and reference is made to the description of the second solar cell.
In this embodiment, the positional relationship between the second electrode and the first electrode on the surface of the first dielectric layer 4 is as shown in fig. 4, and reference may be made to the description of the second solar cell section.
In the present application, the third method for manufacturing a solar cell includes the following steps:
step one: a silicon substrate 1 is provided.
Step two: a second dielectric layer 9 is formed on one side surface (front or front surface) of the silicon substrate 1.
Step three: a tunneling layer 2 is provided on one side surface (back surface or rear surface) of the silicon substrate 1.
Step four: a first doped polysilicon unit and a second doped polysilicon unit are sequentially deposited at intervals on one side of the tunneling layer 2 away from the silicon substrate 1, wherein a plurality of the first doped polysilicon units form the first doped polysilicon layer 3, and a plurality of the second doped polysilicon units form the second doped polysilicon layer 20.
Step five: a first dielectric layer 4 is deposited on the side of the first doped polysilicon layer 3 and the second doped polysilicon layer 20 facing away from the tunneling layer 2.
Step six: printing a first printing electrode slurry on one side of the first dielectric layer 4, which is away from the first doped polysilicon layer 3, and sintering to form a first printing sintering layer, wherein the first printing electrode slurry is burnt through the first dielectric layer 4 to be connected with the first doped polysilicon layer 3, and crystalline first metal nano particles 6 are formed at the junction between the first doped polysilicon layer 3 and the first printing sintering layer.
Step seven: and electroplating and depositing metal on the surface of the first printed sintering layer to form a first metal layer, wherein the first printed sintering layer and the first metal layer form the first main gate electrode 5.
Step eight: printing second printing electrode slurry on one side of the first dielectric layer 4 away from the second doped polysilicon layer 20, and sintering to form a second printing sintering layer, wherein the second printing electrode slurry burns through the first dielectric layer 4 and stretches into the second doped polysilicon layer 20 to be connected.
Step nine: and electroplating and depositing metal on the surface of the second printed sintering layer to form a second metal layer, wherein the second printed sintering layer and the second metal layer form the second main gate electrode 11.
Step ten: a plurality of first openings and second openings penetrating through the first dielectric layer 4 are formed on the first dielectric layer 4, metal is electroplated in the first openings, metal is electroplated in the second openings, a first thin gate electrode 7 and a second thin gate electrode 12 are formed through heat treatment, each first thin gate electrode 7 is intersected with and electrically connected to each first main gate electrode 5, and each second thin gate electrode 12 is intersected with and electrically connected to each second main gate electrode 11.
Specifically, in the fourth step, a plurality of first doped polysilicon units are arranged at equal intervals; the second doped polysilicon units are arranged at equal intervals.
Specifically, in the fifth step, the first dielectric layer 4 is deposited on the surface of the first doped polysilicon unit and the surface of the second doped polysilicon unit, that is, the first dielectric layer 4 covers the surfaces of the first doped polysilicon unit and the second doped polysilicon unit.
Specifically, in step six, a first printed electrode paste is printed on the surface of the first dielectric layer 4 corresponding to the first doped polysilicon layer 3, and sintered to form a first printed sintered layer.
Specifically, in the eighth step, a second printed electrode paste is printed on the surface of the first dielectric layer 4 corresponding to the second doped polysilicon layer 20, and sintered to form a second printed sintered layer.
In the present application, the third method for manufacturing a solar cell includes the following steps:
step one: a silicon substrate 1 is provided.
Step two: a second dielectric layer 9 is formed on one side surface (front or front surface) of the silicon substrate 1.
Step three: a tunneling layer 2 is provided on one side surface of the silicon substrate 1.
Step four: a first doped polysilicon unit and a second doped polysilicon unit are sequentially deposited at intervals on one side of the tunneling layer 2 away from the silicon substrate 1, wherein a plurality of the first doped polysilicon units form the first doped polysilicon layer 3, and a plurality of the second doped polysilicon units form the second doped polysilicon layer 20.
Specifically, a plurality of first doped polysilicon units are arranged at equal intervals; the second doped polysilicon units are arranged at equal intervals.
Step five: a first dielectric layer 4 is deposited on the side of the first doped polysilicon layer 3 and the second doped polysilicon layer 20 facing away from the tunneling layer 2.
Specifically, the first dielectric layer 4 is deposited on the surface of the first doped polysilicon unit and the surface of the second doped polysilicon unit, that is, the first dielectric layer 4 covers the surfaces of the first doped polysilicon unit and the second doped polysilicon unit.
Step six: printing a first printing electrode slurry on one side of the first medium layer 4, which is away from the first doped polysilicon layer 3, and sintering to form a first printing sintering layer, wherein the first printing electrode slurry burns through the first medium layer 4 and stretches into the first doped polysilicon layer 3, and crystalline first metal nano particles 6 are formed at the junction between the first doped polysilicon layer 3 and the first printing sintering layer.
Specifically, a first printing electrode paste is printed on the surface of the first dielectric layer 4 corresponding to the first doped polysilicon layer 3, and a first printing sintered layer is formed by sintering.
Step seven: and electroplating and depositing metal on the surface of the first printed sintering layer to form a first metal layer, wherein the first printed sintering layer and the first metal layer form the first main gate electrode 5.
Step eight: printing second printing electrode slurry on one side of the first dielectric layer 4 away from the second doped polysilicon layer 20, and sintering to form a second printing sintering layer, wherein the second printing electrode slurry burns through the first dielectric layer 4 and stretches into the second doped polysilicon layer 20.
Specifically, in the eighth step, a second printed electrode paste is printed on the surface of the first dielectric layer 4 corresponding to the second doped polysilicon layer 20, and sintered to form a second printed sintered layer.
Step nine: and electroplating and depositing metal on the surface of the second printed sintering layer to form a second metal layer, wherein the second printed sintering layer and the second metal layer form the second main gate electrode 11.
Step ten: a plurality of first openings and second openings penetrating through the first dielectric layer 4 are formed on the first dielectric layer 4, metal is electroplated in the first openings, metal is electroplated in the second openings, a first thin gate electrode 7 and a second thin gate electrode 12 are formed through heat treatment, the first thin gate electrode 7 is connected with the first main gate electrode 5, and the second thin gate electrode 12 is connected with the second main gate electrode 11.
The tunneling layer 2, the first doped polysilicon layer 3, the first dielectric layer 4, the first electrode and the crystalline first metal nanoparticles 6 in this embodiment may refer to the description of the preparation method of the first solar cell, that is, the materials, structures and preparation methods of the tunneling layer 2, the first doped polysilicon layer 3, the first dielectric layer 4, the first electrode and the crystalline first metal nanoparticles 6 of the solar cell may refer to those described in the first solar cell and the preparation method thereof.
Examples
The experimental methods used in the following examples are conventional methods, if no special requirements are imposed.
Materials, reagents and the like used in the examples described below are commercially available unless otherwise specified.
Example 1
The solar cell in this embodiment is a first solar cell, and includes the following steps:
step one: a silicon substrate is provided.
The p-type crystalline silicon layer is obtained by cleaning a silicon wafer, alkali texturing and edge etching, and forming pyramid textured surfaces on the front surface (front surface) of the silicon wafer after texturing.
Step two: forming a doped layer
Boron on the front side of the silicon substrate diffuses to form a doped layer;
the boron diffusion therein may be: the silicon substrate is diffused under high temperature conditions by a boron source, and a doped layer is formed on the front surface by the boron diffusion.
The boron source for boron diffusion may comprise boron tribromide, and the diffusion temperature of the boron diffusion may be in the range of 950-1000 ℃ and the diffusion time may be in the range of 1.5-2.5 hours.
Step three: a tunneling layer is formed.
In the second step, boron diffusion is carried out on the back surface (rear surface) of the silicon substrate to form a back boron diffusion layer, then the back boron diffusion layer is removed, and a tunneling layer is grown on the back surface of the silicon substrate in a thermal oxidation mode, wherein the tunneling layer is a silicon oxide layer and has a thickness of 1nm.
The back boron diffusion layer is removed by a wet etching device.
Specifically, the back boron diffusion layer on the back side can be removed by wet etching by using wet etching equipment, the wet etching equipment can realize single-sided cleaning and etching, and the etching depth can be 1.5-3 microns.
Step four: forming a first doped polysilicon layer
And (3) depositing an in-situ phosphorus-doped amorphous silicon film on one side of the tunneling layer, which is away from the silicon substrate, by adopting LPCVD (low pressure chemical vapor deposition) and introducing silane and phosphine, and then annealing the amorphous silicon film, wherein the annealing temperature is controlled to be 800-1000 ℃ and the annealing time is controlled to be 30 minutes, so that the amorphous silicon is crystallized into polysilicon, and a first doped polysilicon layer is formed. The thickness of the first doped polysilicon layer is 100nm.
When the first doped polysilicon layer is formed, an amorphous silicon film is formed on the doped layer, the amorphous silicon film is removed, particularly, chain type single-sided etching equipment is adopted, HF solution is firstly adopted to remove an oxide layer on the surface of the front amorphous silicon film, and KOH solution is adopted to etch and remove the amorphous silicon film which is wound and plated on the front.
Step five: a first dielectric layer is formed.
And depositing a silicon nitride film on one side of the first doped polysilicon layer, which is away from the tunneling layer, by adopting a tubular PECVD mode to form a first dielectric layer, wherein the thickness of the first dielectric layer is 50nm.
Step six: forming a first electrode
Printing first printing electrode slurry on one side of the first medium layer, which is away from the first doped polysilicon layer, and burning through the first medium layer by the first printing electrode slurry at the sintering temperature of 900 ℃ to connect the first medium layer and the first doped polysilicon layer, and forming crystalline first metal nano particles at the junction of the first doped polysilicon layer and the first printing sintering layer. And electroplating and depositing electrode metal on the surface of the first printed sintering layer to form a first metal layer, wherein the first printed sintering layer and the first metal layer form the first main gate electrode.
A plurality of first openings penetrating through the first dielectric layer are formed in the first dielectric layer, first thin gate electrode metal is electroplated in the first openings, a first thin gate electrode is formed through heat treatment at 250 ℃, and the first thin gate electrode is connected with the first doped polysilicon layer. The straight line where the first thin gate electrode is located is perpendicular to the straight line where the first main gate electrode is located, each first thin gate electrode is intersected with and electrically connected with each first main gate electrode, and the first thin gate electrode and the first main gate electrode form a first electrode.
The first main grid electrode comprises a plurality of first connecting points, a plurality of first connecting grid lines and a plurality of first auxiliary electrodes, wherein the first connecting points are sequentially connected with the first connecting grid lines and extend, the first auxiliary electrodes are positioned at the connecting positions of the first main grid electrode and the first thin grid electrode, one ends of the first auxiliary electrodes are connected with the first connecting points or the first connecting grid lines, and the other ends of the first auxiliary electrodes are connected with the first thin grid lines. The first auxiliary electrode is arc-shaped, and the width of the first auxiliary electrode is in a decreasing trend along a direction away from the first connection point or the first connection grid line.
The first printing electrode slurry is Ag slurry.
The crystalline first metal nanoparticle comprises silver.
The first metal layer is formed to be Ni.
The first thin gate electrode is Ni.
The first main gate electrode has a height of 10 micrometers. The width is 100 microns.
The height of the first thin gate electrode is 5 microns. The width was 10 microns.
Step seven: forming a second dielectric layer
And depositing a silicon nitride film on the surface of one side of the doped layer, which is away from the tunneling layer, by adopting a tubular PECVD (plasma enhanced chemical vapor deposition) mode to form a second dielectric layer, wherein the thickness of the second dielectric layer is 50nm.
Step eight: forming an anti-reflection layer
And depositing an anti-reflection layer on one side of the second dielectric layer, which is away from the doped layer.
The anti-reflection layer is formed by combining an aluminum oxide layer and a silicon nitride layer, wherein the thickness of the aluminum oxide layer is 10nm, and the thickness of the silicon nitride layer is 60nm.
Step nine: forming a second electrode
Printing second printing electrode slurry on one side surface of the anti-reflection layer, and burning through the anti-reflection layer and the second medium layer to extend into the doped layer for connection through the sintering temperature of 900 ℃, wherein crystalline second metal nano particles are formed at the junction between the doped layer and the second printing sintering layer. And electroplating and depositing metal on the surface of the second printed sintering layer to form a second metal layer, wherein the second printed sintering layer and the second metal layer form the second main gate electrode.
The anti-reflection layer is provided with a third opening penetrating through the anti-reflection layer, the second medium layer is provided with a plurality of second openings penetrating through the second medium layer, and the second openings are communicated with the third opening. And electroplating in the second opening and the third opening, and forming a second thin gate electrode through heat treatment at 250 ℃, wherein the second thin gate electrode is connected with the doped layer. The straight line where the second thin gate electrode is located is perpendicular to the straight line where the second main gate electrode is located, each second thin gate electrode intersects with each second main gate electrode and is electrically connected, and the second thin gate electrode and the second main gate electrode form a second electrode.
The second printing electrode slurry is Ag slurry.
The crystalline second metal nanoparticle comprises silver.
And forming the second metal layer to be Ni.
The second thin gate electrode is Ni.
The height of the second main gate electrode is 10 micrometers. The width is 100 microns.
The height of the second fine gate electrode is 5 microns. The width is 10-microns.
Example 2
The solar cell in this embodiment is a second solar cell, and includes the following steps:
step one: providing a silicon substrate (for a specific process reference is made to example 1)
Step two: forming a second dielectric layer
Oxidizing the front surface of the silicon substrate, and forming a silicon oxide layer on the front surface of the silicon substrate, wherein the silicon oxide layer is a second dielectric layer.
Step three: formation of tunneling layer (for specific process reference to example 1)
Step four: formation of a first doped polysilicon layer (for a specific process reference to example 1)
Step five: forming a first dielectric layer
And ablating the first doped polysilicon layer and the tunneling layer at intervals by adopting laser on the surface of the first doped polysilicon layer to expose the silicon substrate, so as to form a plurality of first areas at intervals.
A first dielectric layer is deposited on the surface of the first doped polysilicon layer and on the side of the first doped polysilicon layer, the side of the tunneling layer and the surface of the silicon substrate in the first region (for a specific deposition process reference is made to example 1).
Step six: forming a first electrode and a second electrode
And printing first printing electrode slurry and second printing electrode slurry at intervals on one side of the first medium layer, which is away from the first doped polysilicon layer, wherein the first printing electrode slurry is printed in an area of the first doped polysilicon layer, which is corresponding to the first medium layer, and the second printing electrode slurry is printed in an area of the first medium layer, which is corresponding to the first area. Then forming a first printed sintered layer and a second printed sintered layer by sintering at 800 ℃. The first printing electrode slurry burns through the first medium layer and stretches into the first doped polysilicon layer, crystalline first metal nano particles are formed at the junction of the first doped polysilicon layer and the first printing sintering layer, the second printing electrode slurry burns through the first medium layer and stretches into the silicon substrate, and a eutectic layer and a local back surface field are formed at the junction of the silicon substrate, which is close to the second printing sintering layer.
And electroplating and depositing metal on the surface of the first printed sintering layer to form a first metal layer, wherein the first printed sintering layer and the first metal layer form the first main gate electrode.
And electroplating and depositing metal on the surface of the second printed sintering layer to form a second metal layer, wherein the second printed sintering layer and the second metal layer form the second main gate electrode.
A plurality of first openings and second openings penetrating through the first dielectric layer are formed in the first dielectric layer, metal is respectively electroplated in the first openings and the second openings, a first thin gate electrode and a second thin gate electrode are formed through heat treatment at 250 ℃, each first thin gate electrode is intersected with each first main gate electrode and electrically connected, the first thin gate electrode and the first main gate electrode form a first electrode, each second thin gate electrode is intersected with each second main gate electrode and electrically connected, and the second thin gate electrode and the second main gate electrode form a second electrode.
The first main gate electrode comprises a plurality of first connection points and a plurality of first connection gate lines, wherein two adjacent first connection points are connected through the first connection gate lines, namely the second connection points are sequentially connected with the second connection gate lines and extend to form the first main gate electrode; the first main gate electrodes are arranged in parallel and equidistant.
The second main gate electrode comprises a plurality of second connection points and a plurality of second connection gate lines, wherein two adjacent second connection points are connected through the second connection gate lines, namely the second connection points are sequentially connected with the second connection gate lines and extend to form the second main gate electrode; the second main gate electrodes are arranged in parallel and equidistant.
The second thin gate electrodes and the first thin gate electrodes are alternately parallel to each other. The second main gate electrode and the first main gate electrode are alternately parallel to each other.
The first thin gate electrodes are arranged at equal intervals, the first thin gate electrodes comprise a plurality of first thin gate lines which are separated by the first main gate electrodes and the second main gate electrodes, one ends of the first thin gate lines are connected with the first main gate electrodes, and the other ends of the first thin gate lines are separated by the second main gate electrodes. The first thin gate electrode perpendicularly intersects the first main gate electrode.
The second thin gate electrodes are arranged at equal intervals, the second thin gate electrodes comprise a plurality of second thin gate lines which are separated by the first main gate electrode and the second main gate electrode, one end of each second thin gate line is connected with the second main gate electrode, and the other end of each second thin gate line is separated by the first main gate electrode. The second thin gate electrode perpendicularly intersects the second main gate electrode.
The first printing electrode slurry is Ag slurry.
The crystalline first metal nanoparticle comprises silver.
And forming the first metal layer to be Cu.
The first thin gate electrode is Cu.
The first main gate electrode has a height of 30 micrometers. The width is 1000 microns.
The height of the first thin gate electrode is 15 microns. The width was 40 microns.
The second printing electrode slurry is Ag slurry.
And forming the second metal layer to be Cu.
The second thin gate electrode is Cu.
The second main gate electrode has a height of 30 micrometers and a width of 1000 micrometers.
The second thin gate electrode has a height of 15 microns and a width of 40 microns.
Example 3
In the present application, the third method for manufacturing a solar cell includes the following steps:
step one: a silicon substrate is provided (for a specific process reference is made to example 1).
Step two: forming a second dielectric layer
Oxidizing the front surface of the silicon substrate, and forming a silicon oxide layer on the front surface of the silicon substrate, wherein the silicon oxide layer is a second dielectric layer.
Step three: a tunneling layer is provided on one side surface of the silicon substrate (for a specific process reference to example 1).
Step four: forming a first doped polysilicon layer and a second doped polysilicon layer
And sequentially depositing a first doped polysilicon unit and a second doped polysilicon unit at intervals on one side of the tunneling layer, which is away from the silicon substrate.
A plurality of the first doped polysilicon units form the first doped polysilicon layer; a plurality of the second doped polysilicon units form the second doped polysilicon layer.
The width of the first doped polysilicon layer is 600nm, and the width of the second doped polysilicon layer is 1200nm.
The heights of the first doped polysilicon layer and the second doped polysilicon layer are the same and are 250nm.
Step five: forming a first dielectric layer (for a specific process reference to example 1)
And depositing a first dielectric layer on the surface of one side of the first doped polysilicon layer and the second doped polysilicon layer, which is away from the tunneling layer. The first dielectric layer covers the surfaces of the first doped polysilicon unit and the second doped polysilicon unit.
Step six: formation of the first electrode (for a specific process reference to example 1)
Printing a first printing electrode slurry on one side of the first medium layer, which is away from the first doped polysilicon layer, forming a first printing sintering layer through sintering at 900 ℃, wherein the first printing electrode slurry is burnt through the first medium layer and stretches into the first doped polysilicon layer, and crystalline first metal nano particles are formed at the junction between the first doped polysilicon layer and the first printing sintering layer. And electroplating and depositing metal on the surface of the first printed sintering layer to form a first metal layer, wherein the first printed sintering layer and the first metal layer form the first main gate electrode.
And arranging a plurality of first openings penetrating through the first dielectric layer on the first dielectric layer, wherein the first openings correspond to the first doped polysilicon units, electroplating first thin gate electrode slurry in the first openings, and forming first thin gate electrodes through heat treatment at 300 ℃. Each first thin gate electrode intersects and is electrically connected to each first main gate electrode.
The first printing electrode slurry is Ag slurry.
The crystalline first metal nanoparticle comprises silver.
And forming the first metal layer as/Sn.
The first thin gate electrode is Sn.
The first main gate electrode has a height of 30 micrometers. The width is 1000 microns.
The height of the first thin gate electrode is 5 microns. The width was 10 microns.
Step seven: forming a second electrode
Printing second printing electrode slurry on the surface of one side of the first dielectric layer, which is away from the second doped polysilicon layer, forming a second printing sintering layer through sintering at 900 ℃, wherein the second printing electrode slurry is burnt through the first dielectric layer and is connected with the second doped polysilicon layer.
And electroplating and depositing metal on the surface of the second printed sintering layer to form a second metal layer, wherein the second printed sintering layer and the second metal layer form the second main gate electrode.
And arranging a plurality of second openings penetrating through the first dielectric layer on the first dielectric layer, wherein the second openings correspond to the second doped polysilicon units, electroplating second fine gate electrode slurry in the second openings, and forming second fine gate electrodes through heat treatment at 300 ℃. Each second thin gate electrode intersects and is electrically connected to each second main gate electrode.
The second printing electrode slurry is Ag slurry.
And forming the second metal layer to be Sn.
The second thin gate electrode is Sn.
The second main gate electrode has a height of 30 micrometers and a width of 100 micrometers.
The second thin gate electrode has a height of 15 microns and a width of 40 microns.
In this embodiment, the arrangement manner of the first electrode and the second electrode on the surface of the first dielectric layer may be referred to in example 2.
Although described above in connection with the embodiments of the present application, the present application is not limited to the specific embodiments and fields of application described above, which are intended to be illustrative, instructive, and not limiting. Those skilled in the art, having the benefit of this disclosure, may make numerous forms, and equivalents thereof, without departing from the scope of the invention as defined by the claims.

Claims (22)

1. A solar cell, which is characterized by comprising a silicon substrate, a tunneling layer, a first doped polysilicon layer, a first dielectric layer and a first electrode;
the tunneling layer, the first doped polysilicon layer and the first dielectric layer are sequentially laminated on one side surface of the silicon substrate;
the first electrode comprises a first main gate electrode and a first thin gate electrode, and the first thin gate electrode is intersected with and electrically connected with the first main gate electrode;
the first main gate electrode burns through the first dielectric layer and stretches into the first doped polysilicon layer; a first metal nano particle with a crystalline state at the junction of the first doped polysilicon layer and the first main gate electrode;
a plurality of first openings penetrating through the first dielectric layer are formed in the first dielectric layer; the first thin gate electrode is electroplated on the first doped polysilicon layer exposed by the first opening.
2. The solar cell of claim 1, wherein the crystalline first metal nanoparticles comprise the same metal as the metal material in the first main gate electrode;
the crystalline first metal nano particles are discretely distributed in island shapes at the junction of the first doped polysilicon layer and the first main gate electrode.
3. The solar cell of claim 1, wherein the crystalline first metal nanoparticle comprises metallic silver.
4. The solar cell of claim 1, wherein the first main gate electrode comprises a first printed sintered layer and a first metal layer disposed in a stack,
the first printed sintering layer penetrates through the first dielectric layer and stretches into the first doped polycrystalline silicon layer, and crystalline first metal nano particles are arranged at the junction of the first doped polycrystalline silicon layer and the first printed sintering layer;
the first metal layer is arranged on the surface of one side of the first printing sintering layer, which is away from the first doped polysilicon layer.
5. The solar cell of claim 1, wherein the first main gate electrode further comprises a first auxiliary electrode located at an intersection of the first main gate electrode and the first thin gate electrode; the first auxiliary electrode gradually decreases in cross-sectional area in a direction perpendicular to the silicon substrate in a direction away from the first main gate electrode and toward the first thin gate electrode.
6. The solar cell of any one of claims 1-5, further comprising a second electrode of opposite polarity to the first electrode, the second electrode comprising a second main gate electrode and a second thin gate electrode intersecting and electrically connected to the second main gate electrode;
The second main gate electrode further comprises a second auxiliary electrode, and the second auxiliary electrode is positioned at the intersection of the second main gate electrode and the second fine gate electrode; the second auxiliary electrode gradually decreases in cross-sectional area in a direction perpendicular to the silicon substrate in a direction away from the second main gate electrode and toward the second thin gate electrode.
7. The solar cell according to claim 6, wherein a doped layer is formed on a surface of a side of the silicon substrate facing away from the tunneling layer, and a second dielectric layer is disposed on a surface of the doped layer;
the second main gate electrode burns through the second dielectric layer and stretches into the doping layer;
a second metal nanoparticle having a crystalline state at the junction of the doped layer and the second main gate electrode; or a eutectic layer and a local back field are arranged at the junction of the doped layer and the second main gate electrode.
8. The solar cell of claim 7, wherein the second main gate electrode comprises metallic aluminum or metallic silver;
when the second main gate electrode comprises metal aluminum, a eutectic layer and a local back field are arranged at the junction of the doped layer and the second main gate electrode;
When the second main gate electrode comprises metallic silver, second metal nano particles with crystalline state are arranged at the junction with the second main gate electrode in the doping layer; the crystalline second metal nano particles are discretely distributed at the junction of the doped layer and the second main gate electrode in an island shape.
9. The solar cell of claim 7 wherein the second main gate electrode comprises a second printed sintered layer and a second metal layer disposed in a stack,
the second printed sintering layer penetrates through the second medium layer and stretches into the doping layer, and the junction between the second printed sintering layer and the second printed sintering layer in the doping layer is provided with the crystalline second metal nano particles;
the second metal layer is arranged on the surface of one side of the second printing sintering layer, which is away from the doped layer.
10. The solar cell of any of claims 6, wherein the first electrode and the second electrode are on the same side of the silicon substrate.
11. The solar cell of claim 10, wherein the second thin-gate electrode and the first thin-gate electrode are alternately parallel to each other;
the second main gate electrode and the first main gate electrode are alternately parallel to each other.
12. The solar cell according to claim 10 or 11, wherein the tunneling layer comprises a plurality of tunneling cells arranged at intervals on the surface of the silicon substrate,
the area between adjacent tunneling units is a first area,
the first dielectric layer covers the surface of the first doped polysilicon layer and the side surface of the first doped polysilicon layer, the side surface of the tunneling unit and the surface of the silicon substrate in the first region.
13. The solar cell of claim 12, wherein the second main gate electrode is connected to the silicon substrate through a first dielectric layer in the first region.
14. The solar cell of claim 10 or 11, wherein the first doped polysilicon layer comprises a plurality of first doped polysilicon units disposed at intervals on a surface of the tunneling layer;
the area between the adjacent first doped polysilicon units is a second area;
a second doped polysilicon unit is arranged in the second region, and a plurality of second doped polysilicon units form a second doped polysilicon layer;
the first dielectric layer covers the surfaces of the first doped polysilicon unit and the second doped polysilicon unit;
The second main gate electrode penetrates through the first dielectric layer and is connected with the second doped polysilicon layer.
15. A method of manufacturing a solar cell, comprising the steps of:
providing a silicon substrate;
providing a tunneling layer on one side surface of the silicon substrate;
depositing a first doped polysilicon layer on a side of the tunneling layer facing away from the silicon substrate;
depositing a first dielectric layer on one side of the first doped polysilicon layer away from the tunneling layer;
printing a first printing electrode slurry on one side of the first medium layer, which is away from the first doped polysilicon layer, and sintering the first printing electrode slurry to enable the first printing electrode slurry to burn through the first medium layer to form a first printing sintering layer connected with the first doped polysilicon layer, and forming crystalline first metal nano particles at the junction of the first doped polysilicon layer and the first printing sintering layer;
a plurality of first openings penetrating through the first dielectric layer are formed in the first dielectric layer;
electroplating and depositing metal on the surface of the first printed sintering layer to form a first metal layer, wherein the first printed sintering layer and the first metal layer form the first main gate electrode;
A metal is electrodeposited on a silicon substrate having a first opening.
16. The method of claim 15, further comprising heat treating the deposited metal; the sintering temperature is 750-900 ℃, and the heat treatment temperature is 250-500 ℃.
17. The method of claim 15 or 16, wherein a second dielectric layer is deposited on a surface of the silicon substrate on a side facing away from the tunneling layer;
ablating the first doped polysilicon layer and the tunneling layer at intervals on the surface of the first doped polysilicon layer to expose the silicon substrate, thereby forming a first region;
the first dielectric layer is deposited on the surface of the first doped polysilicon layer and the side surface of the first doped polysilicon layer, the side surface of the tunneling unit and the surface of the silicon substrate in the first region.
18. The method of claim 17, wherein a second printed electrode paste is printed on a surface of the first dielectric layer in the first region, a second printed sintered layer is formed by the sintering, the second printed electrode paste is sintered through the second dielectric layer to connect with a doped layer, and crystalline second metal nanoparticles or eutectic layers and a local back field are formed at a junction of the doped layer near the second printed sintered layer;
Electroplating and depositing metal on the surface of the second printing sintering layer to form a second metal layer;
the second printed sintered layer and the second metal layer form a second main gate electrode.
19. The method of claim 18, wherein a plurality of second openings are provided through the first dielectric layer on the first dielectric layer, a metal is deposited by electroplating in the second openings, a second thin gate electrode is formed by the heat treatment, and the second thin gate electrode is connected to the silicon substrate;
the second thin gate electrode intersects and is electrically connected with the second main gate electrode to form a second electrode.
20. The method of claim 15 or 16, wherein first and second doped polysilicon units are sequentially deposited at intervals on the surface of the tunneling layer,
a plurality of the first doped polysilicon units form the first doped polysilicon layer;
a plurality of the second doped polysilicon units form the second doped polysilicon layer;
the first dielectric layer is deposited on the surface of the first doped polysilicon unit and the surface of the second doped polysilicon unit.
21. The method of claim 20, wherein a second printed electrode paste is printed on a surface of the first dielectric layer corresponding to the second doped polysilicon layer and sintered to form a second printed sintered layer, the second printed electrode paste being sintered through the first dielectric layer and connected to the second doped polysilicon layer;
Electroplating and depositing metal on the surface of the second printing sintering layer to form a second metal layer;
the second printed sintered layer and the second metal layer form a second main gate electrode.
22. The method of claim 21, wherein a plurality of second openings are provided through the first dielectric layer on the first dielectric layer, metal is plated in the second openings, a second thin gate electrode is formed by the heat treatment, and the second thin gate electrode is connected to the second doped polysilicon layer;
the second thin gate electrode intersects and is electrically connected with the second main gate electrode to form a second electrode.
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