The production method of full back electrode solar cell
Technical field
The present invention relates to a kind of production method of full back electrode solar cell.
Background technology
The full back electrode battery that U.S. SunPower company releases adopts N type silicon chip, and electrode is all designed at cell backside; To promote the extinction area of battery front side to greatest extent; It is about 23% that the conversion efficiency of its volume production has reached, and the laboratory peak efficiency reaches 24.2%, but the battery preparation technique complicated steps of SunPower; Cost is high, becomes the bottleneck that scale of mass production is promoted always.
Summary of the invention
Technical problem to be solved by this invention is: a kind of production method of full back electrode solar cell is provided, simplifies processing step, reduce production costs.
The technical solution adopted for the present invention to solve the technical problems is: a kind of production method of full back electrode solar cell has following steps:
1. single face boron diffusion forms the P+ layer at the N type silicon chip back side;
2. deposition making herbs into wool mask layer on overleaf the P+ layer;
3. single face making herbs into wool;
4. phosphorous diffusion prepares front-surface field at the silicon chip sensitive surface;
5. remove making herbs into wool mask layer and PSG;
6. thermal oxide growth SiO2 mask layer;
7. slot in the back surface field zone at the silicon chip back side, groove depth H is greater than the degree of depth that equals P-N knot junction depth+back surface field;
8. printing height deducts the phosphorous dopant of P-N junction depth less than groove depth H in slot area bottom;
9. High temperature diffusion forms the N+ layer at trench bottom;
10. remove PSG and SiO2 mask layer;
11. positive and negative is made passivating film;
12. screen-printed metal electrode;
13. sintering.
Further limit, in the step 1, through two face-to-face silicon chips are stacked together, realize the single face boron diffusion, square resistance is 10-100ohm/Sq.
Further limit, in the step 2, the making herbs into wool mask layer is SiNx or SiO2, and the making herbs into wool mask layer thickness is 20-300nm.
Further limit, in the step 4, phosphorous diffusion prepares front-surface field at the silicon chip sensitive surface, and square resistance is 30-200ohm/Sq.
Further limit, in the step 6, thermal oxide growth SiO2 mask layer, thickness are 30-300nm, simultaneously P+ laminar surface concentration are further reduced, and junction depth further deepens.
Further limit, in the step 7, slotted in the back surface field zone, and carry out etching, form groove depth H with etching liquid cross-notching zone with laser.
Further limit, in the step 7, carry out etching with KOH etching liquid cross-notching zone.
Further limit, in the step 8, in etch areas bottom silk screen printing or inkjet printing printed dopant.
The invention has the beneficial effects as follows: utilize the difference in height in P+ and N+ zone to form the matrix n-quadrant, promoted battery efficiency greatly and reduced production cost, be fit to large-scale production.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is further specified.
Fig. 1 is the structural representation of step 1 of the present invention;
Fig. 2 is the structural representation of step 2 of the present invention;
Fig. 3 is the structural representation of step 3 of the present invention;
Fig. 4 is the structural representation of step 4 of the present invention;
Fig. 5 is the structural representation of step 5 of the present invention;
Fig. 6 is the structural representation of step 6 of the present invention;
Fig. 7 is the structural representation of step 7 of the present invention;
Fig. 8 is the structural representation of step 8 of the present invention;
Fig. 9 is the structural representation of step 9 of the present invention;
Figure 10 is the structural representation of step 10 of the present invention;
Figure 11 is the structural representation of step 11 of the present invention;
Figure 12 is the structural representation of step 12 of the present invention;
Figure 13 is the structural representation of step 13 of the present invention;
Figure 14 is the structural representation of step 14 of the present invention;
Among the figure, 1. silicon chip, 2.P+ layer, 3. making herbs into wool mask layer, 4. front-surface field, 5.SiO2 mask layer, 6.N+ layer, 7. passivating film, 8. metal electrode, 9. dopant.
Embodiment
Shown in Fig. 1 to 14, a kind of production method of full back electrode solar cell has following steps:
1. silicon chip 1 polishing, corrosion thickness is 2-10um;
2. silicon chip 1 carries out the single face boron diffusion face-to-face, is formed for constituting the P+ layer 2 of P-N knot at silicon chip 1 back side, and square resistance is 10-100ohm/Sq;
3. deposition SiNx or SiO2 or other making herbs into wool mask layers 3 on overleaf the P+ layer 2, making herbs into wool mask layer 3 thickness are 20-300nm, can stop the corrosion of next step Woolen-making liquid to P+ layer 2, can not destroy the P-N knot;
4. single face making herbs into wool, making herbs into wool corrosion layer thickness is 2-15um;
5. phosphorous diffusion prepares front-surface field 4, and square resistance is 30-200ohm/Sq;
6. remove SiNx or SiO2 or other making herbs into wool mask layers 3 and PSG (silicon phosphorus glass);
7. thermal oxide growth SiO2 mask layer 5, thickness is 30-300nm, simultaneously P+ layer 2 surface concentration is further reduced, junction depth further deepens;
8. with laser slotted in the back surface field zone;
9. carry out etching with KOH or other etching mode cross-notching zones, etching depth is greater than the degree of depth that equals P-N knot junction depth+back surface field, preferred 4um at least, and this difference in height is the matrix n-quadrant between P+ and N+ just;
10. silk screen printing or inkjet printing or other mode printing height deduct the phosphorous dopant 9 of P-N junction depth less than the etching groove depth in the etching groove; When next step High temperature diffusion, just only form phosphorus-diffused layer in the bottom of groove; Cell wall partly is still matrix; Be equivalent to the matrix n-quadrant between P+ and the N+, can avoid repeatedly the growing mask layer to form the matrix n-quadrant between P+ and the N+ district like this, reduce cost greatly;
11. High temperature diffusion forms n+ layer 6 in the etching groove;
12. remove PSG and SiO2 mask layer 5;
13. positive and negative deposition or thermal oxide growth passivating film 7, the passivating film 7 at the back side is Al
2O
3And SiN
XBuild up passivating film;
14. screen-printed metal electrode 8 and sintering.