The production method of all back-contact electrodes solar cell
Technical field
The present invention relates to a kind of production method of all back-contact electrodes solar cell.
Background technology
The full back electrode cell that SunPower company of the U.S. releases, adopt N-type silicon chip, electrode is all designed at cell backside, to promote the extinction area of battery front side to greatest extent, the conversion efficiency of its volume production has reached about 23%, and laboratory peak efficiency reaches 24.2%, but the battery preparation technique step of SunPower is complicated, cost is high, becomes the bottleneck that scale of mass production is promoted always.
Summary of the invention
Technical problem to be solved by this invention is: the production method providing a kind of all back-contact electrodes solar cell, Simplified flowsheet step, reduces production cost.
The technical solution adopted for the present invention to solve the technical problems is: a kind of production method of all back-contact electrodes solar cell, has following steps:
1. one side boron diffusion, forms P+ layer at the N-type silicon chip back side;
2. P+ layer overleaf deposits making herbs into wool mask layer;
3. one texture-etching side;
4. phosphorus is diffused in silicon chip sensitive surface and prepares front-surface field;
5. remove making herbs into wool mask layer and PSG;
6. thermal oxide growth SiO2 mask layer;
7. slot in the back surface field region of silicon chip back side, groove depth H is greater than the degree of depth equaling P-N junction junction depth+back surface field;
8. bottom slot area, printing height is less than groove depth H and deducts the dark phosphorous dopant of P-N junction;
9. High temperature diffusion, forms N+ layer at trench bottom;
10. remove PSG and SiO2 mask layer;
11. positive and negatives make passivating film;
12. screen-printed metal electrodes;
13. sintering.
Further restriction, in step 1, by being stacked together by face-to-face for two panels silicon chip, realize the diffusion of one side boron, square resistance is 10-100ohm/Sq.
Further restriction, in step 2, making herbs into wool mask layer is SiNx or SiO2, and making herbs into wool mask layer thickness is 20-300nm.
Further restriction, in step 4, phosphorus is diffused in silicon chip sensitive surface and prepares front-surface field, and square resistance is 30-200ohm/Sq.
Further restriction, in step 6, thermal oxide growth SiO2 mask layer, thickness is 30-300nm, and P+ layer surface concentration reduced further, junction depth deepens further simultaneously.
Further restriction, in step 7, slots to back surface field region with laser, and etches with etching liquid cross-notching region, forms groove depth H.
Further restriction, in step 7, etches with KOH etching liquid cross-notching region.
Further restriction, in step 8, in the printing of etch areas bottom web or inkjet printing printed dopant.
The invention has the beneficial effects as follows: utilize the difference in height in P+ and N+ region to form matrix n-quadrant, greatly improve battery efficiency and reduce production cost, being applicable to large-scale production.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the present invention is further described.
Fig. 1 is the structural representation of step 1 of the present invention;
Fig. 2 is the structural representation of step 2 of the present invention;
Fig. 3 is the structural representation of step 3 of the present invention;
Fig. 4 is the structural representation of step 4 of the present invention;
Fig. 5 is the structural representation of step 5 of the present invention;
Fig. 6 is the structural representation of step 6 of the present invention;
Fig. 7 is the structural representation of step 7 of the present invention;
Fig. 8 is the structural representation of step 8 of the present invention;
Fig. 9 is the structural representation of step 9 of the present invention;
Figure 10 is the structural representation of step 10 of the present invention;
Figure 11 is the structural representation of step 11 of the present invention;
Figure 12 is the structural representation of step 12 of the present invention;
Figure 13 is the structural representation of step 13 of the present invention;
Figure 14 is the structural representation of step 14 of the present invention;
In figure, 1. silicon chip, 2.P+ layer, 3. making herbs into wool mask layer, 4. front-surface field, 5.SiO2 mask layer, 6.N+ layer, 7. passivating film, 8. metal electrode, 9. dopant.
Embodiment
As shown in Fig. 1 to 14, a kind of production method of all back-contact electrodes solar cell, has following steps:
1. silicon chip 1 polishing, corrosion thickness is 2-10um;
2. silicon chip 1 carries out the diffusion of one side boron face-to-face, and form the P+ layer 2 for forming P-N junction at silicon chip 1 back side, square resistance is 10-100ohm/Sq;
3. P+ layer 2 overleaf deposits SiNx or SiO2 or other making herbs into wool mask layers 3, making herbs into wool mask layer 3 thickness is 20-300nm, can stop the corrosion of next step Woolen-making liquid to P+ layer 2, can not destroy P-N junction;
4. one texture-etching side, making herbs into wool corrosion layer thickness is 2-15um;
5. phosphorus diffusion is for front-surface field 4, and square resistance is 30-200ohm/Sq;
6. remove SiNx or SiO2 or other making herbs into wool mask layers 3 and PSG(silicon phosphorus glass);
7. thermal oxide growth SiO2 mask layer 5, thickness is 30-300nm, and P+ layer 2 surface concentration reduced further, junction depth deepens further simultaneously;
8. with laser, slotted in back surface field region;
9. etch with KOH or other etching mode cross-notching regions, etching depth is greater than the degree of depth equaling P-N junction junction depth+back surface field, preferably at least 4um, the matrix n-quadrant of this difference in height namely between P+ and N+;
10. in etching groove, silk screen printing or inkjet printing or other mode printing height are less than etching groove depth and deduct the dark phosphorous dopant 9 of P-N junction, just only phosphorus-diffused layer is formed in the bottom of groove when next step High temperature diffusion, cell wall part is still matrix, be equivalent to the matrix n-quadrant between P+ and N+, can avoid so repeatedly growing the matrix n-quadrant between mask layer formation P+ and N+ district, greatly reduce costs;
11. High temperature diffusion, form n+ layer 6 in etching groove;
12. remove PSG and SiO2 mask layer 5;
13. positive and negative deposition or thermal oxide growth passivating films 7, the passivating film 7 at the back side is Al
2o
3and SiN
xbuild up passivating film;
14. screen-printed metal electrodes 8 also sinter.