CN105097978A - N-type back junction crystalline silicon cell and preparation method thereof - Google Patents

N-type back junction crystalline silicon cell and preparation method thereof Download PDF

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CN105097978A
CN105097978A CN201510562066.4A CN201510562066A CN105097978A CN 105097978 A CN105097978 A CN 105097978A CN 201510562066 A CN201510562066 A CN 201510562066A CN 105097978 A CN105097978 A CN 105097978A
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layer
boron
type
diffusion
silicon chip
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张中伟
程鹏飞
李愿杰
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Dongfang Electric Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0216Coatings
    • H01L31/02161Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868Passivation
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/547Monocrystalline silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention provides an N-type back junction crystalline silicon cell and a preparation method thereof. The battery comprises a front surface Ag electrode, a front surface antireflection film, a phosphorus diffusion N+ front surface field layer, an N-type base, a boron diffusion emitter P+ layer, a back passivation composite film and a back AgAl electrode, wherein the PN junction is located on the back surface of the cell; a polishing structure is adopted by the back surface of the battery; the back passivation composite film comprises a borosilicate glass layer and a silicon nitride layer; the borosilicate glass layer is located on the boron diffusion emitter P+ layer; and the silicon nitride layer is deposited on the borosilicate glass layer; a boron emitter is passivated by the borosilicate glass layer and silicon nitride laminated film structure generated in the boron diffusion process; the polishing structure is adopted by the back surface; and the passivation effect of the boron emitter is further improved. The preparation technology of the battery is relatively simple, can be compatible with equipment of the current crystalline silicon cell production line, and is suitable for large-scale industrial production; and the cost can be reduced.

Description

A kind of N-type back of the body crystalline solid silion cell and preparation method thereof
Technical field
The present invention relates to manufacture of solar cells technical field, particularly a kind of N-type back of the body crystalline solid silion cell structure and preparation method thereof.
Background technology
Current crystal silicon cell is the main product in solar cell market, and crystal silicon solar batteries can be divided into again P type crystal silicon battery and N-type crystal silicon battery material matrix type.Relative to p type single crystal silicon battery, n type single crystal silicon battery has the features such as little, the resistance to metal impurity con performance of photo attenuation is good, minority carrierdiffusion length is long, obtain everybody concern gradually, but shortcoming needs in preparation process repeatedly to spread, and the Passivation Treatment to boron emitter, preparation flow is comparatively complicated.
For the N-type crystal silicon battery of simple structure, because relate to a boron diffusion and a phosphorus diffusion, so mutually sheltering in battery preparation flow between boron, phosphorus diffusion process, the passivation of boron emitter has important meaning for lifting battery efficiency.Different producers adopts different preparation technology's flow processs, and for first boron-doping, after completing one side doping formation p+ boron emitter layer, existing technique mainly adopts the SiO of thermal oxide growth 2film, as the diffusion impervious layer mixing phosphorus face, removes SiO afterwards again 2masking layer, then the process carrying out emitter passivation.This method relates to pyroprocess and step is numerous and diverse, the temperatures as high of thermal oxidation more than 1000 DEG C, and the simultaneous oxidation time should be no less than 30min to form the SiO that thickness is greater than 100nm 2film.This pyroprocess easily causes the diffusion profile of p+ layer to change, and as the reduction of surface dopant concentration, the increase of junction depth, causes the series resistance of battery to increase, and electrical contact performance declines; Pyroprocess easily causes the impurity concentration of silicon substrate to increase simultaneously, and the bluk recombination of battery aggravates thereupon, finally shows as the decline of open circuit voltage and whole efficiency.Patent CN102544236B removes Pyrex layer, then utilizes the method for low-pressure chemical vapor deposition (LPCVD) at silicon chip two sides deposition SiN after being reported in one side B doping formation p+ boron emitter layer xfilm, then at the SiN of B extended surface xupper deposition SiO 2, utilize phosphoric acid to remove not by SiO 2the SiN of protection xface, then carries out phosphorus diffusion on this face, and the method relates to repeatedly plated film and cleaning process, and technics comparing is complicated, is unfavorable for enhancing productivity and reducing production cost.
Summary of the invention
The present invention aims to provide a kind of N-type back of the body crystalline solid silion cell and preparation method thereof, PN junction is positioned at cell backside, the Pyrex layer that generates in boron diffusion process and silicon nitride stack membrane structure is utilized to carry out passivation to boron emitter, the back side adopts polishing structure, promotes the passivation effect of boron emitter further; The preparation technology of this structure battery is comparatively simple, can with current crystal silicon cell manufacturing line hardware compatibility, can reduce costs, be suitable for large-scale industrial production.
For achieving the above object, the technical solution used in the present invention is:
A kind of N-type back of the body crystalline solid silion cell, comprise front surface Ag electrode, front surface antireflective coating, phosphorus diffusion N+ front-surface field layer, N-type substrate, boron diffused emitter P+ layer, passivating back composite membrane, back side AgAl electrode, it is characterized in that: PN junction is positioned at cell backside, cell backside adopts polishing structure; Described passivating back composite membrane comprises Pyrex layer and one deck silicon nitride layer of one deck oxidation processes, and Pyrex layer is on boron diffused emitter P+ layer, and silicon nitride layer is then deposited on Pyrex layer.
The thickness range of described Pyrex layer is 40-110nm; In described passivating back composite membrane, the thickness range of silicon nitride layer is 20-70nm.
The preparation method of above-mentioned N-type back of the body crystalline solid silion cell, comprises the steps:
(1) original N-type silicon chip is cleaned, remove the damage layer on N-type silicon chip surface, utilize aqueous slkali to carry out polishing to silicon chip;
(2) the veneer ground, face, front of the N-type silicon chip after step (1) being processed is placed and is carried out the diffusion of one side boron; The back side of N-type silicon chip is boron diffusingsurface, forms boron diffused emitter P+ layer, can form one deck Pyrex layer in diffusion process on boron diffusingsurface;
(3) advance in the temperature-fall period after terminating in boron diffusion, the oxygen passing into certain flow to Pyrex layer and and the interface of N-type silicon chip be oxidized, until be cooled to 760 DEG C ~ 840 DEG C;
(4) Pyrex layer after oxidation deposits one deck silicon nitride layer, the thickness of silicon nitride layer is 25-70nm;
(5) front of N-type silicon chip is carried out alkali formula making herbs into wool etching, remove the diffraction diffusion layer formed in front in boron diffusion process simultaneously, form random pyramid face, good front; The Pyrex layer at the N-type silicon chip back side and silicon nitride layer as the protective layer of boron diffused emitter P+ layer, for preventing alkali liquid corrosion boron emitter;
(6) diffusion of one side phosphorus is carried out at the back side of N-type silicon chip back-to-back, the front of N-type silicon chip is phosphorus diffusion N+ front-surface field layer, and diffused sheet resistance is 50 ~ 80 Ω/, and the Pyrex on boron diffused emitter P+ layer and silicon nitride layer serve as diffusion mask layer;
(7) the periphery knot utilizing plasma etching or laser ablation removal phosphorus to diffuse to form, utilizes one side chemical etching equipment removal phosphorus to be diffused in phosphorus sila matter glassy layer (PSG) of front formation;
(8) at the front deposited silicon nitride antireflective film of silicon chip, thickness is 70-80nm;
(9) at the back up AgAl electrode (containing aluminium mass percent 2% ~ 5% in silver-colored aluminum slurry) of silicon chip, front printing Ag electrode, dries sintering, can obtain N-type back of the body solar cells made of crystalline silicon.
When doing the diffusion of one side boron in step (2), adopt BBr 3liquid source spreads, and diffusion temperature is 900 ~ 970 DEG C, and the time is 30 ~ 60min, and diffused sheet resistance is 50 ~ 80 Ω/.
The flow passing into oxygen in the oxidizing process of step (3) is 3-16slm, and oxidization time is 3-40min.
Depositing temperature in step (4) is 400 ~ 450 DEG C, and the thickness range of the silicon nitride layer of deposition is 20-70nm; Further, the deposition in step (4) adopts plasma reinforced chemical vapour deposition (PECVD) method.
Alkali formula making herbs into wool etching in step (5) utilizes groove type etching equipment to etch.
One side chemical etching equipment is that roll-type transports chemical etching equipment in step (7), and chemical etching chemical solution used is the mixed solution of hydrofluoric acid, sulfuric acid and water.
Beneficial effect of the present invention is as follows:
In battery preparation technique, oxidation processes is carried out to the Pyrex layer that boron emitter P+ layer surface is formed, reduce the concentration of the B atom at silicon and Pyrex bed boundary place, thus reduce the density of interfacial state, reduce interface recombination velocities, achieve the passivation to diffused layer of boron, and adopt the structure of polished backside, passivation effect can be promoted further, the open circuit voltage of battery, short circuit current and photoelectric conversion efficiency can be improved.Adopt the passivation layer serving as boron emitter through the Pyrex layer of oxidation processes and silicon nitride layer laminate film; this laminate film also serves as the corrosion protection layer of follow-up front making herbs into wool, the diffusion mask layer of phosphorus diffusion; the passivation of boron emitter, chemical etching protection and the function of diffusion mask can be realized simultaneously, decrease the process of repeatedly mask deposition and mask etching in processing procedure.Because N-type silicon chip has the long feature of minority carrier life time, therefore the PN junction area that the photo-generated carrier produced at battery front surface also can diffuse to rear surface place is collected, so adopt front surface light, the structure that PN junction is placed in cell backside requires not strict to back side antireflective properties, not harsh to the thickness requirement of Pyrex, increase the fluctuation tolerance of diffusion and oxidation technology.PN junction is placed in the back side, adopts polished backside structure and BSG/SiN xlaminated construction can Simplified flowsheet greatly as the boron emitter passivation layer of battery and diffusion mask layer, improves production efficiency, reduces production technology cost, have positive realistic meaning.
Accompanying drawing explanation
Fig. 1 is battery structure schematic diagram of the present invention;
Wherein, accompanying drawing 1 is labeled as: 1 front silver electrode; 2 front surface antireflection film (SiN x); 3 phosphorus diffusion N+ front-surface field layers; 4 is N-type silicon chip; 5 boron diffused emitter P+ layers; The Pyrex layer (BSG) of 6 oxidation processes; 7 is back side SiN xlayer; 8 is back metal AgAl electrodes.
Embodiment
embodiment 1
A preparation method for back side knot N-type crystal silicon solar batteries, comprises the steps:
(1) adopt n type single crystal silicon silicon chip to be substrate, resistivity is 1 ~ 12Wcm, and thickness is 170 ~ 200mm, is cleaned by silicon chip, and remove the damage layer on surface, utilize NaOH aqueous slkali to carry out polishing to silicon chip, NaOH mass fraction is 20%;
(2) placed and carry out the diffusion of one side boron by face, the front veneer of above-mentioned silicon chip, silicon chip back side is boron diffused emitter P+ layer, and square resistance is 60 Ω/, adopts BBr 3liquid source spreads, and diffusion temperature is 950 degree, and the time is 60min;
(3) advance in boron diffusion the oxygen that passes into certain flow in the temperature-fall period after terminating to Pyrex and and the interface of silicon be oxidized, until be cooled to 790 DEG C, the flow of oxygen is 10slm, and oxidization time is 30min.
(4) Pyrex layer after oxidation deposits one deck silicon nitride film by the method for plasma reinforced chemical vapour deposition (PECVD), thickness is 30nm;
(5) utilize groove type etching equipment to carry out the making herbs into wool of alkali formula to the front side of silicon wafer after PECVD plated film, remove front diffraction layer when boron spreads and prepare random pyramid at front side of silicon wafer;
(6) back-to-back for the silicon chip in (5) being positioned in diffusion furnace is carried out phosphorus diffusion, form phosphorus diffusion N+ front-surface field layer, diffusion temperature is 790-840 DEG C, and deposition and propelling time are total up to 30-40min, and diffused sheet resistance is 70 Ω/;
(7) the periphery knot utilizing the method for plasma etching or laser scribing removal phosphorus to diffuse to form, utilizes one side chemical etching system removal phosphorus to be diffused in phosphorus sila matter glassy layer (PSG) of front formation;
(8) PECVD system is utilized to deposit SiN at front side of silicon wafer xanti-reflecting layer, thickness is 75-80nm;
(9) utilize screen printing apparatus at silicon chip back side printing AgAl slurry, front printing Ag slurry, sintering, prepare N-type back of the body crystalline solid silion cell.
As shown in Figure 1, this N-type back of the body crystalline solid silion cell, comprise front surface Ag electrode, front surface antireflective coating, phosphorus diffusion N+ front-surface field layer, N-type substrate, boron diffused emitter P+ layer, passivating back composite membrane, back side AgAl electrode, PN junction is positioned at cell backside, and cell backside adopts polishing structure; Passivating back composite membrane comprises Pyrex layer and one deck silicon nitride layer of one deck oxidation processes, and Pyrex layer is on boron diffused emitter P+ layer, and silicon nitride layer is then deposited on Pyrex layer.
embodiment 2
A preparation method for back side knot N-type crystal silicon solar batteries, comprises the steps:
(1) adopt n type single crystal silicon silicon chip to be substrate, resistivity is 1 ~ 12Wcm, and thickness is 170 ~ 200mm, is cleaned by silicon chip, and remove the damage layer on surface, utilize potassium hydroxide aqueous slkali to carry out polishing to silicon chip, potassium hydroxide mass concentration is 25%;
(2) placed and carry out the diffusion of one side boron by face, the front veneer of above-mentioned silicon chip, silicon chip back side is boron diffused emitter P+ layer, and square resistance is 50 Ω/, adopts BBr 3liquid source spreads, and diffusion temperature is 970 degree, and the time is 60min;
(3) advance in boron diffusion the oxygen that passes into certain flow in the temperature-fall period after terminating to Pyrex and and the interface of silicon be oxidized, until be cooled to 760 DEG C, the flow of oxygen is 5slm, and oxidization time is 40min.
(4) Pyrex layer after oxidation deposits one deck silicon nitride film by the method for plasma reinforced chemical vapour deposition (PECVD), thickness is 50nm;
(5) utilize groove type etching equipment to carry out the making herbs into wool of alkali formula to the front side of silicon wafer after PECVD plated film, remove front diffraction layer when boron spreads and prepare random pyramid at front side of silicon wafer;
(6) back-to-back for the silicon chip in (5) being positioned in diffusion furnace is carried out phosphorus diffusion, form phosphorus diffusion N+ front-surface field layer, diffusion temperature is 790-840 DEG C, and deposition and propelling time are total up to 30-40min, and diffused sheet resistance is 60 Ω/;
(7) the periphery knot utilizing the method for plasma etching or laser scribing removal phosphorus to diffuse to form, utilizes one side chemical etching system removal phosphorus to be diffused in phosphorus sila matter glassy layer (PSG) of front formation;
(8) PECVD system is utilized to deposit SiN at front side of silicon wafer xanti-reflecting layer, thickness is 70-80nm;
Utilize screen printing apparatus at silicon chip back side printing AgAl slurry, front printing Ag slurry, sintering, prepare back side knot N-type crystal silicon battery.

Claims (10)

1. a N-type back of the body crystalline solid silion cell, comprise front surface Ag electrode, front surface antireflective coating, phosphorus diffusion N+ front-surface field layer, N-type substrate, boron diffused emitter P+ layer, passivating back composite membrane, back side AgAl electrode, it is characterized in that: PN junction is positioned at cell backside, cell backside adopts polishing structure; Described passivating back composite membrane comprises Pyrex layer and one deck silicon nitride layer of one deck oxidation processes, and Pyrex layer is on boron diffused emitter P+ layer, and silicon nitride layer is then deposited on Pyrex layer.
2. N-type back of the body crystalline solid silion cell according to claim 1, is characterized in that: the thickness range of described Pyrex layer is 40-110nm.
3. N-type back of the body crystalline solid silion cell according to claim 1, is characterized in that: the thickness range of described silicon nitride layer is 20-70nm.
4. prepare the method for the N-type back of the body crystalline solid silion cell in claim 1-3 described in any one, it is characterized in that comprising the steps:
(1) original N-type silicon chip is cleaned, remove the damage layer on N-type silicon chip surface, utilize aqueous slkali to carry out polishing to silicon chip;
(2) the veneer ground, face, front of the N-type silicon chip after step (1) being processed is placed and is carried out the diffusion of one side boron; The back side of N-type silicon chip is boron diffusingsurface, forms boron diffused emitter P+ layer, can form one deck Pyrex layer in diffusion process on boron diffusingsurface;
(3) advance in the temperature-fall period after terminating in boron diffusion, the oxygen passing into certain flow to Pyrex layer and and the interface of N-type silicon chip be oxidized, until be cooled to 760 DEG C ~ 840 DEG C;
(4) Pyrex layer after oxidation deposits one deck silicon nitride layer;
(5) front of N-type silicon chip is carried out alkali formula making herbs into wool etching, remove the diffraction diffusion layer formed in front in boron diffusion process simultaneously, form random pyramid face, front; The Pyrex layer at the N-type silicon chip back side and silicon nitride layer as the protective layer of boron diffused emitter P+ layer, for preventing alkali liquid corrosion boron emitter;
(6) diffusion of one side phosphorus is carried out at the back side of N-type silicon chip back-to-back, the front of N-type silicon chip is phosphorus diffusingsurface, and diffused sheet resistance is 50 ~ 80 Ω/, and the Pyrex layer on boron diffused emitter P+ layer and silicon nitride layer serve as diffusion mask layer;
(7) the periphery knot utilizing plasma etching or laser ablation removal phosphorus to diffuse to form, utilizes one side chemical etching equipment removal phosphorus to be diffused in the phosphorus sila matter glassy layer of front formation;
(8) at the front deposited silicon nitride antireflective film of silicon chip, thickness is 70-80nm;
(9) at the back up AgAl electrode of silicon chip, front printing Ag electrode, dries sintering, can obtain N-type back of the body solar cells made of crystalline silicon.
5. the preparation method of N-type back of the body crystalline solid silion cell according to claim 4, is characterized in that: when doing the diffusion of one side boron in step (2), adopt BBr 3liquid source spreads, and diffusion temperature is 900 ~ 970 DEG C, and the time is 30 ~ 60min, and diffused sheet resistance is 50 ~ 80 Ω/.
6. the preparation method of N-type back of the body crystalline solid silion cell according to claim 4, is characterized in that: the flow passing into oxygen in the oxidizing process of described step (3) is 3-16slm, and oxidization time is 3-40min.
7. the preparation method of N-type back of the body crystalline solid silion cell according to claim 4, it is characterized in that: the depositing temperature in step (4) is 400 ~ 450 DEG C, the thickness range of the silicon nitride layer of deposition is 20-70nm.
8. the preparation method of N-type back of the body crystalline solid silion cell according to claim 4, is characterized in that: the deposition in step (4) adopts plasma reinforced chemical vapour deposition method.
9. the preparation method of N-type back of the body crystalline solid silion cell according to claim 4, is characterized in that: the alkali formula making herbs into wool etching in step (5) utilizes groove type etching equipment to etch.
10. the preparation method of N-type back of the body crystalline solid silion cell according to claim 4, it is characterized in that: one side chemical etching equipment is that roll-type transports chemical etching equipment in step (7), chemical etching chemical solution used is the mixed solution of hydrofluoric acid, sulfuric acid and water.
CN201510562066.4A 2015-09-07 2015-09-07 N-type back junction crystalline silicon cell and preparation method thereof Pending CN105097978A (en)

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CN105655424A (en) * 2016-03-31 2016-06-08 江苏顺风光电科技有限公司 Full-back-field diffusion N-type silicon-based battery and preparation method thereof
CN105826428A (en) * 2016-04-26 2016-08-03 泰州中来光电科技有限公司 Passivated contact N type crystal silicon cell, preparation method, assembly and system
CN108039374A (en) * 2017-10-31 2018-05-15 泰州隆基乐叶光伏科技有限公司 The preparation method of N-shaped double-side solar cell
CN108538958A (en) * 2018-03-21 2018-09-14 锦州华昌光伏科技有限公司 A kind of N-type IBC batteries and preparation method thereof
CN109004053A (en) * 2017-06-06 2018-12-14 中国科学院上海微系统与信息技术研究所 The crystalline silicon of double-side photic/film silicon heterojunction solar battery and production method
CN109802008A (en) * 2019-01-18 2019-05-24 江苏大学 A kind of manufacturing method of high efficiency, low cost N-type back knot PERT double-side cell
CN111129217A (en) * 2019-12-20 2020-05-08 浙江爱旭太阳能科技有限公司 Method for producing a solar cell and solar cell
CN111584666A (en) * 2020-06-09 2020-08-25 山西潞安太阳能科技有限责任公司 Novel P-type crystalline silicon cell structure and preparation process thereof

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Cited By (12)

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Publication number Priority date Publication date Assignee Title
CN105514180A (en) * 2015-12-11 2016-04-20 英利能源(中国)有限公司 N-type back junction double-face battery and preparation method thereof
CN105655424A (en) * 2016-03-31 2016-06-08 江苏顺风光电科技有限公司 Full-back-field diffusion N-type silicon-based battery and preparation method thereof
CN105826428A (en) * 2016-04-26 2016-08-03 泰州中来光电科技有限公司 Passivated contact N type crystal silicon cell, preparation method, assembly and system
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CN108538958A (en) * 2018-03-21 2018-09-14 锦州华昌光伏科技有限公司 A kind of N-type IBC batteries and preparation method thereof
CN109802008A (en) * 2019-01-18 2019-05-24 江苏大学 A kind of manufacturing method of high efficiency, low cost N-type back knot PERT double-side cell
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CN111129217B (en) * 2019-12-20 2021-05-18 浙江爱旭太阳能科技有限公司 Method for producing a solar cell and solar cell
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