CN114784140B - Topcon battery preparation method, topcon battery and winding-removing plating tank type cleaning machine - Google Patents
Topcon battery preparation method, topcon battery and winding-removing plating tank type cleaning machine Download PDFInfo
- Publication number
- CN114784140B CN114784140B CN202210353011.2A CN202210353011A CN114784140B CN 114784140 B CN114784140 B CN 114784140B CN 202210353011 A CN202210353011 A CN 202210353011A CN 114784140 B CN114784140 B CN 114784140B
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon wafer
- phosphorus
- oxide layer
- tunneling oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004140 cleaning Methods 0.000 title claims abstract description 123
- 238000007747 plating Methods 0.000 title claims abstract description 54
- 238000002360 preparation method Methods 0.000 title abstract description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 239
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 238
- 239000010703 silicon Substances 0.000 claims abstract description 238
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 165
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 145
- 239000011574 phosphorus Substances 0.000 claims abstract description 145
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 145
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 111
- 230000005641 tunneling Effects 0.000 claims abstract description 96
- 229920005591 polysilicon Polymers 0.000 claims abstract description 94
- 238000009792 diffusion process Methods 0.000 claims abstract description 53
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910052796 boron Inorganic materials 0.000 claims abstract description 43
- 239000005360 phosphosilicate glass Substances 0.000 claims abstract description 43
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims abstract description 40
- 239000011259 mixed solution Substances 0.000 claims abstract description 37
- 238000002161 passivation Methods 0.000 claims abstract description 33
- 239000011521 glass Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 90
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 64
- 239000000243 solution Substances 0.000 claims description 40
- 239000005388 borosilicate glass Substances 0.000 claims description 23
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 21
- 208000005156 Dehydration Diseases 0.000 claims description 3
- 230000018044 dehydration Effects 0.000 claims description 3
- 238000006297 dehydration reaction Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 318
- 235000012431 wafers Nutrition 0.000 description 228
- 238000005530 etching Methods 0.000 description 26
- 238000005406 washing Methods 0.000 description 20
- 239000000654 additive Substances 0.000 description 19
- 230000000996 additive effect Effects 0.000 description 13
- 238000002310 reflectometry Methods 0.000 description 12
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 11
- 239000003513 alkali Substances 0.000 description 10
- 238000002347 injection Methods 0.000 description 10
- 239000007924 injection Substances 0.000 description 10
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 10
- 238000000151 deposition Methods 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 8
- 238000005554 pickling Methods 0.000 description 8
- 239000008367 deionised water Substances 0.000 description 7
- 229910021641 deionized water Inorganic materials 0.000 description 7
- 238000002156 mixing Methods 0.000 description 7
- HEMHJVSKTPXQMS-UHFFFAOYSA-M sodium hydroxide Inorganic materials [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 229910004205 SiNX Inorganic materials 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 6
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 5
- 229910017604 nitric acid Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 4
- 238000005245 sintering Methods 0.000 description 4
- 238000004804 winding Methods 0.000 description 4
- 229910017107 AlOx Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- ILAHWRKJUDSMFH-UHFFFAOYSA-N boron tribromide Chemical compound BrB(Br)Br ILAHWRKJUDSMFH-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002346 layers by function Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000036632 reaction speed Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000002270 dispersing agent Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000002667 nucleating agent Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- -1 particulates Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000004094 surface-active agent Substances 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- WRECIMRULFAWHA-UHFFFAOYSA-N trimethyl borate Chemical compound COB(OC)OC WRECIMRULFAWHA-UHFFFAOYSA-N 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
- H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
- H01L21/67057—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing with the semiconductor substrates being dipped in baths or vessels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67075—Apparatus for fluid treatment for etching for wet etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Life Sciences & Earth Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Sustainable Development (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Weting (AREA)
Abstract
The invention provides a preparation method of a Topcon battery, the Topcon battery and a winding-removing plating tank type cleaning machine, and relates to the technical field of solar photovoltaics.A silicon wafer is provided firstly, the silicon wafer comprises a front surface, a back surface opposite to the front surface, and a side surface connecting the front surface and the back surface, then a boron doped layer is prepared on the front surface, a tunneling oxide layer and a phosphorus doped polysilicon layer are prepared on the back surface, a tunneling oxide layer which winds and plates on the side surface is formed in the preparation process of the tunneling oxide layer, and a phosphorus glass layer which winds and plates on the side surface outside and inwards outside the tunneling oxide layer, a phosphorus doped polysilicon layer and a phosphorus inner diffusion layer which is positioned on the side surface and penetrates through the tunneling oxide layer are formed in the preparation process of the phosphorus doped polysilicon layer; after the phosphosilicate glass layer, the phosphorus doped polysilicon layer and the tunneling oxide layer which are plated around are removed, the silicon wafer is cleaned by adopting a mixed solution of ozone and hydrofluoric acid, the edge of the silicon wafer can be etched continuously, the phosphorus inner expanding layer is effectively removed, the phosphorus over-expanding concentration of the edge is reduced, the front passivation effect is improved, and the electric leakage problem is avoided.
Description
Technical Field
The invention relates to the technical field of solar photovoltaics, in particular to a preparation method of a Topcon battery, the Topcon battery and a winding-removing plating tank type cleaning machine.
Background
The front surface of the tunneling oxide passivation contact (tunnel oxide passivated contact, topcon) battery adopts a laminated passivation film, and the back surface adopts a tunneling oxide passivation contact structure of ultrathin silicon oxide and doped polysilicon (poly-Si), so that the selective passing of majority carriers is realized, the recombination rate of minority carriers is reduced, and the conversion efficiency is improved.
In the preparation process of the Topcon battery, LPCVD ((Low-pressure Chemical Vapor Deposition, low pressure chemical vapor deposition) can be adopted to deposit and prepare poly-Si on the back surface of a silicon wafer for a long time, in actual production, the front surface of the silicon wafer is usually inserted into a clamping groove of a quartz boat in a double way, so that the front surface of the silicon wafer faces inwards and the back surface faces outwards, and in the process of depositing poly-Si on the back surface, the front surface and the side surface of the silicon wafer generate coiling plating of poly-Si due to gaps between the front surfaces of the double-inserted silicon wafer, and the coiling plating of the poly-Si influences the appearance and the performance of the battery.
Disclosure of Invention
The invention provides a Topcon battery preparation method, a Topcon battery and a winding-removing plating tank type cleaning machine, which aim to solve the problem of edge leakage of a finished Topcon battery, reduce edge recombination of the battery and improve the conversion efficiency of the battery.
In a first aspect, an embodiment of the present invention provides a method for preparing a Topcon battery, where the method may include:
providing a silicon wafer, wherein the silicon wafer comprises a front surface and a back surface opposite to the front surface, and a side surface connecting the front surface and the back surface;
preparing a boron doped layer on the front surface, and sequentially preparing a tunneling oxide layer and a phosphorus doped polysilicon layer on the back surface, wherein a tunneling oxide layer which is plated around the side surface is formed in the process of preparing the tunneling oxide layer, and a phosphorus glass layer which is plated around the tunneling oxide layer of the side surface from outside to inside, a phosphorus doped polysilicon layer and a phosphorus inner diffusion layer which is positioned on the side surface and penetrates through the tunneling oxide layer are formed in the process of preparing the phosphorus doped polysilicon layer;
removing the phosphosilicate glass layer which is plated around, the phosphorus doped polysilicon layer which is plated around and the tunneling oxide layer which is plated around;
and cleaning the silicon wafer by adopting a mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner diffusion layer on the side surface.
Optionally, the mass fraction of ozone in the mixed solution is 0.025-0.065%.
Optionally, the mass fraction of the hydrofluoric acid in the mixed solution is 0.0027-0.0068 per mill.
Optionally, the cleaning time of the cleaning is 180-250 seconds.
Optionally, the removing the phosphosilicate glass layer, the phosphorus doped polysilicon layer, and the tunneling oxide layer includes:
removing the phosphosilicate glass layer around the front and the side surfaces;
removing the phosphorus doped polysilicon layer around the front surface and the side surface;
removing the tunneling oxide layer around the front surface and the side surface, the borosilicate glass layer around the front surface, and the phosphosilicate glass layer around the back surface.
Optionally, after the silicon wafer is cleaned by adopting the mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner diffusion layer on the side surface, the method further comprises:
preparing passivation films on the front surface and the back surface;
electrodes are prepared on the front side and the back side.
Optionally, before the silicon wafer is cleaned by adopting the mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner diffusion layer on the side surface, the method further comprises:
adopting potassium hydroxide and hydrogen peroxide to treat the silicon wafer;
optionally, after the silicon wafer is cleaned by adopting the mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner diffusion layer on the side surface, the method further comprises:
And carrying out dehydration treatment on the silicon wafer.
In a second aspect, an embodiment of the present invention provides a Topcon battery, where the Topcon battery is prepared by using the method for preparing a Topcon battery described in the first aspect;
the front side of the Topcon cell is in a round corner pyramid structure.
In a third aspect, an embodiment of the present invention provides a decoiling plating tank type cleaning machine, which includes a first cleaning tank, a second cleaning tank, and a third cleaning tank sequentially disposed, where the first cleaning tank is configured with a potassium hydroxide solution, the second cleaning tank is configured with a hydrofluoric acid solution, and the third cleaning tank is configured with a mixed solution of ozone and hydrofluoric acid;
the unwind plating tank type cleaning machine is used for the Topcon battery preparation method described in the first aspect.
Optionally, the first cleaning tank is used for removing the phosphorus doped polysilicon layer around plating the front surface and the side surface.
Optionally, the second cleaning tank is used for removing the tunneling oxide layer around the front surface and the side surface, the borosilicate glass layer around the front surface, and the phosphosilicate glass layer around the back surface.
Optionally, the third cleaning tank is used for cleaning the silicon wafer by adopting a mixed solution of ozone and hydrofluoric acid so as to remove the phosphorus inner diffusion layer on the side surface.
The method for preparing the Topcon battery comprises the steps of firstly providing a silicon wafer, wherein the silicon wafer comprises a front surface, a back surface opposite to the front surface, and a side surface connecting the front surface and the back surface, preparing a boron doped layer on the front surface of the silicon wafer, and sequentially preparing a tunneling oxide layer and a phosphorus doped polysilicon layer on the back surface, wherein a tunneling oxide layer which is wound and plated on the side surface is formed in the process of preparing the tunneling oxide layer, and a phosphorus glass layer which is wound and plated on the side surface and is outside-in-outside phosphorus doped polysilicon layer and a phosphorus inner expansion layer which is positioned on the side surface and penetrates through the tunneling oxide layer are formed in the process of preparing the phosphorus doped polysilicon layer; and then removing the phosphosilicate glass layer which is plated around, the phosphorus doped polysilicon layer which is plated around and the tunneling oxide layer which is plated around, and then further adopting a mixed solution of ozone and hydrofluoric acid to clean the silicon wafer.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows one of the step flowcharts of a Topcon battery preparation method according to an embodiment of the present invention;
fig. 2 shows a second step flowchart of a Topcon battery preparation method according to an embodiment of the present invention;
fig. 3 shows a schematic diagram of a silicon wafer structure according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 shows one of the step flowcharts of a Topcon battery preparation method according to an embodiment of the present invention, where the method may include:
step 101, providing a silicon wafer, wherein the silicon wafer comprises a front surface and a back surface opposite to the front surface, and a side surface connecting the front surface and the back surface.
The embodiment of the invention is applied to the preparation of the Topcon battery, the Topcon battery generally adopts a silicon wafer as a substrate, the silicon wafer can comprise a front surface and a back surface opposite to the front surface, the side surfaces connecting the front surface and the back surface are the side surfaces of the edges of the silicon wafer, the same side surfaces of the silicon wafer and the light incident side of the Topcon battery are generally used as the front surface, the same side surfaces of the silicon wafer and the backlight side of the Topcon battery are used as the back surface, the edges of the silicon wafer between the front surface and the back surface are the side surfaces, and the front surface of the silicon wafer can be processed or corresponding functional layers can be prepared due to the fact that light is incident from the front surface of the silicon wafer, so that the light absorption efficiency of the Topcon battery is improved.
Step 102, preparing a boron doped layer on the front surface, and sequentially preparing a tunneling oxide layer and a phosphorus doped polysilicon layer on the back surface, wherein a tunneling oxide layer which is wound and plated on the side surface is formed in the process of preparing the tunneling oxide layer, and a phosphorus glass layer which is wound and plated on the side surface and outside the tunneling oxide layer and inside the phosphorus doped polysilicon layer and a phosphorus inner diffusion layer which is positioned on the side surface and penetrates through the tunneling oxide layer are formed in the process of preparing the phosphorus doped polysilicon layer.
In the embodiment of the invention, the preparation of the Topcon battery can prepare the boron doped layer on the front side of the silicon wafer and prepare the tunneling oxide (SiO) sequentially laminated on the back side of the silicon wafer 2 ) The passivation contact structure is formed on the back of the silicon wafer by the layer and the phosphorus doped polysilicon layer, wherein the boron doped layer can be prepared on the front of the silicon wafer by adopting a boron diffusion process, the tunneling oxide layer can be prepared by adopting LPCVD deposition, the phosphorus doped polysilicon layer can be prepared by adopting LPCVD deposition, and the preparation processes for preparing the boron doped layer, the tunneling oxide layer and the phosphorus doped polysilicon layer can be selected by a person skilled in the art according to application requirements and process conditions.
In the embodiment of the invention, a tunneling oxide layer may be formed around plating on the side surface of a silicon wafer in the process of preparing the tunneling oxide layer, a phosphosilicate glass layer, a phosphorus doped polysilicon (Poly-Si) layer and a phosphorus inner expansion layer which is positioned on the side surface and penetrates through the tunneling oxide layer may be formed outside-in around plating outside the tunneling oxide layer on the side surface of the silicon wafer in the process of preparing the phosphorus doped polysilicon layer, and all film layers of the side surface around plating of the silicon wafer affect the appearance and performance of a battery and need to be cleaned and removed in the preparation process.
Step 103, removing the phosphosilicate glass layer which is plated around, the phosphorus doped polysilicon layer which is plated around and the tunneling oxide layer which is plated around.
In the embodiment of the invention, the phosphosilicate glass layer, the phosphorus doped polysilicon layer and the tunneling oxide layer which are plated around the silicon wafer can be removed, and only the boron doped layer on the front side of the silicon wafer, the tunneling oxide layer on the back side and the phosphorus doped polysilicon layer are reserved. Alternatively, during the process of preparing the front boron doped layer, borosilicate glass layers may be formed on the front and back sides of the silicon wafer, wherein the borosilicate glass layer on the back side may be removed before preparing the tunnel oxide layer and the phosphorus doped polysilicon layer, and the borosilicate glass layer on the front side may be removed after preparing the tunnel oxide layer and the phosphorus doped polysilicon layer. The removal sequence and the removal process of each layer on each surface of the silicon wafer can be selected according to the process conditions and the process requirements, for example, a borosilicate glass layer, a coiled and plated phosphosilicate glass layer, a tunneling oxide layer and the like can be removed by acid washing, a coiled and plated phosphorus doped polysilicon layer can be removed by alkali washing, and laser removal can be also used.
Currently, the poly-Si wrap-around plating is generally performed by an alkaline etching process, which includes removing a PSG (Phospho Silicate Glass ) layer on the front surface in a chain cleaner, and then alkaline-washing the front surface and the side surfaces of the poly-Si wrap-around plating in a tank cleaner.
And researches show that after the winding-plated phosphosilicate glass layer, the phosphorus-doped polysilicon layer and the tunneling oxide layer are removed, the phosphorus inner expansion layer which passes through the side winding-plated tunneling oxide layer and is formed in the process of preparing the phosphorus-doped polysilicon layer is arranged at the edge of the silicon wafer, and the existence of the phosphorus inner expansion layer causes the problem of electric leakage at the edge of the silicon wafer, so that the performance of the finished Topcon battery is affected. In particular, since the protective additive is generally used in the alkaline etching process, the protective additive is used for the SiO 2 Etching poly-Si around the plating on the basis of the protection of the layer, while SiO 2 The reaction speed of the layer and the alkali liquor is slower, and the tunneling oxide layer existing under the poly-Si around the side surface of the silicon wafer prevents the continuous etching reaction of the phosphorus inner expansion at the edge of the silicon wafer, so that the phosphorus inner expansion layer passing through the tunneling oxide layer can not be fully removed through the etching reactionAnd (5) removing.
And 104, cleaning the silicon wafer by adopting a mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner diffusion layer on the side surface.
In the embodiment of the present invention, after step 103, ozone (O 3 ) The mixed solution of hydrofluoric acid (HF) cleans the silicon wafer, and the oxidizing property of ozone is higher than that of sulfuric acid (H) 2 SO 4 ) Hydrochloric acid (HCl), hydrogen peroxide (H) 2 O 2 ) And the like, can effectively remove organic contamination on the surface of the silicon wafer, can rapidly grow a compact and ultrathin high-quality silicon oxide layer on the surface of the silicon wafer, can remove the formed compact and high-quality silicon oxide layer by corrosion through hydrofluoric acid, and can continuously remove the phosphorus inner expansion layer at the edge of the silicon wafer, so that the phosphorus inner expansion concentration at the edge of the silicon wafer is reduced, PN junction short circuit is prevented, front passivation effect is improved, and the probability of electric leakage at the edge of a battery is effectively reduced.
In the embodiment of the invention, other functional layers such as a passivation layer, an antireflection layer, a metal electrode and the like can be further prepared on the front surface and the back surface of the silicon wafer to prepare the solar cell.
The method for preparing the Topcon battery comprises the steps of firstly providing a silicon wafer, wherein the silicon wafer comprises a front surface, a back surface opposite to the front surface, and a side surface connecting the front surface and the back surface, preparing a boron doped layer on the front surface of the silicon wafer, and sequentially preparing a tunneling oxide layer and a phosphorus doped polysilicon layer on the back surface, wherein a tunneling oxide layer which is wound and plated on the side surface is formed in the process of preparing the tunneling oxide layer, and a phosphorus glass layer which is wound and plated on the side surface and is outside-in-outside phosphorus doped polysilicon layer and a phosphorus inner expansion layer which is positioned on the side surface and penetrates through the tunneling oxide layer are formed in the process of preparing the phosphorus doped polysilicon layer; and then removing the phosphosilicate glass layer which is plated around, the phosphorus doped polysilicon layer which is plated around and the tunneling oxide layer which is plated around, and then further adopting a mixed solution of ozone and hydrofluoric acid to clean the silicon wafer.
Referring to fig. 2, fig. 2 shows a second step flowchart of a Topcon battery preparation method according to an embodiment of the present invention, where the method may include:
step 201, providing a silicon wafer, wherein the silicon wafer comprises a front surface and a back surface opposite to the front surface, and a side surface connecting the front surface and the back surface.
In the embodiment of the present invention, step 201 may correspond to the description related to step 101, and is not repeated here. Optionally, the silicon wafer can be subjected to texturing treatment, so that a pyramid structure is formed on the surface of the silicon wafer, the reflection of incident light is reduced, the short-circuit current of the battery is improved, and the photoelectric conversion efficiency of the battery is improved, for example, alkali lye such as sodium hydroxide, potassium hydroxide and the like can be used for carrying out alkali texturing treatment on the silicon wafer; additives can be optionally added in the alkali texturing process to adjust the reaction speed, the size of the texturing surface and the like, wherein the additives can comprise surfactants, nucleating agents, dispersants, catalysts, defoamers and the like; in the process, the silicon wafer can be put into a groove type texturing and cleaning machine to carry out alkali texturing process, and the specific conditions of the texturing process in the embodiment of the invention are not particularly limited. The technological temperature of the texturing treatment of the silicon wafer can be 77-83 ℃, the technological time can be 455-465 seconds, the etching amount of the silicon wafer after the texturing treatment can be 0.445-0.455g, and the reflectivity of the surface of the silicon wafer can be 8.7-9.3%.
And 202, performing boron diffusion treatment on the front surface to form a boron doped layer, and performing etching treatment on the back surface of the silicon wafer.
In the embodiment of the invention, after the silicon wafer is textured, the front surface of the silicon wafer can be subjected to boron diffusion treatment so as to form a boron doped layer on the front surface of the silicon wafer. Alternatively, boron diffusion may employ boron sources such as trimethyl borate, boron tribromide, boron trichloride, and the like; the process temperature of boron diffusion can be any temperature between 950 ℃ and 1050 ℃, such as 950 ℃, 955 ℃, 960 ℃, 970 ℃, 980 ℃, 990 ℃, 1000 ℃, 1050 ℃ and the like, and in the embodiment of the application, the sheet resistance of the silicon wafer after boron diffusion can be adjusted to 110-130 Ω/≡according to the application requirements, and the boron source, the process temperature, the diffusion depth and the like of the boron diffusion process are not particularly limited.
In the embodiment of the invention, the boron-surrounding diffusion layer is formed on the back surface of the silicon wafer in the process of carrying out boron diffusion treatment on the silicon wafer, the boron-surrounding diffusion layer on the back surface influences the tunneling oxide layer and the polycrystalline silicon layer deposited on the back surface of the silicon wafer in the subsequent process, and the boron-surrounding diffusion layer on the back surface of the silicon wafer can be removed and the back surface of the silicon wafer is polished by carrying out etching treatment on the back surface of the silicon wafer, so that the passivation effect of the battery passivation contact structure is improved. Alternatively, hydrofluoric acid, nitric acid (HNO 3 ) Mixed solution of Deionized Water (DIW), wherein hydrofluoric acid with mass fraction of 49%, nitric acid with mass fraction of 69% and Deionized Water can be mixed with HF: HNO 3 The DIW is mixed in a ratio of 1:4-7:1-2, and a person skilled in the art can select different etching solutions according to application requirements and process conditions, so that the reflectivity of the back surface of the silicon wafer after etching treatment is 34-36%, and the weight reduction of the silicon wafer during etching treatment is 0.25-0.45g.
And 203, sequentially depositing a tunneling oxide layer and a polysilicon layer on the back surface.
In the embodiment of the invention, after single-sided etching treatment is carried out on the back surface of the silicon wafer, a tunneling oxide layer and a polycrystalline silicon layer can be sequentially deposited on the back surface of the silicon wafer, alternatively, LPCVD (low pressure chemical vapor deposition) deposition can be adopted for preparation, and the thickness of the prepared tunneling oxide layer can be 1.2-1.8nm, for example, the thickness of the tunneling oxide layer can be any thickness between 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm and the like and 1.2-1.8 nm; the thickness of the polysilicon layer may be 50-250nm, for example, the thickness of the polysilicon layer may be any thickness between 50-250nm, such as 50nm, 51nm, 52nm, 53nm, 54nm, 55nm, 60nm, 70nm, 80nm, 90nm, 100nm, 150nm, 200nm, 250nm, etc., and the embodiment of the present invention is not particularly limited.
And 204, performing phosphorus injection on the polysilicon layer to obtain a phosphorus doped polysilicon layer, wherein a tunneling oxide layer which is plated around the side surface is formed in the process of preparing the tunneling oxide layer, and a phosphorus glass layer which is plated around the tunneling oxide layer of the side surface from outside to inside, the phosphorus doped polysilicon layer and a phosphorus inner diffusion layer which is positioned on the side surface and penetrates through the tunneling oxide layer are formed in the process of preparing the phosphorus doped polysilicon layer.
In the embodiment of the invention, the phosphorus diffusion process can be adopted to perform phosphorus injection on the polysilicon layer on the back surface of the silicon wafer to obtain the phosphorus doped polysilicon layer, so that a back contact structure of a tunneling oxide layer/phosphorus doped polysilicon layer is formed on the back surface of the silicon wafer, wherein phosphorus oxychloride (POCl) can be selected 3 ) As a phosphorus source, the polysilicon layer is subjected to phosphorus diffusion by the phosphorus diffusion furnace, and the winding plating layer formed in the process of step 202 to step 204 may be correspondingly referred to the description related to step 102, so that the description is omitted herein for avoiding repetition.
Referring to fig. 3, fig. 3 shows a schematic structural diagram of a silicon wafer according to an embodiment of the present invention, as shown in fig. 3, after step 204, the silicon wafer may include an N-type silicon wafer substrate 1, a phosphosilicate glass layer 2, a phosphorus doped polysilicon layer 3, a tunneling oxide layer 4, and a borosilicate glass layer 5, where the steps include, in order from outside to inside:
The phosphosilicate glass layer 2 is formed on the back surface of the N-type silicon wafer substrate 1 and is formed by coiling plating on the side surface and the front surface in the process of phosphorus injection;
the phosphorus doped polysilicon layer 3 is formed on the back surface of the N-type silicon wafer substrate 1 and is formed by side surface and front surface coiling plating in the process of preparing the polysilicon layer and phosphorus injection;
the tunneling oxide layer 4 is formed on the back surface of the N-type silicon wafer substrate 1 in the process of depositing the tunneling oxide layer 4 and formed by coiling plating on the side surface and the front surface;
and a borosilicate glass layer 5 formed on the front surface of the N-type silicon wafer substrate 1 in the boron diffusion process.
Step 205, removing the phosphosilicate glass layer around the front surface and the side surface.
In the embodiment of the invention, the phosphosilicate glass layers formed on the front and side surfaces of the silicon wafer in the phosphorus injection process can be removed first, so that the phosphorus doped polysilicon layers of the front and side surface coiling plating of the silicon wafer are exposed, and the phosphorus doped polysilicon layer on the back of the silicon wafer is covered by the phosphosilicate glass layers. Optionally, the front and side phosphosilicate glass layers of the silicon wafer can be removed by hydrofluoric acid washing in a chain cleaning machine, wherein the mass fraction of hydrofluoric acid for removing the phosphosilicate glass layer can be 1.96% -5%.
And 206, removing the phosphorus doped polysilicon layer which is plated around the front surface and the side surface.
In the embodiment of the invention, the phosphorus doped polysilicon layer formed on the front and side surfaces of the silicon wafer in the process of preparing the polysilicon layer and injecting phosphorus can be removed under the protection of the phosphorus silicate glass layer, and optionally, the phosphorus doped polysilicon layer on the front and side surfaces of the silicon wafer can be removed by etching with 1-1.5% potassium hydroxide alkali solution by mass fraction, and 0.1-0.3% protective additive can be added; the cleaning temperature for removing the phosphorus doped polysilicon layer around plating may be 60-70 deg.c and the cleaning time may be 200-300 seconds.
Step 207, removing the tunneling oxide layer around the front surface and the side surface, the borosilicate glass layer around the front surface, and the phosphosilicate glass layer around the back surface.
In the embodiment of the invention, after the tunneling oxide layers on the front side and the side of the silicon wafer are exposed by removing the around-plated phosphosilicate glass layer, the tunneling oxide layers formed on the front side and the side of the silicon wafer in the deposition process, the borosilicate glass layer formed on the front side of the silicon wafer in the preparation process of the boron doped layer and the phosphosilicate glass layer formed on the back side of the silicon wafer in the phosphorus injection process can be further removed, and optionally, the etching solution can be obtained by mixing 30% -70% of hydrofluoric acid with the mass fraction of 49%. Further, after step 206, the wafer may also be rinsed with water to remove lye, particulates, additives, etc., prior to step 207.
And 208, treating the silicon wafer by adopting potassium hydroxide and hydrogen peroxide.
In the embodiment of the invention, potassium hydroxide and hydrogen peroxide can be adopted for the siliconThe wafer is treated to perform pSC1 (pseudo SC 1) cleaning, pSC1 cleaning adopts potassium hydroxide (KOH) and hydrogen peroxide chemical cleaning, additives and other chemical components on the surface of the silicon wafer can be removed, alternatively, the silicon wafer can be subjected to pSC1 cleaning at 60-70 ℃, 45% potassium hydroxide solution and 27% hydrogen peroxide solution can be mixed in a volume ratio of 1:5, for example, 4L KOH and 20L H can be adopted 2 O 2 And (5) chemically cleaning the silicon wafer.
And 209, cleaning the silicon wafer by adopting a mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner diffusion layer on the side surface.
In the embodiment of the present invention, step 209 may correspond to the related description of step 104, and is not repeated here.
Optionally, the mass fraction of ozone in the mixed solution is 0.025-0.065%.
In the embodiment of the invention, the mass fraction of ozone in the mixed solution can be any concentration between 0.025 and 0.065 per mill, for example, 0.025 per mill, 0.026 per mill, 0.027 per mill, 0.028 per mill, 0.029 per mill, 0.030 per mill, 0.035 per mill, 0.040 per mill, 0.045 per mill, 0.050 per mill, 0.055 per mill, 0.060 per mill, 0.065 per mill and the like, which is not particularly limited in the embodiment of the invention.
Optionally, the mass fraction of the hydrofluoric acid in the mixed solution is 0.0027-0.0068 per mill.
In the embodiment of the invention, the mass fraction of the hydrofluoric acid in the mixed solution can be any concentration between 0.0027 and 0.0068 per mill, for example, 0.0027 per mill, 0.0028 per mill, 0.0029 per mill, 0.0030 per mill, 0.0035 per mill, 0.0040 per mill, 0.0045 per mill, 0.0050 per mill, 0.0055 per mill, 0.0060 per mill, 0.0065 per mill, 0.0068 per mill and the like, which is not particularly limited in the embodiment of the invention.
Optionally, the cleaning time of the cleaning is 180-250 seconds.
In the embodiment of the invention, the time for cleaning the silicon wafer by adopting the mixed solution of ozone and hydrofluoric acid can be any time between 180 and 250 seconds, such as 180 seconds, 185 seconds, 190 seconds, 200 seconds, 210 seconds, 220 seconds, 230 seconds, 240 seconds, 250 seconds and the like, and the embodiment of the invention is not particularly limited.
And 210, dehydrating the silicon wafer.
In the embodiment of the invention, after the silicon wafer is cleaned by adopting the mixed solution of ozone and hydrofluoric acid to remove the phosphorus internal expansion concentration at the edge, the silicon wafer can be dehydrated, wherein the treatment time of the dehydration treatment can be any time between 180 and 350 seconds, such as 180 seconds, 185 seconds, 190 seconds, 200 seconds, 210 seconds, 220 seconds, 230 seconds, 240 seconds, 250 seconds, 300 seconds, 350 seconds and the like, the silicon wafer can be dehydrated by adopting hydrofluoric acid, hydrochloric acid and the like, and the silicon wafer can be dehydrated by adopting hydrofluoric acid with the mass fraction of 49% and mixing the silicon wafer with the mass fraction of 5 to 15% to dry and dehydrate the silicon wafer.
And 211, preparing passivation films on the front surface and the back surface of the silicon wafer.
In the embodiment of the invention, passivation films can be prepared on the front side and the back side of the silicon wafer, wherein an aluminum oxide layer has a good field effect passivation effect, passivation can be realized on the surface of a boron doped layer, carrier recombination is reduced, minority carrier lifetime is prolonged, and thus the photoelectric conversion efficiency of a battery is improved; furthermore, a silicon nitride layer can be prepared on the front side and the back side of the silicon substrate, namely an aluminum oxide layer and a phosphorus doped polysilicon layer, the silicon nitride layer has good hydrogen passivation and antireflection effects, and can realize good bulk passivation effects, alternatively, a laminated silicon nitride layer can be prepared on the aluminum oxide layer to realize the front passivation and antireflection effects of the battery, a silicon nitride layer with lower refractive index can be prepared on the phosphorus doped polysilicon layer, light loss is reduced, light utilization rate is improved, and a person skilled in the art can prepare the silicon nitride layer according to process conditions and application requirements, and the embodiment of the invention is not particularly limited.
Step 212, preparing electrodes on the front surface and the back surface of the silicon wafer.
In the embodiment of the invention, after each film layer is prepared, electrodes can be prepared on the front surface and the back surface of a silicon wafer to obtain a solar cell, alternatively, the electrodes can be prepared by screen printing metal slurry and sintering, can be prepared by adopting a photoetching plating method, can be prepared by adopting a vacuum evaporation method, and can be silver electrodes, copper electrodes, aluminum electrodes and the like, and the embodiment of the invention is not particularly limited.
The method for preparing the Topcon battery comprises the steps of firstly providing a silicon wafer, wherein the silicon wafer comprises a front surface, a back surface opposite to the front surface, and a side surface connecting the front surface and the back surface, preparing a boron doped layer on the front surface of the silicon wafer, and sequentially preparing a tunneling oxide layer and a phosphorus doped polysilicon layer on the back surface, wherein a tunneling oxide layer which is wound and plated on the side surface is formed in the process of preparing the tunneling oxide layer, and a phosphorus glass layer which is wound and plated on the side surface and is outside-in-outside phosphorus doped polysilicon layer and a phosphorus inner expansion layer which is positioned on the side surface and penetrates through the tunneling oxide layer are formed in the process of preparing the phosphorus doped polysilicon layer; and then removing the phosphosilicate glass layer which is plated around, the phosphorus doped polysilicon layer which is plated around and the tunneling oxide layer which is plated around, and then further adopting a mixed solution of ozone and hydrofluoric acid to clean the silicon wafer.
The embodiment of the invention also provides a Topcon battery, which is prepared by adopting the preparation method of the Topcon battery shown in any one of the figures 1 and 2;
the front of the Topcon battery is in a round corner pyramid structure.
The Topcon battery provided by the embodiment of the invention comprises a silicon wafer, wherein the silicon wafer comprises a front surface, a back surface opposite to the front surface, and a side surface connecting the front surface and the back surface, a boron doped layer is prepared on the front surface of the silicon wafer, and a tunneling oxide layer and a phosphorus doped polysilicon layer are sequentially prepared on the back surface, wherein a tunneling oxide layer which is wound and plated on the side surface is formed in the process of preparing the tunneling oxide layer, and a phosphorus glass layer which is wound and plated on the outside of the tunneling oxide layer on the side surface and is inward, a phosphorus doped polysilicon layer and a phosphorus inner expansion layer which is positioned on the side surface and penetrates through the tunneling oxide layer are formed in the process of preparing the phosphorus doped polysilicon layer; then removing the around-plated phosphosilicate glass layer, the around-plated phosphorus doped polysilicon layer and the around-plated tunneling oxide layer, and then further adopting a mixed solution of ozone and hydrofluoric acid to clean the silicon wafer, wherein the ozone has strong oxidizing property, so that a compact and high-quality silicon oxide layer can be grown on the surface of the silicon wafer, at the moment, the silicon oxide layer formed by the ozone oxidation of the surface of the silicon wafer is etched and removed through the hydrofluoric acid, and the edge of the silicon wafer can be etched continuously, so that the phosphorus inner expansion layer of the edge of the silicon wafer is effectively removed, the phosphorus over-expansion concentration of the edge of the silicon wafer is reduced, the front passivation effect is further improved, and the leakage problem of the edge of the silicon wafer is avoided; and the silicon oxide layer is formed by firstly carrying out ozone oxidation on the pyramid structure on the front side of the silicon wafer, then carrying out hydrofluoric acid etching to remove the silicon oxide layer, and the pyramid tip of the pyramid structure can be rounded, so that the front side of the silicon wafer is in a rounded pyramid structure, and the reflectivity of the front side of the silicon wafer is improved.
The embodiment of the invention also provides a detour plating bath type cleaning machine, which can be used for detour plating cleaning of silicon chips after the phosphosilicate glass layer is removed by adopting a chain type cleaning machine, and optionally comprises a first cleaning tank, a second cleaning tank and a third cleaning tank which are sequentially arranged, wherein the first cleaning tank is provided with a potassium hydroxide solution, the second cleaning tank is provided with a hydrofluoric acid solution, and the third cleaning tank is provided with a mixed solution of ozone and hydrofluoric acid.
The unwind plating tank type cleaning machine is used for the Topcon battery preparation method described in any of the foregoing figures 1 and 2.
Optionally, the first cleaning tank is used for removing the phosphorus doped polysilicon layer around plating the front surface and the side surface;
optionally, the second cleaning tank is used for removing the tunneling oxide layer around the front surface and the side surface, the borosilicate glass layer on the front surface, and the phosphosilicate glass layer around the back surface;
optionally, the third cleaning tank is used for cleaning the silicon wafer by adopting a mixed solution of ozone and hydrofluoric acid so as to remove the phosphorus inner diffusion layer on the side surface.
In the embodiment of the invention, the winding-removing plating bath type cleaning machine can be used for carrying out winding-removing plating treatment in the preparation process of the Topcon battery in any one of the figures 1 to 2, the sequence of each bath body can be adjusted according to specific process requirements, different bath bodies can be added or removed, for example, a water washing bath can be added between a first cleaning bath and a second cleaning bath, a water washing bath, a pSC1 cleaning bath and a water washing bath are sequentially added between the second cleaning bath and a third cleaning bath, and a water washing bath, a pickling bath, a slow-lifting bath, a drying bath and the like are sequentially added after the third cleaning bath;
the method comprises the steps of washing a silicon wafer by using a washing tank, washing the silicon wafer by using a pSC1 washing tank, washing the silicon wafer by using potassium hydroxide and hydrogen peroxide, and washing the silicon wafer by using hydrofluoric acid and hydrochloric acid by using a pickling tank.
The winding-removing plating tank type cleaning machine provided by the embodiment of the invention can perform winding-removing plating treatment in the preparation process of a Topcon battery, and comprises a first cleaning tank, a second cleaning tank and a third cleaning tank which are sequentially arranged, wherein the first cleaning tank is provided with a potassium hydroxide solution, the second cleaning tank is provided with a hydrofluoric acid solution, and the third cleaning tank is provided with a mixed solution of ozone and hydrofluoric acid; the first cleaning tank is used for removing the phosphorus doped polysilicon layer which is wound and plated on the front surface and the side surface of the silicon wafer; the second cleaning tank is used for removing tunneling oxide layers which are wound and plated on the front surface and the side surface of the silicon wafer, borosilicate glass layers which are wound and plated on the front surface, and phosphosilicate glass layers which are wound and plated on the back surface; the third cleaning tank is used for cleaning the silicon wafer by adopting the mixed solution of ozone and hydrofluoric acid, and because the ozone has strong oxidizing property, a compact and high-quality silicon oxide layer can be grown on the surface of the silicon wafer, at the moment, the silicon oxide layer formed by the ozone oxidation on the surface of the silicon wafer is etched and removed by the hydrofluoric acid, and the edge of the silicon wafer can be etched continuously, so that the phosphorus inner expanding layer of the edge of the silicon wafer is effectively removed, the phosphorus over-expanding concentration of the edge of the silicon wafer is reduced, the front passivation effect is improved, the problem of electric leakage of the edge of the silicon wafer is avoided, and pyramid tips of pyramid structures on the front of the silicon wafer can be rounded, so that the front of the silicon wafer is in a rounded pyramid structure, and the reflectivity of the front of the silicon wafer is improved.
The embodiment of the invention also provides a preparation process example of the conventional battery, the sample battery 1 and the sample battery 2, wherein the conventional battery is prepared by adopting a conventional Topcon battery preparation method, and the sample battery 1 and the sample battery 2 are prepared by adopting the Topcon battery preparation method provided by the invention, and the preparation process is specifically as follows:
example preparation of a conventional Battery
S101, texturing N-type silicon wafers with the size of 182mm by adopting a potassium hydroxide solution with the mass fraction of about 1% in a groove texturing cleaning machine, wherein a KOH solution with the mass fraction of 45% is mixed with 2.2L of additives in a mixing ratio, the alkali texturing process temperature is 82 ℃, the process time is 420 seconds, the weight of the N-type silicon wafers is reduced by 0.42g, and the reflectivity is 8.7%.
And S102, preparing a boron doped layer by performing a boron diffusion process on the front side of the N-type silicon wafer after texturing in a boron diffusion furnace tube, and forming a borosilicate glass layer on the surface of the N-type silicon wafer, wherein the sheet resistance of the N-type silicon wafer after boron diffusion is 120Ω/≡.
Step S103, performing single-sided etching treatment on the back surface of the silicon wafer after boron diffusion in a chain cleaning machine to remove a borosilicate glass layer on the back surface, wherein an etching solution comprises 49% hydrofluoric acid, 69% nitric acid and deionized water in percentage by mass, and the etching solution is prepared from HF (hydrogen fluoride)/HNO (hydrogen fluoride) 3 DI=1:7:1, the reflectivity of the back surface of the etched N-type silicon wafer is 35%, and the weight is reduced by 0.35g.
And step S104, depositing a tunneling oxide layer and a polycrystalline silicon layer on the back surface of the N-type silicon wafer by LPCVD, wherein the thickness of the tunneling oxide layer is 1.5nm, and the thickness of the polycrystalline silicon layer is 120nm.
And step S105, performing phosphorus injection on the polysilicon layer by adopting a phosphorus diffusion furnace on the back surface of the N-type silicon wafer to obtain a phosphorus doped polysilicon layer so as to form a passivation contact structure on the back surface of the N-type silicon wafer, and forming the passivation contact structure on the edge of the silicon wafer in the phosphorus injection process.
Further, in step S104-105, a tunnel oxide layer is formed around the side surface of the N-type silicon wafer during the preparation of the tunnel oxide layer, and a phosphorus-doped polysilicon layer is formed around the tunnel oxide layer on the side surface of the N-type silicon wafer during the preparation of the phosphorus-doped polysilicon layer, from outside to inside, and a phosphorus inner diffusion layer is formed around the phosphorus-doped polysilicon glass layer, the phosphorus-doped polysilicon layer and the phosphorus inner diffusion layer is located on the side surface of the N-type silicon wafer and passes through the tunnel oxide layer.
And S106, removing the phosphosilicate glass layers on the front side and the side of the N-type silicon wafer by adopting a hydrofluoric acid solution with the mass fraction of 3% based on the belt speed of 2m/min in a chain cleaning machine.
And S107, removing the phosphorus doped polysilicon layer on the front side and the side of the N-type silicon wafer by adopting a potassium hydroxide solution in a winding-removing plating tank type cleaning machine, wherein the mixing ratio of the 45 mass percent potassium hydroxide solution and the additive is that the 16LKOH solution is mixed with 3.5L of the additive, the process temperature is 66 ℃, and the process time is 260 seconds.
And S108, washing the N-type silicon wafer for 120 seconds in a winding-removing plating bath type cleaning machine.
And S109, removing the borosilicate glass layer on the front side, the tunneling oxide layer on the front side and the tunneling oxide layer on the side of the N-type silicon wafer and the phosphosilicate glass layer on the back side by adopting hydrofluoric acid solution in a winding-removing plating bath type cleaning machine, wherein the hydrofluoric acid solution is prepared by adopting hydrofluoric acid with the mass fraction of 49% in a volume ratio of 50%, and the mass fraction of the hydrofluoric acid in the prepared hydrofluoric acid solution is 17%.
Step S120, cleaning the N-type silicon wafer by adopting potassium hydroxide and hydrogen peroxide in a winding-removing plating bath type cleaning machine to remove the additive and chemical components remained on the surface of the N-type silicon wafer, wherein the mass fraction of the KOH is 45 percent and the volume is 4L; h 2 O 2 Is 27% by mass and 20L by volume; the cleaning temperature was 65 ℃.
And step S121, washing the N-type silicon wafer for 120 seconds in a winding-removing plating bath type cleaning machine.
Step S122, pickling the N-type silicon wafer by adopting hydrofluoric acid solution in a winding-removing plating tank type cleaning machine, wherein the mass fraction of the hydrofluoric acid solution used for pickling is 8%, the treatment time is 180 seconds, and then the N-type silicon wafer is completely dehydrated and dried.
And step S123, preparing an AlOx+SiNx passivation film on the front surface of the N-type silicon wafer, and preparing a SiNx passivation film on the back surface of the N-type silicon wafer.
And step S124, performing screen printing and sintering on the passivation film to prepare an electrode, and then testing and sorting to obtain the conventional battery.
Example preparation of two sample cell 1
Step S201, texturing N-type silicon wafers with the size of 182mm by adopting a potassium hydroxide solution with the mass fraction of about 1% in a groove texturing cleaning machine, wherein the KOH solution with the mass fraction of 45% is mixed with 2.2L of additive in a mixing ratio, the alkali texturing process temperature is 82 ℃, the process time is 420 seconds, the weight of the N-type silicon wafers is reduced by 0.42g, and the reflectivity is 8.7%.
And S202, preparing a boron doped layer by performing a boron diffusion process on the front side of the N-type silicon wafer after texturing in a boron diffusion furnace tube, and forming a borosilicate glass layer on the surface of the N-type silicon wafer, wherein the sheet resistance of the N-type silicon wafer after boron diffusion is 120Ω/≡.
Step S203, performing single-sided etching treatment on the back surface of the silicon wafer after boron diffusion in a chain cleaning machine to remove a borosilicate glass layer on the back surface, wherein an etching solution of the etching solution comprises 49% of hydrofluoric acid, 69% of nitric acid and deionized water in mass percent, and the etching solution is prepared from HF (hydrogen fluoride)/HNO (hydrogen fluoride) 3 DI=1:7:1, the reflectivity of the back surface of the etched N-type silicon wafer is 35%, and the weight is reduced by 0.35g.
And S204, depositing a tunneling oxide layer and a polycrystalline silicon layer on the back surface of the N-type silicon wafer by LPCVD, wherein the thickness of the tunneling oxide layer is 1.5nm, and the thickness of the polycrystalline silicon layer is 120nm.
And step S205, performing phosphorus injection on the polysilicon layer by adopting a phosphorus diffusion furnace on the back surface of the N-type silicon wafer to obtain a phosphorus doped polysilicon layer so as to form a passivation contact structure on the back surface of the N-type silicon wafer.
Further, in step S204-205, a wrap-around tunnel oxide layer is formed on the side surface of the N-type silicon wafer during the preparation of the tunnel oxide layer, and a wrap-around phosphosilicate glass layer, a phosphorus doped polysilicon layer and a phosphorus inner diffusion layer which is located on the side surface of the N-type silicon wafer and passes through the tunnel oxide layer are formed outside the tunnel oxide layer on the side surface of the N-type silicon wafer during the preparation of the phosphorus doped polysilicon layer from outside to inside.
And S206, removing the phosphosilicate glass layers on the front side and the side of the N-type silicon wafer by using a hydrofluoric acid solution with the mass fraction of 3% based on the belt speed of 2m/min in a chain cleaning machine.
And S207, removing the phosphorus doped polysilicon layer on the front side and the side of the N-type silicon wafer by adopting a potassium hydroxide solution in a winding-removing plating tank type cleaning machine, wherein the mixing ratio of the 45 mass percent potassium hydroxide solution and the additive is that the 16LKOH solution is mixed with 3.5L of the additive, the process temperature is 66 ℃, and the process time is 260 seconds.
And step S208, washing the N-type silicon wafer for 120 seconds in a winding-removing plating bath type cleaning machine.
And S209, removing the borosilicate glass layer on the front side, the tunneling oxide layer on the front side and the tunneling oxide layer on the side and the phosphosilicate glass layer on the back side of the N-type silicon wafer by adopting hydrofluoric acid solution in a winding-removing plating tank type cleaning machine, wherein the hydrofluoric acid solution is prepared by adopting hydrofluoric acid with the mass fraction of 49% in a volume ratio of 50%, and the mass fraction of the hydrofluoric acid in the prepared hydrofluoric acid solution is 17%.
Step S210, cleaning the N-type silicon wafer in a 360L tank body in a winding-removing plating tank type cleaning machine by adopting a mixed solution of ozone and hydrofluoric acid, wherein the cleaning time is 180 seconds, the mass fraction of ozone is 4 per mill, the volume of the hydrofluoric acid with the mass fraction of 49% is 200mL, the front surface of the processed N-type silicon wafer is in a rounded pyramid structure, the reflectivity is increased by 0.4%, and the concentration of edge phosphorus internal expansion is 1 multiplied by 10 19 cm -3 Reduced to x 10 17 cm -3 。
Step S211, cleaning the N-type silicon wafer by adopting potassium hydroxide and hydrogen peroxide in a de-winding plating bath type cleaning machine to remove the additive and chemical components remained on the surface of the N-type silicon wafer, wherein the mass fraction of the KOH is 45 percent and the volume is 4L; h 2 O 2 Is 27% by mass and 20L by volume; the cleaning temperature was 65 ℃.
And S212, washing the N-type silicon wafer for 120 seconds in a winding-removing plating bath type cleaning machine.
And S213, pickling the N-type silicon wafer by adopting a hydrofluoric acid solution in a winding-removing plating tank type cleaning machine, wherein the mass fraction of the hydrofluoric acid solution used for pickling is 8%, the treatment time is 180 seconds, and then the N-type silicon wafer is completely dehydrated and dried.
And step S214, preparing an AlOx+SiNx passivation film on the front surface of the N-type silicon wafer, and preparing a SiNx passivation film on the back surface of the N-type silicon wafer.
Step S215, screen printing and sintering are carried out on the passivation film to prepare an electrode, and then test sorting is carried out, so that the sample battery 1 is obtained.
Example preparation of three sample cell 2
Step S301, texturing the N-type silicon wafer with the size of 182mm by adopting a potassium hydroxide solution with the mass fraction of about 1% in a groove texturing cleaning machine, wherein 5.4L of the potassium hydroxide solution with the mass fraction of 45% is mixed with 2.2L of an additive, the alkali texturing process temperature is 82 ℃, the process time is 420 seconds, and the weight of the N-type silicon wafer is reduced by 0.42g and the reflectivity is 8.7%.
And S302, preparing a boron doped layer by performing a boron diffusion process on the front side of the N-type silicon wafer after texturing in a boron diffusion furnace tube, and forming a borosilicate glass layer on the surface of the N-type silicon wafer, wherein the sheet resistance of the N-type silicon wafer after boron diffusion is 120Ω/≡.
Step S303, performing single-sided etching treatment on the back surface of the silicon wafer after boron diffusion in a chain cleaning machine to remove a borosilicate glass layer on the back surface, wherein the etching solution of the etching solution comprises 49% of hydrofluoric acid, 69% of nitric acid and deionized water in percentage by mass, and the etching solution is prepared from HF (hydrogen fluoride)/HNO (hydrogen fluoride) 3 DI=1:7:1, the reflectivity of the back surface of the etched N-type silicon wafer is 35%, and the weight is reduced by 0.35g.
And S304, depositing a tunneling oxide layer and a polycrystalline silicon layer on the back surface of the N-type silicon wafer by LPCVD, wherein the thickness of the tunneling oxide layer is 1.5nm, and the thickness of the polycrystalline silicon layer is 120nm.
And S305, performing phosphorus injection on the polysilicon layer by adopting a phosphorus diffusion furnace on the back surface of the N-type silicon wafer to obtain a phosphorus doped polysilicon layer so as to form a passivation contact structure on the back surface of the N-type silicon wafer.
Further, in step S304-305, a wrap-around tunnel oxide layer is formed on the side surface of the N-type silicon wafer during the preparation of the tunnel oxide layer, and a wrap-around phosphosilicate glass layer, a phosphorus doped polysilicon layer and a phosphorus inner diffusion layer which is located on the side surface of the N-type silicon wafer and passes through the tunnel oxide layer are formed outside the tunnel oxide layer on the side surface of the N-type silicon wafer during the preparation of the phosphorus doped polysilicon layer from outside to inside.
And step S306, removing the phosphosilicate glass layers on the front side and the side of the N-type silicon wafer by adopting a hydrofluoric acid solution with the mass fraction of 3% based on the belt speed of 2m/min in a chain cleaning machine.
And S307, removing the phosphorus doped polysilicon layer on the front side and the side of the N-type silicon wafer by adopting a potassium hydroxide solution in a winding-removing plating tank type cleaning machine, wherein the mixing ratio of the 45 mass percent potassium hydroxide solution and the additive is that the 16LKOH solution is mixed with 3.5L of the additive, the process temperature is 66 ℃, and the process time is 260 seconds.
And step S308, washing the N-type silicon wafer for 120 seconds in a winding-removing plating bath type cleaning machine.
Step S309, removing borosilicate glass layers on the front side, tunneling oxide layers on the front side and the side of the N-type silicon wafer and a phosphosilicate glass layer on the back side by adopting hydrofluoric acid solution in a winding plating tank type cleaning machine, wherein the hydrofluoric acid solution is prepared by adopting hydrofluoric acid with the mass fraction of 49% in a volume ratio of 50%, and the mass fraction of the hydrofluoric acid in the prepared hydrofluoric acid solution is 17%.
Step S310, cleaning the N-type silicon wafer in a 360L tank body in a winding-removing plating tank type cleaning machine by adopting a mixed solution of ozone and hydrofluoric acid, wherein the cleaning time is 180 seconds, the mass fraction of ozone is 6 per mill, the volume of the hydrofluoric acid with the mass fraction of 49% is 500mL, the front surface of the processed N-type silicon wafer is in a rounded pyramid structure, the reflectivity is increased by 0.6%, and the concentration of edge phosphorus internal expansion is 1 multiplied by 10 19 cm -3 Reduced to x 10 17 cm -3 。
Step S311, performing pSC1 cleaning on the N-type silicon wafer by adopting potassium hydroxide and hydrogen peroxide in a winding-removing plating bath type cleaning machine,removing the residual additives and chemical components on the surface of the N-type silicon wafer, wherein the mass fraction of KOH is 45% and the volume is 4L; h 2 O 2 Is 27% by mass and 20L by volume; the cleaning temperature was 65 ℃.
And step S312, washing the N-type silicon wafer in a de-winding plating bath type cleaning machine for 120 seconds.
Step S313, pickling the N-type silicon wafer by adopting hydrofluoric acid solution in a winding-removing plating tank type cleaning machine, wherein the mass fraction of the hydrofluoric acid solution used for pickling is 8%, the treatment time is 180 seconds, and then the N-type silicon wafer is completely dehydrated and dried.
And step S314, preparing an AlOx+SiNx passivation film on the front surface of the N-type silicon wafer, and preparing a SiNx passivation film on the back surface of the N-type silicon wafer.
Step S315, screen printing and sintering are carried out on the passivation film to prepare an electrode, and then test sorting is carried out, so that the sample battery 2 is obtained.
The performance parameters of the conventional battery, the sample battery 1 and the sample battery 2 prepared in the embodiment of the invention are tested, and the test results are shown in the following table 1:
TABLE 1
As shown in table 1, according to the embodiment of the invention, 10877 conventional batteries and 19876 sample batteries 1 and 3200 sample batteries 2 are tested, wherein the leakage ratio of the conventional batteries is 5%, the leakage ratios of the sample batteries 1 and 2 are 0, and the Irev12 (reverse leakage current) of the sample batteries 1 and 2 are far lower than that of the conventional batteries, so that the problem of battery edge leakage is effectively solved by adopting the Topcon battery preparation method provided by the embodiment of the invention; meanwhile, uoc (open circuit voltage) and FF (fill factor) of the sample cell 1 and the sample cell 2 are higher than those of the conventional cell, rs (series resistance) is smaller than that of the conventional cell, rsh (parallel resistance) is larger than that of the conventional cell, and Eta (conversion efficiency) and a short circuit (Isc) are approximately equivalent to those of the conventional cell. It can be seen that compared with the conventional battery, the battery performance of the sample battery 1 and the sample battery 2 in the test is improved, the problem of edge leakage of the battery is effectively solved, and the yield of the battery is improved.
It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts described, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred, and that the acts referred to are not necessarily all required for the embodiments of the present application.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.
Claims (10)
1. A method of preparing a Topcon battery, the method comprising:
providing a silicon wafer, wherein the silicon wafer comprises a front surface and a back surface opposite to the front surface, and a side surface connecting the front surface and the back surface;
preparing a boron doped layer on the front surface, and sequentially preparing a tunneling oxide layer and a phosphorus doped polysilicon layer on the back surface, wherein a tunneling oxide layer which is plated around the side surface is formed in the process of preparing the tunneling oxide layer, and a phosphorus glass layer which is plated around the tunneling oxide layer of the side surface from outside to inside, a phosphorus doped polysilicon layer and a phosphorus inner diffusion layer which is positioned on the side surface and penetrates through the tunneling oxide layer are formed in the process of preparing the phosphorus doped polysilicon layer;
removing the phosphosilicate glass layer which is plated around, the phosphorus doped polysilicon layer which is plated around and the tunneling oxide layer which is plated around;
and cleaning the silicon wafer by adopting a mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner diffusion layer on the side surface.
2. The method according to claim 1, wherein the mass fraction of ozone in the mixed solution is 0.025-0.065%.
3. The method according to claim 1, wherein the mass fraction of the hydrofluoric acid in the mixed solution is 0.0027 to 0.0068%.
4. The method of claim 1, wherein the cleaning time of the cleaning is 180-250 seconds.
5. The method of claim 1, wherein said removing around-plated said phosphosilicate glass layer, around-plated said phosphorus doped polysilicon layer, around-plated said tunneling oxide layer comprises:
removing the phosphosilicate glass layer around the front and the side surfaces;
removing the phosphorus doped polysilicon layer around the front surface and the side surface;
and removing the tunneling oxide layer which is wound on the front surface and the side surface, the borosilicate glass layer which is wound on the front surface, and the phosphosilicate glass layer which is wound on the back surface.
6. The method of claim 1, wherein after said cleaning said wafer with a mixed solution of ozone and hydrofluoric acid to remove said phosphorus inner diffusion layer from said side surface, further comprising:
preparing passivation films on the front surface and the back surface;
electrodes are prepared on the front side and the back side.
7. The method of claim 1, wherein said cleaning said wafer with a mixed solution of ozone and hydrofluoric acid to remove said phosphorus inner diffusion layer from said side surface further comprises:
Adopting potassium hydroxide and hydrogen peroxide to treat the silicon wafer;
the method for cleaning the silicon wafer by adopting the mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner diffusion layer on the side surface further comprises the following steps:
and carrying out dehydration treatment on the silicon wafer.
8. A Topcon battery prepared by the method of any one of claims 1-7;
the front of the Topcon battery is in a round corner pyramid structure.
9. The winding-removing plating tank type cleaning machine is characterized by comprising a first cleaning tank, a second cleaning tank and a third cleaning tank which are sequentially arranged, wherein the first cleaning tank is provided with a potassium hydroxide solution, the second cleaning tank is provided with a hydrofluoric acid solution, and the third cleaning tank is provided with a mixed solution of ozone and hydrofluoric acid;
the unwind plating tank cleaner is used in the Topcon battery manufacturing method of any of the preceding claims 1-7.
10. The de-coiling plating bath type cleaning machine as in claim 9, wherein said first cleaning tank is used for removing said phosphorus doped polysilicon layer coiled plated on said front and said side surfaces;
The second cleaning tank is used for removing the tunneling oxide layer which is wound on the front surface and the side surface, the borosilicate glass layer which is wound on the front surface and the phosphosilicate glass layer which is wound on the back surface;
and the third cleaning tank is used for cleaning the silicon wafer by adopting a mixed solution of ozone and hydrofluoric acid so as to remove the phosphorus inner diffusion layer on the side surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210353011.2A CN114784140B (en) | 2022-04-02 | 2022-04-02 | Topcon battery preparation method, topcon battery and winding-removing plating tank type cleaning machine |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210353011.2A CN114784140B (en) | 2022-04-02 | 2022-04-02 | Topcon battery preparation method, topcon battery and winding-removing plating tank type cleaning machine |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114784140A CN114784140A (en) | 2022-07-22 |
| CN114784140B true CN114784140B (en) | 2024-04-05 |
Family
ID=82426808
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210353011.2A Active CN114784140B (en) | 2022-04-02 | 2022-04-02 | Topcon battery preparation method, topcon battery and winding-removing plating tank type cleaning machine |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114784140B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115498071B (en) * | 2022-09-20 | 2024-05-14 | 通威太阳能（成都）有限公司 | Battery preparation method, battery and electronic product |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111883614A (en) * | 2020-07-30 | 2020-11-03 | 常州时创能源股份有限公司 | Edge isolation method and preparation method of passivated contact battery |
| CN113948611A (en) * | 2021-10-15 | 2022-01-18 | 浙江爱旭太阳能科技有限公司 | P-type IBC battery, preparation method and assembly thereof, and photovoltaic system |
-
2022
- 2022-04-02 CN CN202210353011.2A patent/CN114784140B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111883614A (en) * | 2020-07-30 | 2020-11-03 | 常州时创能源股份有限公司 | Edge isolation method and preparation method of passivated contact battery |
| CN113948611A (en) * | 2021-10-15 | 2022-01-18 | 浙江爱旭太阳能科技有限公司 | P-type IBC battery, preparation method and assembly thereof, and photovoltaic system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114784140A (en) | 2022-07-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110518088B (en) | Preparation method of SE solar cell | |
| US8623688B2 (en) | Solar cell and method for manufacturing such a solar cell | |
| US20080216893A1 (en) | Process for Manufacturing Photovoltaic Cells | |
| CN104037257B (en) | Solaode and manufacture method, single-side polishing apparatus | |
| WO2021012710A1 (en) | Method for preparing n-type crystalline silicon battery | |
| JP2011129867A (en) | Silicon solar cell containing boron diffusion layer and method of manufacturing the same | |
| CN111933752A (en) | Solar cell and preparation method thereof | |
| CN113421949B (en) | Solar cell, preparation method thereof and photovoltaic module | |
| WO2011098549A1 (en) | Method for single side texturing | |
| CN113416547A (en) | Alkali corrosion auxiliary agent for cleaning winding-plated polycrystalline silicon and application thereof | |
| CN114784140B (en) | Topcon battery preparation method, topcon battery and winding-removing plating tank type cleaning machine | |
| CN114447142B (en) | N-type TOPCON solar cell and manufacturing method thereof | |
| CN116741877A (en) | TBC battery preparation method and TBC battery | |
| Zhao et al. | Effective passivation of large area black silicon solar cells by SiO2/SiNx: H stacks | |
| CN113035978A (en) | Silicon wafer with different-surface structure and preparation method thereof, and solar cell and preparation method thereof | |
| CN116314471A (en) | Preparation method of rear SE structure | |
| CN116666479A (en) | Efficient selective emitter crystalline silicon battery with double-sided power generation and preparation method thereof | |
| CN110993740A (en) | Method for producing a solar cell and solar cell | |
| CN116130530A (en) | Topcon solar cell and preparation method thereof | |
| CN115274936A (en) | Solar cell and method for manufacturing same | |
| CN112599618A (en) | Solar cell and manufacturing method thereof | |
| CN109802009B (en) | Preparation method of ultrathin crystalline silicon double-sided solar cell | |
| CN112582484A (en) | Solar cell and manufacturing method thereof | |
| CN113241391A (en) | PERC battery processing technology for reducing back surface field recombination loss | |
| CN116314473B (en) | P-type IBC solar cell and texturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |