CN114784140A - Topcon battery preparation method, Topcon battery and winding-removing plating tank type cleaning machine - Google Patents

Topcon battery preparation method, Topcon battery and winding-removing plating tank type cleaning machine Download PDF

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CN114784140A
CN114784140A CN202210353011.2A CN202210353011A CN114784140A CN 114784140 A CN114784140 A CN 114784140A CN 202210353011 A CN202210353011 A CN 202210353011A CN 114784140 A CN114784140 A CN 114784140A
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silicon wafer
phosphorus
front surface
oxide layer
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CN114784140B (en
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吴帅
张鹏程
张东威
陈晨
袁陨来
叶枫
王建波
吕俊
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Xian Longi Solar Technology Co Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
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Abstract

The invention provides a preparation method of a Topcon battery, the Topcon battery and a winding-free plating tank type cleaning machine, relating to the technical field of solar photovoltaic, wherein the method comprises the steps of firstly providing a silicon wafer, wherein the silicon wafer comprises a front surface, a back surface opposite to the front surface and a side surface connecting the front surface and the back surface, then preparing a boron doping layer on the front surface, preparing a tunneling oxidation layer and a phosphorus doping polycrystalline silicon layer on the back surface, forming a tunneling oxidation layer winding-plated on the side surface in the process of preparing the tunneling oxidation layer, and forming a phosphorus-silicon glass layer winding-plated on the tunneling oxidation layer on the side surface from outside to inside, a phosphorus doping polycrystalline silicon layer and a phosphorus internal expansion layer penetrating through the tunneling oxidation layer on the side surface in the process of preparing the phosphorus doping polycrystalline silicon layer; after the phosphorosilicate glass layer, the phosphorus-doped polycrystalline silicon layer and the tunneling oxide layer which are plated in a winding mode are removed, the silicon wafer is cleaned by adopting a mixed solution of ozone and hydrofluoric acid, the edge of the silicon wafer can be etched continuously, the phosphorus inner expanding layer is effectively removed, the phosphorus overexpansion concentration of the edge is reduced, the front passivation effect is improved, and the electric leakage problem is avoided.

Description

Topcon battery preparation method, Topcon battery and winding-removing plating tank type cleaning machine
Technical Field
The invention relates to the technical field of solar photovoltaic, in particular to a Topcon battery preparation method, a Topcon battery and a winding-free plating tank type cleaning machine.
Background
The front surface of a tunnel oxide passivated contact (Topcon) battery adopts a laminated passivation film, and the back surface adopts a tunnel oxide passivated contact structure of ultrathin silicon oxide and doped polysilicon (poly-Si), so that the selective passing of majority carriers is realized, the recombination rate of minority carriers is reduced, and the conversion efficiency is improved.
In the preparation process of the Topcon battery, LPCVD (Low-pressure Chemical Vapor Deposition) can be used to prepare poly-Si on the back surface of the silicon wafer by long-time Deposition, and in actual production, the front surface and the front surface of the silicon wafer are usually inserted into the slots of a quartz boat in a double-insertion manner, so that the front surface and the back surface of the silicon wafer face inward and outward, and during the Deposition of poly-Si on the back surface, due to the gap between the front surfaces of the double-insertion silicon wafer, poly-Si electroplating is generated on the front surface and the side surface of the silicon wafer, and the poly-Si electroplating affects the appearance and performance of the battery.
Disclosure of Invention
The invention provides a Topcon battery preparation method, a Topcon battery and a winding-free plating tank type cleaning machine, and aims to solve the problem of edge leakage of a finished Topcon battery and reduce edge recombination of the battery so as to improve the conversion efficiency of the battery.
In a first aspect, an embodiment of the present invention provides a Topcon battery manufacturing method, which may include:
providing a silicon wafer, wherein the silicon wafer comprises a front surface, a back surface opposite to the front surface and a side surface connecting the front surface and the back surface;
preparing a boron doped layer on the front surface, and sequentially preparing a tunneling oxide layer and a phosphorus doped polycrystalline silicon layer on the back surface, wherein a tunneling oxide layer which is plated on the side surface in a winding way is formed in the process of preparing the tunneling oxide layer, and a phosphosilicate glass layer which is plated on the side surface in a winding way and is outside the tunneling oxide layer from outside to inside, the phosphorus doped polycrystalline silicon layer and a phosphorus inner expanding layer which is positioned on the side surface and penetrates through the tunneling oxide layer are formed in the process of preparing the phosphorus doped polycrystalline silicon layer;
removing the phosphorus-silicon glass layer subjected to the winding plating, the phosphorus-doped polycrystalline silicon layer subjected to the winding plating and the tunneling oxide layer subjected to the winding plating;
and cleaning the silicon wafer by adopting a mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner expanding layer on the side surface.
Optionally, the mass fraction of the ozone in the mixed solution is 0.025-0.065 ‰.
Optionally, the mass fraction of the hydrofluoric acid in the mixed solution is 0.0027-0.0068 ‰.
Optionally, the washing time of the washing is 180-250 seconds.
Optionally, the removing the phosphosilicate glass layer, the phosphorus-doped polysilicon layer, and the tunnel oxide layer comprises:
removing the phosphorosilicate glass layers wound and plated on the front surface and the side surfaces;
removing the phosphorus-doped polycrystalline silicon layer wound and plated on the front surface and the side surface;
and removing the tunneling oxide layer wound and plated on the front surface and the side surface, the borosilicate glass layer wound and plated on the front surface, and the phosphorosilicate glass layer wound and plated on the back surface.
Optionally, after the silicon wafer is cleaned by using a mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner diffusion layer on the side surface, the method further includes:
preparing a passivation film on the front surface and the back surface;
and preparing electrodes on the front surface and the back surface.
Optionally, before the step of cleaning the silicon wafer with the mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner diffusion layer on the side surface, the method further includes:
treating the silicon wafer by adopting potassium hydroxide and hydrogen peroxide;
optionally, after the silicon wafer is cleaned by using a mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner diffusion layer on the side surface, the method further includes:
and dehydrating the silicon wafer.
In a second aspect, an embodiment of the present invention provides a Topcon battery, which is prepared by the Topcon battery preparation method described in the first aspect;
the front side of the Topcon battery is in a rounded pyramid structure.
In a third aspect, an embodiment of the present invention provides a winding-free plating tank type cleaning machine, including a first cleaning tank, a second cleaning tank, and a third cleaning tank, which are sequentially arranged, wherein the first cleaning tank is configured with a potassium hydroxide solution, the second cleaning tank is configured with a hydrofluoric acid solution, and the third cleaning tank is configured with a mixed solution of ozone and hydrofluoric acid;
the unwinding plating tank type cleaning machine is used for the Topcon battery preparation method of the first aspect.
Optionally, the first cleaning tank is used for removing the phosphorus-doped polysilicon layer which is plated around the front surface and the side surface.
Optionally, the second cleaning tank is used for removing the tunneling oxide layer around the front surface and the side surface, the borosilicate glass layer around the front surface, and the phosphorosilicate glass layer around the back surface.
Optionally, the third cleaning tank is configured to clean the silicon wafer with a mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner diffusion layer on the side surface.
The invention provides a preparation method of a Topcon battery, which comprises the steps of firstly providing a silicon wafer, wherein the silicon wafer comprises a front surface, a back surface opposite to the front surface and a side surface connecting the front surface and the back surface, then preparing a boron doped layer on the front surface of the silicon wafer, and sequentially preparing a tunneling oxide layer and a phosphorus doped polycrystalline silicon layer on the back surface, wherein a tunneling oxide layer wound and plated on the side surface is formed in the process of preparing the tunneling oxide layer, and a phosphosilicate glass layer, a phosphorus doped polycrystalline silicon layer and a phosphorus inner expanding layer, which are positioned on the side surface and penetrate through the tunneling oxide layer, are formed outside and inside the tunneling oxide layer wound and plated on the side surface in the process of preparing the phosphorus doped polycrystalline silicon layer; and then removing the phosphorus-silicon glass layer which is plated in a winding way, the phosphorus-doped polycrystalline silicon layer which is plated in a winding way and the tunneling oxide layer which is plated in a winding way, and then further cleaning the silicon wafer by adopting a mixed solution of ozone and hydrofluoric acid, wherein the ozone has strong oxidizing property, a compact and high-quality silicon oxide layer can be grown on the surface of the silicon wafer, at the moment, the silicon oxide layer formed by ozone oxidation on the surface of the silicon wafer is etched and removed by the hydrofluoric acid, the edge of the silicon wafer can be continuously etched, so that the phosphorus inner expanding layer at the edge of the silicon wafer is effectively removed, the phosphorus overexpansion concentration at the edge of the silicon wafer is reduced, the front passivation effect is further improved, and the problem of electric leakage at the edge of the silicon wafer is avoided.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive labor.
Fig. 1 shows one of the steps of a Topcon cell manufacturing method according to an embodiment of the present invention;
fig. 2 shows a second step flow chart of a Topcon cell manufacturing method according to an embodiment of the present invention;
fig. 3 shows a schematic diagram of a silicon wafer structure according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 shows one of the steps of a flowchart of a Topcon battery manufacturing method provided in an embodiment of the present invention, where the method may include:
step 101, providing a silicon wafer, wherein the silicon wafer comprises a front surface, a back surface opposite to the front surface, and a side surface connecting the front surface and the back surface.
The embodiment of the invention is applied to the preparation of a Topcon battery, the Topcon battery usually adopts a silicon wafer as a substrate, the silicon wafer can comprise a front side and a back side opposite to the front side, the side surface of the edge of the silicon wafer is connected with the front side and the back side, the surface of the silicon wafer on the same side as the light incident side of the Topcon battery is usually taken as the front side, the surface of the silicon wafer on the same side as the backlight side of the Topcon battery is taken as the back side, and the edge of the silicon wafer between the front side and the back side is taken as the side surface.
102, preparing a boron doped layer on the front surface, and sequentially preparing a tunneling oxide layer and a phosphorus doped polycrystalline silicon layer on the back surface, wherein a tunneling oxide layer which is plated around the side surface is formed in the process of preparing the tunneling oxide layer, and a phosphosilicate glass layer which is plated around the tunneling oxide layer on the side surface from outside to inside, the phosphorus doped polycrystalline silicon layer and a phosphorus inner diffusion layer which is positioned on the side surface and penetrates through the tunneling oxide layer are formed in the process of preparing the phosphorus doped polycrystalline silicon layer.
In the embodiment of the invention, the Topcon battery can be prepared by preparing the boron doped layer on the front side of the silicon wafer and preparing the boron doped layer on the back side of the silicon wafer which are sequentially stackedTunneling oxidation (SiO)2) The passivation contact structure is formed on the back surface of the silicon wafer, wherein a boron doping layer can be prepared on the front surface of the silicon wafer by adopting a boron diffusion process, a tunneling oxide layer is prepared by adopting LPCVD deposition, and a phosphorus doping polycrystalline silicon layer is prepared by adopting LPCVD deposition.
In the embodiment of the invention, the tunneling oxide layer is formed on the side surface of the silicon wafer by winding and plating in the process of preparing the tunneling oxide layer, the phosphosilicate glass layer, the phosphorus-doped polycrystalline silicon (Poly-Si) layer and the phosphorus inner expanding layer which is positioned on the side surface and penetrates through the tunneling oxide layer are formed outside the tunneling oxide layer on the side surface of the silicon wafer by winding and plating from outside to inside in the process of preparing the phosphorus-doped polycrystalline silicon layer, and each film layer wound and plated on the side surface of the silicon wafer influences the appearance and the performance of the battery and needs to be cleaned and removed in the preparation process.
103, removing the phosphorus-silicon glass layer subjected to winding plating, the phosphorus-doped polycrystalline silicon layer subjected to winding plating and the tunneling oxide layer subjected to winding plating.
In the embodiment of the invention, the phosphorosilicate glass layer, the phosphorus-doped polycrystalline silicon layer and the tunneling oxide layer which are wound and plated on the silicon wafer can be removed, and only the boron-doped layer on the front surface of the silicon wafer, and the tunneling oxide layer and the phosphorus-doped polycrystalline silicon layer on the back surface are reserved. Optionally, in the process of preparing the boron doped layer on the front side, borosilicate glass layers may be further formed on the front side and the back side of the silicon wafer, wherein the borosilicate glass layer on the back side may be removed before preparing the tunneling oxide layer and the phosphorus doped polysilicon layer, and the borosilicate glass layer on the front side may be removed after preparing the tunneling oxide layer and the phosphorus doped polysilicon layer. The removing sequence and removing process of each layer on each surface of the silicon wafer can be selected according to process conditions and process requirements, for example, an acid cleaning can be adopted to remove the borosilicate glass layer, the wrapped-plated phosphosilicate glass layer, the tunneling oxide layer and the like, an alkali cleaning can be adopted to remove the wrapped-plated phosphorus-doped polysilicon layer, and a laser can also be adopted to remove the wrapped-plated phosphorus-doped polysilicon layer, which is not specifically limited in the embodiment of the invention.
Currently, poly-Si removal coil plating generally employs an alkali direct etching process, which includes first removing a PSG (phosphosilicate Glass) layer on the front surface in a chain washer, and then alkali washing away poly-Si coil plating on the front surface and the side surfaces in a tank washer.
Research shows that after the phosphorus-silicon glass layer, the phosphorus-doped polycrystalline silicon layer and the tunneling oxide layer which are wound and plated are removed, the phosphorus inner expanding layer which penetrates through the side surface of the phosphorus inner expanding layer and is wound and plated with the tunneling oxide layer and is formed in the process of preparing the phosphorus-doped polycrystalline silicon layer exists at the edge of the silicon wafer, and the phosphorus inner expanding layer causes the problem of electric leakage at the edge of the silicon wafer, so that the performance of a finished Topcon battery is influenced. In particular, because protective additives are generally adopted in the alkali direct etching process, the protective additives are added to SiO2poly-Si spin-on etch on the protective base of the layer, and SiO2The reaction rate of the layer and alkali liquor is slow, and the tunneling oxide layer existing under poly-Si coated on the side surface of the silicon chip hinders the continuous etching reaction of phosphorus inner diffusion on the edge of the silicon chip, so that the phosphorus inner diffusion layer penetrating through the tunneling oxide layer can not be fully removed through the etching reaction.
And 104, cleaning the silicon wafer by adopting a mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner expanding layer on the side surface.
In the embodiment of the present invention, after step 103, ozone (O) may be further used3) Cleaning silicon chip with mixed solution of hydrofluoric acid (HF) and ozone with oxidizing property higher than that of sulfuric acid (H)2SO4) Hydrochloric acid (HCl), hydrogen peroxide (H)2O2) And the like, organic contamination on the surface of the silicon wafer can be effectively removed, a compact and ultrathin high-quality silicon oxide layer can rapidly grow on the surface of the silicon wafer, the formed compact and high-quality silicon oxide layer can be corroded and removed by hydrofluoric acid, meanwhile, a phosphorus internal expanding layer on the edge of the silicon wafer can be continuously removed, further, the phosphorus internal expanding concentration on the edge of the silicon wafer is reduced, the PN junction short circuit is prevented, the front passivation effect can be improved, and the probability of electric leakage on the edge of a battery is effectively reduced.
In the embodiment of the present invention, other functional layers such as a passivation layer, an antireflection layer, and a metal electrode may be further prepared on the front side and the back side of the silicon wafer to prepare the solar cell.
The invention provides a preparation method of a Topcon battery, which comprises the steps of firstly providing a silicon wafer, wherein the silicon wafer comprises a front surface, a back surface opposite to the front surface and a side surface connecting the front surface and the back surface, then preparing a boron doped layer on the front surface of the silicon wafer, and sequentially preparing a tunneling oxide layer and a phosphorus doped polycrystalline silicon layer on the back surface, wherein a tunneling oxide layer wound and plated on the side surface is formed in the process of preparing the tunneling oxide layer, and a phosphosilicate glass layer, a phosphorus doped polycrystalline silicon layer and a phosphorus inner expanding layer, which are positioned on the side surface and penetrate through the tunneling oxide layer, are formed outside and inside the tunneling oxide layer wound and plated on the side surface in the process of preparing the phosphorus doped polycrystalline silicon layer; and then removing the phosphorosilicate glass layer which is plated in a winding way, the phosphorus-doped polycrystalline silicon layer which is plated in a winding way and the tunneling oxide layer which is plated in a winding way, and then further cleaning the silicon wafer by adopting a mixed solution of ozone and hydrofluoric acid, wherein the ozone has strong oxidizing property, a compact and high-quality silicon oxide layer can be grown on the surface of the silicon wafer, at the moment, the silicon oxide layer formed by oxidizing the ozone on the surface of the silicon wafer by the hydrofluoric acid is etched and removed, the edge of the silicon wafer can be etched continuously, so that the phosphorus inner expanding layer at the edge of the silicon wafer is effectively removed, the concentration of phosphorus in the edge of the silicon wafer is reduced, the front passivation effect is further improved, and the problem of electric leakage at the edge of the silicon wafer is avoided.
Referring to fig. 2, fig. 2 shows a second flowchart of the steps of a Topcon battery manufacturing method provided in an embodiment of the present invention, where the method may include:
step 201, providing a silicon wafer, wherein the silicon wafer comprises a front surface, a back surface opposite to the front surface, and a side surface connecting the front surface and the back surface.
In the embodiment of the present invention, step 201 may refer to the related description of step 101, and is not described herein again to avoid repetition. Optionally, texturing may be performed on the silicon wafer to form a pyramid structure on the surface of the silicon wafer, so as to reduce reflection of incident light, improve short-circuit current of the battery, and further improve photoelectric conversion efficiency of the battery, for example, alkali solution such as sodium hydroxide and potassium hydroxide may be used to perform alkali texturing on the silicon wafer; optionally adding additives in the alkali texturing process to adjust the reaction speed, the size of the textured surface and the like, wherein the additives can comprise a surfactant, a nucleating agent, a dispersing agent, a catalyst, a defoaming agent and the like; in the process, the silicon wafer can be put into a groove type texture etching cleaning machine to carry out an alkali texture etching process on the silicon wafer, and the specific conditions of the texture etching process in the embodiment of the invention are not particularly limited. Wherein, the process temperature for texturing the silicon wafer can be 77-83 ℃, the process time can be 455-465 seconds, the etching amount of the silicon wafer after texturing treatment can be 0.445-0.455g, and the reflectivity of the surface of the silicon wafer can be 8.7-9.3%.
202, performing boron diffusion treatment on the front side to form a boron doped layer, and performing etching treatment on the back side of the silicon wafer.
In the embodiment of the invention, after the silicon wafer is subjected to texturing, the front surface of the silicon wafer can be subjected to boron diffusion treatment, so that a boron doped layer is formed on the front surface of the silicon wafer. Alternatively, boron sources such as trimethyl borate, boron tribromide, boron trichloride and the like can be adopted for boron diffusion; the process temperature of boron diffusion can be any temperature between 950-.
In the embodiment of the invention, the boron-wound diffusion layer is formed on the back surface of the silicon wafer in the process of performing boron diffusion treatment on the silicon wafer, the boron-wound diffusion layer on the back surface influences the deposition of the tunneling oxide layer and the polycrystalline silicon layer on the back surface of the silicon wafer in the subsequent process, and the boron-wound diffusion layer on the back surface of the silicon wafer can be removed and the back surface of the silicon wafer can be polished by performing etching treatment on the back surface of the silicon wafer, so that the passivation effect of a battery passivation contact structure is improved. Alternatively, hydrofluoric acid, nitric acid (HNO) may be used3) And Deionized Water (DIW), wherein the hydrofluoric acid with mass fraction of 49%, the nitric acid with mass fraction of 69% and the Deionized Water can be mixed with HF: HNO3DIW is 1:4-7:1-2, and the technical personnel can select the mixture according to the application requirement and the process conditionThe reflectivity of the back of the silicon wafer after etching treatment can be 34-36% by using different etching solutions, and the weight of the silicon wafer can be reduced by 0.25-0.45g in the etching treatment process.
And 203, depositing a tunneling oxide layer and a polysilicon layer on the back surface in sequence.
In the embodiment of the invention, after the single-side etching treatment is carried out on the back surface of the silicon wafer, the tunneling oxide layer and the polysilicon layer can be sequentially deposited on the back surface of the silicon wafer, optionally, the silicon wafer can be prepared by LPCVD deposition, and the thickness of the prepared tunneling oxide layer can be 1.2-1.8nm, for example, the thickness of the tunneling oxide layer can be any thickness between 1.2-1.8nm, such as 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm and the like; the thickness of the polysilicon layer may be 50 to 250nm, for example, the thickness of the polysilicon layer may be any thickness between 50 to 250nm, such as 50nm, 51nm, 52nm, 53nm, 54nm, 55nm, 60nm, 70nm, 80nm, 90nm, 100nm, 150nm, 200nm, 250nm, and the like, which is not particularly limited in the embodiment of the present invention.
And 204, performing phosphorus injection on the polycrystalline silicon layer to obtain a phosphorus-doped polycrystalline silicon layer, wherein a tunneling oxide layer which is plated around the side surface is formed in the process of preparing the tunneling oxide layer, and a phosphosilicate glass layer which is plated around the tunneling oxide layer on the side surface from outside to inside, the phosphorus-doped polycrystalline silicon layer and a phosphorus inner diffusion layer which is positioned on the side surface and penetrates through the tunneling oxide layer are formed in the process of preparing the phosphorus-doped polycrystalline silicon layer.
In the embodiment of the invention, phosphorus can be injected into the polysilicon layer on the back of the silicon wafer by adopting a phosphorus diffusion process to obtain a phosphorus-doped polysilicon layer, so that a back contact structure of a tunneling oxide layer/the phosphorus-doped polysilicon layer is formed on the back of the silicon wafer, wherein phosphorus oxychloride (POCl) can be selected3) As a phosphorus source, phosphorus diffusion is performed on the polysilicon layer through the phosphorus diffusion furnace, and the plating layer formed in the process from step 202 to step 204 may correspond to the related description of step 102, and is not described herein again for avoiding repetition.
Referring to fig. 3, fig. 3 shows a schematic structural diagram of a silicon wafer according to an embodiment of the present invention, as shown in fig. 3, after step 204, the silicon wafer may include an N-type silicon wafer substrate 1, a phosphosilicate glass layer 2, a phosphorus-doped polysilicon layer 3, a tunneling oxide layer 4, and a borosilicate glass layer 5, where the silicon wafer sequentially includes, from outside to inside:
a phosphorosilicate glass layer 2 formed on the back surface of the N-type silicon wafer substrate 1 and formed on the side surface and the front surface in a winding plating manner in the process of phosphorus injection;
a phosphorus-doped polycrystalline silicon layer 3 formed on the back of the N-type silicon wafer substrate 1 and formed on the side and the front by winding plating in the processes of preparing the polycrystalline silicon layer and injecting phosphorus;
the tunneling oxide layer 4 is formed on the back surface of the N-type silicon wafer substrate 1 in the process of depositing the tunneling oxide layer 4, and the tunneling oxide layer 4 is formed on the side surface and the front surface in a winding plating mode;
and a borosilicate glass layer 5 formed on the front surface of the N-type silicon wafer substrate 1 in the boron diffusion process.
And 205, removing the phosphorosilicate glass layer which is coated on the front surface and the side surface in a winding way.
In the embodiment of the invention, the phosphorosilicate glass layers formed on the front side and the side surface of the silicon wafer in the phosphorus injection process can be removed firstly, so that the phosphorus-doped polycrystalline silicon layers wound and plated on the front side and the side surface of the silicon wafer are exposed, and the phosphorus-doped polycrystalline silicon layer on the back side of the silicon wafer is covered by the phosphorosilicate glass layers. Optionally, the phosphorosilicate glass layers on the front surface and the side surface of the silicon wafer can be removed by hydrofluoric acid pickling in a chain type cleaning machine, wherein the mass fraction of hydrofluoric acid for removing the phosphorosilicate glass layers can be 1.96% -5%.
And 206, removing the phosphorus-doped polycrystalline silicon layer which is coated on the front surface and the side surface in a winding way.
In the embodiment of the invention, under the protection of the phosphosilicate glass layer, the phosphorus-doped polycrystalline silicon layer formed by preparing the polycrystalline silicon layer and winding and plating the front surface and the side surface of the silicon wafer in the phosphorus injection process can be removed, optionally, the phosphorus-doped polycrystalline silicon layer on the front surface and the side surface of the silicon wafer can be removed by adopting 1-1.5% by mass of potassium hydroxide alkali solution for etching, and 0.1-0.3% by mass of protective additives can be added; the cleaning temperature for removing the phosphorus-doped polysilicon layer by winding plating can be 60-70 ℃, and the cleaning time can be 200-300 seconds.
And 207, removing the tunneling oxide layer wound on the front surface and the side surface, the borosilicate glass layer wound on the front surface, and the phosphorosilicate glass layer wound on the back surface.
In the embodiment of the invention, after the tunnel oxide layers on the front surface and the side surface of the silicon wafer are exposed by removing the phosphorosilicate glass layer subjected to winding plating, the tunnel oxide layers formed on the front surface and the side surface of the silicon wafer in the deposition process, the borosilicate glass layer formed on the front surface of the silicon wafer in the preparation process of the boron doping layer and the phosphorosilicate glass layer formed on the back surface of the silicon wafer in the phosphorus injection process can be further removed, and optionally, an etching solution can be obtained by mixing hydrofluoric acid with the mass fraction of 49% in a volume ratio of 30% -70%. Further, after step 206 and before step 207, the silicon wafer may be washed with water to remove alkali, particles, additives, etc.
And 208, treating the silicon wafer by adopting potassium hydroxide and hydrogen peroxide.
In the embodiment of the invention, potassium hydroxide and hydrogen peroxide can be used for treating the silicon wafer to perform pSC1 (pseudo SC1) cleaning, pSC1 cleaning adopts potassium hydroxide (KOH) and hydrogen peroxide chemical cleaning, additives and other chemical components on the surface of the silicon wafer can be removed, alternatively, pSC1 cleaning can be performed on the silicon wafer at 60-70 ℃, and 45% by mass of potassium hydroxide solution and 27% by mass of hydrogen peroxide solution can be mixed in a volume ratio of 1:5 in cleaning solution, for example, 4L of KOH and 20L H can be used2O2And chemically cleaning the silicon wafer.
And 209, cleaning the silicon wafer by adopting a mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner expanding layer on the side surface.
In the embodiment of the present invention, step 209 may correspond to the related description of step 104, and is not repeated herein to avoid repetition.
Optionally, the mass fraction of the ozone in the mixed solution is 0.025-0.065 ‰.
In the embodiment of the present invention, the mass fraction of ozone in the mixed solution may be any concentration between 0.025% and 0.065%, such as 0.025%, 0.026%, 0.027%, 0.028%, 0.029%, 0.030%, 0.035%, 0.040%, 0.045%, 0.050%, 0.055%, 0.060%, 0.065%, and the like, which is not particularly limited in the embodiment of the present invention.
Optionally, the mass fraction of the hydrofluoric acid in the mixed solution is 0.0027-0.0068 ‰.
In the embodiment of the present invention, the mass fraction of the hydrofluoric acid in the mixed solution may be any concentration between 0.0027 and 0.0068%, such as 0.0027%, 0.0028%, 0.0029%, 0.0030%, 0.0035%, 0.0040%, 0.0045%, 0.0050%, 0.0055%, 0.0060%, 0.0065%, 0.0068%, and the like, which is not particularly limited in this embodiment of the present invention.
Optionally, the cleaning time for the cleaning is 180-250 seconds.
In the embodiment of the present invention, the cleaning time for cleaning the silicon wafer by using the mixed solution of ozone and hydrofluoric acid may be any time between 180 and 250 seconds, such as 180 seconds, 185 seconds, 190 seconds, 200 seconds, 210 seconds, 220 seconds, 230 seconds, 240 seconds, 250 seconds, and the like, which is not limited in this embodiment of the present invention.
And step 210, dehydrating the silicon wafer.
In the embodiment of the invention, after the silicon wafer is cleaned by adopting the mixed solution of ozone and hydrofluoric acid to remove the phosphorus internal diffusion concentration on the edge, the silicon wafer can be dehydrated, wherein the treatment time of the dehydration treatment can be any time within 180-350 seconds, such as 180 seconds, 185 seconds, 190 seconds, 200 seconds, 210 seconds, 220 seconds, 230 seconds, 240 seconds, 250 seconds, 300 seconds, 350 seconds and the like, the silicon wafer can be dehydrated by adopting hydrofluoric acid, hydrochloric acid and the like, and the silicon wafer can be subjected to hydrophobic treatment by adopting hydrofluoric acid with the mass fraction of 49% and mixing at the volume ratio of 5-15% so as to dry and dehydrate the silicon wafer.
And step 211, preparing passivation films on the front side and the back side of the silicon wafer.
In the embodiment of the invention, passivation films can be prepared on the front side and the back side of the silicon wafer, wherein the aluminum oxide layer has a better field effect passivation effect, and can passivate the surface of the boron doped layer, reduce carrier recombination and prolong the minority carrier lifetime, so that the photoelectric conversion efficiency of the battery is improved; further, a silicon nitride layer may be prepared on the front side and the back side of the silicon substrate, that is, on the aluminum oxide layer and the phosphorus-doped polysilicon layer, and the silicon nitride layer has good hydrogen passivation and antireflection effects and can achieve good bulk passivation effects, optionally, a laminated silicon nitride layer may be prepared on the aluminum oxide layer to achieve front side passivation and antireflection effects of the battery, and a silicon nitride layer with a lower refractive index may be prepared on the phosphorus-doped polysilicon layer to reduce light loss and improve light utilization rate.
Step 212, preparing electrodes on the front side and the back side of the silicon wafer.
In the embodiment of the present invention, after each film layer is prepared, electrodes may be prepared on the front side and the back side of the silicon wafer to obtain a solar cell, optionally, the electrodes may be prepared by screen printing a metal paste and sintering, or may be prepared by a photolithography plating method, or may be prepared by a vacuum evaporation method, and optionally, the electrodes may be silver electrodes, copper electrodes, aluminum electrodes, or the like, which is not particularly limited in the embodiment of the present invention.
The invention provides a preparation method of a Topcon battery, which comprises the steps of firstly providing a silicon wafer, wherein the silicon wafer comprises a front surface, a back surface opposite to the front surface and a side surface connecting the front surface and the back surface, then preparing a boron doped layer on the front surface of the silicon wafer, and sequentially preparing a tunneling oxide layer and a phosphorus doped polycrystalline silicon layer on the back surface, wherein a tunneling oxide layer which is coated on the side surface in a winding way is formed in the process of preparing the tunneling oxide layer, and a phosphorus silicon glass layer, a phosphorus doped polycrystalline silicon layer and a phosphorus inner expanding layer which are positioned on the side surface and penetrate through the tunneling oxide layer are formed in the process of preparing the phosphorus doped polycrystalline silicon layer from outside to inside in the winding way; and then removing the phosphorus-silicon glass layer which is plated in a winding way, the phosphorus-doped polycrystalline silicon layer which is plated in a winding way and the tunneling oxide layer which is plated in a winding way, and then further cleaning the silicon wafer by adopting a mixed solution of ozone and hydrofluoric acid, wherein the ozone has strong oxidizing property, a compact and high-quality silicon oxide layer can be grown on the surface of the silicon wafer, at the moment, the silicon oxide layer formed by ozone oxidation on the surface of the silicon wafer is etched and removed by the hydrofluoric acid, the edge of the silicon wafer can be continuously etched, so that the phosphorus inner expanding layer at the edge of the silicon wafer is effectively removed, the phosphorus overexpansion concentration at the edge of the silicon wafer is reduced, the front passivation effect is further improved, and the problem of electric leakage at the edge of the silicon wafer is avoided.
The embodiment of the invention also provides a Topcon battery, which is prepared by adopting the preparation method of the Topcon battery as shown in any one of the figures 1 and 2;
the front of the Topcon battery is in a rounded pyramid structure.
The Topcon battery provided by the embodiment of the invention is characterized in that a silicon chip is provided firstly in the preparation process, the silicon chip comprises a front surface, a back surface opposite to the front surface and a side surface connecting the front surface and the back surface, a boron doped layer is prepared on the front surface of the silicon chip, and a tunneling oxide layer and a phosphorus doped polycrystalline silicon layer are sequentially prepared on the back surface, wherein a tunneling oxide layer wound and plated on the side surface is formed in the preparation process of the tunneling oxide layer, a phosphosilicate glass layer wound and plated on the tunneling oxide layer on the side surface from outside to inside, a phosphorus doped polycrystalline silicon layer and a phosphorus inner expanding layer positioned on the side surface and penetrating through the tunneling oxide layer are formed in the preparation process of the phosphorus doped polycrystalline silicon layer; removing the phosphorus-silicon glass layer, the phosphorus-doped polycrystalline silicon layer and the tunneling oxide layer, cleaning the silicon wafer by using a mixed solution of ozone and hydrofluoric acid, wherein the ozone has strong oxidizing property, a compact and high-quality silicon oxide layer can grow on the surface of the silicon wafer, and the silicon oxide layer formed by ozone oxidation on the surface of the silicon wafer is etched and removed by using the hydrofluoric acid, so that the edge of the silicon wafer can be continuously etched, the phosphorus inner expanding layer at the edge of the silicon wafer is effectively removed, the phosphorus overexpansion concentration at the edge of the silicon wafer is reduced, the front passivation effect is improved, and the problem of electric leakage at the edge of the silicon wafer is solved; and the pyramid structure on the front side of the silicon wafer is firstly oxidized by ozone to form a silicon oxide layer, and then the silicon oxide layer is removed by hydrofluoric acid etching, and the pyramid tip of the pyramid structure can be subjected to corner rounding treatment, so that the front side of the silicon wafer is in a corner-rounded pyramid structure, and the reflectivity of the front side of the silicon wafer is improved.
The invention further provides a winding-removing plating tank type cleaning machine, after the phosphorosilicate glass layer is removed by the chain type cleaning machine, the winding-removing plating tank type cleaning machine can be used for winding-removing plating cleaning of the silicon wafer, optionally, the winding-removing plating tank type cleaning machine comprises a first cleaning tank, a second cleaning tank and a third cleaning tank which are sequentially arranged, the first cleaning tank is provided with a potassium hydroxide solution, the second cleaning tank is provided with a hydrofluoric acid solution, and the third cleaning tank is provided with a mixed solution of ozone and hydrofluoric acid.
The unwinding plating tank type cleaning machine is used for the Topcon battery preparation method shown in any one of the previous figures 1 and 2.
Optionally, the first cleaning tank is used for removing the phosphorus-doped polysilicon layer which is coated around the front surface and the side surface;
optionally, the second cleaning tank is used for removing the tunneling oxide layer wound on the front surface and the side surface, the borosilicate glass layer on the front surface, and the phosphorosilicate glass layer wound on the back surface;
optionally, the third cleaning tank is configured to clean the silicon wafer with a mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner diffusion layer on the side surface.
In the embodiment of the present invention, the winding-removing plating tank type cleaning machine can be used for performing winding-removing plating treatment in the preparation process of the Topcon battery shown in any one of fig. 1 to 2, and according to specific process requirements, the sequence of each tank body can be adjusted to add or remove different tank bodies, for example, a water washing tank can be added between the first cleaning tank and the second cleaning tank, a water washing tank, a pSC1 cleaning tank and a water washing tank are sequentially added between the second cleaning tank and the third cleaning tank, and a water washing tank, a pickling tank, a slow pulling tank, a drying tank and the like are sequentially added after the third cleaning tank;
the washing tank is used for washing the silicon wafers, the pSC1 washing tank is used for washing the silicon wafers with pSC1 by adopting potassium hydroxide and hydrogen peroxide, and the pickling tank is used for pickling the silicon wafers with hydrofluoric acid and hydrochloric acid.
The winding-removing plating tank type cleaning machine provided by the embodiment of the invention can carry out winding-removing plating treatment in the preparation process of a Topcon battery, and comprises a first cleaning tank, a second cleaning tank and a third cleaning tank which are sequentially arranged, wherein the first cleaning tank is configured with a potassium hydroxide solution, the second cleaning tank is configured with a hydrofluoric acid solution, and the third cleaning tank is configured with a mixed solution of ozone and hydrofluoric acid; the first cleaning tank is used for removing the phosphorus-doped polycrystalline silicon layer wound and plated on the front surface and the side surface of the silicon wafer; the second cleaning tank is used for removing tunneling oxide layers wound on the front surface and the side surfaces of the silicon wafer, a borosilicate glass layer wound on the front surface and the phosphorosilicate glass layer wound on the back surface; the third cleaning tank is used for adopting ozone, the mixed solution of hydrofluoric acid is used for cleaning the silicon wafer, because ozone has strong oxidizing property, can grow compactly on the surface of the silicon wafer, high-quality silicon oxide layer, at the moment, the silicon oxide layer formed by ozone oxidation on the surface of the silicon wafer is etched and removed through hydrofluoric acid, the edge of the silicon wafer can be continuously etched, thereby effectively removing the phosphorus inner expanding layer at the edge of the silicon wafer, the phosphorus inner expanding concentration at the edge of the silicon wafer is reduced, further the front passivation effect is improved, the electricity leakage problem at the edge of the silicon wafer is avoided, and the pyramid tip of the pyramid structure at the front side of the silicon wafer can be subjected to round corner treatment, so that the front side of the silicon wafer is in a round corner pyramid structure, and the reflectivity of the front side of the silicon wafer is improved.
The embodiment of the invention also provides a preparation process example of a conventional battery, a sample battery 1 and a sample battery 2, wherein the conventional battery is prepared by adopting a conventional Topcon battery preparation method, and the sample battery 1 and the sample battery 2 are prepared by adopting the Topcon battery preparation method provided by the invention, and the preparation process specifically comprises the following steps:
example preparation of a conventional Battery
S101, adopting a potassium hydroxide solution with the mass fraction of about 1% to perform texturing treatment on an N-type silicon wafer with the size of 182mm in a groove type texturing cleaning machine, wherein 5.4L of KOH solution with the mass fraction of 45% and 2.2L of additives are mixed according to the mixing ratio, the temperature of an alkali texturing process is 82 ℃, the process time is 420 seconds, the weight of the N-type silicon wafer after texturing is reduced by 0.42g, and the reflectivity is 8.7%.
Step S102, carrying out a boron diffusion process on the front surface of the textured N-type silicon wafer in a boron diffusion furnace tube to prepare a boron doped layer, forming a borosilicate glass layer on the surface of the N-type silicon wafer, and enabling the sheet resistance of the N-type silicon wafer after boron diffusion to be 120 omega/□.
Step S103, performing single-sided etching treatment on the back of the silicon wafer after boron diffusion in a chain type cleaning machine to remove the borosilicate glass layer on the back, wherein the etching solution comprises 49% by mass of hydrofluoric acid, 69% by mass of nitric acid and deionized water, and the proportion of the etching solution is HF to HNO3DI is 1:7:1, and the reflectance of the back surface of the N-type silicon wafer after etching is 35%, and the weight is reduced by 0.35 g.
And step S104, depositing a tunneling oxide layer and a polysilicon layer on the back surface of the N-type silicon wafer by LPCVD, wherein the thickness of the tunneling oxide layer is 1.5nm, and the thickness of the polysilicon layer is 120 nm.
And S105, performing phosphorus injection on the polycrystalline silicon layer by adopting a phosphorus diffusion furnace on the back of the N-type silicon wafer to obtain a phosphorus-doped polycrystalline silicon layer so as to form a passivation contact structure on the back of the N-type silicon wafer and form a passivation contact structure on the edge of the silicon wafer in the phosphorus injection process.
Further, in step S104-105, a tunnel oxide layer is formed on the side surface of the N-type silicon wafer during the process of preparing the tunnel oxide layer, and a phosphosilicate glass layer, a phosphorus-doped polysilicon layer, and a phosphorus inner diffusion layer located on the side surface of the N-type silicon wafer and penetrating through the tunnel oxide layer are formed from outside to inside outside the tunnel oxide layer on the side surface of the N-type silicon wafer during the process of preparing the phosphorus-doped polysilicon layer.
And S106, removing the phosphorosilicate glass layers on the front surface and the side surface of the N-type silicon wafer by adopting a hydrofluoric acid solution with the mass fraction of 3% in a chain type cleaning machine based on the belt speed of 2 m/min.
And S107, removing the phosphorus-doped polycrystalline silicon layer wound and plated on the front surface and the side surface of the N-type silicon wafer by adopting a potassium hydroxide solution in a winding-removing plating tank type cleaning machine, wherein the mixing ratio of the potassium hydroxide solution with the mass fraction of 45% to the additive is 16LKOH solution and 3.5L of additive, the process temperature is 66 ℃, and the process time is 260 seconds.
And step S108, washing the N-type silicon wafer in a winding-removing plating tank type cleaning machine for 120 seconds.
Step S109, a hydrofluoric acid solution is adopted in the winding-removing plating tank type cleaning machine to remove the borosilicate glass layer on the front surface of the N-type silicon wafer, the tunneling oxide layers on the front surface and the side surfaces and the phosphorosilicate glass layer on the back surface, wherein the hydrofluoric acid solution is prepared by adopting 49% by mass of hydrofluoric acid according to a volume ratio of 50%, and the mass fraction of the hydrofluoric acid in the prepared hydrofluoric acid solution is 17%.
Step S120, carrying out pSC1 cleaning on the N-type silicon wafer by adopting potassium hydroxide and hydrogen peroxide in a winding-removing plating tank type cleaning machine to remove additives and chemical components remained on the surface of the N-type silicon wafer, wherein the mass fraction of KOH is 45%, and the volume of KOH is 4L; h2O2The mass fraction of (1) is 27%, and the volume is 20L; the washing temperature was 65 ℃.
And step S121, washing the N-type silicon wafer for 120 seconds in a winding-removing plating tank type cleaning machine.
And S122, performing acid cleaning on the N-type silicon wafer by adopting a hydrofluoric acid solution in a winding-removing plating tank type cleaning machine, wherein the hydrofluoric acid solution used for acid cleaning accounts for 8% in mass percent, the treatment time is 180 seconds, and then performing complete dehydration and drying treatment.
And S123, preparing an AlOx + SiNx passivation film on the front side of the N-type silicon wafer, and preparing a SiNx passivation film on the back side of the N-type silicon wafer.
And S124, performing screen printing and sintering on the passivation film to prepare an electrode, and testing and sorting to obtain the conventional battery.
Example preparation of two sample cell 1
Step S201, carrying out texturing treatment on an N-type silicon wafer with the size of 182mm by adopting a potassium hydroxide solution with the mass fraction of about 1% in a groove type texturing cleaning machine, wherein 5.4L of KOH solution with the mass fraction of 45% is mixed with 2.2L of additive, the temperature of an alkali texturing process is 82 ℃, the process time is 420 seconds, the weight of the N-type silicon wafer after texturing is reduced by 0.42g, and the reflectivity is 8.7%.
Step S202, carrying out a boron diffusion process on the front surface of the textured N-type silicon wafer in a boron diffusion furnace tube to prepare a boron doped layer, forming a borosilicate glass layer on the surface of the N-type silicon wafer, and carrying out the sheet resistance of the N-type silicon wafer after boron diffusion to be 120 omega/□.
Step S203, performing single-side etching treatment on the back of the silicon wafer after boron diffusion in a chain type cleaning machine, and removing the borosilicate glass layer on the back, wherein the etching solution of the etching solution comprises 49% by mass of hydrofluoric acid, 69% by mass of nitric acid and deionized water, and the proportion of the etching solution is HF to HNO3DI is 1:7:1, and the reflectance of the back surface of the N-type silicon wafer after etching is 35%, and the weight is reduced by 0.35 g.
And S204, depositing a tunneling oxide layer and a polysilicon layer on the back surface of the N-type silicon wafer by LPCVD, wherein the thickness of the tunneling oxide layer is 1.5nm, and the thickness of the polysilicon layer is 120 nm.
And S205, injecting phosphorus into the polycrystalline silicon layer by adopting a phosphorus diffusion furnace on the back of the N-type silicon wafer to obtain a phosphorus-doped polycrystalline silicon layer so as to form a passivation contact structure on the back of the N-type silicon wafer.
Further, in step S204-205, a tunnel oxide layer is formed on the side surface of the N-type silicon wafer during the process of preparing the tunnel oxide layer, and a phosphosilicate glass layer, a phosphorus-doped polysilicon layer, and a phosphorus under-extension layer that is located on the side surface of the N-type silicon wafer and passes through the tunnel oxide layer are formed on the side surface of the N-type silicon wafer from outside to inside during the process of preparing the phosphorus-doped polysilicon layer.
And S206, removing the phosphorosilicate glass layers on the front surface and the side surface of the N-type silicon wafer by adopting a hydrofluoric acid solution with the mass fraction of 3% in a chain type cleaning machine based on the belt speed of 2 m/min.
And step S207, removing the phosphorus-doped polycrystalline silicon layer wound and plated on the front surface and the side surface of the N-type silicon wafer by adopting a potassium hydroxide solution in a winding-removing plating tank type cleaning machine, wherein the mixing ratio of the potassium hydroxide solution with the mass fraction of 45% to an additive is 16LKOH solution and 3.5L of additive, the process temperature is 66 ℃, and the process time is 260 seconds.
And step S208, washing the N-type silicon wafer for 120 seconds in a winding-free plating tank type cleaning machine.
Step S209, in the winding-removing plating tank type cleaning machine, a hydrofluoric acid solution is adopted to remove the borosilicate glass layer on the front surface of the N-type silicon wafer, the tunneling oxide layers on the front surface and the side surfaces and the phosphorosilicate glass layer on the back surface, wherein the hydrofluoric acid solution is prepared by adopting 49% by mass of hydrofluoric acid according to a volume ratio of 50%, and the mass fraction of the hydrofluoric acid in the prepared hydrofluoric acid solution is 17%.
Step S210, cleaning an N-type silicon wafer in a 360L tank body of a winding-removing plating tank type cleaning machine by adopting a mixed solution of ozone and hydrofluoric acid, wherein the cleaning time is 180 seconds, the mass fraction of the ozone is 4 per thousand, the volume of the hydrofluoric acid with the mass fraction of 49 percent is 200mL, the front surface of the processed N-type silicon wafer is in a rounded pyramid structure, the reflectivity is increased by 0.4 percent, and the concentration of the phosphorus diffusion in the edge is increased from 1 multiplied by 1019cm-3Reduced to x 1017cm-3。
S211, carrying out pSC1 cleaning on the N-type silicon wafer by adopting potassium hydroxide and hydrogen peroxide in a winding-free plating tank type cleaning machine to remove additives and chemical components remained on the surface of the N-type silicon wafer, wherein the mass fraction of KOH is 45%, and the volume of KOH is 4L; h2O2The mass fraction of (2) is 27%, and the volume is 20L; the washing temperature was 65 ℃.
And step S212, washing the N-type silicon wafer for 120 seconds in a winding-free plating tank type cleaning machine.
And S213, performing acid cleaning on the N-type silicon wafer by adopting a hydrofluoric acid solution in a winding-removing plating tank type cleaning machine, wherein the hydrofluoric acid solution used for acid cleaning accounts for 8% in mass percent, the treatment time is 180 seconds, and then performing complete dehydration and drying treatment.
And S214, preparing an AlOx + SiNx passivation film on the front side of the N-type silicon wafer, and preparing the SiNx passivation film on the back side of the N-type silicon wafer.
And S215, performing screen printing and sintering on the passivation film to prepare an electrode, and testing and sorting to obtain the sample battery 1.
Example preparation of three sample cell 2
S301, carrying out texturing treatment on an N-type silicon wafer with the size of 182mm by adopting a potassium hydroxide solution with the mass fraction of about 1% in a groove type texturing cleaning machine, wherein 5.4L of KOH solution with the mass fraction of 45% is mixed with 2.2L of additive, the temperature of an alkali texturing process is 82 ℃, the process time is 420 seconds, the weight of the N-type silicon wafer after texturing is reduced by 0.42g, and the reflectivity is 8.7%.
Step S302, a boron diffusion process is carried out on the front surface of the textured N-type silicon wafer in a boron diffusion furnace tube to prepare a boron doped layer, a borosilicate glass layer is formed on the surface of the N-type silicon wafer, and the sheet resistance of the N-type silicon wafer after boron diffusion is 120 omega/□.
Step S303, performing single-side etching treatment on the back of the silicon wafer after boron diffusion in a chain type cleaning machine, and removing the borosilicate glass layer on the back, wherein the etching solution of the etching solution comprises 49% by mass of hydrofluoric acid, 69% by mass of nitric acid and deionized water, and the proportion of the etching solution is HF to HNO3DI is 1:7:1, and the reflectance of the back surface of the N-type silicon wafer after etching is 35%, and the weight is reduced by 0.35 g.
And S304, depositing a tunneling oxide layer and a polysilicon layer on the back surface of the N-type silicon wafer by LPCVD, wherein the thickness of the tunneling oxide layer is 1.5nm, and the thickness of the polysilicon layer is 120 nm.
And S305, injecting phosphorus into the polycrystalline silicon layer by adopting a phosphorus diffusion furnace on the back of the N-type silicon wafer to obtain a phosphorus-doped polycrystalline silicon layer so as to form a passivation contact structure on the back of the N-type silicon wafer.
Further, in step S304-305, a tunnel oxide layer is formed on the side surface of the N-type silicon wafer during the process of preparing the tunnel oxide layer, and a phosphosilicate glass layer, a phosphorus-doped polysilicon layer, and a phosphorus under-diffusion layer that is located on the side surface of the N-type silicon wafer and passes through the tunnel oxide layer are formed on the side surface of the N-type silicon wafer from outside to inside during the process of preparing the phosphorus-doped polysilicon layer.
And S306, removing the phosphorosilicate glass layers on the front surface and the side surface of the N-type silicon wafer by adopting a hydrofluoric acid solution with the mass fraction of 3% in a chain type cleaning machine based on the belt speed of 2 m/min.
And S307, removing the phosphorus-doped polycrystalline silicon layer wound and plated on the front surface and the side surface of the N-type silicon wafer by adopting a potassium hydroxide solution in a winding-removing plating tank type cleaning machine, wherein the mixing ratio of the potassium hydroxide solution with the mass fraction of 45% and an additive is 16LKOH solution and 3.5L of additive, the process temperature is 66 ℃, and the process time is 260 seconds.
And step S308, washing the N-type silicon wafer for 120 seconds in a winding-free plating tank type cleaning machine.
Step S309, a hydrofluoric acid solution is adopted in the winding-removing plating tank type cleaning machine to remove the borosilicate glass layer on the front surface of the N-type silicon wafer, the tunneling oxide layers on the front surface and the side surfaces and the phosphorosilicate glass layer on the back surface, wherein the hydrofluoric acid solution is prepared by adopting 49% by mass of hydrofluoric acid according to a volume ratio of 50%, and the mass fraction of the hydrofluoric acid in the prepared hydrofluoric acid solution is 17%.
Step S310, cleaning an N-type silicon wafer in a 360L tank body of a winding-removing plating tank type cleaning machine by adopting a mixed solution of ozone and hydrofluoric acid, wherein the cleaning time is 180 seconds, the mass fraction of the ozone is 6 per thousand, the volume of the hydrofluoric acid with the mass fraction of 49 percent is 500mL, the front surface of the processed N-type silicon wafer is in a rounded pyramid structure, the reflectivity is increased by 0.6 percent, and the concentration of the phosphorus diffusion in the edge is increased from 1 multiplied by 1019cm-3Reduced to x 1017cm-3。
S311, carrying out pSC1 cleaning on the N-type silicon wafer by adopting potassium hydroxide and hydrogen peroxide in a winding-free plating tank type cleaning machine to remove additives and chemical components remained on the surface of the N-type silicon wafer, wherein the mass fraction of KOH is 45%, and the volume of KOH is 4L; h2O2The mass fraction of (1) is 27%, and the volume is 20L; the washing temperature was 65 ℃.
And step S312, washing the N-type silicon wafer for 120 seconds in the winding-removing plating tank type cleaning machine.
And step S313, carrying out acid cleaning on the N-type silicon wafer by adopting a hydrofluoric acid solution in a winding-removing plating tank type cleaning machine, wherein the hydrofluoric acid solution used for acid cleaning accounts for 8% by mass, the treatment time is 180 seconds, and then completely dehydrating and drying.
Step S314, preparing an AlOx + SiNx passivation film on the front side of the N-type silicon wafer, and preparing a SiNx passivation film on the back side of the N-type silicon wafer.
And step S315, performing screen printing and sintering on the passive film to prepare an electrode, and then testing and sorting to obtain the sample battery 2.
In the embodiment of the present invention, the conventional battery, the sample battery 1, and the sample battery 2 prepared as above are further subjected to performance parameter tests, and the test results are shown in table 1 below:
TABLE 1
Figure BDA0003579527090000181
Figure BDA0003579527090000191
As shown in table 1, in the embodiment of the present invention, 10877 conventional batteries, 19876 sample batteries 1, 3200 sample batteries 2 were tested, wherein the leakage ratio of the conventional batteries is 5%, the leakage ratios of the sample batteries 1 and 2 are both 0, and Irev12 (reverse leakage current) of the sample batteries 1 and 2 are much lower than Irev12 of the conventional batteries, which shows that the problem of battery edge leakage is effectively solved by using the preparation method of the Topcon battery provided in the embodiment of the present invention; meanwhile, the Uoc (open circuit voltage) and FF (fill factor) of the sample battery 1 and the sample battery 2 are higher than those of the conventional battery, Rs (series resistance) is smaller than that of the conventional battery, Rsh (parallel resistance) is larger than that of the conventional battery, and Eta (conversion efficiency) and a short circuit (Isc) are approximately equivalent to those of the conventional battery. It can be seen that, compared with the conventional battery, the battery performance of the sample battery 1 and the sample battery 2 is improved in the test, the problem of edge electric leakage of the battery is effectively solved, and the yield of the battery is improved.
It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the embodiments are not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the embodiments of the application.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element identified by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
Through the description of the foregoing embodiments, it is clear to those skilled in the art that the method of the foregoing embodiments may be implemented by software plus a necessary general hardware platform, and certainly may also be implemented by hardware, but in many cases, the former is a better implementation. Based on such understanding, the technical solutions of the present invention or portions thereof contributing to the prior art may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the methods according to the embodiments of the present invention.
While the present invention has been described with reference to the particular illustrative embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications, equivalent arrangements, and equivalents thereof, which may be made by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A Topcon battery preparation method is characterized in that the method comprises the following steps:
providing a silicon wafer, wherein the silicon wafer comprises a front surface, a back surface opposite to the front surface and a side surface connecting the front surface and the back surface;
preparing a boron doped layer on the front surface, and sequentially preparing a tunneling oxide layer and a phosphorus doped polycrystalline silicon layer on the back surface, wherein a tunneling oxide layer which is plated on the side surface in a winding way is formed in the process of preparing the tunneling oxide layer, and a phosphosilicate glass layer which is plated on the side surface in a winding way and is outside the tunneling oxide layer from outside to inside, the phosphorus doped polycrystalline silicon layer and a phosphorus inner expanding layer which is positioned on the side surface and penetrates through the tunneling oxide layer are formed in the process of preparing the phosphorus doped polycrystalline silicon layer;
removing the phosphorus-silicon glass layer subjected to the winding plating, the phosphorus-doped polycrystalline silicon layer subjected to the winding plating and the tunneling oxide layer subjected to the winding plating;
and cleaning the silicon wafer by adopting a mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner expanding layer on the side surface.
2. The method as claimed in claim 1, wherein the mass fraction of the ozone in the mixed solution is 0.025-0.065 ‰.
3. The method as claimed in claim 1, wherein the mass fraction of the hydrofluoric acid in the mixed solution is 0.0027-0.0068 ‰.
4. The method as claimed in claim 1, wherein the washing time is 180-250 seconds.
5. The method of claim 1, wherein the removing the phosphosilicate glass layer, the phosphorus doped polysilicon layer, and the tunnel oxide layer comprises:
removing the phosphorosilicate glass layers wound and plated on the front surface and the side surfaces;
removing the phosphorus-doped polycrystalline silicon layer wound on the front surface and the side surface;
and removing the tunneling oxide layer wound and plated on the front surface and the side surface, the borosilicate glass layer wound and plated on the front surface, and the phosphorosilicate glass layer wound and plated on the back surface.
6. The method according to claim 1, wherein after the cleaning the silicon wafer with the mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner diffusion layer on the side surface, the method further comprises:
preparing a passivation film on the front side and the back side;
preparing electrodes on the front surface and the back surface.
7. The method according to claim 1, wherein before the cleaning the silicon wafer with the mixed solution of ozone and hydrofluoric acid to remove the phosphorus under-diffusion layer on the side surface, the method further comprises:
treating the silicon wafer by adopting potassium hydroxide and hydrogen peroxide;
after the silicon wafer is cleaned by adopting the mixed solution of ozone and hydrofluoric acid to remove the phosphorus inner expanding layer on the side surface, the method further comprises the following steps:
and dehydrating the silicon wafer.
8. A Topcon cell, characterized in that the Topcon cell is prepared by the Topcon cell preparation method of any of the preceding claims 1-7;
the front of the Topcon battery is in a rounded pyramid structure.
9. The cleaning machine is characterized by comprising a first cleaning tank, a second cleaning tank and a third cleaning tank which are sequentially arranged, wherein the first cleaning tank is provided with a potassium hydroxide solution, the second cleaning tank is provided with a hydrofluoric acid solution, and the third cleaning tank is provided with a mixed solution of ozone and hydrofluoric acid;
the decoiling tank washer is used in the Topcon cell manufacturing method of any of the preceding claims 1-7.
10. The decoiling bath washer according to claim 9, wherein the first washing tank is for removing the phosphorus doped polysilicon layer recoiled on the front side and the side surface;
the second cleaning tank is used for removing the tunneling oxide layer wound and plated on the front surface and the side surface, the borosilicate glass layer wound and plated on the front surface and the phosphorosilicate glass layer wound and plated on the back surface;
and the third cleaning tank is used for cleaning the silicon wafer by adopting a mixed solution of ozone and hydrofluoric acid so as to remove the phosphorus inner expanding layer on the side surface.
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CN115498071A (en) * 2022-09-20 2022-12-20 中威新能源(成都)有限公司 Preparation method of battery, battery and electronic product

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CN111883614A (en) * 2020-07-30 2020-11-03 常州时创能源股份有限公司 Edge isolation method and preparation method of passivated contact battery
CN113948611A (en) * 2021-10-15 2022-01-18 浙江爱旭太阳能科技有限公司 P-type IBC battery, preparation method and assembly thereof, and photovoltaic system

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CN111883614A (en) * 2020-07-30 2020-11-03 常州时创能源股份有限公司 Edge isolation method and preparation method of passivated contact battery
CN113948611A (en) * 2021-10-15 2022-01-18 浙江爱旭太阳能科技有限公司 P-type IBC battery, preparation method and assembly thereof, and photovoltaic system

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CN115498071B (en) * 2022-09-20 2024-05-14 通威太阳能（成都）有限公司 Battery preparation method, battery and electronic product

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