CN220710327U - Tunneling passivation contact battery structure - Google Patents

Abstract

The utility model discloses a tunneling passivation contact battery structure, which comprises a silicon substrate, wherein the front surface of the silicon substrate is sequentially provided with a front surface tunneling silicon oxide layer, a boron/phosphorus doped silicon carbide layer and a front surface anti-reflection layer from inside to outside, the front surface of the silicon substrate is also provided with a front surface electrode, a front surface boron/phosphorus doped polysilicon layer is also arranged between the front surface electrode and the boron/phosphorus doped silicon carbide layer, and the front surface electrode forms ohmic contact with the front surface boron/phosphorus doped polysilicon layer and the boron/phosphorus doped silicon carbide layer after passing through the front surface anti-reflection layer. According to the utility model, the tunneling contact structure formed by compounding the front tunneling silicon oxide layer, the boron/phosphorus doped silicon carbide layer and the front boron/phosphorus doped polysilicon layer is constructed on the front surface of the silicon substrate, so that the passivation effect of the front passivation structure can be improved, the conversion efficiency of the battery can be remarkably improved, the conversion efficiency is as high as 26.33%, and the novel structure is used for constructing a solar battery with excellent electrical performance.

Description

Tunneling passivation contact battery structure

Technical Field

The utility model belongs to the technical field of photovoltaics, and relates to a solar cell, in particular to a tunneling passivation contact cell.

Background

The tunneling passivation contact battery (TOPCon battery) is used as the next generation N-type main current battery technology of the subsequent PERC battery, the mass production battery efficiency is up to more than 25.5%, and compared with the PERC battery, the efficiency of the current main current TOPCon battery is greatly improved, but the single-sided TOPCon structure theoretical efficiency is 27.1% and is far lower than the double-sided TOPCon structure theoretical efficiency by 28.7%. In the existing double-sided TOPCon structure, tunneling passivation is carried out on the back surface by adopting tunneling silicon oxide and n-type doped polysilicon, and a boron diffusion mode is adopted on the front surface. Meanwhile, in the existing TOPCON battery preparation method, boron diffusion needs to be above 1000 ℃, and the defects of short service life, high preparation and maintenance costs and the like of a quartz tube caused by high energy consumption and high temperature and borosilicate glass produced are overcome; when the selective emitter technology is adopted for boron diffusion, a deep junction with high boron doping concentration is realized only in a metal region, and a non-metal region is still a shallow junction with low boron doping concentration, so that high recombination still exists in the non-metal region, and the battery efficiency is difficult to effectively improve. In addition, researchers have proposed a TOPCon battery with a tunneling contact structure constructed on the front surface, and a heavily doped polysilicon layer and a tunneling layer are disposed under a front electrode on the front surface of a silicon wafer, so as to construct a front tunneling contact structure, however, in the front tunneling contact structure, the front electrode is connected to the heavily doped polysilicon layer, the tunneling layer and the lightly doped layer, and the lightly doped layer still has larger transverse resistance defects through internal expansion, so that transverse resistance between metal electrodes is difficult to reduce, and the heavily doped polysilicon is difficult to thin, and the heavily doped polysilicon layer still has higher parasitic absorption, so that front light absorption efficiency is easy to reduce, and meanwhile, polysilicon passivation is still not performed in a non-metal area, so that recombination of the non-metal area is still very high, and the conversion efficiency of the TOPCon battery is still difficult to effectively improve due to the existence of the defects, and the photoelectric conversion efficiency is still lower than 25.5%. In addition, in the TOPCon battery, the following defects still exist when the conventional back etching technology is adopted to prepare the front tunneling contact structure: (a) The process window is narrow, the etching speed and the etching amount are difficult to control, the feasibility of mass production is low, for example, a polysilicon layer is firstly grown on the front surface, boron is diffused and then passes through a screen printing mask, then wet etching is carried out, the thickness of the polysilicon layer in a nonmetallic area is difficult to accurately control in the preparation mode, and the process window is narrow; (b) The formation of the heavily doped polysilicon layer still needs to be carried out under the high temperature condition, and has the defects of short service life of the quartz tube, high preparation and maintenance cost and the like caused by high energy consumption and high temperature of borosilicate glass; (c) boron doping concentration in the lightly doped layer is difficult to control effectively. Therefore, how to construct a passivation structure with excellent passivation effect on the front surface of the silicon wafer under the condition of lower temperature is of great significance for improving the conversion efficiency of the tunneling passivation contact battery, and realizing the mass production and large-scale application of the tunneling passivation contact battery with low cost and low energy consumption.

Disclosure of Invention

The utility model aims to solve the technical problem of providing a tunneling passivation contact battery structure with high conversion efficiency aiming at the defects in the prior art.

In order to solve the technical problems, the utility model adopts the following technical scheme.

A tunneling passivation contact battery structure comprises a silicon substrate, wherein the front surface of the silicon substrate is sequentially provided with a front tunneling silicon oxide layer, a boron doped silicon carbide layer and a front anti-reflection layer from inside to outside; a front electrode is further arranged on the front surface of the silicon substrate, and a front boron doped polysilicon layer is further arranged between the front electrode and the boron doped silicon carbide layer; and the front electrode passes through the front anti-reflection layer and forms ohmic contact with the front boron-doped polysilicon layer and the boron-doped silicon carbide layer.

According to the tunneling passivation contact battery structure, the back surface of the silicon substrate is sequentially provided with the back surface tunneling silicon oxide layer, the back surface phosphorus doped polysilicon layer and the back surface anti-reflection layer from inside to outside; and a back electrode is further arranged on the back of the silicon substrate, and the back electrode passes through the back anti-reflection layer and forms ohmic contact with the back phosphorus doped polysilicon layer.

According to the tunneling passivation contact battery structure, the thickness of the back tunneling silicon oxide layer is 0.5-3 nm; the thickness of the back phosphorus doped polysilicon layer is 30 nm-300 nm; the back anti-reflection layer is at least one of a silicon nitride film, a silicon oxynitride film and a silicon oxide film or a composite film formed by stacking the silicon nitride film, the silicon oxynitride film and the silicon oxide film; the thickness of the back anti-reflection layer is 60 nm-130 nm; the back electrode is a silver electrode.

According to the tunneling passivation contact battery structure, the thickness of the back tunneling silicon oxide layer is 1-2 nm; the thickness of the back phosphorus doped polysilicon layer is 60 nm-150 nm. More preferably, the thickness of the back phosphorus doped polysilicon layer is 60nm to 120nm.

The tunneling passivation contact battery structure is further improved, wherein the silicon substrate is an N-type silicon wafer; the resistivity of the silicon matrix is 0.3 omega cm-7 omega cm; the thickness of the front tunneling silicon oxide layer is 0.5 nm-3 nm; the thickness of the boron doped silicon carbide layer is 1 nm-100 nm; the doping concentration of the front boron doped polysilicon layer is 1E19cm ^-3 ～8E20cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the front boron doped polysilicon layer is 10 nm-300 nm; the front anti-reflection layer is at least one of a silicon nitride film, a silicon oxynitride film and a silicon oxide film or a composite film formed by stacking the silicon nitride film, the silicon oxynitride film and the silicon oxide film; the thickness of the front anti-reflection layer is 60 nm-130 nm; the front electrode is silver electrode and aluminumAt least one of an electrode and a silver aluminum electrode.

According to the tunneling passivation contact battery structure, the thickness of the front tunneling silicon oxide layer is 1-2 nm; the thickness of the boron doped silicon carbide layer is 3 nm-30 nm, more preferably, the thickness of the boron doped silicon carbide layer is 10 nm-20 nm; the thickness of the front side boron doped polysilicon layer is 30nm to 250nm, and more preferably, the thickness of the front side boron doped polysilicon layer is 100nm to 200nm.

In the utility model, the preparation method of the tunneling passivation contact battery structure comprises the following steps:

s1, double-sided texturing is carried out on a silicon substrate, specifically, alkaline solution is adopted to carry out double-sided texturing on the silicon substrate until a pyramid of 0.5-3 μm is formed on the surface, wherein the silicon substrate is an N-type silicon wafer, and the resistivity is 0.3-7Ω & cm.

S2, sequentially depositing a front tunneling silicon oxide layer, a boron doped amorphous silicon carbide layer, a front boron doped amorphous silicon layer and a silicon oxide mask on the front of the silicon substrate, wherein the steps are as follows: and sequentially depositing a front tunneling silicon oxide layer, a boron doped amorphous silicon carbide layer, a front boron doped amorphous silicon layer and a silicon oxide mask on the front side of the silicon substrate by adopting a PECVD method, wherein the thickness of the front tunneling silicon oxide layer is 0.5-3 nm, the boron doped amorphous silicon carbide layer is a single-layer boron doped amorphous silicon carbide film or a composite film formed by stacking at least two layers of boron doped amorphous silicon carbide films with different doping concentrations, the thickness of the boron doped amorphous silicon carbide layer is 1-100 nm, the thickness of the front boron doped amorphous silicon layer is 10-300 nm, and the thickness of the silicon oxide mask is 2-50 nm.

S3, pickling the back surface of the silicon substrate by adopting hydrofluoric acid solution, removing a silicon oxide mask on the back surface, and alkali-washing the back surface and the edge of the silicon substrate by adopting alkaline solution to remove the boron-doped amorphous silicon carbide layer and the front surface boron-doped amorphous silicon layer.

S4, sequentially depositing a back tunneling silicon oxide layer, a back phosphorus doped amorphous silicon layer and a silicon oxide mask on the back of the silicon substrate, wherein the steps are as follows: and sequentially depositing a back tunneling silicon oxide layer, a back phosphorus doped amorphous silicon layer and a silicon oxide mask on the back of the silicon substrate by adopting a PECVD method, wherein the thickness of the back tunneling silicon oxide layer is 0.5-3 nm, the back phosphorus doped amorphous silicon layer is a single-layer phosphorus doped amorphous silicon film or a composite film formed by stacking at least two layers of phosphorus doped amorphous silicon films with different doping concentrations, the thickness of the back phosphorus doped amorphous silicon layer is 30-300 nm, and the thickness of the silicon oxide mask is 2-50 nm.

S5, annealing the silicon substrate, wherein the temperature of the annealing treatment is 880-1000 ℃, more preferably 920-980 ℃, and after the annealing treatment is finished, tunneling passivation contact structures are formed on both sides of the silicon substrate.

S6, preparing an organic mask on a silicon oxide mask of a metallized area on the front side of the silicon substrate in a screen printing mode, wherein the width of the organic mask in the area where the thin grid lines are located is 50-150 mu m, so as to form a front electrode pattern, or performing graphical windowing on a non-metallized area on the front side of the silicon substrate by adopting laser, wherein the windowing width of the area where the thin grid lines are located in the windowing area is 50-150 mu m, so as to form the front electrode pattern.

And S7, etching the unmasked area on the front surface of the silicon substrate by adopting a wet etching mode until the boron doped silicon carbide layer is exposed, so as to form a poly-finger structure.

S8, cleaning the front surface and the back surface of the silicon substrate, and removing the mask.

And S9, respectively depositing a front anti-reflection layer and a back anti-reflection layer on the front and the back of the silicon substrate by adopting a PECVD method, printing a front electrode and a back electrode by adopting a screen printing mode, sintering and injecting to finish the preparation of the tunneling passivation contact battery.

The utility model also provides a tunneling passivation contact battery structure which comprises a silicon substrate, wherein the front surface of the silicon substrate is sequentially provided with a front tunneling silicon oxide layer, a phosphorus doped silicon carbide layer and a front anti-reflection layer from inside to outside; a front electrode is further arranged on the front surface of the silicon substrate, and a front phosphorus doped polysilicon layer is further arranged between the front electrode and the phosphorus doped silicon carbide layer; and the front electrode passes through the front anti-reflection layer and forms ohmic contact with the front phosphorus-doped polysilicon layer and the phosphorus-doped silicon carbide layer.

According to the tunneling passivation contact battery structure, the back surface of the silicon substrate is sequentially provided with the back surface tunneling silicon oxide layer, the back surface boron doped polysilicon layer and the back surface anti-reflection layer from inside to outside; and a back electrode is further arranged on the back of the silicon substrate, and the back electrode passes through the back anti-reflection layer and forms ohmic contact with the back boron doped polysilicon layer.

According to the tunneling passivation contact battery structure, the thickness of the back tunneling silicon oxide layer is 0.5-3 nm; the thickness of the back boron doped polysilicon layer is 50 nm-300 nm; the back anti-reflection layer is at least one of a silicon nitride film, a silicon oxynitride film and a silicon oxide film or a composite film formed by stacking the silicon nitride film, the silicon oxynitride film and the silicon oxide film; the thickness of the front anti-reflection layer is 60 nm-130 nm; the back electrode is a silver electrode.

According to the tunneling passivation contact battery structure, the thickness of the back tunneling silicon oxide layer is 1-2 nm; the thickness of the back boron doped polysilicon layer is 80 nm-250 nm.

The tunneling passivation contact battery structure is further improved, wherein the silicon substrate is an N-type silicon wafer; the thickness of the front tunneling silicon oxide layer is 0.5 nm-3 nm; the thickness of the phosphorus doped silicon carbide layer is 1 nm-100 nm; the thickness of the front phosphorus doped polysilicon layer is 10 nm-300 nm; the front anti-reflection layer is at least one of a silicon nitride film, a silicon oxynitride film and a silicon oxide film or a composite film formed by stacking the silicon nitride film, the silicon oxynitride film and the silicon oxide film; the thickness of the front anti-reflection layer is 60 nm-130 nm; the front electrode is at least one of a silver electrode, an aluminum electrode and a silver-aluminum electrode.

According to the tunneling passivation contact battery structure, the thickness of the front tunneling silicon oxide layer is 1-2 nm; the thickness of the phosphorus doped silicon carbide layer is 10 nm-30 nm; the thickness of the front phosphorus doped polysilicon layer is 30 nm-50 nm.

In this embodiment, the preparation method of the tunneling passivation contact battery structure includes the following steps:

(1) Double-sided texturing is carried out on the silicon substrate, and the method specifically comprises the following steps: and (3) performing double-sided texturing on the silicon substrate by adopting an alkaline solution until a pyramid of 0.5-3 mu m is formed on the surface, wherein the silicon substrate is an N-type silicon wafer, and the resistivity is 0.3-7Ω & cm.

(2) Sequentially depositing a back tunneling silicon oxide layer, a back boron doped amorphous silicon layer and a silicon oxide mask on the back of a silicon substrate, wherein the method specifically comprises the following steps: and sequentially depositing a back tunneling silicon oxide layer, a back boron doped amorphous silicon layer and a silicon oxide mask on the back of the silicon substrate by adopting a PECVD method, wherein the thickness of the back tunneling silicon oxide layer is 0.5-3 nm, the back boron doped amorphous silicon layer is a single-layer boron doped amorphous silicon film or a composite film formed by stacking at least two layers of boron doped amorphous silicon films with different doping concentrations, the thickness of the back boron doped amorphous silicon layer is 30-300 nm, and the thickness of the silicon oxide mask is 2-50 nm.

(3) And (3) carrying out acid washing on the front side of the silicon substrate by adopting hydrofluoric acid solution, removing a silicon oxide mask on the front side, and carrying out alkali washing on the front side and the edge of the silicon substrate by adopting alkaline solution, so as to remove the boron-doped amorphous silicon layer on the back side.

(4) A front tunneling silicon oxide layer, a phosphorus doped amorphous silicon carbide layer, a front phosphorus doped amorphous silicon layer and a silicon oxide mask are sequentially deposited on the front of a silicon substrate, and specifically: and sequentially depositing a front tunneling silicon oxide layer, a phosphorus doped amorphous silicon carbide layer, a front phosphorus doped amorphous silicon layer and a silicon oxide mask on the front side of the silicon substrate by adopting a PECVD method, wherein the thickness of the front tunneling silicon oxide layer is 0.5-3 nm, the phosphorus doped amorphous silicon carbide layer is a single-layer phosphorus doped amorphous silicon carbide film or a composite film formed by stacking at least two layers of phosphorus doped amorphous silicon carbide films with different doping concentrations, the thickness of the phosphorus doped amorphous silicon carbide layer is 1-100 nm, the thickness of the front phosphorus doped amorphous silicon layer is 10-300 nm, and the thickness of the silicon oxide mask is 2-50 nm.

(5) And (3) annealing the silicon substrate, wherein the temperature of the annealing treatment is 880-1000 ℃, more preferably, the temperature of the annealing treatment is 920-980 ℃, and after the annealing treatment is finished, tunneling passivation contact structures are formed on both sides of the silicon substrate.

(6) Preparing an organic mask on a silicon oxide mask of a metallized area on the front side of a silicon substrate in a screen printing mode, wherein the width of the organic mask in the area where the thin grid line is positioned is 50-150 mu m, so as to form a front electrode pattern, or performing graphical windowing on a non-metallized area on the front side of the silicon substrate by adopting laser, wherein the windowing width of the area where the thin grid line is positioned in the windowing area is 50-150 mu m, so as to form the front electrode pattern.

(7) And etching the unmasked area on the front surface of the silicon substrate by adopting a wet etching mode until the phosphorus doped silicon carbide layer is exposed, so as to form a poly-finger structure.

(8) And cleaning the front and back of the silicon substrate to remove the mask.

(9) And respectively depositing a front anti-reflection layer and a back anti-reflection layer on the front and the back of the silicon substrate by a PECVD method, printing a front electrode and a back electrode by a screen printing mode, sintering and injecting to finish the preparation of the tunneling passivation contact battery.

Compared with the prior art, the utility model has the advantages that:

aiming at the defects of large contact resistance, poor light absorption, poor passivation effect and the like of a front tunneling contact structure in the traditional tunneling passivation contact battery and low battery conversion efficiency caused by the defects, the utility model provides the tunneling passivation contact battery. The tunneling passivation contact battery has the advantages of high conversion efficiency and the like, is a novel solar battery with excellent electrical performance, and has important significance for realizing wide application of the solar battery.

Drawings

In order to make the objects, technical solutions and advantages of the embodiments of the present utility model more clear, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model.

Fig. 1 is a schematic diagram of a tunneling passivation contact cell in embodiment 1 of the present utility model.

Fig. 2 is a schematic diagram of a tunneling passivation contact cell in embodiment 2 of the present utility model.

Legend description:

1. a silicon substrate; 2. a front side tunneling silicon oxide layer; 31. a boron doped silicon carbide layer; 32. a phosphorus doped silicon carbide layer; 41. a front side boron doped polysilicon layer; 42. a front side phosphorus doped polysilicon layer; 5. a front side antireflection layer; 6. a front electrode; 7. a back tunneling silicon oxide layer; 81. a back phosphorus doped polysilicon layer; 82. a back boron doped polysilicon layer; 9. a back antireflection layer; 10. and a back electrode.

Detailed Description

The utility model is further described below in connection with the drawings and the specific preferred embodiments, but the scope of protection of the utility model is not limited thereby.

In the examples below, materials and instruments used are commercially available unless otherwise specified.

Example 1

As shown in fig. 1, a tunneling passivation contact battery structure comprises a silicon substrate 1, wherein the front surface of the silicon substrate 1 is sequentially provided with a front tunneling silicon oxide layer 2, a boron doped silicon carbide layer 31 and a front anti-reflection layer 5 from inside to outside, the front surface of the silicon substrate 1 is further provided with a front electrode 6, a front boron doped polysilicon layer 41 is further arranged between the front electrode 6 and the boron doped silicon carbide layer 31, and the front electrode 6 forms ohmic contact with the front boron doped polysilicon layer 41 and the boron doped silicon carbide layer 31 after passing through the front anti-reflection layer 5.

In this embodiment, the back surface of the silicon substrate 1 is sequentially provided with a back surface tunneling silicon oxide layer 7, a back surface phosphorus doped polysilicon layer 81 and a back surface antireflection layer 9 from inside to outside, the back surface of the silicon substrate 1 is further provided with a back surface electrode 10, the back surface electrode 10 passes through the back surface antireflection layer 9 and forms ohmic contact with the back surface phosphorus doped polysilicon layer 81, wherein the thickness of the back surface tunneling silicon oxide layer 7 is 2.2nm, the thickness of the back surface phosphorus doped polysilicon layer 81 is 110nm, the back surface antireflection layer is a composite film formed by stacking a silicon nitride film and a silicon oxynitride film, the thickness of the back surface antireflection layer 9 is 90nm, and the back surface electrode 10 is a silver electrode.

In this embodiment, the silicon substrate 1 is an N-type silicon wafer, the thickness of the front tunneling silicon oxide layer 2 is 1.5nm, the thickness of the boron doped silicon carbide layer 31 is 15nm, the thickness of the front boron doped polysilicon layer 41 is 200nm, the front anti-reflection layer 5 is a composite film formed by stacking a silicon nitride film and a silicon oxynitride film, the thickness of the front anti-reflection layer 5 is 90nm, and the front electrode 6 is a silver electrode.

The preparation method of the tunneling passivation contact battery structure in the embodiment comprises the following steps:

s1, double-sided texturing is carried out on a silicon substrate, and specifically: and (3) taking an N-type silicon wafer with the resistivity of 1-1.5 omega cm, and forming pyramid suede by alkali texturing, wherein the pyramid size is 0.5-1.5 mu m.

S2, sequentially depositing a front tunneling silicon oxide layer, a boron doped amorphous silicon carbide layer, a front boron doped amorphous silicon layer and a silicon oxide mask on the front of the silicon substrate, wherein the steps are as follows: growing a tunneling silicon oxide layer with the thickness of 1.5nm on the front surface in a PECVD mode, then depositing a layer of lightly doped amorphous silicon carbide with the thickness of 5nm and a layer of heavily doped amorphous silicon carbide with the thickness of 10nm, then depositing a layer of boron doped amorphous silicon with the thickness of 200nm, and finally depositing a layer of silicon oxide mask with the thickness of 8nm.

S3, adopting a single-sided chain type, using hydrofluoric acid solution to acid the back of the silicon substrate, washing off a back silicon oxide mask, performing alkali washing on the back and the edge of the silicon substrate, and removing amorphous silicon and amorphous silicon carbide which are slightly plated around the back and the edge through alkali etching.

S4, sequentially depositing a back tunneling silicon oxide layer, a back phosphorus doped amorphous silicon layer and a silicon oxide mask on the back of the silicon substrate, wherein the method specifically comprises the following steps: growing a tunneling silicon oxide layer with the thickness of 2.2nm on the back by a PECVD (plasma enhanced chemical vapor deposition) mode, then depositing an intrinsic amorphous silicon layer with the thickness of 10nm, and depositing a phosphorus doped amorphous silicon layer with the thickness of 100nm, and finally depositing a silicon oxide mask with the thickness of 8nm.

S5, annealing the silicon substrate, specifically: and (3) annealing in a high-temperature annealing furnace at 940 ℃, converting the doped amorphous silicon into doped polycrystalline silicon after annealing, converting the doped amorphous silicon carbide into doped polycrystalline silicon carbide, and simultaneously forming tunneling passivation contact structures on both sides.

S6, preparing an organic mask on a silicon oxide mask of a metallization area on the front side of the silicon substrate to form a front electrode pattern, wherein the method specifically comprises the following steps: and (3) printing an organic mask on the front silicon oxide mask by utilizing a screen printing mode, protecting the subsequent metallized region, wherein the width of the printed fine grid line mask is 80 mu m, and the non-metal region is not covered by the organic mask. In the step, laser is also used for carrying out graphical windowing on the non-metallized area on the front surface of the silicon substrate to form a front electrode pattern.

S7, etching treatment is carried out on a non-mask area (non-metalized area) on the front surface of the silicon substrate until the boron doped silicon carbide layer is exposed, specifically: the mask-free region is etched by a wet etching method, and the doped silicon carbide and the doped polysilicon are etched at different etching speeds by the etching solution, so that the etching speed of the doped silicon carbide is lower, the doped silicon carbide at the bottom layer forms a barrier layer, the etching solution can be prevented from etching inwards, and the doped polysilicon cannot be etched due to mask protection in the region with the mask, so that the poly-finger structure is formed.

S8, wet cleaning is carried out on the front side and the back side of the silicon substrate, and mask layers on the front side and the back side are removed;

and S9, respectively depositing a front antireflection layer and a back antireflection layer on the front and the back of the silicon substrate in a PECVD mode, wherein the front antireflection layer and the back antireflection layer are composite films formed by stacking silicon nitride films and silicon oxynitride films, the thickness is 90nm, printing a metal silver electrode on the front and the back in a screen printing mode, performing sintering treatment on the battery piece, enabling the metal electrode to form ohmic contact with a silicon wafer, and performing post-treatment on the battery piece in a light injection mode or an electric injection mode and the like to finish the preparation of the tunneling passivation contact battery.

S10, test sorting: and (5) testing, sorting and warehousing the battery pieces.

The performance test of the tunneling passivation contact battery prepared in this example was performed, and the electrical performance test results are shown in table 1.

Example 2

As shown in fig. 2, a tunneling passivation contact battery structure includes a silicon substrate 1, wherein the front surface of the silicon substrate 1 is sequentially provided with a front tunneling silicon oxide layer 2, a phosphorus doped silicon carbide layer 32 and a front anti-reflection layer 5 from inside to outside, the front surface of the silicon substrate 1 is further provided with a front electrode 6, a front phosphorus doped polysilicon layer 42 is further provided between the front electrode 6 and the phosphorus doped silicon carbide layer 32, and the front electrode 6 forms ohmic contact with the phosphorus doped silicon carbide layer 32 after passing through the front anti-reflection layer 5 and the front phosphorus doped polysilicon layer 42.

In this embodiment, the back surface of the silicon substrate 1 is sequentially provided with a back surface tunneling silicon oxide layer 7, a back surface boron doped polysilicon layer 82 and a back surface antireflection layer 9 from inside to outside, the back surface of the silicon substrate 1 is further provided with a back surface electrode 10, the back surface electrode 10 passes through the back surface antireflection layer 9 and forms ohmic contact with the back surface boron doped polysilicon layer 82, wherein the thickness of the back surface tunneling silicon oxide layer 7 is 1.8nm, the thickness of the back surface boron doped polysilicon layer 82 is 160nm, the back surface antireflection layer is a composite film formed by stacking a silicon nitride film, a silicon oxynitride film and a silicon oxide film, the thickness of the back surface antireflection layer 9 is 100nm, and the back surface electrode 10 is a silver electrode.

In this embodiment, the silicon substrate 1 is an N-type silicon wafer, the resistivity is 1 Ω·cm to 1.5 Ω·cm, the thickness of the front tunneling silicon oxide layer 2 is 2.3nm, the thickness of the phosphorus doped silicon carbide layer 32 is 25nm, the thickness of the front phosphorus doped polysilicon layer 42 is 100nm, the front antireflection layer 5 is a composite film formed by stacking a silicon nitride film, a silicon oxynitride film and a silicon oxide film, the thickness of the front antireflection layer 5 is 100nm, and the front electrode 6 is a silver electrode.

The preparation method of the tunneling passivation contact battery structure in the embodiment comprises the following steps:

(1) Double-sided texturing is carried out on the silicon substrate, and the method specifically comprises the following steps: and (3) taking an N-type silicon wafer with the resistivity of 1-1.5 omega cm, and forming pyramid suede by alkali texturing, wherein the pyramid size is 0.5-1.5 mu m.

(2) Sequentially depositing a back tunneling silicon oxide layer, a back boron doped amorphous silicon layer and a silicon oxide mask on the back of a silicon substrate, wherein the method specifically comprises the following steps: and growing a tunneling silicon oxide layer with the thickness of 1.8nm on the back by a PECVD (plasma enhanced chemical vapor deposition) mode, then depositing an intrinsic amorphous silicon layer with the thickness of 10nm, low-boron-doped amorphous silicon layer with the thickness of 50nm, high-boron-doped amorphous silicon layer with the thickness of 150nm, and finally depositing a silicon oxide mask with the thickness of 10nm.

(3) And (3) adopting a single-sided chain type, washing the front side of the silicon substrate by using hydrofluoric acid solution, washing a front side silicon oxide mask, performing alkali washing on the front side and the edge of the silicon substrate, and removing amorphous silicon and amorphous silicon carbide slightly subjected to front side and edge coiling plating by alkali etching.

(4) A front tunneling silicon oxide layer, a phosphorus doped amorphous silicon carbide layer, a front phosphorus doped amorphous silicon layer and a silicon oxide mask are sequentially deposited on the front of a silicon substrate, and specifically: growing a tunneling silicon oxide layer with the thickness of 2.3nm on the front surface in a PECVD mode, then depositing an intrinsic amorphous silicon carbide film with the thickness of 5nm, and then depositing a doped amorphous silicon carbide film with the thickness of 20nm, further depositing a doped amorphous silicon film with the thickness of 30nm and the low phosphorus doping concentration, and depositing a doped amorphous silicon film with the thickness of 70nm and the high phosphorus doping concentration, and finally depositing a silicon oxide mask with the mask thickness of 10nm.

(5) Annealing treatment is carried out on the silicon substrate, specifically: and (3) annealing in a high-temperature annealing furnace at 950 ℃, converting the doped amorphous silicon into doped polycrystalline silicon after annealing, converting the doped amorphous silicon carbide into doped polycrystalline silicon carbide, and simultaneously forming tunneling passivation contact structures on both sides.

(6) Patterning and windowing are carried out on a non-metalized area on the front side of the silicon substrate to form a front electrode pattern, specifically: and (3) carrying out windowing treatment on the silicon oxide mask of the non-metal region in a laser windowing mode, and reserving the silicon oxide mask of the outermost layer for the subsequent metalized region, wherein the width of the non-windowed thin grid line mask is 70 mu m, and the formed pattern is similar to the subsequent grid line pattern. In this step, an organic mask may also be prepared on the silicon oxide mask in the metallized region on the front side of the silicon substrate to form a front electrode pattern.

(7) Etching is carried out on a non-mask area (non-metallized area) on the front surface of the silicon substrate until the phosphorus doped silicon carbide layer is exposed, specifically: the mask-free region is etched by a wet etching method, and the doped silicon carbide and the doped polysilicon are etched at different etching speeds by the etching solution, so that the etching speed of the doped silicon carbide is lower, the doped silicon carbide at the bottom layer forms a barrier layer, the etching solution can be prevented from etching inwards, and the doped polysilicon cannot be etched due to mask protection in the region with the mask, so that the poly-finger structure is formed.

(8) And wet cleaning is carried out on the front and the back of the silicon substrate, and the mask layers on the front and the back are removed.

(9) And respectively depositing a front antireflection layer and a back antireflection layer on the front and the back of the silicon substrate, wherein the front antireflection layer and the back antireflection layer are composite films formed by stacking a silicon nitride film, a silicon oxynitride film and a silicon oxide film, the thickness is 100nm, a metal silver electrode is printed on the front and the back by a screen printing mode, the battery piece is subjected to sintering treatment, ohmic contact is formed between the metal electrode and a silicon wafer, and then the battery piece is subjected to post-treatment by means of light injection or electric injection and the like, so that the preparation of the tunneling passivation contact battery is completed.

(10) Test sorting: and (5) testing, sorting and warehousing the battery pieces.

The performance test of the tunneling passivation contact battery prepared in this example was performed, and the electrical performance test results are shown in table 1.

Table 1 electrical performance data for tunneling passivation contact cells in examples 1 and 2 of the present utility model

As shown in Table 1, compared with the conventional tunneling passivation contact battery, the conversion efficiency of the tunneling passivation contact battery prepared by the method is remarkably improved by 0.55%. Therefore, the tunneling passivation contact battery structure can improve the conversion efficiency, can be used for constructing novel solar batteries with excellent electrical properties, and has important significance for realizing large-scale popularization and application of the tunneling passivation contact battery.

The above description is only of the preferred embodiment of the present utility model, and is not intended to limit the present utility model in any way. While the utility model has been described in terms of preferred embodiments, it is not intended to be limiting. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present utility model or equivalent embodiments using the method and technical solution disclosed above without departing from the spirit and technical solution of the present utility model. Therefore, any simple modification, equivalent substitution, equivalent variation and modification of the above embodiments according to the technical substance of the present utility model, which do not depart from the technical solution of the present utility model, still fall within the scope of the technical solution of the present utility model.

Claims (8)

1. The tunneling passivation contact battery structure is characterized by comprising a silicon substrate, wherein the front surface of the silicon substrate is sequentially provided with a front tunneling silicon oxide layer, a boron doped silicon carbide layer and a front anti-reflection layer from inside to outside; a front electrode is further arranged on the front surface of the silicon substrate, and a front boron doped polysilicon layer is further arranged between the front electrode and the boron doped silicon carbide layer; and the front electrode passes through the front anti-reflection layer and forms ohmic contact with the front boron-doped polysilicon layer and the boron-doped silicon carbide layer.

2. The tunneling passivation contact cell structure of claim 1, wherein the back surface of the silicon substrate is, in order from inside to outside, a back surface tunneling silicon oxide layer, a back surface phosphorus doped polysilicon layer, and a back surface anti-reflection layer; and a back electrode is further arranged on the back of the silicon substrate, and the back electrode passes through the back anti-reflection layer and forms ohmic contact with the back phosphorus doped polysilicon layer.

3. The tunneling passivation contact cell structure of claim 2, wherein the thickness of the back tunneling silicon oxide layer is 0.5nm to 3nm; the thickness of the back phosphorus doped polysilicon layer is 30 nm-300 nm; the back anti-reflection layer is at least one of a silicon nitride film, a silicon oxynitride film and a silicon oxide film or a composite film formed by stacking the silicon nitride film, the silicon oxynitride film and the silicon oxide film; the thickness of the back anti-reflection layer is 60 nm-130 nm; the back electrode is a silver electrode.

4. The tunneling passivation contact cell structure of any of claims 1-3, wherein the silicon substrate is an N-type silicon wafer; the thickness of the front tunneling silicon oxide layer is 0.5 nm-3 nm; the thickness of the boron doped silicon carbide layer is 1 nm-100 nm; the thickness of the front boron doped polysilicon layer is 10 nm-300 nm; the front anti-reflection layer is at least one of a silicon nitride film, a silicon oxynitride film and a silicon oxide film or a composite film formed by stacking the silicon nitride film, the silicon oxynitride film and the silicon oxide film; the thickness of the front anti-reflection layer is 60 nm-130 nm; the front electrode is at least one of a silver electrode, an aluminum electrode and a silver-aluminum electrode.

5. The tunneling passivation contact battery structure is characterized by comprising a silicon substrate, wherein the front surface of the silicon substrate is sequentially provided with a front tunneling silicon oxide layer, a phosphorus doped silicon carbide layer and a front anti-reflection layer from inside to outside; a front electrode is further arranged on the front surface of the silicon substrate, and a front phosphorus doped polysilicon layer is further arranged between the front electrode and the phosphorus doped silicon carbide layer; and the front electrode passes through the front anti-reflection layer and forms ohmic contact with the front phosphorus-doped polysilicon layer and the phosphorus-doped silicon carbide layer.

6. The tunneling passivation contact cell structure of claim 5, wherein the back surface of the silicon substrate is, in order from inside to outside, a back surface tunneling silicon oxide layer, a back surface boron doped polysilicon layer, and a back surface anti-reflection layer; and a back electrode is further arranged on the back of the silicon substrate, and the back electrode passes through the back anti-reflection layer and forms ohmic contact with the back boron doped polysilicon layer.

7. The tunneling passivation contact cell structure of claim 6, wherein the thickness of the back tunneling silicon oxide layer is 0.5 nm-3 nm; the thickness of the back boron doped polysilicon layer is 50 nm-300 nm; the back anti-reflection layer is at least one of a silicon nitride film, a silicon oxynitride film and a silicon oxide film or a composite film formed by stacking the silicon nitride film, the silicon oxynitride film and the silicon oxide film; the thickness of the back anti-reflection layer is 60 nm-130 nm; the back electrode is a silver electrode.

8. The tunneling passivation contact cell structure of any of claims 5-7, wherein the silicon substrate is an N-type silicon wafer; the thickness of the front tunneling silicon oxide layer is 0.5 nm-3 nm; the thickness of the phosphorus doped silicon carbide layer is 1 nm-100 nm; the thickness of the front phosphorus doped polysilicon layer is 10 nm-300 nm; the front anti-reflection layer is at least one of a silicon nitride film, a silicon oxynitride film and a silicon oxide film or a composite film formed by stacking the silicon nitride film, the silicon oxynitride film and the silicon oxide film; the thickness of the front anti-reflection layer is 60 nm-130 nm; the front electrode is at least one of a silver electrode, an aluminum electrode and a silver-aluminum electrode.