CN115101620B - P-type HBC battery structure and preparation method thereof - Google Patents

P-type HBC battery structure and preparation method thereof Download PDF

Info

Publication number
CN115101620B
CN115101620B CN202210896409.0A CN202210896409A CN115101620B CN 115101620 B CN115101620 B CN 115101620B CN 202210896409 A CN202210896409 A CN 202210896409A CN 115101620 B CN115101620 B CN 115101620B
Authority
CN
China
Prior art keywords
type
silicon wafer
amorphous silicon
layer
battery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202210896409.0A
Other languages
Chinese (zh)
Other versions
CN115101620A (en
Inventor
杨飞
倪志春
连维飞
刘松民
张景洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhejiang Aikang New Energy Technology Co ltd
Jiangsu Akcome Energy Research Institute Co ltd
Original Assignee
Zhejiang Aikang New Energy Technology Co ltd
Jiangsu Akcome Energy Research Institute Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhejiang Aikang New Energy Technology Co ltd, Jiangsu Akcome Energy Research Institute Co ltd filed Critical Zhejiang Aikang New Energy Technology Co ltd
Priority to CN202210896409.0A priority Critical patent/CN115101620B/en
Publication of CN115101620A publication Critical patent/CN115101620A/en
Application granted granted Critical
Publication of CN115101620B publication Critical patent/CN115101620B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/074—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a heterojunction with an element of Group IV of the Periodic Table, e.g. ITO/Si, GaAs/Si or CdTe/Si solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022433—Particular geometry of the grid contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/208—Particular post-treatment of the devices, e.g. annealing, short-circuit elimination
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Sustainable Development (AREA)
  • Sustainable Energy (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Photovoltaic Devices (AREA)

Abstract

The invention relates to a P-type HBC battery structure and a preparation method thereof, the structure comprises a P-type silicon substrate, wherein a P-type heavily doped region is arranged in the middle of the back surface of the P-type silicon substrate, amorphous silicon intrinsic layers are arranged on the front surface and the back surface of the P-type silicon substrate, an N-type amorphous silicon doped layer is arranged on the outer side of the amorphous silicon intrinsic layer on the back surface of the P-type silicon substrate, and SiN is arranged on the outer side of the amorphous silicon intrinsic layer on the front surface of the P-type silicon substrate X An antireflection film; a TCO conductive film is arranged on the outer side of the N-type amorphous silicon doped layer; the outer side of the TCO conductive film is provided with a plurality of N-type Ag electrodes, the TCO conductive film is provided with a notch, the depth of the notch penetrates through the TCO conductive film and the N-type amorphous silicon doped layer, the bottom of the P-type heavily doped region is exposed, and the bottom of the P-type heavily doped region is connected with the P-type Ag electrodes. The invention realizes the local P++ layer by using the aluminum paste presintering mode, realizes the heat treatment and gettering treatment of the silicon wafer, and improves the internal quality of the silicon wafer.

Description

P-type HBC battery structure and preparation method thereof
Technical Field
The invention relates to the technical field of photovoltaic high-efficiency batteries, in particular to a P-type HBC battery structure and a preparation method thereof.
Background
The interdigital back contact heterojunction monocrystalline silicon Solar Cell (Interdigitated Back Contact Silicon Heterojunction Solar Cell, HBC Solar Cell for short) has the advantages of both an interdigital back contact Solar Cell (Interdigitated back contact Solar Cell, IBC Solar Cell for short) and a heterojunction Solar Cell with a thin intrinsic layer (Heterojunction with Intrinsic Thin-layer Solar Cell, HIT Solar Cell for short), removes a front surface metal electrode, reduces shading loss, obtains larger short-circuit current, and greatly reduces interface states, reduces surface recombination and improves open-circuit voltage by inserting a layer of high-quality intrinsic amorphous silicon passivation layer between heavily doped amorphous silicon and crystalline silicon. The HBC cell combines the advantages of the IBC cell and the HJT cell with the following advantages: zero grid line shielding on the front surface of the battery is avoided, current loss caused by grid line shielding is avoided, and high short-circuit current is achieved; the metal electrode is positioned on the back surface of the battery, and the metal electrode of the battery can be optimized without being limited by optical shielding, so that the serial resistance increase caused by metallization is greatly reduced.
The HBC technology combined with the IBC and HJ technology can further improve the battery efficiency, and the structure is shown in fig. 1, and the process steps are as follows. The front surface of the cell structure of the HBC is provided with an ARC (anti-reflection coating) and a front surface field FSF (FSF), the back surface of the n-c-Si material is provided with a buffer layer i-a-Si: H material, a doped amorphous silicon layer is arranged below the buffer layer and distributed in an interdigital mode, wherein p-a-Si: H is taken as an emitter, n-a-Si: H is taken as a back surface field BSF, and the widths of the buffer layer i-a-Si: H are respectively Wemit and W BSF . Finally, a metal contact layer is covered on the emitter and the BSF, and the emitter and the back surface field are isolated by a dielectric layer. The HBC utilizes the excellent surface passivation performance of amorphous silicon, combines the structural advantage that the front surface of the IBC structure is free from metal shielding, and adopts the same device structure.
HBC cells represent the highest efficiency level of crystalline silicon cells, but HBC has been limited to higher mass production costs and has evolved more curvingly. The HBC battery has the advantages of both the IBC battery and the HJT battery, and simultaneously maintains the difficulty of the respective production processes of the IBC battery and the HJT battery. The key problem of the IBC cell process is how to prepare P-regions and N-regions in an interdigitated spaced arrangement on the back of the cell and form metallization contacts and gate lines thereon, respectively. The diffusion of the common solar cell only needs to form an N-type diffusion region on a P-type substrate, and the IBC cell has phosphorus diffusion forming a back N region (BSF) and boron diffusion forming a PN junction, namely P-type doping is carried out on the N-type substrate, and meanwhile, because the positive electrode and the negative electrode of the IBC cell are both positioned on the back surface, a strict electrode isolation process is needed during the cell manufacturing. The HJT battery process has the key problems that firstly, the requirement on the silicon wafer is relatively high, the HJT battery process is a low-temperature process, no high-temperature heat treatment and impurity absorption process are adopted, the defects of oxygen donors, new donors and the like of the silicon wafer cannot be eliminated, and the impurity content of the silicon wafer is high, so that the battery efficiency is affected; in addition, the high-concentration P-type amorphous silicon thin film is very difficult to manufacture due to the low solid solubility of boron element in silicon.
The structure of the conventional HBC battery is shown in figure 1, the preparation of the interdigital PN region does not bypass the mask-grooving-depositing-etching processes, however, the battery has narrow process window and extremely high requirements on process cleanliness when being used for preparing intrinsic and doped amorphous silicon, and the HBC battery has the defects of high investment equipment, long working procedure and high investment cost due to the reasons of the above.
Disclosure of Invention
The invention aims to overcome the defects and provide a P-type HBC battery structure and a preparation method thereof, so that a TCO conductive film obtains better transmittance and conductivity and improves the performance of a heterojunction solar battery.
The purpose of the invention is realized in the following way:
a P-type HBC battery structure comprises a P-type silicon substrate, wherein a P-type heavily doped region is arranged in the middle of the back surface of the P-type silicon substrate, amorphous silicon intrinsic layers are arranged on the front surface and the back surface of the P-type silicon substrate, an N-type amorphous silicon doped layer is arranged on the outer side of the amorphous silicon intrinsic layer on the back surface of the P-type silicon substrate, and SiN is arranged on the outer side of the amorphous silicon intrinsic layer on the front surface of the P-type silicon substrate X An antireflection film; a TCO conductive film is arranged on the outer side of the N-type amorphous silicon doped layer; the outer side of the TCO conductive film is provided with a plurality of N-type Ag electrodes, the TCO conductive film is provided with a notch, the depth of the notch penetrates through the TCO conductive film and the N-type amorphous silicon doped layer, the bottom of the P-type heavily doped region is exposed, the bottom of the P-type heavily doped region is connected with the P-type Ag electrodes, and ohmic contact is realized by using P-type low-temperature silver paste and aluminum paste of the P-type heavily doped region.
Further, the width of the P-type heavily doped region is 20-60 micrometers, and the height is 1-20 micrometers.
Further, the N-type Ag electrode is connected with the TCO conductive film by using N-type low-temperature silver paste.
Further, the width of the notch is larger than that of the P-type heavily doped region.
The preparation method of the P-type HBC battery structure comprises the following steps:
step one, cleaning a silicon wafer:
selecting a P-type silicon wafer, and performing texturing and cleaning treatment on the P-type silicon wafer; the silicon wafer is subjected to high-efficiency cleaning and then is textured, and a textured surface layer is formed on the front surface of the silicon wafer;
step two, printing aluminum paste:
printing on the back surface of the silicon wafer on one side, wherein the sizing agent is aluminum paste, and the printing position is a P-type heavily doped region of the battery;
step three, sintering at high temperature:
placing the printed silicon wafer into a furnace body, sintering the silicon wafer in the furnace body, and forming ohmic contact between aluminum paste and a silicon wafer substrate to form a P-type heavily doped region;
step four, cleaning the silicon wafer:
the sintered silicon wafer is efficiently cleaned, the sintered aluminum paste still leaks on the surface of the silicon wafer, and the thickness of the aluminum paste ensures that the aluminum paste can form contact with low-temperature silver paste;
fifthly, coating the double-sided intrinsic layer and the N-type amorphous silicon doped layer:
respectively plating an intrinsic amorphous silicon film on the front and back surfaces of the battery piece through PECVD technology to form an amorphous silicon intrinsic layer; plating an N-type amorphous silicon doped layer on the back surface of the battery piece by PECVD technology;
step six, preparing an antireflection film:
SiN is plated on the front surface of the battery piece by PECVD method X An antireflection film;
step seven, depositing a TCO conductive film:
plating a transparent TCO conductive film on the battery piece by adopting a PVD equipment technology;
step eight, laser grooving:
laser grooving is carried out at the bottom of the P-type heavily doped region on the back of the battery piece, the TCO conductive film, the N-type amorphous silicon doped layer and the amorphous silicon intrinsic layer are laser ablated, and the aluminum paste is exposed on the surface of the silicon wafer;
step nine, electrode printing and sintering:
printing P-type silver paste and N-type silver paste on the back of the battery respectively through a screen printing process, wherein the P-type and N-type pastes are low-temperature silver paste; after low-temperature sintering, the N-type low-temperature silver paste is connected with the TCO film layer; after low-temperature sintering, ohmic contact is realized by the P-type low-temperature silver paste and the aluminum paste;
step ten, sorting test:
the required battery pieces are selected through sorting tests.
Further, in the second step, the width of the aluminum paste printing paste is 20-60 micrometers, and the height is 1-20 micrometers.
Further, the sintering temperature in the furnace body in the third step is 300-900 ℃.
Further, in the fifth step, the thickness of the amorphous silicon intrinsic layer is 5-10 nm, and the thickness of the N-type amorphous silicon doped layer is 5-15 nm.
Further, the width of the laser kerf in step eight is 100 microns.
Further, in the eighth step, the aluminum paste is exposed on the surface of the silicon wafer to a height of 5 micrometers.
Compared with the prior art, the invention has the beneficial effects that:
the invention realizes a local P++ layer by using an aluminum paste presintering mode, realizes the heat treatment and gettering treatment of the silicon wafer, and solves the problem of the internal quality of the silicon wafer; solves the difficult problem of manufacturing the heavily doped P-type amorphous silicon in the HBC.
The invention prepares the P area and the N area which are arranged at intervals in an interdigital way by utilizing the laser slotting technology, avoids the complex process flows of mask, slotting, deposition, etching and the like, solves the most complex PN manufacturing process of the HBC, greatly optimizes the process steps of the HBC battery and reduces the manufacturing cost of the battery.
Drawings
Fig. 1 is a schematic structural diagram of a conventional HBC cell.
Fig. 2 is a schematic structural diagram of a P-type HBC cell of the present invention.
Wherein:
p-type silicon substrate 1, P-type heavily doped region 2, amorphous silicon intrinsic layer 3, N-type amorphous silicon doped layer 4, siN X An anti-reflection film 5, a TCO conductive film 6, an N-type Ag electrode 7 and a P-type Ag electrode 8.
Detailed Description
Example 1:
referring to fig. 2, the P-type HBC cell structure according to the present invention includes a P-type silicon substrate 1, wherein a P-type heavily doped region 2 is disposed in the middle of the back surface of the P-type silicon substrate 1, and the width of the P-type heavily doped region 2 is 20-60 micrometers, and the height is 1-20 micrometers.
The front and back of the P-type silicon substrate 1 are respectively provided with an amorphous silicon intrinsic layer 3, the outer side of the amorphous silicon intrinsic layer 3 on the back of the P-type silicon substrate 1 is provided with an N-type amorphous silicon doped layer 4, and the outer side of the amorphous silicon intrinsic layer 3 on the front of the P-type silicon substrate 1 is provided with SiN X An antireflection film 5; the outside of the N-type amorphous silicon doped layer 4 is provided with a TCO conductive film 6.
The outer side of the TCO conductive film 6 is provided with a plurality of N-type Ag electrodes 7, and the N-type low-temperature silver paste is used for forming connection with the TCO conductive film 6.
The TCO conducting film 6 is provided with a notch, the width of the notch is 100 micrometers, the depth of the notch penetrates through the TCO conducting film 6 and the N-type amorphous silicon doped layer 4, the bottom of the P-type heavily doped region 2 is exposed, the bottom of the P-type heavily doped region 2 is connected with the P-type Ag electrode 8, and ohmic contact is realized by using P-type low-temperature silver paste and aluminum paste of the P-type heavily doped region 2.
The invention relates to a preparation method of a P-type HBC battery structure, which comprises the following steps:
s1, cleaning silicon wafer
Selecting a P-type silicon wafer with the thickness of 130 micrometers, and performing texturing and cleaning treatment on the P-type silicon wafer; the silicon wafer is subjected to a cleaning process, so that organic dirt, metal impurities and a surface damage layer on the surface of the silicon wafer are removed; the silicon wafer is subjected to high-efficiency cleaning and then is textured, and a textured surface layer is formed on the front surface of the silicon wafer;
s2, printing aluminum paste
Printing on the back surface of the silicon wafer on one side, wherein the sizing agent is aluminum paste, the printing position is a P-type heavily doped region of the battery, the width of the aluminum paste printing sizing agent is 30 micrometers, and the height is 5 micrometers;
s3, sintering at high temperature
Placing the printed silicon wafer into a furnace body, sintering the silicon wafer in the furnace body at 300-900 ℃, and forming ohmic contact between aluminum paste and a silicon wafer substrate to form a P-type heavily doped region; the width of the P-type heavily doped region is 20-60 micrometers, and the height is 1-20 micrometers;
s4, cleaning silicon wafers
The sintered silicon wafer is efficiently cleaned, organic dirt and other impurities on the surface of the silicon wafer are removed, and the two surfaces of the silicon wafer form clean surfaces; the sintered aluminum paste still leaks on the surface of the silicon wafer, and the thickness of the aluminum paste ensures that the aluminum paste can form contact with low-temperature silver paste;
s5, coating film of double-sided intrinsic layer and N-type amorphous silicon doped layer
Respectively plating an intrinsic amorphous silicon film on the front and back surfaces of the battery piece through PECVD technology to form an amorphous silicon intrinsic layer, wherein the thickness of the amorphous silicon intrinsic layer is 5nm;
plating an N-type amorphous silicon doped layer on the back surface of the battery piece by PECVD technology, wherein the thickness of the N-type amorphous silicon doped layer is 10nm;
s6, preparation of antireflection film
SiN is plated on the front surface of the battery piece by PECVD method X An antireflection film;
s7, TCO conductive film deposition
Plating a transparent TCO conductive film on the battery piece by adopting a PVD equipment technology;
s8, laser grooving
The back of the battery piece is grooved by laser, and the width of the grooved is 100 micrometers;
slotting an aluminum paste spreading area (the bottom of a P-type heavily doped area) of the silicon wafer by adopting laser, and laser ablating the TCO conductive film, the N-type amorphous silicon doped layer and the amorphous silicon intrinsic layer to expose the aluminum paste on the surface of the silicon wafer, wherein the height of the aluminum paste is 5 microns; the back of the battery piece is grooved by laser, so that the isolation of the P area and the N area is realized;
s9, electrode printing
Printing P-type silver paste and N-type silver paste on the back of the battery respectively through a screen printing process, wherein the P-type silver paste and the N-type silver paste are low-temperature silver paste to form a P-type Ag electrode and an N-type Ag electrode;
s10, sintering
After low-temperature sintering, the N-type low-temperature silver paste is connected with the TCO film layer; after low-temperature sintering, ohmic contact is realized by the P-type low-temperature silver paste and the aluminum paste;
s11, sorting test
The required battery piece is selected through sorting test, the efficiency of the battery piece is tested, voc reaches 745mV, and the conversion efficiency of the battery is as high as 25.15%.
Comparative example 1:
comparative example 1 preparation method of HBC cell conventional in the prior art
S1, cleaning silicon wafer
Selecting a P-type silicon wafer with the thickness of 130 micrometers, and performing texturing and cleaning treatment on the P-type silicon wafer; the silicon wafer is subjected to a cleaning process, so that organic dirt, metal impurities and a surface damage layer on the surface of the silicon wafer are removed; the silicon wafer is subjected to high-efficiency cleaning and then is textured, and a textured surface layer is formed on the front surface of the silicon wafer;
s2, coating film of double-sided intrinsic layer and N-type amorphous silicon doped layer
Respectively plating an intrinsic amorphous silicon film on the front and back surfaces of the battery piece through PECVD technology to form an amorphous silicon intrinsic layer, wherein the thickness of the amorphous silicon intrinsic layer is 5nm;
plating an N-type amorphous silicon doped layer on the back surface of the battery piece by PECVD technology, wherein the thickness of the N-type amorphous silicon doped layer is 10nm;
s3, preparation of back PN region
Preparing a back PN region through mask-slotting-depositing-etching and other processes;
s4, preparation of antireflection film
Plating a SiNX antireflection film on the front surface of the battery piece by a PECVD method;
s5, TCO conductive film deposition
Plating a transparent TCO conductive film on the battery piece by adopting a PVD equipment technology;
s6, sintering the electrode printing electrode
Silver paste is printed on the back of the battery through a screen printing process, and then the battery is sintered at a low temperature and connected with the TCO film layer to realize ohmic contact;
s7, sorting test
Through test, the efficiency of the battery piece is 743mV, the Isc is 40.49mA/cm < 2 >, the FF 84.64% and the conversion efficiency of the battery is up to 25.46%.
The electrical performance comparison of example 1 and comparative example 1 is shown in the following table, and is mainly represented by the open circuit voltage Voc, the short circuit current Isc and the fill factor FF, the improvement of the electrical performance parameters of the solar cell of the present invention can be obtained.
The foregoing is merely a specific application example of the present invention, and the protection scope of the present invention is not limited in any way. All technical schemes formed by equivalent transformation or equivalent substitution fall within the protection scope of the invention.

Claims (6)

1. The preparation method of the P-type HBC battery structure is characterized by comprising the following steps:
step one, cleaning a silicon wafer: selecting a P-type silicon wafer, and performing texturing and cleaning treatment on the P-type silicon wafer; the silicon wafer is subjected to high-efficiency cleaning and then is textured, and a textured surface layer is formed on the front surface of the silicon wafer;
step two, printing aluminum paste:
printing on the back surface of the silicon wafer on one side, wherein the sizing agent is aluminum paste, and the printing position is a P-type heavily doped region of the battery;
step three, sintering at high temperature:
placing the printed silicon wafer into a furnace body, sintering the silicon wafer in the furnace body, and forming ohmic contact between aluminum paste and a silicon wafer substrate to form a P-type heavily doped region;
step four, cleaning the silicon wafer:
the silicon wafer sintered at high temperature is efficiently cleaned, the sintered aluminum paste is still exposed on the surface of the silicon wafer, and the thickness of the aluminum paste ensures that the aluminum paste can form contact with low-temperature silver paste;
fifthly, coating the double-sided intrinsic layer and the N-type amorphous silicon doped layer:
respectively plating an intrinsic amorphous silicon film on the front and back surfaces of the battery piece through PECVD technology to form an amorphous silicon intrinsic layer; plating an N-type amorphous silicon doped layer on the back surface of the battery piece by PECVD technology;
step six, preparing an antireflection film:
SiN is plated on the front surface of the battery piece by PECVD method X An antireflection film;
step seven, depositing a TCO conductive film:
plating a transparent TCO conductive film on the battery piece by adopting a PVD equipment technology;
step eight, laser grooving:
laser grooving is carried out at the bottom of the P-type heavily doped region on the back of the battery piece, the TCO conductive film, the N-type amorphous silicon doped layer and the amorphous silicon intrinsic layer are laser ablated, and the aluminum paste is exposed on the surface of the silicon wafer;
step nine, electrode printing and sintering:
printing P-type silver paste and N-type silver paste on the back of the battery respectively through a screen printing process, wherein the P-type and N-type pastes are low-temperature silver paste; after low-temperature sintering, the N-type low-temperature silver paste is connected with the TCO film layer; after low-temperature sintering, ohmic contact is realized by the P-type low-temperature silver paste and the aluminum paste;
step ten, sorting test:
the required battery pieces are selected through sorting tests.
2. The method for preparing the P-type HBC cell structure according to claim 1, wherein: in the second step, the width of the aluminum paste printing paste is 20-60 micrometers, and the height is 1-20 micrometers.
3. The method for preparing the P-type HBC cell structure according to claim 1, wherein: and in the third step, the sintering temperature in the furnace body is 300-900 ℃.
4. The method for preparing the P-type HBC cell structure according to claim 1, wherein: and fifthly, the thickness of the amorphous silicon intrinsic layer is 5-10 nm, and the thickness of the N-type amorphous silicon doped layer is 5-15 nm.
5. The method for preparing the P-type HBC cell structure according to claim 1, wherein: the width of the laser grooving in the step eight is 100 micrometers.
6. The method for preparing the P-type HBC cell structure according to claim 1, wherein: and step eight, exposing the aluminum paste on the surface of the silicon wafer to a height of 5 microns.
CN202210896409.0A 2022-07-28 2022-07-28 P-type HBC battery structure and preparation method thereof Active CN115101620B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210896409.0A CN115101620B (en) 2022-07-28 2022-07-28 P-type HBC battery structure and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210896409.0A CN115101620B (en) 2022-07-28 2022-07-28 P-type HBC battery structure and preparation method thereof

Publications (2)

Publication Number Publication Date
CN115101620A CN115101620A (en) 2022-09-23
CN115101620B true CN115101620B (en) 2024-02-20

Family

ID=83301014

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210896409.0A Active CN115101620B (en) 2022-07-28 2022-07-28 P-type HBC battery structure and preparation method thereof

Country Status (1)

Country Link
CN (1) CN115101620B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103489933A (en) * 2013-09-06 2014-01-01 晶澳（扬州）太阳能科技有限公司 Novel crystalline silicon solar cell and preparation method thereof
CN104167471A (en) * 2014-08-26 2014-11-26 中国电子科技集团公司第四十八研究所 Preparing method of whole back electrode P type crystalline silicon heterojunction solar battery
CN105957921A (en) * 2016-06-23 2016-09-21 大连理工大学 Method for preparing N-type silicon IBC solar cell by using printing technology
CN107342333A (en) * 2017-07-19 2017-11-10 青海黄河上游水电开发有限责任公司光伏产业技术分公司 A kind of HIBC batteries and preparation method thereof
CN112054093A (en) * 2020-08-31 2020-12-08 江苏润阳悦达光伏科技有限公司 Method for improving PERC battery back contact
CN113611755A (en) * 2021-08-06 2021-11-05 无锡琨圣智能装备股份有限公司 Local passivation contact IBC battery structure and preparation method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108091719A (en) * 2017-11-15 2018-05-29 君泰创新（北京）科技有限公司 Heterojunction solar battery and preparation method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103489933A (en) * 2013-09-06 2014-01-01 晶澳（扬州）太阳能科技有限公司 Novel crystalline silicon solar cell and preparation method thereof
CN104167471A (en) * 2014-08-26 2014-11-26 中国电子科技集团公司第四十八研究所 Preparing method of whole back electrode P type crystalline silicon heterojunction solar battery
CN105957921A (en) * 2016-06-23 2016-09-21 大连理工大学 Method for preparing N-type silicon IBC solar cell by using printing technology
CN107342333A (en) * 2017-07-19 2017-11-10 青海黄河上游水电开发有限责任公司光伏产业技术分公司 A kind of HIBC batteries and preparation method thereof
CN112054093A (en) * 2020-08-31 2020-12-08 江苏润阳悦达光伏科技有限公司 Method for improving PERC battery back contact
CN113611755A (en) * 2021-08-06 2021-11-05 无锡琨圣智能装备股份有限公司 Local passivation contact IBC battery structure and preparation method thereof

Also Published As

Publication number Publication date
CN115101620A (en) 2022-09-23

Similar Documents

Publication Publication Date Title
US9887312B2 (en) Solar cell and solar-cell module
CN115498057B (en) Combined passivation back contact solar cell and preparation method thereof based on laser diffusion
WO2023093604A1 (en) Solar cell and preparation method for solar cell
CN110047965A (en) A kind of novel back contacts hetero-junction solar cell and preparation method thereof
CN112397596A (en) Low-cost high-efficiency solar cell and preparation method thereof
CN114038922A (en) Back contact heterojunction solar cell capable of improving insulation and isolation effects and manufacturing method thereof
KR101612133B1 (en) Metal Wrap Through type solar cell and method for fabricating the same
CN112768549A (en) HJT battery with high photoelectric conversion efficiency and preparation method thereof
CN116914012A (en) Double-sided doped polycrystalline silicon passivation contact battery and preparation method thereof
CN216597603U (en) Back contact heterojunction solar cell capable of improving insulation and isolation effects
CN102214720B (en) Back contact heterojunction solar battery based on P-type silicon slice
CN108615775B (en) Interdigital back contact heterojunction monocrystalline silicon battery
CN115985992A (en) N-type monocrystalline silicon HBC solar cell structure and preparation method thereof
CN208507687U (en) Interdigital back contact heterojunction monocrystalline silicon battery
CN110416329A (en) A kind of crystal-silicon solar cell
CN114937717B (en) perovskite-HBC laminated double-sided battery preparation method
CN115101620B (en) P-type HBC battery structure and preparation method thereof
TWI407576B (en) Method of manufacturing a differential doped solar cell
CN115295659A (en) High-efficiency HJT battery structure and preparation method thereof
JP5645734B2 (en) Solar cell element
CN115528136A (en) Back contact battery, manufacturing method thereof, battery assembly and photovoltaic system
CN113437161A (en) Solar cell, preparation method thereof and photovoltaic module
CN113451446A (en) Sliced silicon heterojunction solar cell, preparation method and solar cell module
CN218849510U (en) N-type monocrystalline silicon HBC solar cell structure
CN112670368A (en) Method for producing a solar cell and solar cell

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: No. 188, Huachang Road, yangshe Town, Zhangjiagang City, Suzhou City, Jiangsu Province

Applicant after: JIANGSU AKCOME ENERGY RESEARCH INSTITUTE Co.,Ltd.

Applicant after: Zhejiang Aikang New Energy Technology Co.,Ltd.

Address before: No. 188, Huachang Road, yangshe Town, Zhangjiagang City, Suzhou City, Jiangsu Province

Applicant before: JIANGSU AKCOME ENERGY RESEARCH INSTITUTE Co.,Ltd.

Applicant before: JIANGYIN AKCOME SCIENCE AND TECHNOLOGY Co.,Ltd.

CB02 Change of applicant information
GR01 Patent grant
GR01 Patent grant
PP01 Preservation of patent right

Effective date of registration: 20240624

Granted publication date: 20240220

PP01 Preservation of patent right