CN115101620A - P-type HBC battery structure and preparation method thereof - Google Patents

P-type HBC battery structure and preparation method thereof Download PDF

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CN115101620A
CN115101620A CN202210896409.0A CN202210896409A CN115101620A CN 115101620 A CN115101620 A CN 115101620A CN 202210896409 A CN202210896409 A CN 202210896409A CN 115101620 A CN115101620 A CN 115101620A
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amorphous silicon
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CN115101620B (en
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杨飞
倪志春
连维飞
刘松民
张景洋
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Jiangyin Akcome Science And Technology Co ltd
Jiangsu Akcome Energy Research Institute Co ltd
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Jiangsu Akcome Energy Research Institute Co ltd
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Abstract

The P-type HBC battery structure comprises a P-type silicon substrate, wherein a P-type heavily doped region is arranged in the middle of the back of the P-type silicon substrate, amorphous silicon intrinsic layers are arranged on the front and the back of the P-type silicon substrate, an N-type amorphous silicon doped layer is arranged on the outer side of the amorphous silicon intrinsic layer on the back of the P-type silicon substrate, and SiN is arranged on the outer side of the amorphous silicon intrinsic layer on the front of the P-type silicon substrate X A antireflection film; a TCO conductive film is arranged on the outer side of the N-type amorphous silicon doping layer; the outer side of the TCO conductive film is provided with a plurality of N-type Ag electrodes, a notch is formed in the TCO conductive film, the depth of the notch penetrates through the TCO conductive film and the N-type amorphous silicon doped layer, the bottom of the P-type heavily doped region is exposed, and the bottom of the P-type heavily doped region is connected with the P-type Ag electrodes. The invention realizes partial P + by using the way of pre-sintering the aluminum slurryAnd the layer + realizes the heat treatment and gettering treatment of the silicon wafer, and improves the internal quality of the silicon wafer.

Description

P-type HBC battery structure and preparation method thereof
Technical Field
The invention relates to the technical field of photovoltaic high-efficiency batteries, in particular to a P-type HBC battery structure and a preparation method thereof.
Background
The interdigital Back Contact Heterojunction Silicon Solar Cell (HBC Solar Cell for short) has the advantages of the interdigital Back Contact Solar Cell (IBC Solar Cell for short) and the Heterojunction Solar Cell (HIT Solar Cell for short) with a Thin Intrinsic layer, removes a front surface metal electrode, reduces shading loss and obtains larger short-circuit current, and greatly reduces an interface state by inserting a layer of high-quality Intrinsic amorphous Silicon monocrystalline Silicon passivation layer between the heavily doped amorphous Silicon and the crystalline Silicon, reduces surface recombination and improves open-circuit voltage, thereby being the Solar Cell with highest photoelectric conversion efficiency in the world at present. The HBC battery combines the advantages of the IBC battery and the HJT battery, and has the following advantages: zero grid line shielding is carried out on the front surface of the battery, current loss caused by grid line shielding is avoided, and high short-circuit current is achieved; the metal electrode is positioned on the back surface of the battery, and the optimization of the metal electrode of the battery can not be limited by optical shielding, so that the increase of series resistance caused by metallization is greatly reduced.
The HBC technology, which combines the IBC and the HJ technologies, can further improve the cell efficiency, and the structure is shown in fig. 1, and the process steps are as follows. The cell structure front side of HBC is an antireflection layer ARC and a front surface field FSF, the back side of n-c-Si material is added with a buffer layer i-a-Si: H material for improving surface passivation performance, a doped amorphous silicon layer is arranged under the buffer layer and distributed in an interdigital manner, wherein p-a-Si: H is used as an emitter, n-a-Si: H is used as a back surface field BSF, and the widths of the n-a-Si: H are respectively Wemit and W BSF . Finally, a metal contact layer is covered on the emitter and the BSF, the emitter andthe back surface fields are isolated by a dielectric layer. The HBC utilizes the excellent surface passivation performance of amorphous silicon and combines the structural advantage that the front surface of the IBC structure is not shielded by metal, and the same device structure is adopted.
The HBC cell represents the highest efficiency level of the crystalline silicon cell, but the HBC is always limited by higher mass production cost and has a more tortuous development. The HBC battery retains the advantages of the HBC battery and the HJT battery and simultaneously retains the difficulty of respective production processes of the IBC battery and the HJT battery. The key problem of the IBC battery technology is how to prepare P regions and N regions which are arranged at intervals in an interdigital manner on the back of the battery and respectively form metallized contacts and grid lines on the P regions and the N regions. The diffusion of the common solar cell only needs to form an N-type diffusion region on a P-type substrate, while the IBC cell not only forms phosphorus diffusion of a back N region (BSF) but also forms boron diffusion of a PN junction, namely P-type doping is carried out on the N-type substrate, and simultaneously, because positive and negative electrodes of the IBC cell are positioned on the back surface, a strict electrode isolation process is needed during the cell manufacturing. The key problems of the HJT battery technology are that firstly, the requirement on the silicon wafer is high, the HJT battery technology is a low-temperature process and does not have high-temperature heat treatment and gettering processes, the defects of oxygen donors, new donors and the like of the silicon wafer cannot be eliminated, and the impurity content of the silicon wafer is high, so that the battery efficiency is influenced; in addition, since boron itself has low solid solubility in silicon, it is very difficult to form a high-concentration P-type amorphous silicon thin film.
The structure of the conventional HBC battery is shown in figure 1, the processes of 'mask-grooving-deposition-etching' and the like are not avoided in the preparation of the interdigital PN region, however, the process window of the coating process of the battery in the preparation of the intrinsic and doped amorphous silicon is narrow, the requirement on process cleanliness is extremely high, and the HBC battery is expensive in investment equipment, long in working procedure and high in investment cost due to the reasons of the above and the like.
Disclosure of Invention
The invention aims to overcome the defects and provides a P-type HBC cell structure and a preparation method thereof, so that the TCO conductive film has better transmittance and conductivity, and the performance of the heterojunction solar cell is improved.
The purpose of the invention is realized by the following steps:
a P-type HBC battery structure comprises PThe silicon wafer comprises a P-type silicon substrate, wherein a P-type heavily doped region is arranged in the middle of the back surface of the P-type silicon substrate, amorphous silicon intrinsic layers are arranged on the front surface and the back surface of the P-type silicon substrate, an N-type amorphous silicon doped layer is arranged on the outer side of the amorphous silicon intrinsic layer on the back surface of the P-type silicon substrate, and SiN is arranged on the outer side of the amorphous silicon intrinsic layer on the front surface of the P-type silicon substrate X An antireflection film; a TCO conductive film is arranged on the outer side of the N-type amorphous silicon doping layer; the outer side of the TCO conductive film is provided with a plurality of N-type Ag electrodes, a notch is formed in the TCO conductive film, the depth of the notch penetrates through the TCO conductive film and the N-type amorphous silicon doped layer, the bottom of the P-type heavily doped region is exposed, the bottom of the P-type heavily doped region is connected with the P-type Ag electrodes, and ohmic contact is achieved through P-type low-temperature silver paste and aluminum paste of the P-type heavily doped region.
Furthermore, the width of the P-type heavily doped region is 20-60 micrometers, and the height of the P-type heavily doped region is 1-20 micrometers.
Further, the N-type Ag electrode is connected with the TCO conducting film by using N-type low-temperature silver paste.
Further, the width of the notch is larger than that of the P-type heavily doped region.
A preparation method of the P-type HBC battery structure comprises the following steps:
step one, silicon wafer cleaning:
selecting a P-type silicon wafer, and performing texturing and cleaning treatment on the P-type silicon wafer; etching the silicon wafer after efficient cleaning, and forming a textured layer on the front side of the silicon wafer;
step two, printing aluminum paste:
printing a single surface of the back of the silicon wafer, wherein the slurry is aluminum slurry, and the printed position is a P-type heavily doped region of the battery;
step three, high-temperature sintering:
placing the printed silicon wafer into a furnace body, sintering in the furnace body, and forming ohmic contact between the aluminum paste and the silicon wafer substrate to form a P-type heavily doped region;
step four, silicon wafer cleaning:
the sintered silicon wafer is efficiently cleaned, the sintered aluminum paste still leaks on the surface of the silicon wafer, and the thickness of the aluminum paste ensures that the aluminum paste can be contacted with low-temperature silver paste;
step five, coating films on the double-sided intrinsic layer and the N-type amorphous silicon doped layer:
respectively plating intrinsic amorphous silicon thin films on the front surface and the back surface of the cell piece by a PECVD technology to form an amorphous silicon intrinsic layer; plating an N-type amorphous silicon doping layer on the back surface of the cell through a PECVD technology;
step six, preparing a antireflection film:
plating SiN on the front surface of the cell slice by a PECVD method X A antireflection film;
step seven, TCO conductive film deposition:
plating a transparent TCO conductive film on the cell by adopting a PVD equipment technology;
step eight, laser grooving:
laser grooving is carried out on the bottom of a P-type heavily doped region on the back surface of the battery piece, the TCO conductive film, the N-type amorphous silicon doped layer and the amorphous silicon intrinsic layer are ablated by laser, and the aluminum slurry is exposed on the surface of the silicon chip;
ninth, electrode printing and sintering:
respectively printing P-type silver paste and N-type silver paste on the back of the battery by a screen printing process, wherein the P-type paste and the N-type paste are both low-temperature silver paste; after low-temperature sintering, connecting the N-type low-temperature silver paste with the TCO film layer; after low-temperature sintering, ohmic contact is realized between the P-type low-temperature silver paste and the aluminum paste;
step ten, sorting and testing:
and selecting the required battery pieces through sorting test.
Further, in the second step, the width of the aluminum paste printing slurry is 20-60 micrometers, and the height of the aluminum paste printing slurry is 1-20 micrometers.
Further, the sintering temperature in the furnace body in the third step is 300-900 ℃.
Furthermore, in the fifth step, the thickness of the film layer of the amorphous silicon intrinsic layer is 5-10 nm, and the thickness of the N-type amorphous silicon doped layer is 5-15 nm.
Further, the width of the laser groove in the step eight is 100 micrometers.
And further, in the step eight, the aluminum paste is exposed on the surface of the silicon wafer, and the height of the aluminum paste is 5 micrometers.
Compared with the prior art, the invention has the beneficial effects that:
the invention realizes the local P + + layer by using the aluminum paste presintering mode, realizes the heat treatment and the gettering treatment of the silicon chip and solves the problem of the inherent quality of the silicon chip; the difficulty in manufacturing the heavily doped P-type amorphous silicon in the HBC is solved.
The invention utilizes the laser grooving technology, and the P area and the N area which are arranged at intervals in an interdigital shape are prepared on the back surface of the cell, thereby avoiding complex process flows of 'mask-grooving-deposition-etching' and the like, solving the most complex PN manufacturing process of HBC, greatly optimizing the process steps of the HBC cell and reducing the manufacturing cost of the cell.
Drawings
Fig. 1 is a schematic structural view of a conventional HBC cell.
Fig. 2 is a schematic diagram of the structure of the P-type HBC cell of the present invention.
Wherein:
p-type silicon substrate 1, P-type heavily doped region 2, amorphous silicon intrinsic layer 3, N-type amorphous silicon doped layer 4 and SiN X An antireflection film 5, a TCO conductive film 6, an N-type Ag electrode 7 and a P-type Ag electrode 8.
Detailed Description
Example 1:
referring to fig. 2, the P-type HBC battery structure according to the present invention includes a P-type silicon substrate 1, wherein a P-type heavily doped region 2 is disposed in the middle of the back surface of the P-type silicon substrate 1, and the P-type heavily doped region 2 has a width of 20 to 60 micrometers and a height of 1 to 20 micrometers.
The front and the back of the P-type silicon substrate 1 are both provided with amorphous silicon intrinsic layers 3, the outer side of the amorphous silicon intrinsic layer 3 on the back of the P-type silicon substrate 1 is provided with an N-type amorphous silicon doped layer 4, and the outer side of the amorphous silicon intrinsic layer 3 on the front of the P-type silicon substrate 1 is provided with SiN X An antireflection film 5; and a TCO conductive film 6 is arranged on the outer side of the N-type amorphous silicon doped layer 4.
The outer side of the TCO conductive film 6 is provided with a plurality of N-type Ag electrodes 7, and N-type low-temperature silver paste is used for forming connection with the TCO conductive film 6.
The TCO conductive film 6 is provided with a notch, the width of the notch is 100 micrometers, the depth of the notch penetrates through the TCO conductive film 6 and the N-type amorphous silicon doped layer 4, the bottom of the P-type heavily doped region 2 is exposed, the bottom of the P-type heavily doped region 2 is connected with a P-type Ag electrode 8, and ohmic contact is achieved by using P-type low-temperature silver paste and aluminum paste of the P-type heavily doped region 2.
The invention relates to a preparation method of a P-type HBC battery structure, which comprises the following steps:
s1 cleaning silicon wafer
Selecting a P-type silicon wafer, wherein the thickness of the silicon wafer is 130 microns, and performing texturing and cleaning treatment on the P-type silicon wafer; organic dirt, metal impurities and a surface damage layer on the surface of the silicon wafer are removed through a cleaning process; etching the silicon wafer after efficient cleaning, and forming a textured layer on the front side of the silicon wafer;
s2 printing aluminum paste
Printing a single surface of the back surface of the silicon wafer, wherein the slurry is aluminum slurry, the printing position is a P-type heavily doped region of the battery, the width of the aluminum slurry printing slurry is 30 microns, and the height of the aluminum slurry printing slurry is 5 microns;
s3, high-temperature sintering
Placing the printed silicon wafer into a furnace body, sintering at 300-900 ℃ in the furnace body, and forming ohmic contact between the aluminum paste and the silicon wafer substrate to form a P-type heavily doped region; the width of the P-type heavily doped region is 20-60 microns, and the height is 1-20 microns;
s4, cleaning silicon wafers
The sintered silicon wafer is efficiently cleaned, organic matter dirt and other impurities on the surface of the silicon wafer are removed, and two surfaces of the silicon wafer form clean surfaces; the sintered aluminum paste still leaks on the surface of the silicon chip in a naked mode, and the thickness of the aluminum paste ensures that the aluminum paste can be in contact with low-temperature silver paste;
s5, double-sided intrinsic layer and N-type amorphous silicon doped layer coating film
Respectively plating intrinsic amorphous silicon thin films on the front surface and the back surface of the cell piece by a PECVD technology to form an amorphous silicon intrinsic layer, wherein the thickness of the film layer is 5 nm;
plating an N-type amorphous silicon doped layer on the back surface of the cell through a PECVD technology, wherein the thickness of the N-type amorphous silicon doped layer is 10 nm;
s6 preparation of antireflection film
Plating SiN on the front surface of the cell piece by a PECVD method X A antireflection film;
s7 TCO conductive film deposition
Plating a transparent TCO conductive film on the cell by adopting a PVD equipment technology;
s8, laser grooving
Laser grooving is carried out on the back surface of the battery piece, and the width of the grooving is 100 micrometers;
slotting in an aluminum paste diffusion area (the bottom of a P-type heavily doped area) of the silicon wafer by adopting laser, ablating the TCO conductive film, the N-type amorphous silicon doped layer and the amorphous silicon intrinsic layer by the laser, and exposing the aluminum paste on the surface of the silicon wafer to 5 microns; laser grooving is carried out on the back surface of the battery piece, so that the P area and the N area are isolated;
s9, electrode printing
Respectively printing P-type silver paste and N-type silver paste on the back of the battery by a screen printing process, wherein the P-type paste and the N-type paste are both low-temperature silver pastes to form a P-type Ag electrode and an N-type Ag electrode;
s10, sintering
After low-temperature sintering, connecting the N-type low-temperature silver paste with the TCO film layer; after low-temperature sintering, ohmic contact is realized between the P-type low-temperature silver paste and the aluminum paste;
s11, sorting test
Required battery pieces are selected through sorting test, and through testing the efficiency of the battery pieces, the Voc reaches 745mV, and the battery conversion efficiency reaches 25.15%.
Comparative example 1:
comparative example 1 preparation method using conventional HBC cell in the prior art
S1 cleaning silicon wafer
Selecting a P-type silicon wafer, wherein the thickness of the silicon wafer is 130 microns, and performing texturing and cleaning treatment on the P-type silicon wafer; organic dirt, metal impurities and a surface damage layer on the surface of the silicon wafer are removed through a cleaning process; etching the silicon wafer after efficient cleaning, and forming a textured layer on the front side of the silicon wafer;
s2, double-sided intrinsic layer and N-type amorphous silicon doped layer coating film
Respectively plating intrinsic amorphous silicon thin films on the front surface and the back surface of the cell piece by a PECVD technology to form an amorphous silicon intrinsic layer, wherein the thickness of the film layer is 5 nm;
plating an N-type amorphous silicon doped layer on the back surface of the cell by a PECVD (plasma enhanced chemical vapor deposition) technology, wherein the thickness of the N-type amorphous silicon doped layer is 10 nm;
s3 preparation of back PN region
Preparing a back PN region through the processes of masking, slotting, depositing, etching and the like;
s4 preparation of antireflection film
Plating a SiNX anti-reflection film on the front surface of the cell piece by a PECVD method;
s5 TCO conductive film deposition
Plating a transparent TCO conductive film on the cell by adopting a PVD equipment technology;
s6 sintering of electrode printing electrode
After silver paste is printed on the back of the cell through a screen printing process, the cell is sintered at a low temperature and then is connected with the TCO film layer to realize ohmic contact;
s7, sorting test
Through testing the efficiency of the battery piece, the Voc reaches 743mV, the Isc is 40.49mA/cm2, the FF 84.64% and the battery conversion efficiency reaches 25.46%.
Comparison of electrical properties of example 1 and comparative example 1 referring to the table below, an improvement in the electrical performance parameters of the solar cell of the present invention can be obtained, primarily from the open circuit voltage Voc, the short circuit current Isc, and the fill factor FF.
Figure DEST_PATH_IMAGE002
The above is only a specific application example of the present invention, and the protection scope of the present invention is not limited in any way. All the technical solutions formed by equivalent transformation or equivalent replacement fall within the protection scope of the present invention.

Claims (10)

1. A P-type HBC cell structure, characterized by: the solar cell comprises a P-type silicon substrate (1), wherein a P-type heavily doped region (2) is arranged in the middle of the back of the P-type silicon substrate (1), amorphous silicon intrinsic layers (3) are arranged on the front and the back of the P-type silicon substrate (1), an N-type amorphous silicon doped layer (4) is arranged on the outer side of the amorphous silicon intrinsic layer (3) on the back of the P-type silicon substrate (1), and the P-type silicon substrate (1)The outer side of the front amorphous silicon intrinsic layer (3) is provided with SiN X A antireflection film (5); a TCO conductive film (6) is arranged on the outer side of the N-type amorphous silicon doped layer (4); the bottom of the P-type heavily doped region (2) is connected with the P-type Ag electrode (8), and ohmic contact is realized by using P-type low-temperature silver paste and aluminum paste of the P-type heavily doped region (2).
2. A P-type HBC cell structure according to claim 1, wherein: the width of the P-type heavily doped region (2) is 20-60 micrometers, and the height of the P-type heavily doped region is 1-20 micrometers.
3. A P-type HBC cell structure according to claim 1, wherein: the N-type Ag electrode (7) is connected with the TCO conducting film (6) through N-type low-temperature silver paste.
4. A P-type HBC cell structure according to claim 1, wherein: the width of the notch is larger than that of the P-type heavily doped region (2).
5. A method of preparing the P-type HBC cell structure of claim 1, comprising:
step one, silicon wafer cleaning: selecting a P-type silicon wafer, and performing texturing and cleaning treatment on the P-type silicon wafer; etching the silicon wafer after efficient cleaning, and forming a textured layer on the front side of the silicon wafer;
step two, printing aluminum paste:
printing a single surface of the back of the silicon wafer, wherein the slurry is aluminum slurry, and the printed position is a P-type heavily doped region of the battery;
step three, high-temperature sintering:
placing the printed silicon wafer into a furnace body, sintering in the furnace body, and forming ohmic contact between the aluminum paste and the silicon wafer substrate to form a P-type heavily doped region;
step four, silicon wafer cleaning:
the sintered silicon wafer is efficiently cleaned, the sintered aluminum paste still leaks on the surface of the silicon wafer, and the thickness of the aluminum paste ensures that the aluminum paste can be in contact with low-temperature silver paste;
step five, coating films on the double-sided intrinsic layer and the N-type amorphous silicon doped layer:
respectively plating intrinsic amorphous silicon thin films on the front surface and the back surface of the cell piece by a PECVD technology to form an amorphous silicon intrinsic layer; plating an N-type amorphous silicon doping layer on the back surface of the cell through a PECVD technology;
step six, preparing a antireflection film:
plating SiN on the front surface of the cell piece by a PECVD method X A antireflection film;
step seven, TCO conductive film deposition:
plating a transparent TCO conductive film on the cell by adopting a PVD equipment technology;
step eight, laser grooving:
laser grooving is carried out on the bottom of a P-type heavily doped region on the back surface of the battery piece, the TCO conductive film, the N-type amorphous silicon doped layer and the amorphous silicon intrinsic layer are ablated by laser, and the aluminum slurry is exposed on the surface of the silicon chip;
ninth, electrode printing and sintering:
respectively printing P-type silver paste and N-type silver paste on the back of the battery by a screen printing process, wherein the P-type paste and the N-type paste are both low-temperature silver paste; after low-temperature sintering, connecting the N-type low-temperature silver paste with the TCO film layer; after low-temperature sintering, ohmic contact is realized between the P-type low-temperature silver paste and the aluminum paste;
step ten, sorting and testing:
and selecting the required battery pieces through sorting test.
6. The method of claim 5, wherein the method comprises the steps of: in the second step, the width of the aluminum paste printing slurry is 20-60 micrometers, and the height of the aluminum paste printing slurry is 1-20 micrometers.
7. The method of claim 5, wherein the method comprises the steps of: in the third step, the sintering temperature in the furnace body is 300-900 ℃.
8. The method of claim 5, wherein the method comprises the steps of: in the fifth step, the thickness of the film layer of the amorphous silicon intrinsic layer is 5-10 nm, and the thickness of the N-type amorphous silicon doped layer is 5-15 nm.
9. The method for preparing a P-type HBC cell structure according to claim 5, wherein: and in the step eight, the width of the laser groove is 100 microns.
10. The method for preparing a P-type HBC cell structure according to claim 5, wherein: and step eight, exposing the aluminum paste on the surface of the silicon wafer to the height of 5 microns.
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