CN114038922A - Back contact heterojunction solar cell capable of improving insulation and isolation effects and manufacturing method thereof - Google Patents
Back contact heterojunction solar cell capable of improving insulation and isolation effects and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention relates to a manufacturing method of a back contact heterojunction solar cell for improving the insulation isolation effect, wherein a first main surface of a semiconductor substrate is divided into a first conductive region of a first conductive type and a second conductive region of a second conductive type; the first conductive region inner region of the first main surface of the semiconductor substrate is etched to form a first conductive region groove, and the second conductive region of the first main surface of the semiconductor substrate is etched to form a second conductive region groove. The invention aims to provide a back contact heterojunction solar cell for improving the insulation and isolation effect and a manufacturing method thereof, which improve the stability of the process, avoid the complexity of the process caused by multiple mask operations and are suitable for large-scale process production.
Description
Technical Field
The invention relates to a back contact heterojunction solar cell for improving an insulation isolation effect and a manufacturing method thereof.
Background
The improvement of the conversion efficiency of the industrial production of the solar cell is a key research subject of the development of the solar industry and the gradual replacement of the traditional energy. The main method for improving the conversion efficiency of the solar cell is to improve electrical parameters such as open-circuit voltage, fill factor, short-circuit current density and the like. The heterojunction solar cell greatly improves the surface passivation effect of the substrate silicon by inserting the intrinsic amorphous silicon layer between the amorphous silicon layer and the monocrystalline silicon substrate, and can obtain higher minority carrier service life and open-circuit voltage, thereby improving the conversion efficiency. The electrodes of the back contact solar cell are all distributed on the back, namely the P electrode and the N electrode are arranged on the back of the cell in a crossed mode, photo-generated carriers generated by the crystalline silicon photovoltaic effect are collected respectively, and the front of the cell is not distributed with any electrode, so that optical loss caused by shielding of metal electrode grid lines is avoided, short-circuit current of a cell piece can be effectively increased, and conversion efficiency is greatly improved. The back contact heterojunction monocrystalline silicon solar cell combines the advantages of the two solar technologies, and can obtain extremely high photoelectric conversion efficiency. The highest laboratory efficiency of the solar cell is reported to reach 26.63%.
However, back contact heterojunction solar cells present a number of difficulties in the manufacturing process. The back surface of the solar cell is provided with an N-type region and a P-type region which are arranged in a crossed manner, the two regions need to be completely isolated and insulated, and the phenomenon that the performance of the cell is seriously influenced by contact short circuit is avoided, so that the phenomenon that film layers with two polarities are mutually overlapped to cause carrier recombination is avoided in the film coating process or a mask mode is adopted; or after the film coating, removing the film layer with the other polarity by a local etching mode. In both of the above two methods, the masking operation and the strict alignment requirement are required to be performed for many times, so that the stability of the production process is difficult to ensure, and the method is not suitable for large-scale mass production.
Disclosure of Invention
The invention aims to provide a back contact heterojunction solar cell for improving the insulation and isolation effect and a manufacturing method thereof, which improve the stability of the process, avoid the complexity of the process caused by multiple mask operations and are suitable for large-scale process production.
The purpose of the invention is realized by the following technical scheme:
a back contact heterojunction solar cell for improving insulation isolation effect comprises a semiconductor substrate, a first conductive region groove and a second conductive region groove, wherein the first main surface of the semiconductor substrate is divided into a first conductive region of a first conductive type and a second conductive region of a second conductive type; the first conductive region and the second conductive region are not etched to form a convex edge.
A manufacturing method of a back contact heterojunction solar cell for improving an insulation isolation effect divides a first main surface of a semiconductor substrate into a first conductive region of a first conductive type and a second conductive region of a second conductive type; the first conductive region inner region of the first main surface of the semiconductor substrate is etched to form a first conductive region groove, and the second conductive region of the first main surface of the semiconductor substrate is etched to form a second conductive region groove.
Compared with the prior art, the invention has the advantages that:
(1) through the arrangement of the first conductive region groove and the second conductive region groove, the respective semiconductor film layers of the first conductive region and the second conductive region are formed into films in the corresponding grooves, so that the generation of electric leakage between the film layers of the first conductive region and the second conductive region is effectively avoided, and the improvement of the filling factor is facilitated.
(2) In the manufacturing process, the laser etching process is adopted, so that the complexity of performance damage and alignment caused by multiple coating and mask etching in the manufacturing process is reduced, the requirement of future large-scale mass production is met, and the manufacturing process is greatly shortened.
Drawings
FIG. 1 is a schematic diagram of one embodiment of a solar cell of the present invention.
Fig. 2 is a flowchart of a method for manufacturing a solar cell according to an embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of a manufacturing process of a solar cell unit according to the present invention.
Fig. 4 is a schematic cross-sectional view of a manufacturing process of a solar cell unit according to the present invention.
Fig. 5 is a schematic cross-sectional view of a manufacturing process of a solar cell unit according to the present invention.
Fig. 6 is a schematic cross-sectional view of a manufacturing process of a solar cell unit according to the present invention.
Fig. 7 is a schematic cross-sectional view of a manufacturing process of a solar cell unit according to the present invention.
Fig. 8 is a schematic cross-sectional view of a manufacturing process of a solar cell unit according to the present invention.
Fig. 9 is a schematic cross-sectional view of a manufacturing process of a solar cell unit according to the present invention.
Fig. 10 is a partial schematic view of a manufacturing process of a solar cell according to the present invention.
Fig. 11 is a partial schematic view of a manufacturing process of a solar cell according to the present invention.
Fig. 12 is a partial schematic view of a manufacturing process of a solar cell according to the present invention.
Fig. 13 is a partial schematic view of a manufacturing process of a solar cell unit according to the present invention.
Detailed Description
A back contact heterojunction solar cell for improving insulation isolation effect comprises a semiconductor substrate, a first conductive region groove and a second conductive region groove, wherein the first main surface of the semiconductor substrate is divided into a first conductive region of a first conductive type and a second conductive region of a second conductive type; the first conductive region and the second conductive region are not etched to form a convex edge.
The semiconductor substrate is a monocrystalline silicon wafer, a cast monocrystalline silicon wafer or a polycrystalline silicon wafer.
And a third conductive film layer and an antireflection film layer are sequentially arranged on the second main surface of the semiconductor substrate from bottom to surface.
The depth of the first conductive area groove is 10-50 um; the depth of the second conductive region groove is 10-50 um.
The first conductive area is covered with a first conductive film layer, and the surface of the first conductive film layer at the convex edge part of the first conductive area is covered with a first insulating film layer; the second conductive region and the first insulating film layer are covered with a second conductive film layer.
The first conductive film layer comprises a first semiconductor passivation layer and a first semiconductor layer; the second conductive type film layer includes a second semiconductor passivation layer and a second semiconductor layer.
The first semiconductor passivation layer and the second semiconductor passivation layer are silicon dioxide layers, amorphous silicon intrinsic layers or composite film layers formed by combining the silicon dioxide layers and the amorphous silicon intrinsic layers, and the thickness is controlled to be 1-10 nm.
The first semiconductor layer and the second semiconductor layer are respectively an N-type conductive semiconductor layer or a P-type conductive semiconductor layer; the first semiconductor layer and the second semiconductor layer are different in conductivity type.
The first semiconductor layer is an N-type amorphous silicon doped layer or a P-type amorphous silicon doped layer; when the semiconductor substrate is an N-type monocrystalline silicon substrate, the first semiconductor layer is an N-type amorphous silicon doped layer, and the second semiconductor layer is a P-type amorphous silicon doped layer.
The first insulating film layer may be a single layer of an insulating film or may be a combined layer of an insulating film and a mask layer. In order to facilitate the corrosion of the subsequent processes and the protection of the functional film, the first insulating film layer preferably includes a first insulating layer and a first mask layer sequentially disposed from bottom to top with the first conductive film layer as a substrate, the first mask layer may be a thin film such as amorphous silicon, and the polarity of the solution resistance should be opposite to the polarity of the first insulating layer.
The back contact heterojunction solar cell further comprises a first conductive layer arranged on the first conductive region and electrically connected with the first conductive type film layer, a first electrode arranged on the first conductive layer, a second conductive layer arranged on the second conductive region and electrically connected with the second conductive type film layer, and a second electrode arranged on the second conductive layer; an insulating separation groove is arranged between the first conducting layer and the second conducting layer.
In one embodiment, the back contact heterojunction solar cell comprises a silicon substrate, wherein a first semiconductor passivation layer, a first semiconductor layer and an antireflection layer are sequentially arranged on the front surface of the silicon substrate, a first semiconductor passivation layer is arranged on the back surface of the silicon substrate, the first semiconductor passivation layer is overlapped with the first semiconductor layer, the second semiconductor passivation layer is overlapped with the second semiconductor layer, a laminated layer formed by the first semiconductor passivation layer and the first semiconductor layer (a first semiconductor laminated layer) and a laminated layer formed by the second semiconductor passivation layer and the second semiconductor layer (a second semiconductor laminated layer) are arranged in a staggered mode, an insulating isolation layer and an insulating opening are arranged between the first semiconductor laminated layer and the second semiconductor laminated layer, the first semiconductor laminated layer and the second semiconductor laminated layer are formed in a groove of the silicon substrate, and transparent conducting layers are respectively arranged on the two semiconductor laminated layers, the transparent conductive layer is provided with an electrode.
The antireflection layer is a silicon oxide layer, a silicon nitride layer or an aluminum oxide layer, and the thickness of the antireflection layer is controlled to be 50-150 nm.
A manufacturing method of a back contact heterojunction solar cell for improving an insulation isolation effect divides a first main surface of a semiconductor substrate into a first conductive region of a first conductive type and a second conductive region of a second conductive type; the first conductive region inner region of the first main surface of the semiconductor substrate is etched to form a first conductive region groove, and the second conductive region of the first main surface of the semiconductor substrate is etched to form a second conductive region groove.
The steps of the method for fabricating the back contact heterojunction solar cell are as follows,
step A, etching a partial area of a first conductive area except for a boundary area with a second conductive area on a first main surface of a semiconductor substrate to form a first conductive area groove;
step B, forming a first conductive type film layer and a first insulating film layer on the first main surface of the semiconductor substrate in sequence;
step C, etching and removing the first insulating film layer and the first conductive film layer in the area outside the first conductive area, and etching the exposed first main surface of the semiconductor substrate to form a first conductive area with the first insulating film layer attached to the surface and an exposed second conductive area groove;
a step D of forming a second conductive type film layer on the first main surface of the semiconductor substrate processed in the step C;
step E, etching and removing the second conductive type film layer and the first insulating film layer which cover the groove region of the first conductive region;
step F, forming a conductive film layer on the first main surface of the semiconductor substrate;
and G, grooving for insulating and separating the first conductive region and the second conductive region and forming electrodes of the first conductive region and the second conductive region in the first conductive region area where the first conductive region groove is not etched.
The specific method of the step A comprises the following steps of carrying out laser etching on a first conductive area region where a first conductive area groove needs to be formed, and then carrying out chemical etching to form a first conductive area groove in the first conductive area region except for a boundary region with a second conductive area; the depth of the first conductive region groove is 10-50 um. In one embodiment, a first conductive region groove is etched on one side of a semiconductor substrate by using a solution after laser scribing, wherein the depth of the first conductive region groove is 10-50um, the solution is an alkaline solution, and potassium hydroxide and/or sodium hydroxide and the like with the total mass percent of 3% -10% are preferably used.
Performing laser etching on the first insulating film layer covered by the second conductive region, then performing chemical etching to remove the film layer covered on the second conductive region and etching the semiconductor substrate so as to form a second conductive region groove on the first main surface of the semiconductor substrate; the depth of the second conductive region groove is 10-50 um.
The first insulating film layer is formed by sequentially forming a first insulating layer and a first mask layer from bottom to surface by taking the first conductive film layer as a substrate; the specific method of step C is to perform laser etching on the first mask layer covered by the second conductive region, then perform chemical etching to remove the first insulating layer and the first conductive film layer covered on the second conductive region and etch the semiconductor substrate, so as to form a second conductive region groove on the first main surface of the semiconductor substrate. In one embodiment, the first mask layer is removed with a pulsed laser having a pulse width of less than 20 nanoseconds, preferably less than 100 picoseconds, and a low fluence wavelength of green light around 560nm, and the first insulating layer is removed with an acidic solution.
And in the step E, the second conductive type film layer in the groove area of the first conductive area is removed by laser, and the exposed first insulating film layer is removed by chemical etching. In order to prevent the laser from damaging the functional film layer in the first conductive region, it is preferable that the laser is pulsed, the pulse width is less than 20 ns, the energy density is low, and the wavelength of the green light is around 560nm, and the laser only etches the second conductive type film layer, and the exposed first insulating film layer removes the insulating film with an acidic solution.
In the step G, the first conductive region electrode and the second conductive region electrode are formed by performing corresponding manufacturing on the first conductive region and the second conductive region by using a screen printing method or an electroplating method.
The invention is described in detail below with reference to the drawings and examples of the specification:
fig. 1 to 13 are schematic diagrams illustrating a back contact heterojunction solar cell with improved insulation isolation effect and a method for fabricating the same according to an embodiment of the present invention.
The novel back contact heterojunction solar cell designed by the invention takes an N-type monocrystalline silicon substrate as an example, and the structure of the novel back contact heterojunction solar cell as shown in figure 1 comprises the following components: the semiconductor structure comprises an N-type monocrystalline silicon substrate 1, a front and back first semiconductor passivation layer 2a, a front and back first semiconductor layer 2b, a back second semiconductor passivation layer 3a, a back second semiconductor layer 3b, a front and back antireflection layer 4, a back transparent conductive layer 5, a back electrode 6, a stack (first semiconductor stack) formed by the back first semiconductor layer 2b and the back transparent conductive layer 5 and a stack (second semiconductor stack) formed by the second semiconductor layer 3b and the back transparent conductive layer 5, wherein the first semiconductor stack is positioned in a first conductive region groove 1b, the second semiconductor stack is positioned in a second conductive region groove 1c) of the silicon substrate 1, and an opening is formed between the first semiconductor stack and the second semiconductor stack.
In the solar cell structure in this embodiment, the front and back first semiconductor passivation layers 2a are the intrinsic amorphous silicon layer i containing H, and the back first semiconductor passivation layer 2a only needs to achieve the passivation effect, and has no specific requirement for the thickness thereof, which may be within the range of the thickness thereof
To (c) to (d); the first semiconductor passivation layer 2a on the front side requires a passivation effect while avoiding blocking of incident light, and preferably has a thickness controlled to be
To (c) to (d);
the second semiconductor passivation layer 3a of the backlight surface is an amorphous silicon intrinsic layer i containing H, the second semiconductor passivation layer i of the backlight surface only needs to achieve the passivation effect, no specific requirement is made on the thickness of the second semiconductor passivation layer, and the thickness of the second semiconductor passivation layer i of the backlight surface can be within the range of
To (c) to (d);
a front and back first semiconductor layer 2b which is a semiconductor amorphous silicon layer to which an n-type dopant is added; the second semiconductor layer 3b on the back surface is a semiconductor amorphous silicon layer to which a P-type dopant is added, and the thicknesses of the N-type and P-type semiconductor layers are not particularly limited, but preferably, the thickness of the N-type semiconductor layer may be set to be equal to that of the N-type semiconductor layer
The thickness of the P-type amorphous semiconductor layer may be
The doping concentration of the P-type and N-type semiconductor layers is 1019-10 20cm-3The film layer has the characteristics of high-concentration doping and high conductivity.
The N-type semiconductor region composed of the first semiconductor passivation layer 2a and the first semiconductor layer 2b on the back surface and the P-type semiconductor region composed of the second semiconductor passivation layer 3a and the second semiconductor layer 3b on the back surface are distributed in the groove region of the silicon substrate, so that short circuit between the two regions can be effectively avoided, and the filling factor is improved.
The N-type semiconductor region and the P-type semiconductor region on the back surface are arranged in a crossed manner, and an interdigital distribution mode is formed on the back surface.
An antireflective layer 4, which has both the function of an antireflective film and the function of a protective film, is provided on the front surface N-type semiconductor amorphous silicon layer, and may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like, preferably a silicon nitride film layer. The thickness of the antireflection layer can be about 70nm-1.5 um;
the insulating layer on the back N-type semiconductor amorphous silicon layer is a combined layer of the antireflection layer and the mask layer, and the polarity of the solution resistance of the mask layer is opposite to that of the insulating film. For example, the mask layer is made of amorphous silicon, polysilicon or other thin films which can resist acid corrosion, and the insulating film is made of silicon nitride or other thin films which can resist alkali corrosion.
An opening is formed between the lamination formed by the back N-type semiconductor polycrystalline layer and the transparent conducting layer and the lamination formed by the P-type semiconductor amorphous layer and the transparent conducting layer, so that the problem that the electrical performance is reduced due to short circuit between the two doped layers is solved.
Next, a method for manufacturing a back contact hetero solar cell according to the present embodiment will be described with reference mainly to fig. 2 to 13:
first, an N-type single crystal silicon substrate 1 is prepared. Next, in step S1, the front and back surfaces of the silicon substrate are cleaned. The silicon substrate was polished on both sides to remove the mechanical loss layer and then surface cleaned to reduce solution residue and reduce surface recombination as shown in figure 3. The surface of the monocrystalline silicon substrate can be a polished surface or a textured surface, and preferably a pyramid textured surface is formed on the surface of the substrate, so that the reflectivity is reduced;
in step S2, a patterned region of the first conductive region is etched on one side of the silicon substrate by laser, and a region bordering the second conductive region is not etched, as shown in fig. 4; after laser scribing, the local part of the silicon substrate is in a loose state and is easier to etch compared with the area without scribing. Then soaking and corroding a groove 1b of the first conductive area by using an alkaline solution, wherein the depth of the groove is controlled to be about 10-50um as shown in figure 5; the alkaline solution is preferably a potassium hydroxide solution or a sodium hydroxide solution with the total mass percentage of 3-10%;
in step S3, depositing a first semiconductor passivation layer, i.e., the intrinsic passivation layer 2a of hydrogenated amorphous silicon, the N-type amorphous silicon doped layer 2b and the anti-reflective layer 4 on the front and back surfaces of the silicon substrate, where the anti-reflective layer 4 may be formed of a single material such as silicon oxide, silicon nitride, silicon oxynitride, or a multi-layer composite material, and preferably, silicon nitride is used as the anti-reflective layer in this embodiment, as shown in fig. 5; the above three film layers may be formed by a thin film forming method such as a sputtering method or a CVD method, and are preferably deposited by a PECVD method.
In order to avoid damage of subsequent laser scribing, a first mask layer (the first mask layer is not separately shown in fig. 5 and subsequent figures) such as an amorphous silicon film layer is arranged behind the anti-reflection layer 4 which is positioned on the back surface and forms the first insulating layer, and is used as an etching mask layer of the sacrificial film layer and the subsequent insulating layer. The polarity of the solution resistance of the first mask layer should be opposite to the polarity of the anti-reflection layer 4, in this embodiment, the first mask layer, such as amorphous silicon, polysilicon and other films, may be resistant to acid corrosion, and the anti-reflection layer 4 is a silicon nitride and other film layers that may be resistant to alkali corrosion.
In step S4, removing the first mask layer on the anti-reflective layer by laser on the back surface, and then removing the anti-reflective layer by solution etching to form the structure shown in fig. 7; then, continuously removing the amorphous silicon layer and part of bulk silicon below the antireflection layer by using a solution etching method to form a second conductive region groove 1c, wherein the laser preferentially uses low-energy-density picosecond green light, the wavelength of the laser is about 560nm to etch the antireflection layer, the damage of the laser to the first semiconductor layer of other non-laser regions is reduced, and the amorphous silicon film layer and part of the silicon substrate are removed by using a solution etching method to form the second conductive region groove 1c, as shown in fig. 8;
in step S5, as shown in fig. 9, a second semiconductor passivation layer, i.e., an amorphous silicon intrinsic layer 3a, a P-type amorphous silicon layer 3b, is deposited on the back surface of the silicon base sheet, which can be formed by a thin film forming method such as sputtering or CVD, preferably by PECVD in this embodiment;
in step S6, removing the second semiconductor passivation layer, the second semiconductor layer, and the anti-reflective layer on the first conductive region to form the first semiconductor stacked region and the second semiconductor stacked region in an interlaced manner, so as to facilitate subsequent contact with the transparent conductive layer, where the film layer is removed by screen printing etching ink, wet etching under the protection of the protective ink, or directly laser etching, and preferably, in this embodiment, the second semiconductor passivation layer, and the first mask layer on the first conductive region are removed by laser etching, and then the anti-reflective layer is removed by etching with an etching solution, so as to form the structure shown in fig. 10; the laser is pulsed with a pulse width of less than 20 nanoseconds, preferably less than 100 picoseconds;
in step S7, a transparent conductive layer is deposited on the back surface of the silicon substrate sheet, and as shown in fig. 11, the transparent conductive layer may be formed of a transparent conductive oxide such as ITO or AZO, and the transparent conductive layer may be formed by evaporation, sputtering, or the like, preferably, the present embodiment is formed by PVD sputtering;
in step S8, the stack of N-type polysilicon and transparent conductive layer on the back surface of the silicon substrate is insulated and separated from the stack of P-type amorphous silicon layer and transparent conductive layer, as shown in fig. 12; specifically, the two regions can be isolated by laser scribing, screen printing and etching grooves with etching ink, preferably, the embodiment is performed by laser scribing;
in step S9, electrodes are formed on the first and second conductive regions on the back surface of the silicon substrate, respectively, and the electrodes may be formed by screen printing, low temperature sintering (< 250 ℃) to form silver gate electrodes, or by electroplating, as shown in fig. 13. Preferably, the gate line electrode is formed by electroplating.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. It is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Claims (10)
1. The utility model provides a promote back of body contact heterojunction solar cell of insulating isolation effect which characterized in that: the semiconductor substrate is divided into a first conductive area of a first conductive type and a second conductive area of a second conductive type by a first main surface, a first conductive area groove is formed by etching the semiconductor substrate in the inner area of the first conductive area, and a second conductive area groove is formed by etching the semiconductor substrate of the second conductive area; the first conductive region and the second conductive region are not etched to form a convex edge.
2. The back contact heterojunction solar cell with improved insulation isolation effect of claim 1, wherein: the first conductive area is covered with a first conductive film layer, and the surface of the first conductive film layer at the convex edge part of the first conductive area is covered with a first insulating film layer; the second conductive region and the first insulating film layer are covered with a second conductive film layer.
3. The back contact heterojunction solar cell with improved insulation isolation effect of claim 2, wherein: the first insulating film layer comprises a first insulating layer and a first mask layer which are sequentially arranged from bottom to surface by taking the first conductive film layer as a substrate.
4. The back contact heterojunction solar cell with improved insulation isolation effect according to any one of claims 2 to 3, wherein: the semiconductor device further comprises a first conductive layer arranged on the first conductive region and electrically connected with the first conductive type film layer, a first electrode arranged on the first conductive layer, a second conductive layer arranged on the second conductive region and electrically connected with the second conductive type film layer, and a second electrode arranged on the second conductive layer; an insulating separation groove is arranged between the first conducting layer and the second conducting layer.
5. The method for manufacturing a back contact heterojunction solar cell with improved insulation isolation effect according to any one of claims 1 to 4, wherein: dividing a first main surface of a semiconductor substrate into a first conductive region of a first conductivity type and a second conductive region of a second conductivity type; the first conductive region inner region of the first main surface of the semiconductor substrate is etched to form a first conductive region groove, and the second conductive region of the first main surface of the semiconductor substrate is etched to form a second conductive region groove.
6. The method for manufacturing a back contact heterojunction solar cell with improved insulation and isolation effects as claimed in claim 5, wherein: the steps of the method are as follows,
step A, etching a partial area of a first conductive area except for a boundary area with a second conductive area on a first main surface of a semiconductor substrate to form a first conductive area groove;
step B, forming a first conductive type film layer and a first insulating film layer on the first main surface of the semiconductor substrate in sequence;
and step C, etching the first insulating film layer and the first conductive film layer in the area except the first conductive area, and etching the exposed first main surface of the semiconductor substrate to form a first conductive area with the first insulating film layer attached to the surface and an exposed second conductive area groove.
7. The method for manufacturing a back contact heterojunction solar cell with improved insulation and isolation effects as claimed in claim 6, wherein: the specific method of the step A comprises the following steps of carrying out laser etching on a first conductive area region where a first conductive area groove needs to be formed, and then carrying out chemical etching to form a first conductive area groove in the first conductive area region except for a boundary region with a second conductive area; the depth of the first conductive region groove is 10-50 um.
8. The method for manufacturing a back contact heterojunction solar cell with improved insulation and isolation effects as claimed in claim 6, wherein: performing laser etching on the first insulating film layer covered by the second conductive region, then performing chemical etching to remove the film layer covered on the second conductive region and etching the semiconductor substrate so as to form a second conductive region groove on the first main surface of the semiconductor substrate; the depth of the second conductive region groove is 10-50 um.
9. The method for manufacturing a back contact heterojunction solar cell with improved insulation and isolation effects as claimed in claim 8, wherein: the first insulating film layer is formed by sequentially forming a first insulating layer and a first mask layer from bottom to surface by taking the first conductive film layer as a substrate; the specific method of step C is to perform laser etching on the first mask layer covered by the second conductive region, then perform chemical etching to remove the first insulating layer and the first conductive film layer covered on the second conductive region and etch the semiconductor substrate, so as to form a second conductive region groove on the first main surface of the semiconductor substrate.
10. The method for manufacturing a back contact heterojunction solar cell with improved insulation isolation effect according to any one of claims 5 to 9, wherein: it also comprises the steps of, as follows,
a step D of forming a second conductive type film layer on the first main surface of the semiconductor substrate processed in the step C;
step E, etching and removing the second conductive type film layer and the first insulating film layer which cover the groove region of the first conductive region;
step F, forming a conductive film layer on the first main surface of the semiconductor substrate;
and G, grooving for insulating and separating the first conductive region and the second conductive region and forming a first electrode of the first conductive region and a second electrode of the second conductive region in the first conductive region area where the first conductive region groove is not etched.
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| EP4340046A1 (en) * | 2022-09-16 | 2024-03-20 | Golden Solar (Quanzhou) New Energy Technology Co., Ltd. | Hybrid passivation back contact cell and fabrication method thereof |
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| EP4340046A1 (en) * | 2022-09-16 | 2024-03-20 | Golden Solar (Quanzhou) New Energy Technology Co., Ltd. | Hybrid passivation back contact cell and fabrication method thereof |
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