CN111864014A - Solar cell and manufacturing method thereof - Google Patents
Solar cell and manufacturing method thereof Download PDFInfo
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- CN111864014A CN111864014A CN202010719689.9A CN202010719689A CN111864014A CN 111864014 A CN111864014 A CN 111864014A CN 202010719689 A CN202010719689 A CN 202010719689A CN 111864014 A CN111864014 A CN 111864014A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
The invention discloses a solar cell and a manufacturing method thereof, and relates to the technical field of solar cells. The P-type regions and the N-type regions which are alternately distributed are formed on the backlight surface of the substrate by adopting the hard mask, so that the patterning process of the backlight surface of the solar cell is simplified, and the manufacturing cost of the solar cell is reduced. The method for manufacturing the solar cell comprises the following steps: providing a substrate, forming P-type regions and N-type regions which are alternately distributed on the backlight surface of the substrate by adopting a hard mask, and forming electrodes which are respectively contacted with the P-type regions and the N-type regions. The manufacturing method of the solar cell is used for manufacturing the solar cell.
Description
Technical Field
The invention belongs to the technical field of solar cells, and particularly relates to a solar cell and a manufacturing method thereof.
Background
A crystalline silicon solar cell is a device that can directly convert solar energy into electrical energy. The improvement of the conversion efficiency of the crystalline silicon solar cell and the reduction of the production cost of the crystalline silicon solar cell are the continuous pursuit targets in the industry. In order to improve the conversion efficiency of the crystalline silicon solar cell, a plurality of high-efficiency crystalline silicon solar cells with novel structures are developed at home and abroad, such as structures of a grooved buried gate, a selective emitter, a crystalline silicon Heterojunction with Intrinsic Thin-layer (HIT), a Back-junction Back-contact structure (IBC) and the like, and the structures can improve the conversion efficiency of the crystalline silicon solar cell by 25% or more.
Compared with the common crystalline silicon solar cell, the tunneling oxide passivation contact solar cell completely transfers the P-type region and the N-type region to the back of the cell, so that the shading loss of the light receiving surface can be basically reduced to 0, and the short-circuit current is greatly improved. Meanwhile, the open-circuit voltage of the cell is further improved by the tunnel oxide passivation contact structure, so that the tunnel oxide passivation contact solar cell has higher conversion efficiency.
However, after the P-type region and the N-type region of the light receiving surface of the tunnel oxide passivation contact solar cell are transferred to the backlight surface, the P-type region and the N-type region are distributed in the backlight surface of the tunnel oxide passivation contact solar cell in a staggered manner, and a spacing region exists between the P-type region and the N-type region, so that the patterning process for forming the P-type region, the N-type region and the spacing region becomes complicated, and therefore, the manufacturing cost of the cell is very high.
Disclosure of Invention
The invention aims to provide a solar cell and a manufacturing method thereof, which can simplify the graphical process of the backlight surface of the solar cell and reduce the manufacturing cost of the solar cell on the premise of ensuring the conversion efficiency of the solar cell.
In order to achieve the above object, the present invention provides a method of manufacturing a solar cell, the method comprising:
providing a substrate; forming a P-type region and an N-type region which are alternately distributed on the backlight surface of the substrate by adopting a hard mask; electrodes are formed in contact with the P-type region and the N-type region, respectively.
Preferably, the P-type region is a P-type silicon germanium region and the N-type region is an N-type silicon germanium region.
Preferably, after providing a substrate, before forming the P-type regions and the N-type regions alternately distributed on the back surface of the substrate by using the hard mask, the method for manufacturing the solar cell further includes: and sequentially forming a backlight passivation layer and an intrinsic amorphous silicon layer on the backlight surface of the substrate.
Preferably, the hard mask is used to form the P-type regions and the N-type regions alternately distributed, including: forming alternately distributed P-type regions and N-type regions on the intrinsic amorphous silicon layer by adopting a low-temperature chemical vapor deposition process under the masking of a hard mask; the intrinsic amorphous silicon layer corresponding to the positions where the P-type and N-type regions are formed is removed, and the intrinsic amorphous silicon layer between the adjacent P-type and N-type regions is maintained.
Preferably, the temperature of the low temperature chemical vapor deposition process is 300 ℃ to 400 ℃.
Preferably, after the alternately distributed P-type regions and N-type regions are formed, and before electrodes respectively contacting the P-type regions and the N-type regions are formed, the method for manufacturing solar energy further includes: an isolation layer is formed to cover the P-type region, the N-type region, and a region between the P-type region and the N-type region.
Preferably, forming the electrodes in contact with the P-type region and the N-type region, respectively, includes: and forming electrodes respectively in contact with the P-type region and the N-type region by adopting a screen printing process.
Preferably, the backlight passivation layer is at least one of aluminum oxide and silicon oxide, and the thickness of the backlight passivation layer is 1nm-20 nm; and/or the isolating layer is at least one of silicon nitride, silicon oxide, silicon oxynitride and silicon carbide, and the thickness of the isolating layer is 60nm-200 nm.
Preferably, the P-type region and the N-type region have a pitch of 5 μm to 100. mu.m.
Compared with the prior art, the manufacturing method of the solar cell provided by the invention has the following beneficial effects:
in the invention, the hard mask is used as a mask on the backlight surface of the substrate to form an N-type region and a P-type region which are alternately distributed. That is, the hard mask may first define a pattern including an N-type region and a P-type region, and based on this, the N-type region and the P-type region are formed on the back surface of the substrate. Compared with the prior art that the mask material layer or the photoresist layer is coated on the backlight surface of the substrate and is patterned to form the alternately distributed N-type regions and the alternately distributed P-type regions, the processes of forming the mask material layer or the photoresist layer, patterning the mask material layer or the photoresist layer and the like on the backlight surface of the substrate are reduced, so that the process of forming the alternately distributed P-type regions and the alternately distributed N-type regions on the backlight surface of the substrate is simplified. Therefore, the manufacturing cost of the solar cell can be effectively reduced, and the solar cell manufacturing method is more suitable for mass production of the solar cell.
The invention also provides a solar cell, which at least comprises a substrate, a backlight surface passivation layer formed on the backlight surface of the substrate, a P-type region and an N-type region which are alternately distributed on the backlight surface passivation layer, and an intrinsic amorphous silicon layer distributed on the backlight surface passivation layer between the P-type region and the N-type region; an isolation layer formed on the P-type region, the N-type region and the intrinsic amorphous silicon layer, and an electrode penetrating the isolation layer to be in contact with the P-type region and the N-type region, respectively.
Compared with the prior art, the beneficial effects of the solar cell provided by the invention are the same as those of the solar cell manufacturing method in the technical scheme, and the details are not repeated here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a solar cell in the prior art;
fig. 2-6 are schematic structural diagrams of a solar cell manufacturing process according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a solar cell according to an embodiment of the present invention.
Wherein, in fig. 1: 100 is a substrate, 101 is a backlight surface passivation layer, 102 is a backlight surface N-type polysilicon region, 103 is a backlight surface P-type polysilicon region, 104 is an isolation layer, 105 is a negative electrode, 106 is a positive electrode, 107 is a light receiving surface passivation layer, and 108 is a light receiving surface antireflection layer;
in fig. 2-7: the light-receiving-surface-doped thin film transistor comprises a substrate 1, a light-receiving-surface passivation layer 2, a light-receiving-surface doped layer 3, an anti-reflection layer 4, a backlight-surface passivation layer 5, an intrinsic amorphous silicon layer 6, an N-type silicon germanium region 7, a P-type silicon germanium region 8, an isolation layer 9 and an electrode 10.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
The tunneling oxide passivation contact solar cell completely transfers the P-type region and the N-type region to the backlight surface of the cell, so that the shading loss of the light receiving surface is reduced to 0, the short-circuit current is greatly improved, meanwhile, the tunneling oxide passivation contact structure further improves the open-circuit voltage of the cell, and the characteristics can improve the conversion efficiency of the cell. Tunneling oxide passivated contact solar cells also face some problems.
Fig. 1 shows a schematic structure diagram of a conventional tunnel oxide passivated contact solar cell. As shown in fig. 1, the tunnel oxide passivated contact solar cell includes a substrate 100, a light receiving surface passivation layer 107, a light receiving surface antireflection layer 108, a backlight surface passivation layer 101, and a backlight surface N-type polysilicon region 102 as a base region, a backlight surface P-type polysilicon region 103 as an emitter, and a space exists between adjacent base regions and emitters. The isolation layer 104 covers the base region, the emitter, and the space between the base region and the emitter, a negative electrode 105 is formed on the base region, a positive electrode 106 is formed on the emitter, the negative electrode 105 is in direct contact with the base region, and the positive electrode 106 is in direct contact with the emitter. The backlight passivation layer 101, the backlight N-type polysilicon region 102, and the backlight P-type polysilicon region 103 form a tunnel oxide passivation contact structure on the backlight surface of the substrate 100.
It should be noted that, as shown in fig. 1, in the prior art, an oxide is coated on a backlight passivation layer 101 as a mask material layer, and the mask material layer is lithographically etched to form a mask pattern, where the mask pattern may define a region of a backlight N-type polysilicon region 102 serving as a base region and a region of a backlight P-type polysilicon region 103 serving as an emitter on a backlight surface of a substrate 100. And forming the backlight surface N-type polycrystalline silicon regions 102 and the backlight surface P-type polycrystalline silicon regions 103 which are alternately distributed in the figure 1 under the masking of the mask pattern. It should be understood that the alternating distribution herein refers to a spatial distribution, for example, a plurality of backlight N-type polysilicon regions 102 and backlight P-type polysilicon regions 103 may be formed on a backlight surface of the substrate 100, where the backlight N-type polysilicon regions 102 and the backlight P-type polysilicon regions 103 are present in pairs, and a space is provided between each pair of the backlight N-type polysilicon regions 102 and the backlight P-type polysilicon regions 103, and a space is also provided between adjacent pairs. At this time, the plurality of backlight N-type polysilicon regions 102 and the plurality of backlight P-type polysilicon regions 103 are distributed on the backlight side of the substrate 100 in a manner similar to comb teeth in a comb.
As shown in fig. 1, when the above-mentioned process provided by the related art is used to form the N-type polysilicon region 102 and the P-type polysilicon region 103 on the backlight surface of the substrate 100, the patterning process is complicated, which greatly increases the manufacturing cost of the solar cell, so that the process provided by the related art cannot be applied to the mass production of the solar cell.
In order to solve the above problems, embodiments of the present invention provide a method for manufacturing a solar cell. The manufacturing method comprises the following steps:
as shown in fig. 2, a substrate 1 is provided, and a light-receiving-surface passivation layer 2, a light-receiving-surface doping layer 3, and a light-receiving-surface antireflection layer 4 are formed in this order on the light-receiving surface of the substrate 1.
The substrate 1 may be a semiconductor substrate, for example, an N-type silicon substrate, or may be a P-type silicon substrate.
The following describes a method for manufacturing a solar cell based on an N-type silicon substrate, taking the N-type silicon substrate as an example. It is to be understood that the following description is intended to be illustrative, and not restrictive.
First, as shown in fig. 2, a light receiving surface passivation layer 2 may be formed on a light receiving surface of an N-type silicon substrate by any conventional deposition process such as thermal oxidation, ALD, PECVD, or the like. The light-receiving-surface passivation layer 2 may be made of any one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon carbide, and amorphous silicon. Any combination of two or more kinds may be used, and for example, the light-receiving-surface passivation layer 2 is a stack of silicon oxide and aluminum oxide. The thickness of the light-receiving surface passivation layer 2 may be determined according to actual requirements, and may be any value selected from 1nm to 20nm, for example, 1nm, 10nm, or 20nm, but is not limited thereto.
As shown in fig. 2, since the material of the light-receiving-surface passivation layer 2 has a high optical band gap, such as silicon oxide or aluminum oxide, and also has a certain concentration of charges, the certain concentration of charges in the light-receiving-surface passivation layer 2 can saturate dangling bonds on the light-receiving surface of the N-type silicon substrate. And the negative charge in the light receiving surface passivation layer 2 generates an electric field on the light receiving surface of the N-type silicon substrate, and the negative charge repels photo-generated electrons on the light receiving surface of the N-type silicon substrate, so that the separation of the photo-generated electrons and holes is promoted, the recombination probability of the electrons and the holes on the surface of the N-type silicon substrate is effectively reduced, and a good surface passivation effect is further obtained.
Then, as shown in fig. 2, a light-receiving-surface doped layer 3 is formed on the light-receiving-surface passivation layer 2. The light-receiving-surface doped layer 3 may be formed by doping an N-type silicon substrate film to form a homojunction. A wide bandgap doped silicon thin film may be grown on the light-receiving-surface passivation layer 2 to form the light-receiving-surface doped layer 3 in the form of a heterojunction. When the light receiving surface doping layer 3 is prepared by growing the wide bandgap doped silicon-based film on the light receiving surface passivation layer 2, the wide bandgap doped silicon-based film may be grown on the light receiving surface passivation layer 2, and N-type or P-type doping may be obtained by performing in-situ doping, diffusion, ion implantation, or the like on the wide bandgap doped silicon-based film, that is, the light receiving surface doping layer 3 is obtained. The thickness of the light-receiving surface doped layer 3 may be determined according to actual requirements, and may be any value, for example, 5nm to 20nm, for example, 5nm, 10nm, or 20nm, but is not limited thereto. The forbidden band width of the silicon-based thin film can be 1.8ev to 2.2ev, for example, 1.8ev, 2.0ev or 2.2ev, but is not limited thereto.
Next, as shown in fig. 2, the light-receiving-surface antireflection layer 4 is formed on the light-receiving-surface doped layer 3. The light receiving surface antireflection layer 4 may be any one of silicon nitride, indium tin oxide, silicon oxynitride, aluminum oxide, silicon carbide, and magnesium fluoride, or a combination of any two or more of them. The thickness of the light receiving surface antireflection layer 4 may be 65nm to 90nm, and the specific thickness may vary depending on the refractive index and thickness of the light receiving surface passivation layer 3. The specific method for forming the light receiving surface antireflection layer 4 may be a method commonly used in the art depending on the material for forming the same, and for example, when the light receiving surface antireflection layer 4 is silicon nitride, the light receiving surface antireflection layer 4 may be formed by an LPCVD method, an APCVD method, a PECVD method, or the like. For another example, when the light-receiving-surface antireflection layer 4 is magnesium fluoride, the light-receiving-surface antireflection layer 4 may be formed by an evaporation method or a magnetron sputtering method. When other materials are used, CVD or PVD methods may also be used for growth. Of course, those skilled in the art may select other suitable methods for forming the light receiving surface antireflection layer 4 according to practical situations.
It is to be explained that, as shown in fig. 2, after the light receiving surface passivation layer 2 is formed on the substrate 1, the light receiving surface antireflection layer 4 may also be formed directly on the light receiving surface passivation layer 2. That is, the light-receiving-surface doping layer 3 is not formed between the light-receiving-surface passivation layer 2 and the light-receiving-surface antireflection layer 4.
As shown in fig. 3, a backlight passivation layer 5 is formed on the backlight surface of the N-type silicon substrate. The material of the backlight passivation layer 5 may be any compound having passivation and tunneling effects, for example, the material of the backlight passivation layer 5 may be an oxide, a nitride and/or a conductive polymer. Specifically, the material may be any one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon carbide, and amorphous silicon, or a combination of any two or more of them. Those skilled in the art can select other suitable oxides to form the backlight passivation layer 5 according to the embodiment of the present invention. More specifically, to ensure that the backlight passivation layer 5 has better passivation and tunneling effects to further improve the efficiency of the crystalline silicon solar cell, the backlight passivation layer 5 preferably comprises a silicon oxide layer or an aluminum oxide layer, and the thickness may be 1nm to 20nm, for example, 1nm, 10nm or 20 nm.
As shown in fig. 3, the specific forming manner of the backlight passivation layer 5 can be selected according to actual situations. For example, a silicon oxide layer is used as an example, and the silicon oxide layer can be formed by wet chemical growth, such as soaking in concentrated nitric acid solution or soaking in deionized water containing ozone. Of course, dry growth, such as ultraviolet ozone oxidation or thermal oxygen oxidation, may also be employed.
As shown in fig. 3, when the material of the backlight passivation layer 5 is silicon oxide or aluminum oxide, or a stack of silicon oxide and aluminum oxide, the silicon oxide and aluminum oxide not only have a high optical band gap, but also have a certain concentration of negative charges. At the moment, the dangling bond defect of the backlight surface of the N-type silicon substrate can be effectively passivated, so that the recombination probability of a current carrier on the backlight surface of the N-type silicon substrate is reduced, and the conversion efficiency of the solar cell is improved. Meanwhile, the backlight surface passivation layer 5 can realize the transport of carriers on two sides of the backlight surface passivation layer 5 through a tunneling effect or a pinhole structure and the like. Therefore, the recombination of the carriers on the backlight surface of the silicon substrate is reduced through the backlight surface passivation layer 5, the transmission of the carriers is not influenced, the filling factor of the battery is improved, and the conversion efficiency of the battery is improved.
As shown in fig. 4, an intrinsic amorphous silicon layer 6 is formed on the backlight passivation layer 5, and N-type silicon germanium regions 7 and P-type silicon germanium regions 8 are formed alternately on the intrinsic amorphous silicon layer 6 using a hard mask.
As shown in fig. 4, in the embodiment of the present invention, an intrinsic amorphous silicon layer 6 is formed on a backlight passivation layer 5, the thickness of the intrinsic amorphous silicon layer 6 may be 5nm to 10nm, and then an N-type silicon germanium region 7 and a P-type silicon germanium region 8 are formed on the intrinsic amorphous silicon layer 6 and alternately distributed by using a hard mask as a mask.
Illustratively, as shown in fig. 4, a P-type sige region 8 is masked by a hard mask having a pattern of N-type sige regions 7 to expose the N-type sige regions 7, and an N-type sige thin film is grown on the intrinsic amorphous si layer 6 corresponding to the N-type sige regions 7 to form comb-shaped N-type sige regions 7. And then, masking the N-type silicon germanium region 7 by using a hard mask with a P-type silicon germanium region 8 pattern to expose the P-type silicon germanium region 8, and growing a P-type silicon germanium thin film on the intrinsic amorphous silicon layer 6 corresponding to the P-type silicon germanium region 8 to form the comb-shaped P-type silicon germanium region 8. Specifically, the N-type sige regions 7 and the P-type sige regions 8 are alternately arranged in a fork shape, and a space is formed between the adjacent N-type sige regions 7 and the adjacent P-type sige regions 8. It should be understood that the N-type sige regions 7 and the P-type sige regions 8 are not formed in a strict order, and the P-type sige regions 8 may be formed first and then the N-type sige regions 7 may be formed.
As shown in fig. 4, in the present invention, a hard mask is used as a mask to form N-type sige regions 7 and P-type sige regions 8 alternately distributed on the back surface of a substrate 1. That is, the hard mask may be patterned to include the N-type sige regions 7 and the P-type sige regions 8, and based on this, the N-type sige regions 7 and the P-type sige regions 8 are formed on the back surface of the substrate 1. Compared with the prior art in which the mask material layer or the photoresist layer is coated on the backlight surface of the substrate and is patterned to form the alternately distributed N-type polycrystalline regions and the alternately distributed P-type polycrystalline silicon regions, the processes of forming the mask material layer or the photoresist layer and patterning the mask material layer or the photoresist layer on the backlight surface of the substrate 1 are reduced, so that the process of forming the alternately distributed P-type silicon germanium regions 8 and the alternately distributed N-type silicon germanium regions 7 on the backlight surface of the substrate 1 is simplified. And a space exists between the adjacent N-type silicon germanium region 7 and the adjacent P-type silicon germanium region 8, and the formed space further simplifies the patterning process and saves the cost. Therefore, the manufacturing cost of the solar cell can be effectively reduced, and the solar cell manufacturing method is more suitable for mass production of the solar cell.
Specifically, as shown in fig. 4, under the mask of the hard mask, the method for forming the above-mentioned N-type silicon germanium regions 7 and P-type silicon germanium regions 8 may be a method commonly used in the art, for example, polycrystalline silicon germanium may be grown by using Low Pressure Chemical Vapor Deposition (LPCVD), Atmospheric Pressure Chemical Vapor Deposition (APCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), catalytic chemical vapor deposition (Cat-CVD), etc., and the doping may be in situ doped or may be achieved by diffusion, ion implantation, etc. In order to alleviate the influence of high temperature treatment on the quality of the previously formed backlight passivation layer 5 and the N-type silicon substrate as much as possible, the N-type silicon germanium regions 7 and the P-type silicon germanium regions 8 may be grown by using a low temperature chemical vapor deposition process, and specifically, the low temperature chemical vapor deposition temperature may be 300 ℃ to 400 ℃. Taking the PECVD method as an example: growing a silicon germanium film on the intrinsic amorphous silicon layer 6 at low temperature, and carrying out in-situ doping of phosphorus ions and boron ions during the growth of the silicon germanium film, wherein the specific doping concentration can be 1 × 1019cm-3～1×1021cm-3The thickness of the N-type SiGe regions 7 and the P-type SiGe regions 8 may be 50nm to 200 nm. Or a silicon germanium film can be grown on the intrinsic amorphous silicon layer 6 at a low temperature, and then phosphorus ions and boron ions can be doped in the N-type silicon germanium region 7 and the P-type silicon germanium region 8 respectively by means of ion implantation and the like, specifically, the doping concentration can be 1 × 1019cm-3～1×1021cm-3The thickness of the N-type SiGe regions 7 and the P-type SiGe regions 8 may be 50nm to 200 nm. Other suitable methods may be selected by those skilled in the art to form the doped poly-silicon-germanium layers of the present disclosure depending on the application.
It should be explained that, as shown in fig. 4, whether in-situ doping is adopted or doping is performed by diffusion, ion implantation, etc., the N-type sige regions 7 and the P-type sige regions 8 are formed by selectively growing the sige thin film through low temperature chemical vapor deposition, during the growth of the sige thin film, the intrinsic amorphous si layer 6 corresponding to the portions below the N-type sige regions 7 and the P-type sige regions 8 is etched away, so that the N-type sige regions 7 and the P-type sige regions 8 are in direct contact with the back side passivation layer 5, and the intrinsic amorphous si layer 6 between the adjacent P-type sige regions 8 and the N-type sige regions 7 is not etched away.
It should be understood that, as shown in fig. 4, the P-type silicon germanium regions 8 and the N-type silicon germanium regions 7 which are in direct contact with the backlight passivation layer 5 and are alternately distributed are formed on the intrinsic amorphous silicon layer 6, the P-type silicon germanium regions 8 and the backlight passivation layer 5 form a P-type passivation contact structure to realize selective collection of holes, and the N-type silicon germanium regions 7 and the backlight passivation layer 5 form an N-type passivation contact structure to realize selective collection of electrons, so that the alternately distributed base regions and emitter electrodes are respectively formed on the backlight surface of the silicon substrate, and the N-type passivation contact structure and the P-type passivation contact structure are respectively used to realize selective collection of electrons and holes, thereby greatly reducing the recombination probability of electrons and holes, maintaining a high open-circuit voltage, and improving the fill factor. And an intrinsic amorphous silicon layer 6 is arranged between the N-type silicon germanium region 7 and the P-type silicon germanium region 8 as an interval, so that the N-type silicon germanium region 7 is prevented from being directly contacted with the P-type silicon germanium region 8 to cause electric leakage, the filling factor of the solar cell is favorably improved, and the conversion efficiency of the solar cell is further improved. Specifically, the spacing width between the N-type sige regions 7 and the P-type sige regions 8 may be 5 μm to 100 μm, and the specific width depends on the solar cell manufacturing process, and the smaller the width, the higher the design requirement for the mask, but the optimal value of the spacing width varies according to the cell structure.
As shown in fig. 5, an isolation layer 9 is formed to cover the N-type silicon germanium regions 7, the P-type silicon germanium regions 8, and the region between the N-type silicon germanium regions 7 and the P-type silicon germanium regions 8. The isolation layer 9 may be any one of silicon nitride, silicon oxide, silicon oxynitride, and silicon carbide, or a combination of any two or more of them. The thickness of the isolation layer 9 may be 60nm to 200 nm. The isolation layer 9 may be formed by a method commonly used in the art, for example, LPCVD, APCVD, PECVD, or the like may be used. Illustratively, a PECVD method is used to grow a silicon nitride film on the N-type silicon germanium regions 7, the P-type silicon germanium regions 8, and the region between the N-type silicon germanium regions 7 and the P-type silicon germanium regions 8, such as the intrinsic amorphous silicon layer 6 between the N-type silicon germanium regions 7 and the P-type silicon germanium regions 8, wherein the thickness of the silicon nitride film is 75 nm. It should be appreciated that the spacer layer 9 forms a layer of protection against contamination and oxidation of the intrinsic amorphous silicon layer 6 in the spaces between the N-type silicon germanium regions 7, the P-type silicon germanium regions 8, the N-type silicon germanium regions 7 and the P-type silicon germanium regions 8. And the intrinsic amorphous silicon layer 6 has higher hydrogen content, can provide hydrogen passivation, further enhance the passivation capability of the backlight surface of the silicon substrate and improve the conversion efficiency of the solar cell.
As shown in fig. 6, the electrodes 10 contacting the N-type sige regions 7 and the P-type sige regions 8, respectively, are formed by a screen printing process, and it is understood that the electrodes 10 may be metal electrodes. The metal electrode on the backlight surface of the silicon substrate can be finished by adopting a screen printing or evaporation method. For example: and printing a metallization slurry on the isolation layer 9 corresponding to the N-type silicon germanium region 7 and the P-type silicon germanium region 8 by adopting a screen printing process, sintering to form ohmic contact, and burning through a silicon nitride film below the metal electrode by metal to ensure that the metal electrode is in direct contact with the N-type silicon germanium region 7 and the P-type silicon germanium region 8 respectively. Or opening holes on the N-type silicon germanium silicon region 7 and the P-type silicon germanium region 8 on the backlight surface of the silicon substrate, and preparing metal electrodes by adopting an evaporation method to realize the contact between the metal electrodes and the polycrystalline silicon germanium layer. Of course, other methods may be adopted, and those skilled in the art may select an appropriate method according to the actual situation, which is not described herein again. It will be appreciated that the metal electrode is disposed on the polysilicon germanium layer to avoid direct contact between the electrode 10 and the silicon substrate, and to avoid high recombination in the contact area, thereby not only maintaining a high open circuit voltage but also increasing the fill factor and thus improving the conversion efficiency of the cell. Specifically, the electrode 10 formed on the N-type silicon germanium region 7 is a negative electrode, the electrode 10 formed on the P-type silicon germanium region 8 is a positive electrode, and the positive electrode and the negative electrode are alternately distributed on the backlight surface of the battery.
Thus, the solar cell shown in fig. 6 is formed by the above-described manufacturing method. As shown in fig. 6, in the solar cell manufacturing method of the present disclosure, a backlight passivation layer 5 is formed on a backlight surface of a silicon substrate, an intrinsic amorphous silicon layer 6 is formed on the backlight passivation layer 5, a hard mask is used as a mask on the intrinsic amorphous silicon layer 6, and N-type silicon germanium regions 7 and P-type silicon germanium regions 8 which are alternately distributed and directly contact with the backlight passivation layer 5 are formed through a low temperature chemical vapor deposition process, so as to obtain an N-type passivation contact structure and a P-type passivation contact structure. Because the silicon germanium thin films in the N-type silicon germanium region 7 and the P-type silicon germanium region 8 exist in a polycrystalline form, the carrier mobility is high, the growth rate is high, and meanwhile, the influence of a high-temperature process on the quality of the silicon substrate and the backlight surface passivation layer 5 can be avoided by adopting a low-temperature chemical vapor deposition process. Meanwhile, selective collection of electrons and holes is achieved through the N-type passivation contact structure and the P-type passivation contact structure, the recombination probability of current carriers is greatly reduced, a high open circuit is maintained, the filling factor is improved, and therefore the conversion efficiency of the battery is improved.
As shown in fig. 7, an embodiment of the present invention further provides a solar cell, where the solar cell disclosed herein at least includes a substrate 1, a backlight passivation layer 5 formed on a backlight surface of the substrate 1, and P-type regions and N-type regions alternately distributed on the backlight passivation layer 5, where the P-type regions are P-type silicon germanium regions 8, the N-type regions are N-type silicon germanium regions 7, and an intrinsic amorphous silicon layer 6 distributed on the backlight passivation layer 5 between the P-type silicon germanium regions 8 and the N-type silicon germanium regions 7; an isolation layer 9 formed on the P-type silicon germanium region 8, the N-type silicon germanium region 7 and the intrinsic amorphous silicon layer 6, and an electrode 10 contacting the P-type silicon germanium region 8 and the N-type silicon germanium region 7, respectively, through the isolation layer 9.
Compared with the prior art, the beneficial effects of the solar cell provided by the invention are the same as those of the solar cell manufacturing method in the technical scheme, and the details are not repeated here.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A method of manufacturing a solar cell, comprising:
providing a substrate;
forming a P-type region and an N-type region which are alternately distributed on the backlight surface of the substrate by adopting a hard mask;
and forming electrodes respectively in contact with the P-type region and the N-type region.
2. The method of claim 1, wherein the P-type region is a P-type SiGe region and the N-type region is an N-type SiGe region.
3. The method of claim 2, wherein after providing a substrate, before forming the alternating P-type and N-type regions on a back surface of the substrate using the hard mask, the method further comprises:
and sequentially forming a backlight passivation layer and an intrinsic amorphous silicon layer on the backlight surface of the substrate.
4. The method of claim 3, wherein the forming the alternating P-type and N-type regions with the hard mask comprises:
under the masking of the hard mask, forming alternately distributed P-type regions and N-type regions on the intrinsic amorphous silicon layer by adopting a low-temperature chemical vapor deposition process; the intrinsic amorphous silicon layer corresponding to the positions where the P-type and N-type regions are formed is removed, and the intrinsic amorphous silicon layer between the adjacent P-type and N-type regions is maintained.
5. The method of claim 4, wherein the low temperature chemical vapor deposition process is at a temperature of 300 ℃ to 400 ℃.
6. The method of claim 3, wherein after forming the alternately arranged P-type and N-type regions, and before forming electrodes in contact with the P-type and N-type regions, respectively, the method further comprises:
and forming an isolation layer covering the P-type region, the N-type region and the region between the P-type region and the N-type region.
7. The method of claim 1, wherein forming electrodes in contact with the P-type region and the N-type region, respectively, comprises:
and forming electrodes respectively contacted with the P-type region and the N-type region by adopting a screen printing process.
8. The method for manufacturing a solar cell according to claim 6,
the backlight surface passivation layer is at least one of aluminum oxide and silicon oxide, and the thickness of the backlight surface passivation layer is 1nm-20 nm;
and/or the presence of a gas in the gas,
the isolation layer is at least one of silicon nitride, silicon oxide, silicon oxynitride and silicon carbide, and the thickness of the isolation layer is 60nm-200 nm.
9. The method for manufacturing a solar cell according to claim 1,
the distance between the P type region and the N type region is 5-100 mu m.
10. The solar cell is characterized by at least comprising a substrate, a backlight surface passivation layer formed on a backlight surface of the substrate, a P-type region and an N-type region which are alternately distributed on the backlight surface passivation layer, and an intrinsic amorphous silicon layer distributed on the backlight surface passivation layer between the P-type region and the N-type region; the isolation layer is formed on the P type region, the N type region and the intrinsic amorphous silicon layer, and the electrode penetrates through the isolation layer and is respectively contacted with the P type region and the N type region.
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