CN211907442U - Solar cell with electrode-free front surface - Google Patents
Solar cell with electrode-free front surface Download PDFInfo
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- CN211907442U CN211907442U CN202020490239.2U CN202020490239U CN211907442U CN 211907442 U CN211907442 U CN 211907442U CN 202020490239 U CN202020490239 U CN 202020490239U CN 211907442 U CN211907442 U CN 211907442U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
The utility model discloses a solar wafer that positive face does not have electrode and preparation method thereof has simplified preparation technology and solar wafer has higher conversion efficiency. The solar cell piece comprises: a P-type silicon substrate; an oxide film formed on a back surface of the P-type silicon substrate; a polycrystalline/amorphous silicon layer formed over the oxide film; a back passivation layer formed on the poly/amorphous silicon layer; an N-type doped silicon nitride layer formed on the back passivation layer; a P-type electrode; and an N-type electrode; the P-type silicon substrate is provided with a heavily doped P-type region, a P-type electrode sequentially penetrates through the N-type doped silicon nitride layer, the back passivation layer, the polycrystalline/amorphous silicon layer and the oxide film to form ohmic contact with the heavily doped P-type region of the P-type silicon substrate, and the N-type electrode sequentially penetrates through the N-type doped silicon nitride layer and the back passivation layer to form ohmic contact with the polycrystalline/amorphous silicon layer.
Description
Technical Field
The utility model belongs to crystalline silicon solar cell field relates to a solar wafer of positive electrodeless and preparation method thereof.
Background
With the development of photovoltaic technology, the structures of the cells produced in mass production in the industry at present are all provided with electrode structures on the front and back sides, and the metallized electrode on the front side can shield the incidence of solar light to cause the increase of optical loss. In order to solve this problem, an ibc (indirect back contact) cell structure has been developed, in which both positive and negative electrodes are disposed on the back side of the cell, and no electrode is disposed on the front side, so as to avoid optical shielding of the cell front electrode from incident light. With the development of the passivation contact technology, on the basis of the IBC battery, the back electrode adopts a passivation contact structure (silicon oxide/polycrystalline silicon), the structure reduces the difficulty of the battery process to a certain extent, and simultaneously reduces the carrier recombination at the metal electrode, thereby further improving the conversion efficiency of the battery. However, this structure has the following problems in terms of process implementation.
First, the conventional ICB cell structure employs a high-priced n-type silicon wafer. At present, the price of the n-type silicon wafer is far higher than that of the p-type silicon wafer, for the cost structure of the solar cell, the cost of the silicon wafer is the majority of the cost of the cell, and the cost of the cell is further increased by the n-type silicon wafer.
Secondly, the difficulty of the back graphic design process is high. In order to realize the existence of two cell electrodes of n/p on the back surface and two diffusion areas of an n/p area, the cell process is very complicated.
Thirdly, the problem of the winding plating is difficult to solve. Currently, a silicon oxide/polysilicon passivation contact layer is usually prepared by a Low Pressure Chemical Vapor Deposition (LPCVD) method, but the Deposition method has a wraparound plating during the preparation process, and the Deposition can be deposited on the other side of the battery to cause short circuit, thereby affecting the conversion efficiency of the battery. In order to solve the problem, the edge is usually subjected to wet etching isolation by a wet etching process after the preparation of the passivation contact layer; or a layer of mask layers such as silicon nitride, silicon carbide, silicon oxide and the like is deposited on the other surface in advance, but the realization difficulty and the manufacturing cost are increased in any method in terms of process, and the yield and the industrial application advancing speed are greatly limited;
fourth, the optical parasitic absorption is large. The optical absorption coefficient of the polycrystalline silicon/amorphous silicon layer in the passivation contact layer is high, and when the passivation contact layer is applied to the surface of a battery, the improvement range of the conversion efficiency of the battery is greatly limited due to the problem of large parasitic absorption. To address this problem, the industry typically employs thinner polysilicon/amorphous silicon layers. When a thin polysilicon layer is adopted, later-stage polysilicon doping is difficult to control, and a doping source easily penetrates through a silicon oxide layer to damage the passivation efficiency of the silicon oxide; meanwhile, as the doping source penetrates into the surface of the silicon substrate, the doping concentration of the substrate is increased, the difference value of the doping concentrations at two sides of the silicon oxide layer is reduced, the tunneling probability of carriers is reduced, and the contact resistance is increased.
SUMMERY OF THE UTILITY MODEL
To at least one among the above-mentioned technical problem, the utility model aims at providing a solar wafer and preparation method thereof has simplified preparation technology and solar wafer has higher conversion efficiency.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
a solar cell sheet comprising:
a P-type silicon substrate;
an oxide film formed on a back surface of the P-type silicon substrate;
a polycrystalline/amorphous silicon layer formed over the oxide film;
a back passivation layer formed on the poly/amorphous silicon layer;
an N-type doped silicon nitride layer formed on the back passivation layer;
a P-type electrode; and
an N-type electrode;
the P-type silicon substrate is provided with a heavily doped P-type region, the P-type electrode sequentially penetrates through the N-type doped silicon nitride layer, the back passivation layer, the polycrystalline/amorphous silicon layer and the oxide film to form ohmic contact with the heavily doped P-type region of the P-type silicon substrate, and the N-type electrode sequentially penetrates through the N-type doped silicon nitride layer and the back passivation layer to form ohmic contact with the polycrystalline/amorphous silicon layer.
In one embodiment, the P-type electrodes and the N-type electrodes are alternately arranged and isolated from each other, the area occupied by the P-type electrodes is 1-20% of the total area of the back surface of the solar cell, and the area occupied by the N-type electrodes is larger than that occupied by the P-type electrodes.
Preferably, the P-type electrode has a first body and a plurality of first fingers, the N-type electrode has a second body and a plurality of second fingers, the first body and the second body are juxtaposed, at least some of the first fingers and the second fingers are located between the first body and the second body and are staggered, and each of the first fingers is adjacent to at least one of the second fingers.
More preferably, the length of the first and/or second fingers is greater than half the spacing of the first and second bodies.
More preferably, the first body and the second body extend in a longitudinal direction, and the first finger and the second finger extend in a transverse direction.
In one embodiment, the P-type silicon substrate is doped with boron or gallium.
Furthermore, the heavily doped P-type region is doped with one or more of boron, aluminum, gallium and indium, and the doping concentration of the heavily doped P-type region is greater than that of other regions of the P-type silicon substrate.
In one embodiment, the doping element of the N-type doped silicon nitride layer is phosphorus.
In one embodiment, the oxide film is a silicon oxide film.
In one embodiment, the solar cell further comprises a front passivation layer formed on the P-type silicon substrate and an anti-reflection layer formed on the front passivation layer.
The utility model adopts the above scheme, compare prior art and have following advantage:
the utility model discloses a solar wafer and preparation method thereof through N type doping silicon nitride layer, has avoided around plating phenomenons such as washing, mask, has simplified technology, and the productivity promotes the yield and promotes, and the cost is descended. And because the front surface of the solar cell is not optically shielded by the electrode, the conversion efficiency is greatly improved.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic cross-sectional view of a part of a solar cell according to an embodiment of the present invention;
fig. 2 is a schematic back view of a part of a solar cell according to an embodiment of the present invention.
Wherein,
1. an anti-reflective layer; 2. a front passivation layer; 3. a P-type silicon substrate; 31. heavily doped P-type region; 4. an oxide film; 5. a polycrystalline/amorphous silicon layer; 6. a back passivation layer; 7. an N-type doped silicon nitride layer; 8. a P-type electrode; 81. a first body; 82. a first finger portion; 9. an N-type electrode; 91. a second body; 92. a second finger.
Detailed Description
The following detailed description of the preferred embodiments of the invention, taken in conjunction with the accompanying drawings, enables the advantages and features of the invention to be more readily understood by those skilled in the art. It should be noted that the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited thereto. Furthermore, the technical features mentioned in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The present embodiment provides a solar cell, which has no electrode on the front surface and no electrode on the front surface, and prevents the light incident on the front surface of the solar cell from being blocked. Fig. 1 shows a partial cross section of the solar cell sheet. Referring to fig. 1, the solar cell comprises an anti-reflection layer 1, a front passivation layer 2, a P-type silicon substrate 3, an oxide film 4, a polycrystalline/amorphous silicon layer 5, a back passivation layer 6 and a doped silicon nitride layer 7, which are sequentially stacked, and further comprises a P-type electrode 8 and an N-type electrode 9 arranged on the back. Wherein the P-type silicon substrate 3 has one or more heavily doped P-type regions 31. The P-type electrode 8 sequentially penetrates through the N-type doped silicon nitride layer 7, the back passivation layer 6, the polycrystalline/amorphous silicon layer 5 and the oxide film 4 to form ohmic contact with the heavily doped P-type region 31 of the P-type silicon substrate 3. The N-type electrode 9 is in ohmic contact with the poly/amorphous silicon layer 5 through the N-type doped silicon nitride layer 7 and the back passivation layer 6 in this order.
In the embodiment, the front passivation layer 2 is an aluminum oxide layer deposited on the front surface of the P-type silicon substrate 3, and the thickness is 1-10 nm; it may also be a silicon oxide layer. The antireflection layer 1 is a silicon nitride antireflection layer 1 formed on the front passivation layer 2, and the thickness of the antireflection layer 1 is 40-150 nm. The resistivity of the P-type silicon substrate 3 is 0.4-1.5 omega-cm, and the doping element is boron or gallium; a plurality of heavily doped P-type regions 31 are formed In the silicon substrate, the doping element is one or more of B, Al, Ga and In, and the doping concentration of the doping element is higher than that of other regions of the silicon substrate. The oxide film 4 is a silicon oxide film formed on the back surface of the P-type silicon substrate 3, and has a thickness of 1 to 5 nm. The polycrystalline/amorphous silicon layer 5 is formed on the oxide film 4 to have a thickness of 10 to 80 nm. An N-doped silicon nitride layer 7 is deposited on the poly/amorphous silicon layer 5, the doping element being phosphorus. The P-type electrode 8 includes one or more of Al, Cu, Ag. The N-type electrode 9 includes one or both of Cu and Ag.
Fig. 2 shows a part of the back side of the solar cell sheet. Referring to fig. 2, the solar cell includes a plurality of P-type electrodes 8 and a plurality of N-type electrodes 9 isolated from each other; the P-type electrodes 8 and the N-type electrodes 9 are arranged in a staggered mode and are isolated from each other. The area occupied by the P-type electrode 8 is 1-20% of the total area of the back surface of the solar cell, and the area occupied by the N-type electrode 9 is larger than that occupied by the P-type electrode 8. Each P-type electrode 8 has a first body 81 and a plurality of first fingers 82, and each N-type electrode 9 has a second body 91 and a plurality of second fingers 92. Any one of the first bodies 81 is adjacent to and juxtaposed with at least one of the second bodies 91, at least a portion of the first fingers 82 and the second fingers 92 are disposed between the first bodies 81 and the second bodies 91 and are arranged alternately, and each of the first fingers 82 is adjacent to at least one of the second fingers 92, thereby forming interdigitated electrodes on the back side of the solar cell. Preferably, the length of the first finger 82 and/or the second finger 92 is greater than half of the distance between the adjacent first body 81 and the second body 91, that is, the first finger 82 or the second finger 92 extends to most of the distance between the adjacent first body 81 and the second body 91. Further, the first body 81 and the second body 91 extend in the longitudinal direction, and the first finger 82 and the second finger 92 extend in the transverse direction, respectively. The current carriers can be effectively separated, and meanwhile, the resistance loss of the current carriers which are conducted to the main grid line through the thin grid line and output to the outside is reduced.
The embodiment also provides a preparation method of the solar cell, which comprises the following steps:
A. preparing an oxide film 4 on the back of the silicon wafer after texturing;
B. depositing a polycrystalline/amorphous silicon layer 5 on the back of the silicon wafer;
C. respectively depositing a passivation layer on the front side and the back side of the silicon wafer;
D. depositing an antireflection layer 1 on the front side of the silicon wafer;
E. depositing an N-type doped silicon nitride layer 7 on the back of the silicon wafer;
F. performing laser grooving on the N-type silicon nitride layer, the back passivation layer 6, the polycrystalline/amorphous silicon layer 5 and the oxide film 4 to form a patterned grooved area;
G. printing the slurry of the P-type electrode 8 in the slotted area;
H. printing slurry of an N-type electrode 9 on a non-groove area on the back of the silicon wafer;
I. and (5) sintering.
The step A is specifically implemented as follows: and carrying out thermal oxidation on the textured silicon wafer, and introducing mixed gas of oxygen and nitrogen into a tubular thermal oxidation furnace at a flow ratio of 1: 0.1-1: 15 for 5-30 min and at a temperature of 650 plus 800 ℃.
The step B is specifically implemented as follows: in the tube type LPCVD furnace, the front surface of a silicon wafer in a quartz boat is close to an insert, the pressure is 50 mtorr-20 torr, the flow ratio of silane and argon gas mixed gas is 1: 0-1: 1, the time is 5-30 min, the temperature is 650-800 ℃, and the deposition thickness is 20-200 nm.
The preparation method also comprises a surface cleaning step before the step C, so as to remove the polycrystalline/amorphous silicon layer which is plated around the front side of the silicon wafer. The method comprises the following specific steps: contacting the single side of the silicon wafer with an alkali solution (NaOH, KOH, TMAOH, ammonia water and other alkali solutions) with the front side facing downwards, and cleaning the silicon wafer to a polycrystalline/amorphous silicon layer which is plated around the front side in 2-10 min; immersing the silicon wafer into an HF acid solution for 2-10 min, wherein the volume percentage concentration of the HF acid solution is 5-20%; then washing with deionized water for 1-5 min.
The step C is specifically implemented as follows: and depositing aluminum oxide layers on the two sides of the silicon wafer in the ALD equipment, wherein the deposition thicknesses are respectively 1-10 nm.
The step D is implemented specifically as follows: depositing a doped silicon nitride layer in a tubular PECVD device, wherein the reaction gas is silane and ammonia gas, the flow ratio is 1:6 to 1:15, the deposition temperature is 440 ℃ to 700 ℃, the gas pressure range is 1600 Torr to 1800 Torr, the power range is 13000W to 25000W, and the doped silicon nitride layer with the refractive index of 1.9 to 2.4 and the film thickness of 50 to 200nm is deposited.
The step E is specifically implemented as follows: depositing a doped silicon nitride layer in a tubular PECVD device, wherein the reaction gas is silane and ammonia gas, the flow ratio is 1:6: to 1:15, the deposition temperature is 440 ℃ to 700 ℃, the gas pressure range is 1600 Torr to 1800 Torr, the power range is 13000W to 25000W, and the doped silicon nitride film with the refractive index of 1.9-2.4 and the film thickness of 50-200 nm is deposited. Doping source gas is introduced in the deposition process to realize doping, and the N-type doping source can be gas of VA group elements such as phosphorus and the like, and can be similar gas such as phosphine, phosphorus oxychloride and the like.
The step F is specifically implemented as follows: and carrying out patterned laser ablation membrane opening on the region to be formed with the P-type electrode on the back of the silicon wafer by using laser membrane opening equipment, and ablating the N-type doped silicon nitride layer 7, the back passivation layer 6, the polycrystalline/amorphous silicon layer 5 and the oxide film 4 in the region, wherein the diameter of a laser spot is 20-70 mu m, and the laser spot interval is 0-1 mu m. The laser open die pattern is shown in the area covered by the P-type electrode 8 in FIG. 2
The step G is specifically implemented as follows: and printing aluminum paste and silver paste in the film opening area through screen printing, wherein the linear width of the aluminum paste and the silver paste is larger than the diameter of a laser spot, specifically 50-2000 mu m, and the printing pattern is shown in the area where the P-type electrode 8 is positioned in the figure 2.
The step H is specifically implemented as follows: silver paste is printed on the non-film-opening area by screen printing, the width of the silver paste is 5-100 mu m, and the printing pattern is shown in the area where the N-type electrode 9 is positioned in figure 2.
The step I is implemented specifically as follows: co-firing is carried out through a sintering furnace under a certain sintering curve. The P-type electrode 8 region forms a P + + heavily doped layer, i.e., a middle doped region as shown in fig. 1; the N-type electrode 9 burns through the N-type doped silicon nitride layer 7, the back passivation layer 6 and the polycrystalline/amorphous silicon layer 5 to form ohmic contact; meanwhile, the doping element in the doped silicon nitride layer 7 in fig. 1 dopes the aluminum oxide layer region during sintering to form a doped poly/amorphous silicon layer 5.
The preparation method also comprises an annealing step after the step E or the step F. In this embodiment, an annealing step is performed after step E, and an annealing step is performed after step F. The annealing step is specifically implemented as follows: annealing in an annealing furnace at 700-1100 ℃ for 5-30 min to ensure more sufficient doping.
The preparation method avoids the phenomena of plating cleaning, masking and the like through a film layer doping technology, greatly simplifies the process, and is suitable for a polycrystalline/amorphous silicon layer with lower thickness in the doping process. Compared with the prior art, the preparation method of the solar cell greatly simplifies the process, the process steps of more than 20 steps in the prior art are simplified to about 10 steps, the yield is improved, and the cost is greatly reduced. And because the front surface of the solar cell is not optically shielded by the electrode, the conversion efficiency is greatly improved.
The above embodiments are only for illustrating the technical concept and features of the present invention, and are preferred embodiments, which are intended to enable persons skilled in the art to understand the contents of the present invention and to implement the present invention, and thus, the protection scope of the present invention cannot be limited thereby. All equivalent changes or modifications made according to the principles of the present invention are intended to be covered by the scope of the present invention.
Claims (7)
1. A solar cell, comprising:
a P-type silicon substrate;
an oxide film formed on a back surface of the P-type silicon substrate;
a polycrystalline/amorphous silicon layer formed over the oxide film;
a back passivation layer formed on the poly/amorphous silicon layer;
an N-type doped silicon nitride layer formed on the back passivation layer;
a P-type electrode; and
an N-type electrode;
the P-type silicon substrate is provided with a heavily doped P-type region, the P-type electrode sequentially penetrates through the N-type doped silicon nitride layer, the back passivation layer, the polycrystalline/amorphous silicon layer and the oxide film to form ohmic contact with the heavily doped P-type region of the P-type silicon substrate, and the N-type electrode sequentially penetrates through the N-type doped silicon nitride layer and the back passivation layer to form ohmic contact with the polycrystalline/amorphous silicon layer.
2. The solar cell sheet according to claim 1, wherein: the P-type electrodes and the N-type electrodes are arranged in a staggered mode and are isolated from each other, the occupied area of the P-type electrodes is 1-20% of the total area of the back face of the solar cell piece, and the occupied area of the N-type electrodes is larger than that of the P-type electrodes.
3. The solar cell sheet according to claim 2, wherein: the P-type electrode is provided with a first body and a plurality of first fingers, the N-type electrode is provided with a second body and a plurality of second fingers, the first body and the second body are arranged in parallel, the first fingers extend from the first body to the adjacent second body, the second fingers extend from the second body to the adjacent first body, at least part of the first fingers and the second fingers are positioned between the first body and the second body and are arranged in a staggered mode, and each first finger is adjacent to at least one second finger.
4. The solar cell sheet according to claim 3, wherein: the length of the first and/or second fingers is greater than half of the spacing of the first and second bodies.
5. The solar cell sheet according to claim 3, wherein: the first body and the second body extend longitudinally, respectively, and the first finger and the second finger extend transversely, respectively.
6. The solar cell sheet according to claim 1, wherein: the oxide film is a silicon oxide film.
7. The solar cell sheet according to claim 1, wherein: the solar cell piece also comprises a front passivation layer formed on the P-type silicon substrate and an antireflection layer formed on the front passivation layer.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111477695A (en) * | 2020-04-07 | 2020-07-31 | 苏州腾晖光伏技术有限公司 | Solar cell with electrode-free front surface and preparation method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111477695A (en) * | 2020-04-07 | 2020-07-31 | 苏州腾晖光伏技术有限公司 | Solar cell with electrode-free front surface and preparation method thereof |
| CN111477695B (en) * | 2020-04-07 | 2024-07-16 | 苏州腾晖光伏技术有限公司 | Front-side electrodeless solar cell and preparation method thereof |
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