JP2019054028A - Semiconductor device, and display device - Google Patents

Abstract

To provide a semiconductor device capable of high integration.SOLUTION: A transistor 100 and a transistor 100A can be formed on the same substrate 102 via the same process. The transistor 100 and a transistor 100A have the substantially same configuration, excepting presence or absence of a sidewall insulation layer, different channel length and channel width, and different thickness of the gate insulation layer. The insulation layer 316 is provided to cover the top face of an insulation layer 110a, the lateral face of a metal oxide layer 114, and the lateral face of a conductive layer 112. An insulation layer 316 has a function as a sidewall insulation layer. A metal oxide layer 117 is provided to cover the top face of an insulation layer 104, the top face and the lateral face of a semiconductor layer 108, the lateral faces of the insulation layer 110a and the insulation layer 316, and the top face of the conductive layer 112. An insulation layer 118 is provided to cover the metal oxide layer 117.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a semiconductor device, a display device, and a manufacturing method thereof. One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor film and a manufacturing method thereof.

  Note that one embodiment of the present invention is not limited to the above technical field. Technical fields of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, and driving methods thereof , Or a method for producing them, can be mentioned as an example.

  Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor, a semiconductor circuit, an arithmetic device, a memory device, or the like is one embodiment of a semiconductor device. In addition, an imaging device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like) and an electronic device may include a semiconductor device.

  In recent years, semiconductor devices have been developed, and LSIs, CPUs, and memories are mainly used. The CPU is an aggregate of semiconductor elements having a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer and formed with electrodes serving as connection terminals.

  A semiconductor circuit (IC chip) such as an LSI, a CPU, or a memory is mounted on a circuit board, for example, a printed wiring board, and used as one of various electronic device components. In addition, a display device having high resolution has been studied to reduce the number of components by incorporating peripheral circuits such as driver circuits.

  Therefore, a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material. For example, in Patent Document 1, a plurality of oxide semiconductor layers are stacked, and among the plurality of oxide semiconductor layers, the oxide semiconductor layer serving as a channel contains indium and gallium, and the proportion of indium is the proportion of gallium. A semiconductor device is disclosed in which the field effect mobility (which may be simply referred to as mobility or μFE) is increased by increasing the field effect mobility.

JP 2014-7399 A

A semiconductor device requires a plurality of transistors having different functions depending on the intended use and required electrical characteristics. Therefore, it is desirable to make transistors separately so as to have the required characteristics.

In view of the above, an object of one embodiment of the present invention is to provide a transistor that can operate at high speed and has a low driving voltage and a thin film transistor that has high withstand voltage and high reliability with respect to voltage. Another object is to provide a highly reliable semiconductor device. Another object is to provide a novel semiconductor device. Another object is to provide a highly reliable display device. Another object is to provide a novel display device.

  Note that the description of these problems does not disturb the existence of other problems. In one embodiment of the present invention, it is not necessary to solve all of these problems. Issues other than those described above can be extracted from the description, drawings, claims, and the like.

One embodiment of the present invention includes a first transistor and a second transistor, and the first transistor includes a first semiconductor layer, a first insulating layer, a first conductive layer, A first insulating layer positioned between the first semiconductor layer and the first conductive layer, and an end portion of the first conductive layer is defined by the first insulating layer. The sidewall insulating layer is in contact with the upper surface of the first insulating layer and the side surface of the first conductive layer, and the second transistor includes the second semiconductor layer and the second insulating layer. And a second conductive layer, the second insulating layer is located between the second semiconductor layer and the second conductive layer, and the second gate insulating layer is The semiconductor device is thicker than the gate insulating layer.

In the above-described semiconductor device, the sidewall insulating layer preferably has the same material as the second insulating layer, and more preferably is formed by processing the same insulating film as the second insulating layer.

In the above semiconductor device, the second transistor further includes a third insulating layer, and the third insulating layer is located between the second semiconductor layer and the second insulating layer. It is preferable that the upper surface shape of the insulating layer and the second insulating layer substantially coincide with each other.

In the above semiconductor device, the third insulating layer preferably has the same material as the first insulating layer, and more preferably is formed by processing the same insulating film as the first insulating layer.

In the above-described semiconductor device, the width of the first conductive layer in the channel length direction is preferably smaller than the width of the second conductive layer in the channel length direction.

In the above semiconductor device, each of the first semiconductor layer and the second semiconductor layer preferably includes a metal oxide.

One embodiment of the present invention is a display device including the above-described semiconductor device and a liquid crystal element or a light-emitting element which is electrically connected to the semiconductor device.

  According to one embodiment of the present invention, a semiconductor device that can operate at high speed and has a low driving voltage and a thin film transistor that has high withstand voltage and high reliability with respect to voltage can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a novel semiconductor device can be provided. Alternatively, a highly reliable display device can be provided. Alternatively, a novel display device can be provided.

2 shows a structure example of a transistor. 2 shows a structure example of a transistor. 2 shows a structure example of a transistor. 2 shows a structure example of a transistor. 10A to 10D illustrate a method for manufacturing a transistor. 10A to 10D illustrate a method for manufacturing a transistor. 10A to 10D illustrate a method for manufacturing a transistor. The top view of a display apparatus. Sectional drawing of a display apparatus. Sectional drawing of a display apparatus. Sectional drawing of a display apparatus. Sectional drawing of a display apparatus. Sectional drawing of a display apparatus. The block diagram and circuit diagram of a display apparatus. The block diagram of a display apparatus. Configuration example of an electronic device. Configuration example of an electronic device. 2 shows a configuration example of a television device.

  Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

  In each drawing described in this specification, the size, the layer thickness, or the region of each component is exaggerated for clarity in some cases. Therefore, it is not necessarily limited to the scale.

  In addition, the ordinal numbers “first”, “second”, and “third” used in the present specification are given in order to avoid confusion between components, and are not limited numerically.

  In addition, in this specification, terms indicating arrangement such as “above” and “below” are used for convenience to describe the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.

  In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel formation region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and between the source and drain via the channel formation region. A current can flow. Note that in this specification and the like, a channel formation region refers to a region through which a current mainly flows.

  In addition, the functions of the source and drain may be switched when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.

  In this specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In the case of “OS FET”, it can be said to be a transistor including a metal oxide or an oxide semiconductor.

  Further, in this specification and the like, there are cases where they are described as CAAC (c-axis aligned crystal) and CAC (Cloud-aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material structure.

  In this specification and the like, a CAC-OS or a CAC-metal oxide has a conductive function in part of a material and an insulating function in part of the material, and the whole material is a semiconductor. It has the function of. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

  In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in a material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. There is.

  Moreover, CAC-OS or CAC-metal oxide is comprised by the component which has a different band gap. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.

  That is, CAC-OS or CAC-metal oxide can also be called a matrix composite material or a metal matrix composite material.

  The CAAC structure is one of crystal structures such as a thin film having a plurality of nanocrystals (a crystal region having a maximum diameter of less than 10 nm), and each nanocrystal has a c-axis oriented in a specific direction, and The a-axis and the b-axis are crystal structures having the characteristics that the nanocrystals are continuously connected without forming a grain boundary without having orientation. In particular, a thin film having a CAAC structure has a feature that the c-axis of each nanocrystal is easily oriented in the thickness direction of the thin film, the normal direction of the surface to be formed, or the normal direction of the surface of the thin film.

(Embodiment 1)
In this embodiment, a structural example of a semiconductor device of one embodiment of the present invention and an example of a manufacturing method thereof will be described.

One embodiment of the present invention is a semiconductor device including a first transistor and a second transistor, in which the first transistor and the second transistor are provided over the same substrate. The first transistor and the second transistor have different structures. The first transistor is a thin transistor with a thin gate insulating layer. The first transistor is provided with an insulating layer functioning as a sidewall (hereinafter also referred to as a sidewall insulating layer) in contact with the top surface of the gate insulating film and the side surface of the gate electrode. With such a structure, the first transistor can be a transistor that operates at high speed and low voltage. The second transistor is a transistor having a thicker gate insulating layer than the first transistor. With such a structure, the second transistor can be a transistor with high withstand voltage.

By providing transistors with different structures over the same substrate, the degree of integration of the semiconductor device can be increased. Alternatively, different functions can be given to each transistor by providing transistors with different structures over the same substrate. For example, in the case where a semiconductor device including transistors having different structures is used for a display device, one transistor can be used for a driver circuit portion and the other transistor can be used for a transistor in a pixel portion. In addition, transistors with different structures can be manufactured through substantially the same process, and a semiconductor device having transistors with different structures can be manufactured with high productivity.

In the case of using a semiconductor device for a display device, for example, a first transistor that operates at high speed is applied to one of transistors provided in a driver circuit, and a second transistor with high breakdown voltage is applied to one of transistors provided in a pixel. Transistors can be applied.

The first transistor is a transistor including a semiconductor layer on which a channel is formed, a gate insulating layer on the semiconductor layer, and a gate electrode on the gate insulating layer. The first transistor is preferably a so-called top gate transistor in which a gate electrode is provided over a semiconductor layer with a gate insulating layer interposed therebetween.

As the semiconductor layer, crystalline silicon, polycrystalline silicon, amorphous silicon, metal oxide, organic semiconductor, carbon nanotube, or the like can be used. The semiconductor layer preferably includes a metal oxide exhibiting semiconductor characteristics (hereinafter also referred to as an oxide semiconductor). Moreover, as a metal oxide, it is preferable that an energy gap is 2 eV or more, Preferably it is 2.5 eV or more. By using a metal oxide having a large energy gap, off-state current of the transistor can be reduced.

In the first transistor, the end portion of the gate electrode is located inside the end portion of the gate insulating layer.

The semiconductor layer has a region where a channel can be formed in a portion overlapping with the gate electrode (hereinafter also referred to as a channel formation region). Further, the semiconductor layer has a pair of low resistance regions sandwiching the channel formation region. The low resistance region functions as a source or a drain.

  The low resistance region is a region having a higher carrier concentration than the channel formation region. For example, the low resistance region can be a region containing more hydrogen than the channel formation region or a region containing more oxygen vacancies than the channel formation region. When an oxygen vacancy and a hydrogen atom in an oxide semiconductor are combined, a carrier generation source is obtained.

  The semiconductor layer preferably has a first region between the channel formation region and the low resistance region. When the transistor is not in operation, the first region is a region having the same carrier concentration as the channel formation region and a carrier concentration lower than that of the low resistance region. For example, the first region is a region where the content of hydrogen and oxygen vacancies is approximately the same as that of the channel formation region, and the content of either one or both of hydrogen and oxygen vacancies is lower than that of the low resistance region. be able to.

  The carrier concentration in the first region may not be uniform and may have a gradient such that the concentration decreases from the low resistance region side to the channel formation region side. For example, any one or more of the contents of hydrogen or oxygen vacancies in the first region may have a gradient such that the concentration decreases from the low resistance region side to the channel formation region side.

  When processing for forming a low resistance region in the semiconductor layer (hydrogen supply processing or oxygen deficiency formation processing) is performed, the resistance reduction is suppressed by covering part of the semiconductor layer with a sidewall insulating layer. The first region having a carrier concentration lower than that of the low resistance region can be formed.

  With such a structure, the channel formation region and the low-resistance region can be prevented from being in contact with each other. This prevents hydrogen from diffusing from the low resistance region to the channel formation region due to heat applied during the manufacturing process, or oxygen vacancies from being diffused from the oxygen in the channel formation region to the low resistance region. Can do. Accordingly, the carrier concentration in the channel formation region can be extremely reduced, and a transistor having good and stable electrical characteristics can be realized.

In addition, since the first region is provided at both ends of the channel formation region, the electric field applied between the low resistance regions, particularly the electric field concentration in the vicinity of the low resistance region in contact with the drain electrode can be reduced. Voltage fluctuations can be suppressed. In addition, since electric field concentration can be reduced, the transistor can be prevented from being destroyed by electric field concentration. In other words, the transistor is a transistor with improved breakdown voltage and suppressed deterioration of electrical characteristics. Further, by having the first region, it is possible to reduce deterioration in a voltage-temperature stress test in which a voltage is applied to the drain electrode and deterioration in current stress. In particular, in a transistor with a short channel length, the breakdown of the transistor or the deterioration of electric characteristics may occur due to electric field concentration. The transistor according to one embodiment of the present invention includes the first region, so that the withstand voltage is improved. Thus, a transistor in which deterioration of electrical characteristics is suppressed can be obtained. Note that the first region can be referred to as an offset region.

The sidewall insulating layer and the gate insulating layer are preferably formed in a self-aligned manner without using a photomask. For example, by forming a sidewall insulating film to be a sidewall insulating layer and performing anisotropic etching on the sidewall insulating film, the sidewall along the upper surface of the gate insulating film and the side surface of the gate electrode An insulating layer is formed. Subsequently, the sidewall insulating layer and the gate insulating layer can be formed in a self-aligning manner by etching the gate insulating film to be the gate insulating layer using the sidewall insulating layer as a mask.

The second transistor is a transistor including a semiconductor layer in which a channel is formed, a gate insulating layer over the semiconductor layer, and a gate electrode over the gate insulating layer over a formation surface. The first transistor is preferably a so-called top gate transistor in which a gate electrode is provided over a semiconductor layer with a gate insulating layer interposed therebetween.

As the semiconductor layer, crystalline silicon, polycrystalline silicon, amorphous silicon, metal oxide, organic semiconductor, carbon nanotube, or the like can be used. The semiconductor layer preferably includes a metal oxide exhibiting semiconductor characteristics (hereinafter also referred to as an oxide semiconductor). Moreover, as a metal oxide, it is preferable that an energy gap is 2 eV or more, Preferably it is 2.5 eV or more. By using a metal oxide having a large energy gap, off-state current of the transistor can be reduced.

The gate insulating film of the second transistor is thicker than the gate insulating film of the first transistor. With such a structure, the second transistor can be a transistor with high withstand voltage.

In addition to the above, in one embodiment of the present invention, the second gate electrode is provided below the semiconductor layer, and the second gate insulating layer is provided between the second gate electrode and the semiconductor layer. It is preferable to have. At this time, the gate electrode over the semiconductor layer can also be referred to as a first gate electrode, and the gate insulating layer over the semiconductor layer can be referred to as a first gate insulating layer.

<Configuration example of semiconductor device>
A transistor that can be used in the semiconductor device of one embodiment of the present invention is described below with reference to drawings. Here, two types of transistors having different structures will be described. In the following description, components common to the two transistors are denoted by the same reference numerals, and redundant description may be omitted.

[Configuration example 1]
A top view of the transistor 100 is shown in FIG. 1A1, and cross-sectional views thereof are shown in FIGS. 1B1 and 1C1. 1B1 corresponds to a cross-sectional view of the cross section taken along the dashed-dotted line A1-A2 in FIG. 1A1, and FIG. 1C1 is cut along the dashed-dotted line B1-B2 in FIG. 1A1. It corresponds to a sectional view of the surface.

A top view of the transistor 100A is shown in FIG. 1A2, and cross-sectional views thereof are shown in FIGS. 1B2 and 1C2. 1B2 corresponds to a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 1A2, and FIG. 1C2 is cut along dashed-dotted line B3-B4 in FIG. 1A2. It corresponds to a sectional view of the surface.

  Note that in FIGS. 1A1 and 1A2, some components (such as a gate insulating layer) of the transistor 100 and the transistor 100A are not illustrated. The alternate long and short dash lines A1-A2 direction and A3-A4 direction may be referred to as a channel length direction, and the alternate long and short dash lines B1-B2 direction and B3-B4 direction may be referred to as a channel width direction.

  The transistor 100 and the transistor 100A are transistors that can be formed over the same substrate 102 through the same steps. The transistor 100 and the transistor 100A have substantially the same structure except that a sidewall insulating layer is present, a channel length and a channel width are different, and a gate insulating layer is different in thickness.

  First, the transistor 100 is described.

  The transistor 100 includes an insulating layer 104, a semiconductor layer 108, an insulating layer 110a, a metal oxide layer 114, a conductive layer 112, an insulating layer 316, a metal oxide layer 117, an insulating layer 118, and the like. The semiconductor layer 108 is provided over the insulating layer 104. The insulating layer 110a, the metal oxide layer 114, and the conductive layer 112 are stacked over the semiconductor layer 108 in this order.

The insulating layer 316 is provided so as to cover the upper surface of the insulating layer 110 a, the side surface of the metal oxide layer 114, and the side surface of the conductive layer 112. The insulating layer 316 functions as a sidewall insulating layer. The metal oxide layer 117 is provided to cover the top surface of the insulating layer 104, the top and side surfaces of the semiconductor layer 108, the side surfaces of the insulating layer 110 a and the insulating layer 316, and the top surface of the conductive layer 112. The insulating layer 118 is provided so as to cover the metal oxide layer 117.

  Part of the conductive layer 112 functions as a gate electrode. Part of the insulating layer 110a functions as a gate insulating layer. The transistor 100 is a so-called top gate transistor in which a gate electrode is provided over the semiconductor layer 108.

  The conductive layer 112 and the metal oxide layer 114 have substantially the same top shape. The end portions of the conductive layer 112 and the metal oxide layer 114 are located inside the end portions of the insulating layer 110a.

  Note that in this specification and the like, “the top surface shape is approximately the same” means that at least a part of the contour overlaps between the stacked layers. For example, the case where the upper layer and the lower layer are processed by the same mask pattern or a part thereof by the same mask pattern is included. However, strictly speaking, the contours do not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer.

An enlarged view of a cross section in the channel length direction of the transistor 100 is illustrated in FIG. In the transistor 100, the semiconductor layer 108 includes a region 108i overlapping with the conductive layer 112, a pair of regions 108x sandwiching the region 108i, and a pair of regions 108n sandwiching the region 108i and the region 108x.

The region 108i functions as a channel formation region.

In the semiconductor layer 108, a pair of regions that are located outside the region 108i, do not overlap with the conductive layer 112, and overlap with the insulating layer 316 are referred to as regions 108x. It can be said that the region 108 x overlaps with the insulating layer 316 in the semiconductor layer 108. In addition, as illustrated in FIG. 2A, the upper surface of the region 108x is preferably provided in contact with the insulating layer 110a.

  The region 108x is a part of the semiconductor layer 108, and is a region having the same carrier concentration as that of the region 108i when the transistor is not operating. The region 108x is a region having a lower carrier concentration than the region 108n.

In the semiconductor layer 108, a pair of regions located outside the region 108i and the pair of regions 108x is referred to as a region 108n. As shown in FIG. 2A, the upper surface of the region 108n is preferably provided in contact with the metal oxide layer 117.

  The region 108n is a part of the semiconductor layer 108 and has a lower resistance than the regions 108i and 108x. The region 108n is a region having a higher carrier concentration than the regions 108i and 108x, an n-type region, or a region having a high hydrogen concentration.

  The region 108x is located between the region 108i and the region 108n and can also be referred to as a first region.

  Note that the carrier concentration in the region 108x may not be uniform, and may have a gradient such that the concentration decreases from the region 108n side to the region 108i side. For example, either or both of the hydrogen concentration and the oxygen deficiency concentration in the region 108x may have a gradient such that the concentration decreases from the region 108n side to the region 108i side.

  The insulating layer 316 is provided in contact with the upper surface of the insulating layer 110 a and the side surfaces of the metal oxide layer 114 and the conductive layer 112.

  With such a structure, as described later, the insulating layer 316 can be formed in a self-aligned manner, so that a photomask for forming the insulating layer 316 is not necessary and manufacturing cost is reduced. it can. In addition, since the insulating layer 316 is formed in a self-aligning manner so that relative displacement between the insulating layer 316 and the conductive layer 112 does not occur, a pair of regions functioning as the first region in the semiconductor layer 108 The width of 108x can be roughly matched.

The width of the region 108x in the channel length direction is 10 nm to 10 μm, preferably 30 nm to 5 μm, and more preferably 50 nm to 1 μm. If the width of the region 108x in the channel length direction is long, the effective channel length becomes long and the driving speed of the transistor may be slow. With the above width, a transistor with high driving speed can be obtained.

  The insulating layer 316 can be formed using a material similar to that of the insulating layer 110a or the insulating layer 118, for example. For example, as the insulating layer 316, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used.

  As described later, the insulating layer 316 is preferably formed by processing the same insulating film as the insulating layer 210 of the transistor 100A. Thus, the insulating layer 316 can be formed without increasing the number of steps.

  With the insulating layer 316, the physical distance between the conductive layer 112 and the conductive layer 120a or 120b can be increased. Accordingly, parasitic capacitance between the conductive layer 112 and the conductive layer 120a and between the conductive layer 112 and the conductive layer 120b can be reduced in some cases.

  Here, as illustrated in FIG. 2A, the channel length L1 in the transistor 100 is the width of the conductive layer 112 in the channel length direction. Further, as illustrated in FIG. 1C1, the channel width W1 in the transistor 100 is a width in a channel width direction in a portion of the semiconductor layer 108 which overlaps with the conductive layer 112.

  Further, as illustrated in FIGS. 1A1 and 1B1, the transistor 100 may include a conductive layer 120a and a conductive layer 120b over the insulating layer 118. The conductive layer 120a and the conductive layer 120b function as a source electrode or a drain electrode. The conductive layer 120a and the conductive layer 120b are electrically connected to the region 108n through the opening 141a or the opening 141b provided in the metal oxide layer 117 and the insulating layer 118, respectively.

  The insulating layer 110a functioning as a gate insulating layer preferably has a function of releasing oxygen by heating. Accordingly, oxygen can be supplied into the region 108i and the region 108x by heat treatment after formation of the insulating layer 110a. Accordingly, oxygen vacancies that can be formed in the regions 108i and 108x can be filled; thus, a highly reliable semiconductor device can be provided.

  The metal oxide layer 114 located between the insulating layer 110a and the conductive layer 112 functions as a barrier film that prevents oxygen released from the insulating layer 110a from diffusing to the conductive layer 112 side. For the metal oxide layer 114, for example, a material that is less likely to transmit oxygen than the insulating layer 110a can be used.

  In this structure, since the metal oxide layer 114 having a high barrier property is provided between the conductive layer 112 and the insulating layer 110a, a metal that easily absorbs oxygen such as aluminum or copper is used for the conductive layer 112. Even in this case, oxygen can be prevented from diffusing from the insulating layer 110a to the conductive layer 112. Further, even when the conductive layer 112 contains hydrogen, supply of hydrogen from the conductive layer 112 to the semiconductor layer 108 through the insulating layer 110a is suppressed. As a result, the carrier concentration in the region 108 i that is the channel formation region of the semiconductor layer 108 can be reduced.

  As the metal oxide layer 114, an insulating material or a conductive material can be used. In the case where the metal oxide layer 114 has an insulating property, it functions as part of the gate insulating layer. On the other hand, when the metal oxide layer 114 has conductivity, it functions as a part of the gate electrode.

  In particular, as the metal oxide layer 114, an insulating material having a dielectric constant higher than that of silicon oxide is preferably used. In particular, an aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, or the like is preferably used.

Alternatively, a metal oxide film containing no nitrogen as a main component, such as an aluminum oxide film or a hafnium oxide film, can be used between the semiconductor layer 108 and the conductive layer 112 functioning as a gate electrode. Therefore, the metal oxide layer 114 can form a level in the film of nitrogen oxide (NO _x , x is larger than 0 and 2 or less, preferably 1 or more and 2 or less, typically NO ₂ or NO). It can be set as the structure with very little content. Thereby, a transistor having excellent electrical characteristics and reliability can be realized.

  Aluminum oxide films, hafnium oxide films, hafnium aluminate films, etc. have sufficiently high barrier properties even when they are thin (for example, about 5 nm thick), so they can be formed thin and improve productivity. Can be made. For example, the thickness of the metal oxide layer 114 can be 1 nm to 50 nm, preferably 3 nm to 30 nm. Furthermore, an aluminum oxide film, a hafnium oxide film, and a hafnium aluminate film have a feature that the dielectric constant is higher than that of a silicon oxide film or the like. As described above, since an insulating film having a high dielectric constant can be formed thin as the metal oxide layer 114, the strength of the gate electric field applied to the semiconductor layer 108 can be increased as compared with the case where a silicon oxide film or the like is used. As a result, the drive voltage can be lowered and the power consumption can be reduced.

  The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an aluminum oxide film is formed using a sputtering apparatus, oxygen can be preferably added to the semiconductor layer 108 by being formed in an atmosphere containing oxygen gas. In addition, when an aluminum oxide film is formed using a sputtering apparatus, the film density can be increased, which is preferable.

  In the case where a conductive material is used for the metal oxide layer 114, an oxide conductive material such as indium oxide or indium tin oxide can be used. Alternatively, a metal oxide that can be used for the semiconductor layer 108 may be used. In particular, a material containing the same element as the semiconductor layer 108 is preferably used. At this time, for example, it is preferable to form by a sputtering method using the same metal oxide target as the semiconductor layer 108 because a film formation apparatus can be shared.

  In addition, it is preferable that the metal oxide layer 114 hardly diffuses water or hydrogen. Accordingly, even when the conductive layer 112 uses a material that easily diffuses water or hydrogen, it is possible to prevent water and hydrogen from diffusing into the insulating layer 110a and the semiconductor layer 108. In particular, an aluminum oxide film or a hafnium oxide film is preferable because of its high barrier property against water and hydrogen.

  The metal oxide layer 117 is preferably formed using a material that does not easily transmit oxygen. Accordingly, oxygen can be prevented from being released from the semiconductor layer 108, the insulating layer 110a, and the like due to heat applied during the process and diffused to the insulating layer 118 side. Therefore, an increase in carrier concentration in the region 108i functioning as a channel formation region can be prevented, and a highly reliable transistor can be realized.

  As the metal oxide layer 117, a film similar to the metal oxide layer 114 can be used. By providing the metal oxide layer 117 and the metal oxide layer 114, the carrier concentration of the region 108i functioning as a channel formation region of the semiconductor layer 108 can be more effectively reduced.

  Here, oxygen vacancies that can be formed in the semiconductor layer 108 will be described.

  Oxygen deficiency formed in the semiconductor layer 108 is a problem because it affects transistor characteristics. For example, when an oxygen vacancy is formed in the semiconductor layer 108, hydrogen is bonded to the oxygen vacancy and can serve as a carrier supply source. When a carrier supply source is generated in the semiconductor layer 108, a change in electrical characteristics of the transistor 100, typically, a threshold voltage shift occurs. Therefore, it is preferable that the semiconductor layer 108 has fewer oxygen vacancies.

  Therefore, in one embodiment of the present invention, the insulating film in the vicinity of the semiconductor layer 108, specifically, the insulating layer 110a formed over the semiconductor layer 108 has a structure containing oxygen that can be released by heating. By transferring oxygen from the insulating layer 110a to the semiconductor layer 108, oxygen vacancies in the semiconductor layer 108 can be reduced.

  Note that the insulating layer 104 located below the semiconductor layer 108 may contain oxygen that can be released by heating. At this time, oxygen vacancies in the semiconductor layer 108 can be further reduced by transferring oxygen also from the insulating layer 104 to the semiconductor layer 108.

  Here, in the case where the semiconductor layer 108 is a metal oxide containing In, Ga, and Zn, the bonding force between In and oxygen is weaker than the bonding force between Ga and oxygen, so that when the atomic ratio of In is large, Oxygen vacancies are easily formed in the metal oxide film. Further, even when the metal element represented by M is used instead of Ga, there is a similar tendency. When many oxygen vacancies exist in the metal oxide film, the electrical characteristics and reliability of the transistor are deteriorated.

  However, in one embodiment of the present invention, a very large amount of oxygen can be supplied into the semiconductor layer 108 containing a metal oxide; thus, a metal oxide material having a large atomic ratio of In can be used. Thus, a transistor having extremely high field effect mobility, stable electrical characteristics, and high reliability can be realized.

  For example, a metal oxide in which the atomic ratio of In is 1.5 times or more, or 2 times or more, or 3 times or more, or 3.5 times or more, or 4 times or more of the atomic ratio of M Can be preferably used.

  In particular, the ratio of the number of atoms of In, M, and Zn in the semiconductor layer 108 is preferably In: M: Zn = 5: 1: 6 or the vicinity thereof. Here, in the vicinity, when In is 5, M is 0.5 or more and 1.5 or less, and Zn is 5 or more and 7 or less.

  Note that the semiconductor layer 108 is not limited to the above composition. For example, the ratio of the number of In, M, and Zn atoms in the semiconductor layer 108 is preferably In: M: Zn = 4: 2: 3 or the vicinity thereof.

  Further, as the composition of the semiconductor layer 108, the ratio of the number of atoms of In, M, and Zn in the semiconductor layer 108 may be approximately equal. That is, the ratio of the number of atoms of In, M, and Zn may include In: M: Zn = 1: 1: 1 or a material in the vicinity thereof. Further, the ratio of the number of atoms of In, M, and Zn may include a material in the vicinity of In: M: Zn = 1: 1: 0.5.

When the semiconductor layer 108 has a region where the atomic ratio of In is larger than the atomic ratio of M, the field-effect mobility of the transistor 100 can be increased. Specifically, the field-effect mobility of the transistor 100 can exceed 10 cm ² / Vs, and more preferably, the field-effect mobility of the transistor 100 can exceed 30 cm ² / Vs.

  For example, a display device with a narrow frame width (also referred to as a narrow frame) can be provided by using the above transistor with high field-effect mobility for a gate driver that generates a gate signal. In addition, the transistor with high field-effect mobility described above is used for a source driver that supplies signals from a signal line included in a display device (particularly, a demultiplexer connected to an output terminal of a shift register included in the source driver). Thus, a display device with a small number of wirings connected to the display device can be provided.

  Note that even when the semiconductor layer 108 has a region where the atomic ratio of In is larger than the atomic ratio of M, the field-effect mobility may be low when the semiconductor layer 108 has high crystallinity.

  The crystallinity of the semiconductor layer 108 can be analyzed by, for example, analyzing using X-ray diffraction (XRD: X-Ray Diffraction), or analyzing using a transmission electron microscope (TEM: Transmission Electron Microscope). .

  Here, impurities such as hydrogen or moisture mixed in the semiconductor layer 108 are problematic because they affect the transistor characteristics. Therefore, it is preferable that the semiconductor layer 108 have fewer impurities such as hydrogen or moisture.

As the semiconductor layer 108, a metal oxide film with a low impurity concentration and a low density of defect states is preferably used because a transistor having excellent electrical characteristics can be manufactured. Here, low impurity concentration and low defect level density (low oxygen deficiency) are referred to as high purity intrinsic or substantially high purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic metal oxide film has a small number of carrier generation sources, and thus can have a low carrier concentration. Therefore, a transistor in which a channel formation region is formed in the metal oxide film rarely has electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. In addition, since a highly purified intrinsic or substantially highly purified intrinsic metal oxide film has a low defect level density, the trap level density may also be low. In addition, a highly purified intrinsic or substantially highly purified intrinsic metal oxide film has an extremely small off-state current, a channel width of 1 × 10 ⁶ μm, and a channel length of 10 μm. When the voltage between the electrodes (drain voltage) is in the range of 1V to 10V, the off-state current can be less than the measurement limit of the semiconductor parameter analyzer, that is, 1 × 10 ⁻¹³ A or less.

  Further, the semiconductor layer 108 may have a stacked structure of two or more layers.

  For example, the semiconductor layer 108 in which two or more metal oxide films having different compositions are stacked can be used.

  For example, when an In—Ga—Zn oxide is used, the ratio of the number of atoms of In, M, and Zn is In: M: Zn = 5: 1: 6, In: M: Zn = 4: 2: 3. In: M: Zn = 1: 1: 1, In: M: Zn = 1: 3: 4, In: M: Zn = 1: 3: 2, or a film formed with a sputtering target in the vicinity thereof Of these, it is preferable to use two or more layers.

  Alternatively, the semiconductor layer 108 in which two or more metal oxide films having different crystallinity are stacked can be used.

  For example, in the case where the semiconductor layer 108 is formed by stacking two metal oxide films with different crystallinity, the same oxide target is used and the film formation conditions are different, so that the semiconductor layer 108 is continuously formed without being exposed to the atmosphere. Is preferred.

  For example, the oxygen flow rate ratio at the time of forming the first metal oxide film formed first is made smaller than the oxygen flow rate ratio at the time of forming the second metal oxide film formed later. Alternatively, oxygen is not allowed to flow when the first metal oxide film is formed. Thereby, oxygen can be effectively supplied when forming the second metal oxide film. In addition, the first metal oxide film can be a film having lower crystallinity and higher electrical conductivity than the second metal oxide film. On the other hand, the second metal oxide film provided on the upper part is a film having higher crystallinity than the first metal oxide film, so that damage during the processing of the semiconductor layer 108 or the film formation of the insulating layer 110a. Can be suppressed. For example, a CAC-OS film can be used for the first metal oxide film, and a CAAC-OS film can be used for the second metal oxide film.

  More specifically, the oxygen flow rate ratio during the formation of the first metal oxide film is 0% or more and less than 50%, preferably 0% or more and 30% or less, more preferably 0% or more and 20% or less. Specifically, it is 10%. The oxygen flow rate ratio during the formation of the second metal oxide film is 50% to 100%, preferably 60% to 100%, more preferably 80% to 100%, and still more preferably 90% or more. 100% or less, typically 100%. In addition, the first metal oxide film and the second metal oxide film may have different conditions such as pressure, temperature, and power at the time of film formation, but the conditions other than the oxygen flow rate ratio are the same. This is preferable because the time required for the film forming process can be shortened.

  When the semiconductor layer 108 has such a stacked structure, a transistor with excellent electrical characteristics and high reliability can be realized.

  Next, the transistor 100A will be described. Hereinafter, differences from the transistor 100 will be mainly described. Since the above description can be used for a portion common to the transistor 100, a detailed description thereof is omitted.

  The transistor 100A includes the insulating layer 104, the semiconductor layer 108, the insulating layer 110b, the insulating layer 210, the metal oxide layer 314, the conductive layer 312, the metal oxide layer 117, the insulating layer 118, and the like. The semiconductor layer 108 is provided over the insulating layer 104. The insulating layer 110b, the insulating layer 210, the metal oxide layer 314, and the conductive layer 312 are stacked over the semiconductor layer 108 in this order. The metal oxide layer 117 is provided to cover the upper surface of the insulating layer 104, the upper surface and side surfaces of the semiconductor layer 108, the side surfaces of the insulating layer 110b, the insulating layer 210, and the metal oxide layer 314, and the side surfaces and upper surface of the conductive layer 312. ing. The insulating layer 118 is provided so as to cover the metal oxide layer 117.

  Part of the conductive layer 312 functions as a gate electrode. Part of the insulating layer 110b and the insulating layer 210 functions as a gate insulating layer. The transistor 100A is a so-called top-gate transistor in which a gate electrode is provided over the semiconductor layer 108.

  In addition, the conductive layer 112, the metal oxide layer 114, the insulating layer 210, and the insulating layer 110b have substantially the same top shape.

An enlarged view of a cross section of the transistor 100A in the channel length direction is illustrated in FIG. In the transistor 100, the semiconductor layer 108 includes a region 108i that overlaps with the conductive layer 112 and a pair of regions 108n that sandwich the region 108i.

  The transistor 100A includes an insulating layer 110b and an insulating layer 210 which function as a gate insulating layer. The total thickness of the insulating layer 110 b and the insulating layer 210 is thicker than at least the insulating layer 110 a included in the transistor 100. The insulating layer 210 can be formed using the same material as the insulating layer 316. Note that the interface between the insulating layer 110b and the insulating layer 210 may not be clearly observed by cross-sectional observation. Even in that case, in the composition analysis such as SIMS analysis, the etching gas components (for example, fluorine, chlorine, boron, etc.) of the conductive film 112f and the metal oxide film 114f may be detected in the vicinity of the interface.

  The thickness of the insulating layer 110b can be, for example, 5 nm to 50 nm, preferably 10 nm to 40 nm, more preferably 10 nm to 30 nm. Here, since the metal oxide film applicable to the semiconductor layer 108 can increase the flatness of the surface, a highly reliable transistor can be realized even when the insulating layer 110b is thinned to about 5 nm. it can.

  The thickness of the insulating layer 210 may be at least greater than the thickness of the insulating layer 110a, and may be, for example, 30 nm to 300 nm, preferably 50 nm to 250 nm, more preferably 100 nm to 200 nm. Note that the thickness of the insulating layer 210 is not limited to this, and may be larger than 300 nm depending on a withstand voltage characteristic required for the transistor 100A.

  FIG. 2B shows the channel length L2 of the transistor 100A, and FIG. 1C2 shows the channel width W2 of the transistor 100A.

  The channel length L1 of the transistor 100 is shorter than the channel length L2 of the transistor 100A. In addition, the channel width W2 of the transistor 100A may be approximately the same as or larger than the channel width W1 of the transistor 100.

  The channel length L1 of the transistor 100 is less than 1.5 μm, preferably 1.2 μm or less, more preferably 1.0 μm or less, further preferably 0.9 μm or less, more preferably 0.8 μm or less, and further preferably 0.6 μm. It is below and it is preferable that it is 0.1 micrometer or more. On the other hand, the channel length L2 of the transistor 100A is 1 μm or more, preferably 1.2 μm or more, more preferably 1.4 μm or more, and is 20 μm or less, preferably 15 μm or less, more preferably 10 μm or less. Note that the channel length L1 of the transistor 100 and the channel length L2 of the transistor 100A are not limited to this, and can be set to optimum sizes according to required transistor characteristics.

  Here, in a transistor using general polysilicon, an impurity is doped in order to reduce the resistance of the source region and the drain region. At this time, part of the doped impurities diffuses into the channel formation region. Therefore, when the channel length L is extremely shortened (for example, 3 μm or less), it may be difficult to obtain transistor characteristics. On the other hand, the transistor 100 to which the metal oxide of one embodiment of the present invention is applied can obtain favorable transistor characteristics even when the channel length L is reduced to 0.7 μm or less.

  In addition, since the general polysilicon film has extremely large surface undulations due to crystallization, there is a problem that a sufficient gate breakdown voltage cannot be obtained if the gate insulating layer is made thinner than the undulations. . Therefore, in a transistor using a general polysilicon film, it is difficult to make the gate insulating layer thin, and the thickness needs to be about 100 nm even if it is thin. On the other hand, since the surface of the metal oxide film used for the semiconductor layer 108 of the transistor 100 of one embodiment of the present invention is extremely flat, the thickness of the insulating layer 110a functioning as a gate insulating layer is sufficiently thin (eg, 20 nm). The following):

  The above is the description of the configuration example 1.

[Configuration example 2]
A structural example of a transistor having a part of the structure different from that of the above structural example 1 will be described. In addition, below, description may be abbreviate | omitted about the part which overlaps with the structural example 1. FIG. Further, in the drawings shown below, portions having the same functions as those of the configuration example 1 have the same hatching pattern and may not be denoted by reference numerals.

A top view of the transistor 100B is shown in FIG. 3A1, and cross-sectional views thereof are shown in FIGS. 3B1 and 3C1. 3B1 corresponds to a cross-sectional view of the cross section taken along the dashed-dotted line A1-A2 in FIG. 3A1, and FIG. 3C1 is cut along the dashed-dotted line B1-B2 shown in FIG. 3A1. It corresponds to a sectional view of the surface.

A top view of the transistor 100C is shown in FIG. 3A2, and cross-sectional views thereof are shown in FIGS. 3B2 and 3C2. 3B2 corresponds to a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 3A2, and FIG. 3C2 is cut along dashed-dotted line B3-B4 in FIG. 3A2. It corresponds to a sectional view of the surface.

  Similar to the relationship between the transistor 100 and the transistor 100A, the transistor 100B and the transistor 100C are different in the presence or absence of the sidewall insulating layer, the channel length and the channel width, and the thickness of the insulating layer functioning as the gate insulating layer. It is mainly different in point.

  The transistor 100B and the transistor 100C are mainly different from the structure example 1 in that the conductive layer 106 is provided between the substrate 102 and the insulating layer 104. The conductive layer 106 has a portion overlapping with the semiconductor layer 108 with the insulating layer 104 interposed therebetween.

  In the transistor 100B and the transistor 100C, the conductive layer 106 functions as a first gate electrode (also referred to as a bottom gate electrode), and the conductive layer 112 serves as a second gate electrode (also referred to as a top gate electrode). It has a function. A part of the insulating layer 104 functions as a first gate insulating layer, and a part of the insulating layer 110a or the insulating layer 210 functions as a second gate insulating layer.

An enlarged view of a cross section of the transistor 100B in the channel length direction is illustrated in FIG. In the transistor 100B, the semiconductor layer 108 includes a region 108i overlapping with the conductive layer 112, a pair of regions 108x sandwiching the region 108i, and a pair of regions 108n sandwiching the region 108i and the region 108x.

The region 108i functions as a channel formation region.

In the semiconductor layer 108, a pair of regions that are located outside the region 108i, do not overlap with the conductive layer 112, and overlap with the insulating layer 316 are referred to as regions 108x. It can be said that the region 108 x overlaps with the insulating layer 316 in the semiconductor layer 108. As shown in FIG. 4A, the upper surface of the region 108x is preferably provided in contact with the insulating layer 110a.

  The region 108x is a part of the semiconductor layer 108, and is a region having the same carrier concentration as that of the region 108i when the transistor is not operating. The region 108x is a region having a lower carrier concentration than the region 108n.

In the semiconductor layer 108, a pair of regions located outside the region 108i and the pair of regions 108x is referred to as a region 108n. As shown in FIG. 4A, the upper surface of the region 108n is preferably provided in contact with the metal oxide layer 117.

  The region 108n is a part of the semiconductor layer 108 and has a lower resistance than the regions 108i and 108x. The region 108n is a region having a higher carrier concentration than the regions 108i and 108x, an n-type region, or a region having a high hydrogen concentration.

  A portion of the semiconductor layer 108 that overlaps with at least one of the conductive layer 112 and the conductive layer 106 functions as a channel formation region. Note that a portion overlapping with the conductive layer 112 of the semiconductor layer 108 (a portion corresponding to the region 108 i) is sometimes referred to as a channel formation region in the following description for ease of explanation. In addition, a channel can be formed in a portion overlapping with the conductive layer 106 (a portion corresponding to the region 108x and the region 108n).

  Here, as illustrated in FIGS. 3A1 and 3B1, the channel length L1 of the transistor 100B is the width of the conductive layer 112 positioned above the semiconductor layer 108 in the channel length direction. Further, as illustrated in FIGS. 3A1 and 3C1, the channel width W1 in the transistor 100B is a width in a channel width direction in a portion overlapping with the conductive layer 112 of the semiconductor layer 108. The same applies to the channel length L2 and the channel width W2 of the transistor 100C.

  In addition, as illustrated in FIGS. 3C1 and 3C2, the conductive layer 106 is electrically connected to the conductive layer 112 through an opening 142 provided in the insulating layer 104 and the insulating layer 110a or the insulating layer 210. It may be connected to. Accordingly, the same potential can be applied to the conductive layer 106 and the conductive layer 112.

  The conductive layer 106 can be formed using a material similar to that of the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, the conductive layer 106 is preferably formed using a material containing copper because resistance can be reduced.

  In addition, as illustrated in FIGS. 3A1 and 3C1, 3A2, and 3C2, the conductive layer 112 and the conductive layer 106 are end portions of the semiconductor layer 108 in the channel width direction. It is preferable to protrude outward. At this time, as illustrated in FIGS. 3C1 and 3C2, the entire semiconductor layer 108 in the channel width direction is electrically connected to the conductive layer 112 through the insulating layer 110a or the insulating layer 210 and the insulating layer 104. The structure is covered with the layer 106.

  With such a structure, the semiconductor layer 108 can be electrically surrounded by an electric field generated by the pair of gate electrodes. At this time, it is particularly preferable to apply the same potential to the conductive layer 106 and the conductive layer 112. Accordingly, an electric field for inducing a channel can be effectively applied to the semiconductor layer 108, so that the on-state current of the transistor 100B and the transistor 100C can be increased. Therefore, the transistor 100B can be miniaturized.

  Note that the conductive layer 112 and the conductive layer 106 may not be connected to each other. At this time, a constant potential may be applied to one of the pair of gate electrodes, and a signal for driving the transistor 100B or the transistor 100C may be applied to the other. At this time, the threshold voltage when the transistor 100B or the transistor 100C is driven by the other electrode can be controlled by the potential applied to the one electrode.

  The above is the description of the configuration example 2.

  In each transistor illustrated in Structural Example 1 and Structural Example 2, the metal oxide layer 117 and the insulating layer 118 are provided between the gate electrode located above the semiconductor layer 108 and the source and drain electrodes. Compared with a bottom-gate transistor, the parasitic capacitance between them is reduced. In particular, the insulating layer 118 has little influence on the electrical characteristics of the transistor even when the thickness is increased, and thus parasitic capacitance can be further reduced. Therefore, each of the transistors exemplified in Configuration Example 1 and Configuration Example 2 can be easily driven at a high frequency, and thus can be suitably used for a display portion of a display device or a drive circuit portion.

<Constituent elements of semiconductor device>
Next, components included in the semiconductor device of the present embodiment will be described in detail.

〔substrate〕
There is no particular limitation on the material of the substrate 102, but it is necessary that the substrate 102 have at least heat resistance to withstand heat treatment performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. In addition, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied, and a semiconductor element is provided over these substrates. A substrate may be used as the substrate 102.

  Alternatively, a flexible substrate may be used as the substrate 102, and the transistor 100 or the like may be formed directly over the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and the transistor 100 or the like. The separation layer can be used for separation from the substrate 102 and transfer to another substrate after the semiconductor device is partially or entirely completed thereon. At that time, the transistor 100 or the like can be transferred to a substrate having poor heat resistance or a flexible substrate.

[Insulating layer 104]
The insulating layer 104 can be formed using a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. As the insulating layer 104, for example, an oxide insulating film or a nitride insulating film can be formed as a single layer or a stacked layer. Note that in order to improve interface characteristics with the semiconductor layer 108, at least a region in contact with the semiconductor layer 108 in the insulating layer 104 is preferably formed using an oxide insulating film. Further, by using an oxide insulating film from which oxygen is released by heating as the insulating layer 104, oxygen contained in the insulating layer 104 can be transferred to the semiconductor layer 108 by heat treatment.

  The thickness of the insulating layer 104 can be greater than or equal to 50 nm, or greater than or equal to 100 nm and less than or equal to 3000 nm, or greater than or equal to 200 nm and less than or equal to 1000 nm. By increasing the thickness of the insulating layer 104, the amount of oxygen released from the insulating layer 104 can be increased, and interface states at the interface between the insulating layer 104 and the semiconductor layer 108 and oxygen vacancies included in the semiconductor layer 108 can be reduced. Is possible.

  As the insulating layer 104, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga—Zn oxide can be used, and the insulating layer 104 can be provided as a single layer or a stacked layer. In this embodiment, a stacked structure of a silicon nitride film and a silicon oxynitride film is used as the insulating layer 104. In this manner, oxygen can be efficiently introduced into the semiconductor layer 108 by using the insulating layer 104 as a stacked structure and using a silicon nitride film on the lower layer side and a silicon oxynitride film on the upper layer side.

  Alternatively, a film other than an oxide film such as a silicon nitride film can be used on the side in contact with the semiconductor layer 108 of the insulating layer 104. At this time, it is preferable to perform pretreatment such as oxygen plasma treatment on the surface of the insulating layer 104 in contact with the semiconductor layer 108 to oxidize the surface of the insulating layer 104 or the vicinity thereof.

[Conductive film]
As the conductive layer 112 functioning as a gate electrode, the conductive layer 312 and the conductive layer 106, the conductive layer 120a functioning as a source electrode, and the conductive layer 120b functioning as a drain electrode, chromium, copper, aluminum, gold, silver, zinc, molybdenum , Tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, an alloy containing the above metal elements, or an alloy that combines the above metal elements. it can.

  The conductive layer 112 functioning as a gate electrode, the conductive layer 312 and the conductive layer 106, the conductive layer 120a functioning as a source electrode, and the conductive layer 120b functioning as a drain electrode include an oxide containing indium and tin (In- Sn oxide), oxide containing indium and tungsten (In-W oxide), oxide containing indium, tungsten and zinc (In-W-Zn oxide), oxide containing indium and titanium ( In-Ti oxide), oxide containing indium, titanium and tin (In-Ti-Sn oxide), oxide containing indium and zinc (In-Zn oxide), indium, tin and silicon. Oxides (In-Sn-Si oxide), oxides including indium, gallium, and zinc (In-Ga-Zn oxide) It is also possible to apply a conductor or a metal oxide film.

  Here, the oxide conductor will be described. In this specification and the like, the oxide conductor may be referred to as OC (Oxide Conductor). As an oxide conductor, for example, when an oxygen vacancy is formed in a metal oxide and hydrogen is added to the oxygen vacancy, a donor level is formed in the vicinity of the conduction band. As a result, the metal oxide becomes highly conductive and becomes a conductor. The conductive metal oxide can be referred to as an oxide conductor. In general, a metal oxide has a large energy gap and thus has a light-transmitting property with respect to visible light. On the other hand, an oxide conductor is a metal oxide having a donor level near the conduction band. Therefore, the oxide conductor is less affected by the absorption due to the donor level and has a light-transmitting property similar to that of the metal oxide with respect to visible light.

  Alternatively, the conductive layer 112, the conductive layer 312, and the conductive layer 106 may have a stacked structure of a conductive film including the oxide conductor (metal oxide) and a conductive film including a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced. At this time, a conductive film including an oxide conductor is preferably applied to a side in contact with the insulating layer functioning as a gate insulating film.

  The conductive layer 112, the conductive layer 312, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b include a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). May be applied. By using a Cu-X alloy film, it can be processed by a wet etching process, and thus manufacturing costs can be suppressed.

  In addition, the conductive layer 112, the conductive layer 312, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b may be any one selected from titanium, tungsten, tantalum, and molybdenum among the above metal elements, or It is preferable to have a plurality. In particular, a tantalum nitride film is preferably used as the conductive layer 112, the conductive layer 312, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b. The tantalum nitride film has conductivity and high barrier properties against copper or hydrogen. Further, since the tantalum nitride film emits less hydrogen from itself, it can be preferably used as a conductive film in contact with the semiconductor layer 108 or a conductive film in the vicinity of the semiconductor layer 108.

[Insulating layer 316, insulating layer 110a, insulating layer 110b, insulating layer 210]
As the insulating layer 316 functioning as a sidewall insulating layer, such as the transistor 100, the insulating layer 110 a functioning as a gate insulating film, the insulating layer 110 b, and the insulating layer 210, plasma enhanced chemical vapor deposition (PECVD) is used. ) Method, sputtering method, etc., silicon oxide film, silicon oxynitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, An insulating layer including one or more of a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film can be used. Note that the insulating layer 316, the insulating layer 110a, the insulating layer 110b, or the insulating layer 210 may have a two-layer structure or a three-layer structure.

  The insulating layer 110a in contact with the semiconductor layer 108 functioning as a channel formation region of the transistor 100 or the like is preferably an oxide insulating film, and includes a region containing excess oxygen than the stoichiometric composition (excess oxygen region). ) Is more preferable. In other words, the insulating layer 110a is an insulating film capable of releasing oxygen. Note that in order to provide the excess oxygen region in the insulating layer 110a, for example, the insulating layer 110a may be formed in an oxygen atmosphere, or the insulating layer 110a after film formation may be heat-treated in an oxygen atmosphere.

  Further, when hafnium oxide is used for the insulating layer 316, the insulating layer 110a, the insulating layer 110b, and the insulating layer 210, the following effects can be obtained. Hafnium oxide has a higher dielectric constant than silicon oxide or silicon oxynitride. Accordingly, the thickness of the insulating layer 316, the insulating layer 110a, the insulating layer 110b, and the insulating layer 210 can be increased as compared with the case where silicon oxide is used, so that a leakage current due to a tunnel current can be reduced. That is, a transistor with a small off-state current can be realized. Further, hafnium oxide having a crystal structure has a higher dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with low off-state current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include a monoclinic system and a cubic system. Note that one embodiment of the present invention is not limited thereto.

The insulating layer 316, the insulating layer 110a, the insulating layer 110b, and the insulating layer 210 preferably have few defects. Typically, it is preferable that the number of signals observed by electron spin resonance (ESR) be small. . For example, the signal described above includes the E ′ center where the g value is observed at 2.001. The E ′ center is caused by silicon dangling bonds. As the insulating layer 316, the insulating layer 110a, the insulating layer 110b, and the insulating layer 210, the spin density due to the E ′ center is 3 × 10 ¹⁷ spins / cm ³ or less, preferably 5 × 10 ¹⁶ spins / cm ³ or less. A silicon oxide film or a silicon oxynitride film may be used.

[Semiconductor layer 108]
In the case where the semiconductor layer 108 is an In-M-Zn oxide, the atomic ratio of the metal elements of the sputtering target used for forming the In-M-Zn oxide preferably satisfies In> M. As the atomic ratio of the metal elements of such a sputtering target, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 6, In: M: Zn = 5: 1: 7, In: M: Zn = 5: 1: 8, In: M: Zn = 6: 1: 6, In: M: Zn = 5: 2: 5, and the like.

  In the case where the semiconductor layer 108 is an In-M-Zn oxide, a target including a polycrystalline In-M-Zn oxide is preferably used as the sputtering target. By using a target including a polycrystalline In—M—Zn oxide, the semiconductor layer 108 having crystallinity can be easily formed. Note that the atomic ratio of the semiconductor layer 108 to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element included in the sputtering target. For example, when the composition of the sputtering target used for the semiconductor layer 108 is In: Ga: Zn = 4: 2: 4.1 [atomic ratio], the composition of the semiconductor layer 108 to be formed is In: Ga: Zn = It may be in the vicinity of 4: 2: 3 [atomic ratio].

  The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a wide energy gap.

  The semiconductor layer 108 preferably has a non-single crystal structure. The non-single-crystal structure includes, for example, a CAAC-OS (C Axis Crystalline Oxide Semiconductor), a polycrystalline structure, a microcrystalline structure, or an amorphous structure. In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

  The above is the description of the components of the semiconductor device.

<Example of production method>
Hereinafter, an example of a method for forming two transistors having different structures on the same substrate will be described. Here, the transistor 100 and the transistor 100A exemplified in the above configuration example 1 are described as examples.

A thin film (insulating film, semiconductor film, conductive film, etc.) constituting a semiconductor device is formed by sputtering, chemical vapor deposition (CVD), vacuum evaporation, or pulse laser deposition (PLD). Further, it can be formed by using an atomic layer deposition (ALD) method or the like. Examples of the CVD method include a plasma enhanced chemical vapor deposition (PECVD) method and a thermal CVD method. As one of thermal CVD methods, there is a metal organic chemical vapor deposition (MOCVD) method.

  In addition, thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices are spin coating, dipping, spray coating, ink jet, dispensing, screen printing, offset printing), doctor knives, slit coating, rolls, etc. Tools (equipment) such as a coat, a curtain coat, and a knife coat can be used.

  Further, when a thin film included in the semiconductor device is processed, the thin film can be processed using a photolithography method or the like. In addition, the thin film may be processed by a nanoimprint method, a sand blast method, a lift-off method, or the like. Further, the island-shaped thin film may be directly formed by a film forming method using a shielding mask such as a metal mask.

  As a photolithography method, there are typically the following two methods. One is a method in which a resist mask is formed on a thin film to be processed, the thin film is processed by etching or the like, and the resist mask is removed. The other is a method in which a thin film having photosensitivity is formed and then exposed and developed to process the thin film into a desired shape.

  In photolithography, light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or light obtained by mixing these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can be used. Further, exposure may be performed by an immersion exposure technique. Further, extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may be used as light used for exposure. Further, an electron beam can be used instead of the light used for exposure. It is preferable to use extreme ultraviolet light, X-rays, or an electron beam because extremely fine processing is possible. Note that a photomask is not necessary when exposure is performed by scanning a beam such as an electron beam.

  For etching the thin film, a dry etching method, a wet etching method, a sand blasting method, or the like can be used.

  5 and 7 are cross-sectional views in the channel length direction for describing a method for manufacturing the transistor 100 and the transistor 100A. In each figure, the left side from the broken line at the center is a region where the transistor 100 is formed, and the right side is a region where the transistor 100A is formed.

[Formation of Insulating Layer 104]
First, the insulating layer 104 is formed over the substrate 102. The insulating layer 104 can be formed by a plasma CVD method, an ALD method, a sputtering method, or the like.

  Note that in the case where the conductive layer 106 described in Structural Example 2 is provided, the conductive layer 106 can be formed before the insulating layer 104 is formed. The conductive layer 106 can be formed by forming a conductive film over the substrate 102 and processing it by etching.

[Formation of Semiconductor Layer 108]
Subsequently, a metal oxide film 108f is formed over the insulating layer 104 (FIG. 5A).

  The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target.

  In forming the metal oxide film 108f, an inert gas (eg, helium gas, argon gas, xenon gas, or the like) may be mixed in addition to the oxygen gas. Note that the ratio of oxygen gas to the entire deposition gas when forming the metal oxide film (hereinafter also referred to as oxygen flow ratio) is 0% to 100%, preferably 5% to 20%. It is preferable to do. A transistor with an increased on-state current can be obtained by reducing the oxygen flow rate ratio and forming the metal oxide film 108f with relatively low crystallinity.

  The metal oxide film 108f may be formed at a substrate temperature of room temperature to 250 ° C., preferably a substrate temperature of 130 ° C. to less than 220 ° C. It is preferable that the substrate temperature at the time of forming the metal oxide film 108f be, for example, room temperature or higher and lower than 220 ° C. because productivity is increased. In addition, by forming the metal oxide film with the substrate temperature being high, it is easy to form a metal oxide film with high crystallinity. In addition, when the metal oxide film 108f is formed with the substrate temperature set to room temperature or without intentional heating, the metal oxide film 108f with low crystallinity can be easily formed.

  The thickness of the metal oxide film 108f may be 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 60 nm.

  Note that when a large glass substrate (for example, the sixth generation to the twelfth generation) is used as the substrate 102, the substrate temperature when the metal oxide film 108f is formed is 220 ° C. or higher and 300 ° C. or lower. 102 may be deformed (distorted or warped). Therefore, in the case where a large glass substrate is used, deformation of the glass substrate can be suppressed by setting the substrate temperature at the time of forming the metal oxide film 108f to a room temperature or higher and lower than 220 ° C.

  In addition, it is necessary to increase the purity of the sputtering gas. For example, oxygen gas or argon gas used as a sputtering gas is a gas having a dew point of −40 ° C. or lower, preferably −80 ° C. or lower, more preferably −100 ° C. or lower, more preferably −120 ° C. or lower. By using it, moisture and the like can be prevented from being taken into the metal oxide film 108f as much as possible.

In the case where the metal oxide film 108f is formed by a sputtering method, the chamber in the sputtering apparatus is provided with an adsorption-type vacuum exhaust pump such as a cryopump so as to remove water or the like that is an impurity for the metal oxide as much as possible. It is preferable to use and exhaust to a high vacuum (from about 5 × 10 ⁻⁷ Pa to about 1 × 10 ⁻⁴ Pa). In particular, the partial pressure of gas molecules corresponding to H ₂ O in the chamber (gas molecules corresponding to m / z = 18) in the standby state of the sputtering apparatus is 1 × 10 ⁻⁴ Pa or less, preferably 5 × 10 ^−5. It is preferable to set it to Pa or less.

  Further, before the metal oxide film 108f is formed, heat treatment for desorbing water or hydrogen adsorbed on the surface of the insulating layer 104 is preferably performed. For example, heat treatment can be performed at a temperature of 70 ° C to 400 ° C in a reduced pressure atmosphere. At this time, it is preferable to continuously form the metal oxide film 108f without exposing the surface of the insulating layer 104 to the atmosphere. For example, the film formation apparatus preferably has a structure in which a heating chamber for heating the substrate and a film formation chamber for forming the metal oxide film 108f are connected to each other through a gate valve or the like.

  Subsequently, the metal oxide film 108f is processed to form an island-shaped semiconductor layer 108 (FIG. 5B).

  Either or both of a wet etching method and a dry etching method may be used for processing the metal oxide film 108f.

  Alternatively, after the metal oxide film 108f is formed or processed into the semiconductor layer 108, heat treatment may be performed to dehydrogenate or dehydrate the metal oxide film 108f or the semiconductor layer 108. The temperature of the heat treatment is typically 150 ° C. or higher and lower than the strain point of the substrate, 250 ° C. or higher and 450 ° C. or lower, or 300 ° C. or higher and 450 ° C. or lower.

  The heat treatment can be performed in an inert gas atmosphere containing nitrogen or a rare gas such as helium, neon, argon, xenon, or krypton. Alternatively, after heating in an inert gas atmosphere, heating may be performed in an oxygen atmosphere. In addition, it is preferable that hydrogen, water, etc. are not contained in the said inert gas atmosphere and oxygen atmosphere. The treatment time may be 3 minutes or more and 24 hours or less.

  For the heat treatment, an electric furnace, an RTA (Rapid Thermal Annealing) apparatus, or the like can be used. By using the RTA apparatus, heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a short time. Therefore, the heat treatment time can be shortened.

The metal oxide film 108f is formed while being heated, or after the metal oxide film 108f is formed, heat treatment is performed, whereby the hydrogen concentration in the metal oxide film 108f obtained by SIMS is set to 5 × 10 ¹⁹ atoms. / Cm ³ or less, or 1 × 10 ¹⁹ atoms / cm ³ or less, 5 × 10 ¹⁸ atoms / cm ³ or less, or 1 × 10 ¹⁸ atoms / cm ³ or less, or 5 × 10 ¹⁷ atoms / cm ³ or less, or 1 × 10 ¹⁶ atoms / cm ³ or less.

[Formation of Insulating Film 110f]
Next, an insulating film 110f to be the insulating layer 110a and the insulating layer 210 is formed over the semiconductor layer 108 and the insulating layer 104 (FIG. 5C).

  As the insulating film 110f, an oxide film such as a silicon oxide film or a silicon oxynitride film is preferably formed using a plasma chemical vapor deposition apparatus (a PECVD apparatus or simply a plasma CVD apparatus). In this case, it is preferable to use a deposition gas and an oxidation gas containing silicon as the source gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and fluorinated silane. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide.

  In addition, as the insulating film 110f, PECVD is performed such that the flow rate of the oxidizing gas with respect to the flow rate of the deposition gas is greater than 20 times and less than 100 times, or 40 times or more and 80 times or less, and the pressure in the processing chamber is less than 100 Pa or 50 Pa or less. By using the apparatus, a silicon oxynitride film with a small amount of defects can be formed.

  In addition, as the insulating film 110f, a substrate placed in a evacuated processing chamber of the PECVD apparatus is held at 280 ° C. or higher and 400 ° C. or lower, and a raw material gas is introduced into the processing chamber so that the pressure in the processing chamber is 20 Pa or higher and 250 Pa. Hereinafter, a dense silicon oxide film or silicon oxynitride film can be formed as the insulating film 110f under the condition where the pressure is higher than or equal to 100 Pa and lower than or equal to 250 Pa and high-frequency power is supplied to the electrode provided in the processing chamber.

  Alternatively, the insulating film 110f may be formed using a PECVD method using microwaves. Microwave refers to the frequency range from 300 MHz to 300 GHz. Microwaves have a low electron temperature and a low electron energy. In addition, in the supplied power, the ratio used for accelerating electrons is small, it can be used for dissociation and ionization of more molecules, and high density plasma (high density plasma) can be excited. . Therefore, the insulating film 110f with less plasma damage and less defects on the deposition surface and the deposit can be formed.

[Formation of Metal Oxide Film 114f]
Subsequently, a metal oxide film 114f to be the metal oxide layer 114 is formed over the insulating film 110f.

  The metal oxide film 114f is preferably formed, for example, in an atmosphere containing oxygen. In particular, it is preferably formed by a sputtering method in an atmosphere containing oxygen. Accordingly, oxygen can be supplied to the insulating film 110f when the metal oxide film 114f is formed.

  For example, as a film formation condition of the metal oxide film 114f, it is preferable to form the metal oxide film by a reactive sputtering method using oxygen as a film formation gas and using a metal target. When aluminum is used as the metal target, for example, an aluminum oxide film can be formed.

  When the metal oxide film 114f is formed, the higher the ratio (oxygen flow ratio) of the oxygen flow rate to the total flow rate of the film formation gas introduced into the film formation chamber of the film formation apparatus or the higher the oxygen partial pressure in the film formation chamber, the higher The oxygen supplied into the film 110f can be increased. The oxygen flow rate ratio or the oxygen partial pressure is, for example, 50% to 100%, preferably 65% to 100%, more preferably 80% to 100%, and still more preferably 90% to 100%. In particular, it is preferable that the oxygen flow rate ratio is 100% and the oxygen partial pressure is as close as possible to 100%.

  In this manner, by forming the metal oxide film 114f by a sputtering method in an atmosphere containing oxygen, oxygen is supplied to the insulating film 110f when the metal oxide film 114f is formed, and oxygen is supplied from the insulating film 110f. Desorption can be prevented. As a result, a very large amount of oxygen can be confined in the insulating film 110f. A large amount of oxygen can be supplied to the semiconductor layer 108 by heat treatment performed later. As a result, oxygen vacancies in the semiconductor layer 108 can be reduced and a highly reliable transistor can be realized.

  In the case of the structure exemplified in Structure Example 2, the metal oxide film 114f, the insulating film 110f, and part of the insulating layer 104 are etched after the metal oxide film 114f is formed, whereby the conductive layer 106 is formed. Form an opening to reach. Accordingly, the conductive layer 112 and the conductive layer 106 to be formed later can be electrically connected through the opening.

[Formation of Conductive Film 112f]
Subsequently, a conductive film 112f to be the conductive layer 112 is formed over the metal oxide film 114f (FIG. 5D).

  The conductive film 112f is preferably formed by a sputtering method using a metal or alloy sputtering target.

[Formation of Metal Oxide Layer 114 and Conductive Layer 112]
Subsequently, the conductive film 112f and the metal oxide film 114f are etched to form the conductive layer 112 and the metal oxide layer 114, and part of the insulating film 110f is exposed (FIG. 5E).

  Here, the conductive film 112f and the metal oxide film 114f are preferably processed using the same resist mask. Alternatively, the metal oxide film 114f may be etched using the etched conductive layer 112 as a hard mask.

  As shown in FIG. 5E, after etching the conductive film 112f and the metal oxide film 114f, in the region where the transistor 100 is formed, the island-shaped conductive layer 112 and the metal oxide layer whose top shapes are approximately the same. 114 is formed.

  Note that when the conductive film 112f and the metal oxide film 114f are etched, part of the insulating film 110f that is not covered with the metal oxide layer 114 is also etched to be thin.

  Here, when the resist mask is formed on the conductive film 112f, the pattern width of the resist mask can be reduced more than the minimum processing dimension in an apparatus such as an exposure machine or a developing machine by adjusting the exposure time. For example, a resist pattern finer than the minimum processing dimension can be formed by using a photomask having a pattern width thinner than the minimum processing dimension and shortening the exposure time as compared with the conventional case. Alternatively, a resist pattern finer than the minimum processing dimension may be formed by using a photomask having a pattern width equal to or larger than the minimum processing dimension, for example, by making the exposure time longer than the conventional one.

  Alternatively, the resist mask formed over the conductive film 112f may be subjected to slimming treatment to reduce the width of the resist mask, and the processed conductive layer 112 may be reduced in width in the channel length direction. Alternatively, in the case where the conductive film 112f or the like is etched using a hard mask, a slimming process can be performed on the resist mask used when the hard mask is processed. As the slimming treatment, for example, after forming a resist mask, the pattern width of the resist mask is increased by plasma treatment or heat treatment in an atmosphere containing oxygen, or treatment of irradiating ultraviolet light in a state exposed to an ozone atmosphere. Can be reduced.

  By the above-described method, a resist pattern having a width smaller than the minimum processing dimension can be formed. For example, even when an apparatus having a minimum pattern width processing size of about 2.0 μm or about 1.5 μm is used, the pattern width is less than 1.5 μm, preferably less than 1.0 μm, more preferably less than 0.5 μm. It becomes possible to reduce.

[Formation of Insulating Film 210f]
Subsequently, an insulating film 210f to be the insulating layer 316 and the insulating layer 210 is formed over the insulating film 110f, the metal oxide layer 114, and the conductive layer 112 (FIG. 6A).

  Note that the surface of the insulating film 110f may be cleaned before the insulating film 210f is formed. For example, diluted hydrofluoric acid or phosphoric acid can be used. At this time, it is preferable to set the concentration and the processing time so that the insulating film 110f is not lost. By performing the cleaning treatment, the insulating film 110f may be thinned.

  Since the description of the insulating film 110f can be referred to for the insulating film 210f, detailed description thereof is omitted. The insulating film 210f may be formed using the same material as the insulating film 110f, or may be formed using a different material.

[Formation of Metal Oxide Film 314f]
Subsequently, a metal oxide film 314f to be the metal oxide layer 314 is formed over the insulating film 210f.

  Since the description of the metal oxide film 114f can be referred to for the metal oxide film 314f, detailed description thereof is omitted. The metal oxide film 314f may be formed using the same material as the metal oxide film 114f, or may be formed using a different material.

  In the case of the structure exemplified in Structure Example 2, an opening reaching the conductive layer 106 is formed by etching part of the metal oxide film 314f and the insulating film 210f after the metal oxide film 314f is formed. To do. Accordingly, the conductive layer 312 and the conductive layer 106 to be formed later can be electrically connected through the opening.

[Formation of Conductive Film 312f]
Next, a conductive film 312f to be the conductive layer 312 is formed over the metal oxide film 314f (FIG. 6B).

  Since the description of the conductive film 112f can be referred to for the conductive film 312f, detailed description is omitted. The conductive film 312f may be formed using the same material as the conductive film 112f or a different material.

[Formation of Metal Oxide Layer 314 and Conductive Layer 312]
Subsequently, the conductive film 312f and the metal oxide film 314f are etched to form the conductive layer 312 and the metal oxide layer 314, and part of the insulating film 210f is exposed (FIG. 6C).

  Here, the conductive film 312f and the metal oxide film 314f are preferably processed using the same resist mask. Alternatively, the metal oxide film 314f may be etched using the conductive layer 312 after etching as a hard mask.

  As shown in FIG. 6C, after etching the conductive film 312f and the metal oxide film 314f, in the region where the transistor 100A is formed, the island-shaped conductive layer 312 and the metal oxide layer whose top shapes are approximately the same. 314 is formed.

  Note that when the conductive film 312f and the metal oxide film 314f are etched, part of the insulating film 210f that is not covered with the metal oxide layer 314 is also etched to be thin.

  Here, when the resist mask is formed on the conductive film 312f, the pattern width of the resist mask can be reduced more than the minimum processing dimension in an apparatus such as an exposure machine or a developing machine by adjusting the exposure time. For example, a resist pattern finer than the minimum processing dimension can be formed by using a photomask having a pattern width thinner than the minimum processing dimension and shortening the exposure time as compared with the conventional case. Alternatively, a resist pattern finer than the minimum processing dimension may be formed by using a photomask having a pattern width equal to or larger than the minimum processing dimension, for example, by making the exposure time longer than the conventional one.

  Alternatively, the resist mask formed over the conductive film 312f may be subjected to slimming treatment to reduce the width of the resist mask, and the processed conductive layer 312 may have a reduced width in the channel length direction. Alternatively, in the case where the conductive film 312f or the like is etched using a hard mask, a slimming process can be performed on the resist mask used when the hard mask is processed. As the slimming treatment, for example, after forming a resist mask, the pattern width of the resist mask is increased by plasma treatment or heat treatment in an atmosphere containing oxygen, or treatment of irradiating ultraviolet light in a state exposed to an ozone atmosphere. Can be reduced.

  By the above-described method, a resist pattern having a width smaller than the minimum processing dimension can be formed. For example, even when an apparatus having a minimum pattern width processing size of about 2.0 μm or about 1.5 μm is used, the pattern width is less than 1.5 μm, preferably less than 1.0 μm, more preferably less than 0.5 μm. It becomes possible to reduce.

[Formation of Insulating Layer 316, Insulating Layer 110a, Insulating Layer 110b, and Insulating Layer 210]
Subsequently, anisotropic dry etching is performed without forming a resist mask over the insulating film 210f, whereby the insulating layer 316 and the insulating layer 210 are formed. Thus, in the region where the transistor 100 is formed, the insulating layer 316 provided in contact with the upper surface of the insulating film 110f, the side surfaces of the conductive layer 112, and the metal oxide layer 114 is formed. The insulating layer 316 preferably has a thicker width as it approaches the semiconductor layer 108 along the side surfaces of the conductive layer 112 and the metal oxide layer 114. In the region where the transistor 100A is formed, the conductive layer 312 functions as a hard mask and a portion overlapping with the conductive layer 312 remains, so that the insulating layer 210 can be formed in a self-aligned manner.

By forming the insulating layer 316 in this way, the width (area) of the portion in contact with the upper surface of the insulating layer 110a can be made substantially equal. That is, in the L length direction of the transistor 100, the pair of insulating layers 316 can have a symmetrical shape. In addition, the width of the portion where the insulating layer 316 and the insulating layer 110a are in contact can be controlled by the thickness of the insulating film 110f.

  Subsequently, the insulating film 110f is etched without forming a resist mask (FIG. 6D). As an etching method, an anisotropic dry etching method is preferably used. At this time, in the region where the transistor 100 is formed, the conductive layer 112 and the insulating layer 316 function as a hard mask, and a portion overlapping with the conductive layer 112 and the insulating layer 316 remains, so that the insulating layer 110a is formed in a self-aligned manner. can do. In the region where the transistor 100A is formed, the conductive layer 312 functions as a hard mask and a portion overlapping with the conductive layer 312 remains, so that the insulating layer 110b can be formed in a self-aligned manner. Note that the semiconductor layer 108 in a region which is not in contact with the insulating layer 110a and the insulating layer 110b may be thinned by etching part of the semiconductor layer 108 when the insulating film 110f is etched.

[Formation of the first layer 116]
Subsequently, the first layer 116 is formed (FIG. 6E).

  Here, as the first layer 116, an insulating film or a conductive film can be formed.

  As the first layer 116, a film containing at least one of metal elements such as aluminum, titanium, tantalum, tungsten, chromium, and ruthenium is formed. In particular, at least one of aluminum, titanium, tantalum, and tungsten is preferably included. In particular, a nitride containing at least one of these metal elements or an oxide containing at least one of these metal elements can be preferably used. As the insulating film, a nitride film such as an aluminum titanium nitride film, a titanium nitride film, or an aluminum nitride film, an oxide film such as an aluminum titanium oxide film, or the like can be preferably used.

  For example, as the first layer 116, a metal film or an alloy film containing at least one of metal elements such as aluminum, titanium, tantalum, tungsten, chromium, and ruthenium can be formed in addition to the above. In particular, at least one of aluminum, titanium, tantalum, and tungsten is preferably included.

  Here, the first layer 116 is preferably formed by a sputtering method using nitrogen gas or oxygen gas as a deposition gas. Thereby, even when the same sputtering target is used, the film quality can be easily controlled by controlling the flow rate of the film forming gas.

[Heat treatment]
Subsequently, heat treatment is performed. As shown in FIG. 6E, the resistance of the region in contact with the first layer 116 of the semiconductor layer 108 is reduced by heat treatment, so that a low-resistance region 108 n is formed in the semiconductor layer 108.

  The heat treatment is preferably performed in an inert gas atmosphere such as nitrogen or a rare gas. The higher the temperature of the heat treatment, the better, but the temperature can be set in consideration of the heat resistance of the substrate 102, the conductive layer 106, the conductive layer 112, and the like. For example, the temperature can be 120 ° C. or higher and 500 ° C. or lower, preferably 150 ° C. or higher and 450 ° C. or lower, more preferably 200 ° C. or higher and 400 ° C. or lower, and even more preferably 250 ° C. or higher and 400 ° C. or lower. For example, by setting the temperature of the heat treatment to about 350 ° C., a semiconductor device can be manufactured with high yield using a production facility using a large glass substrate.

  By the heat treatment, oxygen in the semiconductor layer 108 is extracted to the first layer 116, whereby oxygen vacancies are generated. The oxygen vacancies and hydrogen contained in the semiconductor layer 108 are combined to increase the carrier concentration, so that the portion in contact with the first layer 116 is reduced in resistance.

  Alternatively, in some cases, the metal element contained in the first layer 116 is diffused into the semiconductor layer 108 by heat treatment, so that part of the semiconductor layer 108 is alloyed and the resistance is reduced.

  Alternatively, nitrogen included in the first layer 116, nitrogen included in the atmosphere of the heat treatment, or the like may diffuse into the semiconductor layer 108 due to the heat treatment, and thus the resistance may be reduced.

  The region 108n of the semiconductor layer 108 whose resistance is reduced by such a composite action is an extremely stable low resistance region. The region 108n formed in this manner has a characteristic that resistance is not easily increased even if, for example, a process of supplying oxygen is performed in a later process.

  In particular, a film that releases hydrogen by heating is provided in contact with part of the semiconductor layer 108, and the resistance is reduced by supplying the hydrogen to part of the semiconductor layer 108, so that it is less diffusible than hydrogen. It is preferable to use a method of reducing resistance by supplying a metal element or an element such as nitrogen to part of the semiconductor layer 108. Accordingly, an increase in carrier concentration in the region 108i functioning as a channel formation region can be suppressed. As a result, good switching characteristics can be obtained even when the channel length of the transistor is extremely short. For example, good switching characteristics can be obtained even with a fine transistor with a channel length of 100 nm or less.

[Removal of the first layer 116]
Subsequently, the first layer 116 is removed by etching.

  When the first layer 116 is etched, part of the conductive layer 112, the metal oxide layer 114, the insulating layer 110a or the insulating layer 210, the semiconductor layer 108, or the like may be etched. In particular, when a metal film or an alloy film is used for the first layer 116, it is preferable to select an etching method using a material different from that of the conductive layer 112 and having a high selectivity of the etching rate.

  Note that in the case where an insulating material is used for the first layer 116 or a material which is insulated by the heat treatment is used, the first layer 116 may be left without being etched.

[Formation of Metal Oxide Layer 117]
Subsequently, a metal oxide layer 117 is formed over the first layer 116. The metal oxide layer 117 can be formed by a method similar to that of the metal oxide film 114f.

  When the metal oxide layer 117 is formed, oxygen may be added to the region 108n of the semiconductor layer 108. However, the region 108n is difficult to increase in resistance and maintains a low resistance state.

  Further, when the metal oxide layer 117 is formed, oxygen can be supplied from the side surface of the insulating layer 110 a or the insulating layer 210 functioning as a gate insulating layer through the first layer 116. In some cases, oxygen can be supplied to the insulating layer 104 through the semiconductor layer 108.

  Heat treatment may be performed after the metal oxide layer 117 is formed. By performing heat treatment while the semiconductor layer 108 is covered with the metal oxide layer 117 functioning as a barrier layer, the insulating layer 110a or the insulating layer 210 or the insulating layer 104 is formed in the region 108i which is a channel formation region of the semiconductor layer 108. Thus, oxygen can be preferably supplied to reduce the carrier concentration.

[Formation of Insulating Layer 118]
Subsequently, an insulating layer 118 is formed so as to cover the metal oxide layer 117 (FIG. 7A).

  The insulating layer 118 can be formed by a plasma CVD method, a sputtering method, or the like.

[Formation of Openings 141a and 141b]
Subsequently, after a mask is formed by lithography at a desired position of the insulating layer 118, the insulating layer 118 and a part of the metal oxide layer 117 are etched, whereby the opening 141a and the opening 141b reaching the region 108n are obtained. Is formed (FIG. 7B).

[Formation of Conductive Layers 120a and 120b]
Subsequently, a conductive film is formed over the insulating layer 118 so as to cover the opening 141a and the opening 141b, and the conductive film is processed into a desired shape, so that the conductive layer 120a and the conductive layer 120b are formed. (FIG. 7C).

  Through the above steps, the transistor 100 having a sidewall insulating layer, a thin gate insulating layer, and a fine transistor 100 and a transistor 100A having a thick gate insulating layer and high withstand voltage performance can be formed over the same substrate at the same time. it can.

  The above is the description of the manufacturing method example.

  The structure example, the manufacturing method example, and the drawings corresponding to the structure example described in this embodiment can be implemented in appropriate combination with at least part of the structure example, the manufacturing method example, the drawing, or the like.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 2)
In this embodiment, an example of a display device including the transistor described in the above embodiment will be described.

<Configuration example>
FIG. 8A is a top view illustrating an example of a display device. A display device 700 illustrated in FIG. 8A includes a pixel portion 702 provided over a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided over the first substrate 701, and a pixel. A sealant 712 disposed so as to surround the portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706, and a second substrate 705 provided so as to face the first substrate 701. Note that the first substrate 701 and the second substrate 705 are attached to each other with a sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed with the first substrate 701, the sealant 712, and the second substrate 705. Note that although not illustrated in FIG. 8A, a display element is provided between the first substrate 701 and the second substrate 705.

  In the display device 700, an FPC terminal portion 708 (FPC: Flexible printed circuit) is provided in a region different from the region surrounded by the sealant 712 over the first substrate 701. The FPC terminal portion 708 is electrically connected to each of the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706. In addition, an FPC 716 is connected to the FPC terminal portion 708, and various signals are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716. A signal line 710 is connected to each of the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708. Various signals and the like supplied by the FPC 716 are supplied to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 through the signal line 710.

  In addition, a plurality of gate driver circuit portions 706 may be provided in the display device 700. In addition, as the display device 700, an example in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed over the same first substrate 701 as the pixel portion 702 is shown; however, the display device 700 is not limited to this structure. For example, only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, an IC including a substrate over which a source driver circuit, a gate driver circuit, or the like is formed (eg, a driver circuit substrate formed with a single crystal semiconductor film or a polycrystalline semiconductor film) is provided over the first substrate 701 or the FPC 716. It is good also as a structure. Note that a connection method of a separately formed driver circuit substrate is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

  The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 each include a plurality of transistors, and a transistor that is a semiconductor device of one embodiment of the present invention can be used. .

  In addition, the display device 700 can include various elements. Examples of the element include, for example, an electroluminescence (EL) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element, an LED, and the like), a light-emitting transistor element (a transistor that emits light in response to current), an electron Examples include an emission element, a liquid crystal element, an electronic ink element, an electrophoretic element, an electrowetting element, a plasma display panel (PDP), a MEMS (micro electro mechanical system) display, and a piezoelectric ceramic display.

  An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type flat display (SED: Surface-Conduction Electron-Emitter Display), or the like. An example of a display device using a liquid crystal element is a liquid crystal display. An example of a display device using an electronic ink element or an electrophoretic element is electronic paper.

  Note that as a display method in the display device 700, a progressive method, an interlace method, or the like can be used. Further, the color elements controlled by the pixels when performing color display are not limited to three colors of RGB (R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, as in a pen tile arrangement, one color element may be configured for two colors of RGB, and two different colors may be selected and configured depending on the color element. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. The size of the display area may be different for each dot of the color element. Note that the disclosed invention is not limited to a display device for color display, and can be applied to a display device for monochrome display.

  In addition, a colored layer (also referred to as a color filter) is used in order to cause the display device to perform color display using white light emission (W) in a backlight or a front light (such as an organic EL element, an inorganic EL element, an LED, or a fluorescent lamp). It may be used. For example, red (R), green (G), blue (B), yellow (Y), and the like can be used in appropriate combination for the colored layer. By using the colored layer, the color reproducibility can be increased as compared with the case where the colored layer is not used. At this time, white light in a region having no colored layer may be directly used for display by arranging a region having a colored layer and a region having no colored layer. By disposing a region that does not have a colored layer in part, a decrease in luminance due to the colored layer can be reduced during bright display, and power consumption can be reduced by about 20% to 30%. However, when a full color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and W may be emitted from elements having respective emission colors. By using a self-luminous element, power consumption may be further reduced as compared with the case where a colored layer is used.

  In addition, as a colorization method, in addition to a method (color filter method) in which part of the light emission from the white light emission described above is passed through a color filter to convert it into red, green, and blue light emission of red, green, and blue A method of using each (three-color method) or a method of converting a part of light emission from blue light emission to red or green (color conversion method, quantum dot method) may be applied.

  A display device 700A illustrated in FIG. 8B is a display device that can be preferably used for an electronic device having a large screen. For example, it can be suitably used for a television device, a monitor device, a digital signage, and the like.

  The display device 700A includes a plurality of source driver ICs 721 and a pair of gate driver circuits 722.

  The plurality of source driver ICs 721 are each attached to the FPC 723. The plurality of FPCs 723 have one terminal connected to the substrate 701 and the other terminal connected to the printed circuit board 724. By bending the FPC 723, the printed circuit board 724 can be disposed on the back side of the pixel portion 702 and mounted on an electric device, so that space saving of the electronic device can be achieved.

  On the other hand, the gate driver circuit 722 is formed on the substrate 701. Thereby, an electronic device with a narrow frame can be realized.

  With such a configuration, a large-sized and high-resolution display device can be realized. For example, the present invention can be applied to a display device whose screen size is 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more. In addition, a display device with extremely high resolution such as full high vision, 4K2K, or 8K4K can be realized.

<Cross-section configuration example>
Hereinafter, a structure in which a liquid crystal element and an EL element are used as display elements will be described with reference to FIGS. Note that FIG. 9 is a cross-sectional view taken along one-dot chain line QR shown in FIG. 8A and has a structure in which an EL element is used as a display element. FIGS. 10 and 11 are cross-sectional views taken along one-dot chain line QR shown in FIG. 8A, each using a liquid crystal element as a display element.

  First, common parts shown in FIGS. 9 to 11 will be described first, and then different parts will be described below.

[Description of common parts of display device]
A display device 700 illustrated in FIGS. 9 to 11 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. Further, the lead wiring portion 711 includes a signal line 710. In addition, the pixel portion 702 includes a transistor 750 and a transistor 752. In addition, the source driver circuit portion 704 includes a transistor 754.

  The transistor illustrated in Embodiment 1 can be used as the transistor 750, the transistor 752, and the transistor 754.

  The transistor used in this embodiment includes an oxide semiconductor film which is highly purified and suppresses formation of oxygen vacancies. The transistor can have low off-state current. Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.

  In addition, the transistor used in this embodiment can have a relatively high field-effect mobility, and thus can be driven at high speed. For example, by using such a transistor capable of high-speed driving for a display device, the switching transistor in the pixel portion and the driver transistor used in the driver circuit portion can be formed over the same substrate. That is, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate drive circuit, the number of parts of the semiconductor device can be reduced. In the pixel portion, a high-quality image can be provided by using a transistor that can be driven at high speed.

  9 to 11, a planarization insulating film 770 is provided over the transistor 750, the transistor 752, and the transistor 754.

  The signal line 710 is formed through the same process as the conductive film functioning as the source electrode and the drain electrode of the transistor 750, the transistor 752, and the transistor 754. The signal line 710a is formed through the same process as the conductive film functioning as the gate electrodes of the transistor 750, the transistor 752, and the transistor 754. For example, when a material containing a copper element is used as the signal line 710, signal delay due to wiring resistance is small and display on a large screen is possible.

  The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. Note that the connection electrode 760 is formed through the same process as the conductive film functioning as the source electrode and the drain electrode of the transistor 750, the transistor 752, and the transistor 754. The connection electrode 760 is electrically connected to a terminal included in the FPC 716 through an anisotropic conductive film 780.

  In addition, as the first substrate 701 and the second substrate 705, for example, glass substrates can be used. Alternatively, a flexible substrate may be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate.

  A structure body 778 is provided between the first substrate 701 and the second substrate 705. The structure body 778 is a columnar spacer and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure body 778.

  On the second substrate 705 side, a light-blocking film 738 functioning as a black matrix, a colored film 736 functioning as a color filter, and an insulating film 734 in contact with the light-blocking film 738 and the colored film 736 are provided.

[Display device using light emitting element]
A display device 700 illustrated in FIG. 9 includes a light-emitting element 782. The light-emitting element 782 includes a conductive film 772, an EL layer 786, and a conductive film 788. The display device 700 illustrated in FIG. 9 can display an image when the EL layer 786 included in the light-emitting element 782 provided for each pixel emits light.

  The EL layer 786 includes an organic compound or an inorganic compound such as a quantum dot. As a material that can be used for the organic compound, a fluorescent material, a phosphorescent material, or the like can be given. Examples of materials that can be used for the quantum dots include colloidal quantum dot materials, alloy type quantum dot materials, core / shell type quantum dot materials, and core type quantum dot materials. Alternatively, a material including an element group of Group 12 and Group 16, Group 13 and Group 15, or Group 14 and Group 16 may be used. Or cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As ), A quantum dot material having an element such as aluminum (Al) may be used.

The display device 700 includes a transistor 752 and a transistor 750 in the pixel portion 702. The transistor 752 controls the selection state of the light-emitting element 782, and is a transistor that requires high-speed operation. The structure of the first transistor described in Embodiment 1 can be applied to the transistor 752. When the transistor 752 includes a sidewall insulating layer, a gate insulating layer is thin, and a minute transistor is used, high-speed operation can be performed. The transistor 750 is a transistor that controls current flowing in the light-emitting element 782, and preferably has high withstand voltage performance. The structure of the second transistor described in Embodiment 1 can be applied to the transistor 750. By using a transistor with a gate insulating layer thicker than the transistor 752 and a long channel length as the transistor 750, a transistor with high withstand voltage performance can be obtained.

The display device 700 includes a transistor 754 in the source driver circuit portion 704. The transistor 754 is a transistor that is required to operate at high speed among the transistors included in the source driver circuit portion 704. The structure of the first transistor described in Embodiment 1 can be applied to the transistor 754. When the transistor 754 includes a sidewall insulating layer, the gate insulating layer is thin, and a minute transistor is used, high-speed operation can be performed.

Note that FIG. 9 illustrates an example in which the first transistor is used as the transistor 752 and the transistor 754 and the second transistor is used as the transistor 750; however, one embodiment of the present invention is not limited thereto.

  The conductive film 772 is electrically connected to a conductive film functioning as a source electrode or a drain electrode of the transistor 750. The conductive film 772 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element.

  In the display device 700 illustrated in FIG. 9, an insulating film 730 is provided over the planarization insulating film 770 and the conductive film 772. The insulating film 730 covers part of the conductive film 772. Note that the light-emitting element 782 has a top emission structure. Accordingly, the conductive film 788 has a light-transmitting property and transmits light emitted from the EL layer 786. In the present embodiment, the top emission structure is illustrated, but is not limited thereto. For example, a bottom emission structure in which light is emitted to the conductive film 772 side or a dual emission structure in which light is emitted to both the conductive film 772 and the conductive film 788 can be used.

  A colored film 736 is provided at a position overlapping with the light emitting element 782, and a light shielding film 738 is provided at a position overlapping with the insulating film 730, the lead wiring portion 711, and the source driver circuit portion 704. Further, the coloring film 736 and the light shielding film 738 are covered with an insulating film 734. A space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that in the display device 700 illustrated in FIG. 11, the structure in which the colored film 736 is provided is illustrated, but the present invention is not limited to this. For example, in the case where the EL layer 786 is formed in an island shape for each pixel, that is, formed by separate coating, the coloring film 736 may not be provided.

[Configuration Example of Display Device Using Liquid Crystal Element]
A display device 700 illustrated in FIG. 10 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode. The display device 700 illustrated in FIG. 10 can display an image by controlling transmission and non-transmission of light by changing the alignment state of the liquid crystal layer 776 depending on voltages applied to the conductive films 772 and 774.

The display device 700 includes a transistor 750 in the pixel portion 702. The transistor 750 is a transistor that drives the liquid crystal element 775 and is a transistor that is required to operate at high speed. The structure of the first transistor described in Embodiment 1 can be applied to the transistor 750.

The display device 700 includes a transistor 754 in the source driver circuit portion 704. The transistor 754 is preferably provided in a level shifter circuit, a buffer circuit, or the like that is driven at a relatively high voltage among the transistors included in the source driver circuit portion 704 and has high withstand voltage performance. The structure of the second transistor described in Embodiment 1 can be applied to the transistor 754.

Note that although FIG. 9 illustrates an example in which the first transistor is used as the transistor 750 and the second transistor is used as the transistor 754, one embodiment of the present invention is not limited thereto.

  The conductive film 772 is electrically connected to a conductive film functioning as a source electrode or a drain electrode of the transistor 750. The conductive film 772 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element.

  As the conductive film 772, a conductive film that transmits visible light or a conductive film that reflects visible light can be used. As the conductive film that transmits visible light, for example, a material containing one kind selected from indium, zinc, and tin may be used. As the conductive film that reflects visible light, for example, a material containing aluminum or silver is preferably used.

  In the case where a conductive film that reflects visible light is used for the conductive film 772, the display device 700 is a reflective liquid crystal display device. In the case where a conductive film that transmits visible light is used for the conductive film 772, the display device 700 is a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates sandwiching a liquid crystal element is provided.

  Further, by changing the structure over the conductive film 772, the driving method of the liquid crystal element can be changed. An example of this case is shown in FIG. A display device 700 illustrated in FIG. 11 is an example of a configuration using a horizontal electric field method (eg, an FFS mode) as a driving method of a liquid crystal element. In the case of the structure illustrated in FIG. 10, the insulating film 773 is provided over the conductive film 772, and the conductive film 774 is provided over the insulating film 773. In this case, the conductive film 774 functions as a common electrode (also referred to as a common electrode), and the alignment of the liquid crystal layer 776 is generated by an electric field generated between the conductive film 772 and the conductive film 774 through the insulating film 773. The state can be controlled.

  Although not illustrated in FIGS. 10 and 11, an alignment film may be provided on one or both of the conductive film 772 and the conductive film 774 on the side in contact with the liquid crystal layer 776. Although not shown in FIGS. 10 and 11, an optical member (optical substrate) such as a polarizing member, a retardation member, or an antireflection member may be provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as the light source.

  When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a polymer network liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.

  In the case of employing a horizontal electric field method, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. Since the rubbing process is also unnecessary, electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. A liquid crystal material exhibiting a blue phase has a small viewing angle dependency.

  When a liquid crystal element is used as a display element, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axial Symmetrical Aligned MicroB cell) mode, Compensated Birefringence (FLC) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti-Ferroelectric Liquid Crystal) mode, ECB (Electrically Controlled Birefringence) mode, etc. can be used.

  Alternatively, a normally black liquid crystal display device such as a transmissive liquid crystal display device employing a vertical alignment (VA) mode may be used. There are several examples of the vertical alignment mode. For example, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV mode, and the like can be used.

[Configuration example in which an input / output device is provided in a display device]
Further, an input / output device may be provided in the display device 700 illustrated in FIGS. Examples of the input / output device include a touch panel.

  A configuration in which the touch panel 791 is provided in the display device 700 illustrated in FIG. 9 is illustrated in FIG. 12, and a configuration in which the touch panel 791 is provided in the display device 700 illustrated in FIG. 11 is illustrated in FIG.

  12 is a cross-sectional view of a configuration in which the touch panel 791 is provided in the display device 700 illustrated in FIG. 10, and FIG.

  First, the touch panel 791 shown in FIGS. 12 and 13 will be described below.

  A touch panel 791 illustrated in FIGS. 12 and 13 is a so-called in-cell type touch panel provided between the substrate 705 and the coloring film 736. The touch panel 791 may be formed on the substrate 705 side before the light shielding film 738 and the coloring film 736 are formed.

  Note that the touch panel 791 includes a light-blocking film 738, an insulating film 792, an electrode 793, an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797. For example, it is possible to detect a change in capacitance between the electrode 793 and the electrode 794 that may occur when a detection target such as a finger or a stylus approaches.

  In addition, above the transistor 750 illustrated in FIGS. 12 and 13, the intersection of the electrode 793 and the electrode 794 is clearly shown. The electrode 796 is electrically connected to two electrodes 793 sandwiching the electrode 794 through an opening provided in the insulating film 795. 12 and 13 exemplify the structure in which the region where the electrode 796 is provided is provided in the pixel portion 702, but the present invention is not limited to this. For example, the region may be formed in the source driver circuit portion 704.

  The electrodes 793 and 794 are provided in a region overlapping with the light-blocking film 738. In addition, as illustrated in FIG. 12, it is preferable that the electrode 793 be provided so as not to overlap with the light-emitting element 782. In addition, as illustrated in FIG. 13, the electrode 793 is preferably provided so as not to overlap with the liquid crystal element 775. In other words, the electrode 793 has an opening in a region overlapping with the light-emitting element 782 and the liquid crystal element 775. That is, the electrode 793 has a mesh shape. With such a structure, the electrode 793 can be configured not to block light emitted from the light-emitting element 782. Alternatively, the electrode 793 can have a structure that does not block light transmitted through the liquid crystal element 775. Therefore, since a reduction in luminance due to the arrangement of the touch panel 791 is extremely small, a display device with high visibility and low power consumption can be realized. Note that the electrode 794 may have a similar structure.

  In addition, since the electrode 793 and the electrode 794 do not overlap with the light-emitting element 782, a metal material with low visible light transmittance can be used for the electrode 793 and the electrode 794. Alternatively, since the electrode 793 and the electrode 794 do not overlap with the liquid crystal element 775, a metal material with low visible light transmittance can be used for the electrode 793 and the electrode 794.

  Therefore, the resistance of the electrode 793 and the electrode 794 can be reduced as compared with an electrode using an oxide material with high visible light transmittance, and the sensor sensitivity of the touch panel can be improved.

  For example, conductive nanowires may be used for the electrodes 793, 794, and 796. The nanowire may have an average diameter of 1 nm to 100 nm, preferably 5 nm to 50 nm, more preferably 5 nm to 25 nm. Moreover, as said nanowire, metal nanowires, such as Ag nanowire, Cu nanowire, or Al nanowire, or a carbon nanotube etc. may be used. For example, when an Ag nanowire is used for any one or all of the electrodes 793, 794, and 796, the light transmittance in visible light can be 89% or more, and the sheet resistance value can be 40Ω / □ or more and 100Ω / □ or less. .

  12 and 13 exemplify the configuration of the in-cell type touch panel, the present invention is not limited to this. For example, a so-called on-cell touch panel formed over the display device 700 or a so-called out-cell touch panel used by being attached to the display device 700 may be used.

  As described above, the display device of one embodiment of the present invention can be used in combination with various forms of touch panels.

  The structure examples exemplified in this embodiment and the corresponding drawings can be implemented by combining at least part of the structure examples with other structure examples or the drawings as appropriate.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 3)
In this embodiment, a display device including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

  A display device illustrated in FIG. 14A includes a circuit portion (hereinafter referred to as a driver circuit) including a region having pixels (hereinafter referred to as a pixel portion 502) and a circuit which is disposed outside the pixel portion 502 and drives the pixels. Part 504), a circuit having a protection function of an element (hereinafter referred to as a protection circuit 506), and a terminal part 507. Note that the protection circuit 506 may be omitted.

  A part or all of the driver circuit portion 504 is preferably formed over the same substrate as the pixel portion 502. Thereby, the number of parts and the number of terminals can be reduced. When part or all of the driver circuit portion 504 is not formed over the same substrate as the pixel portion 502, part or all of the driver circuit portion 504 is formed by COG or TAB (Tape Automated Bonding). Can be implemented.

  The pixel portion 502 includes a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The driver circuit portion 504 outputs a signal for selecting a pixel (scanning signal) (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel (a data signal). Hereinafter, it has a drive circuit such as a source driver 504b).

  The gate driver 504a includes a shift register and the like. The gate driver 504a receives a signal for driving the shift register via the terminal portion 507, and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, and the like and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring to which a scan signal is supplied (hereinafter referred to as gate lines GL_1 to GL_X). Note that a plurality of gate drivers 504a may be provided, and the gate lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of supplying an initialization signal. However, the present invention is not limited to this, and the gate driver 504a can supply another signal.

  The source driver 504b includes a shift register and the like. In addition to a signal for driving the shift register, the source driver 504b receives a signal (image signal) as a source of a data signal through the terminal portion 507. The source driver 504b has a function of generating a data signal to be written in the pixel circuit 501 based on the image signal. In addition, the source driver 504b has a function of controlling output of a data signal in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, or the like. The source driver 504b has a function of controlling the potential of a wiring to which a data signal is supplied (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, the source driver 504b has a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b can supply another signal.

  The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b can output a signal obtained by time-dividing the image signal as a data signal by sequentially turning on the plurality of analog switches. Further, the source driver 504b may be configured using a shift register or the like.

  Each of the plurality of pixel circuits 501 receives a pulse signal through one of the plurality of scanning lines GL to which the scanning signal is applied, and receives the data signal through one of the plurality of data lines DL to which the data signal is applied. Entered. In each of the plurality of pixel circuits 501, writing and holding of data signals are controlled by the gate driver 504a. For example, the pixel circuit 501 in the m-th row and the n-th column receives a pulse signal from the gate driver 504a through the scanning line GL_m (m is a natural number equal to or less than X), and the data line DL_n (n Is a natural number less than or equal to Y), a data signal is input from the source driver 504b.

  The protection circuit 506 illustrated in FIG. 14A is connected to, for example, a scanning line GL that is a wiring between the gate driver 504a and the pixel circuit 501. Alternatively, the protection circuit 506 is connected to the data line DL that is a wiring between the source driver 504 b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to a wiring between the gate driver 504 a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to a wiring between the source driver 504 b and the terminal portion 507. Note that the terminal portion 507 is a portion where a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device is provided.

  The protection circuit 506 is a circuit that brings a wiring into a conductive state when a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected.

  As shown in FIG. 14A, by providing a protection circuit 506 in each of the pixel portion 502 and the driver circuit portion 504, resistance of the display device to an overcurrent generated by ESD (Electro Static Discharge) is increased. be able to. However, the configuration of the protection circuit 506 is not limited thereto, and for example, a configuration in which the protection circuit 506 is connected to the gate driver 504a or a configuration in which the protection circuit 506 is connected to the source driver 504b may be employed. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.

  FIG. 14A illustrates an example in which the driver circuit portion 504 is formed using the gate driver 504a and the source driver 504b; however, the present invention is not limited to this structure. For example, only the gate driver 504a may be formed, and a substrate on which a separately prepared source driver circuit is formed (for example, a driver circuit substrate formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.

  Here, FIG. 15 shows a different structure from FIG. In FIG. 15, a pair of source lines (for example, source line DLa1 and source line DLb1) are arranged so as to sandwich a plurality of pixels arranged in the source line direction. Two adjacent gate lines (for example, the gate line GL_1 and the gate line GL_2) are electrically connected.

  The pixel connected to the gate line GL_1 is connected to one source line (source line DLa1, source line DLa2, etc.), and the pixel connected to the gate line GL_2 is connected to the other source line (source line DLb1, source line DLa1). Line DLb2 etc.).

  With such a configuration, two gate lines can be selected simultaneously. Thereby, the length of one horizontal period can be doubled compared with the structure shown to FIG. Therefore, it is easy to increase the resolution and enlarge the screen of the display device.

  In addition, the plurality of pixel circuits 501 illustrated in FIGS. 14A and 15 can have the structure illustrated in FIG. 14B, for example.

  A pixel circuit 501 illustrated in FIG. 14B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The transistor described in the above embodiment can be applied to the transistor 550.

  One potential of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specification of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Further, a different potential may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.

  For example, as a driving method of a display device including the liquid crystal element 570, various methods such as a TN mode, a VA mode, an IPS mode, an FFS mode, and a guest host mode can be used.

  In the pixel circuit 501 in the m-th row and the n-th column, one of the source electrode and the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The In addition, the gate electrode of the transistor 550 is electrically connected to the scan line GL_m. The transistor 550 has a function of controlling data writing of the data signal.

  One of the pair of electrodes of the capacitor 560 is electrically connected to a wiring to which a potential is supplied (hereinafter, potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The Note that the value of the potential of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

  For example, in a display device including the pixel circuit 501 in FIG. 14B, for example, the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write data.

  The pixel circuit 501 in which data is written is brought into a holding state when the transistor 550 is turned off. By sequentially performing this for each row, an image can be displayed.

  In addition, the plurality of pixel circuits 501 illustrated in FIG. 14A can have a structure illustrated in FIG. 14C, for example.

  In addition, the pixel circuit 501 illustrated in FIG. 14C includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572. The transistor described in any of the above embodiments can be applied to one or both of the transistor 552 and the transistor 554.

  One of a source electrode and a drain electrode of the transistor 552 is electrically connected to the data line DL_n, and a gate electrode is electrically connected to the scan line GL_m.

  The transistor 552 has a function of controlling data writing of the data signal.

  One of the pair of electrodes of the capacitor 562 is electrically connected to the potential supply line VL_a, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

  The capacitor 562 functions as a storage capacitor that stores written data.

  One of a source electrode and a drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

  One of an anode and a cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

  As the light-emitting element 572, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light-emitting element 572 is not limited thereto, and an inorganic EL element containing an inorganic material may be used.

  Note that one of the potential supply line VL_a and the potential supply line VL_b is supplied with the high power supply potential VDD, and the other is supplied with the low power supply potential VSS.

  In the display device including the pixel circuit 501 in FIG. 14C, for example, the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write.

  The pixel circuit 501 in which data is written is brought into a holding state when the transistor 552 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled in accordance with the potential of the written data signal, and the light-emitting element 572 emits light with luminance corresponding to the amount of flowing current. By sequentially performing this for each row, an image can be displayed.

  The structure examples exemplified in this embodiment and the corresponding drawings can be implemented by combining at least part of the structure examples with other structure examples or the drawings as appropriate.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 4)
In this embodiment, an electronic device including a display device manufactured using one embodiment of the present invention will be described.

  FIG. 16A is a diagram illustrating an appearance of the camera 8000 with the viewfinder 8100 attached.

  A camera 8000 includes a housing 8001, a display portion 8002, operation buttons 8003, a shutter button 8004, and the like. The camera 8000 is attached with a detachable lens 8006.

  Here, the camera 8000 is configured such that the lens 8006 can be removed from the housing 8001 and replaced, but the lens 8006 and the housing may be integrated.

  The camera 8000 can take an image by pressing a shutter button 8004. In addition, the display portion 8002 has a function as a touch panel and can capture an image by touching the display portion 8002.

  A housing 8001 of the camera 8000 includes a mount having an electrode, and a strobe device or the like can be connected in addition to the finder 8100.

  The viewfinder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

  The housing 8101 has a mount that engages with the mount of the camera 8000, and the finder 8100 can be attached to the camera 8000. In addition, the mount includes an electrode, and an image received from the camera 8000 via the electrode can be displayed on the display portion 8102.

  The button 8103 has a function as a power button. A button 8103 can be used to switch display on the display portion 8102 on and off.

  The display device of one embodiment of the present invention can be applied to the display portion 8002 of the camera 8000 and the display portion 8102 of the viewfinder 8100.

  Note that in FIG. 16A, the camera 8000 and the viewfinder 8100 are separate electronic devices and can be attached to and detached from each other. However, a finder including a display device is incorporated in the housing 8001 of the camera 8000. Also good.

  FIG. 16B is a diagram showing the appearance of the head mounted display 8200.

  The head mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like. In addition, a battery 8206 is built in the mounting portion 8201.

  A cable 8205 supplies power from the battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver and the like, and can display video information such as received image data on the display portion 8204. In addition, it is possible to use the user's viewpoint as an input unit by capturing the movement of the user's eyeball or eyelid with a camera provided in the main body 8203 and calculating the coordinates of the user's viewpoint based on the information. it can.

  In addition, the mounting portion 8201 may be provided with a plurality of electrodes at a position where the user touches the user. The main body 8203 may have a function of recognizing the user's viewpoint by detecting a current flowing through the electrode in accordance with the movement of the user's eyeball. Moreover, you may have a function which monitors a user's pulse by detecting the electric current which flows into the said electrode. The mounting portion 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display portion 8204. Further, the movement of the user's head or the like may be detected, and the video displayed on the display unit 8204 may be changed in accordance with the movement.

  The display device of one embodiment of the present invention can be applied to the display portion 8204.

  16C, 16D, and 16E are views showing the appearance of the head mounted display 8300. FIG. The head mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

  The user can view the display on the display portion 8302 through the lens 8305. Note that the display portion 8302 is preferably arranged curved. By arranging the display portion 8302 to be curved, the user can feel a high sense of realism. Note that although a structure in which one display portion 8302 is provided is described in this embodiment mode, the present invention is not limited thereto, and for example, a structure in which two display portions 8302 are provided may be employed. In this case, if one display unit is arranged in one eye of the user, three-dimensional display using parallax or the like can be performed.

  Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. Since the display device including the semiconductor device of one embodiment of the present invention has extremely high definition, the pixel is not visually recognized by the user even when the display device is enlarged using the lens 8305 as illustrated in FIG. More realistic video can be displayed.

  Next, examples of electronic devices that are different from the electronic devices illustrated in FIGS. 16A to 16E are illustrated in FIGS.

  An electronic device illustrated in FIGS. 17A to 17G includes a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (power) , Displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration , Including a function of measuring odor or infrared light), a microphone 9008, and the like.

  The electronic devices illustrated in FIGS. 17A to 17G have various functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for controlling processing by various software (programs), A wireless communication function, a function of reading and executing a program or data recorded in a recording medium, and the like can be provided. Note that the functions of the electronic devices illustrated in FIGS. 17A to 17G are not limited to these. The electronic device may have a plurality of display units. In addition, a camera or the like may be provided in the electronic device so that a still image or a moving image is captured and stored in a recording medium (externally or built in the camera).

  Details of the electronic devices illustrated in FIGS. 17A to 17G are described below.

  FIG. 17A is a perspective view illustrating a television device 9100. FIG. The television device 9100 can incorporate a display portion 9001 having a large screen, for example, 50 inches or more, or 100 inches or more.

  FIG. 17B is a perspective view showing the portable information terminal 9101. The portable information terminal 9101 has one or a plurality of functions selected from, for example, a telephone, a notebook, an information browsing device, or the like. Specifically, it can be used as a smartphone. Note that the portable information terminal 9101 may include a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. Further, the portable information terminal 9101 can display characters and image information on the plurality of surfaces. For example, three operation buttons 9050 (also referred to as operation icons or simply icons) can be displayed on one surface of the display portion 9001. Further, information 9051 indicated by a broken-line rectangle can be displayed on another surface of the display portion 9001. As an example of the information 9051, a display for notifying an incoming call such as an e-mail, SNS (social networking service), a telephone call, a title such as an e-mail or SNS, a sender name such as an e-mail or SNS, a date and time, and a time , Battery level, antenna reception strength and so on. Alternatively, an operation button 9050 or the like may be displayed instead of the information 9051 at a position where the information 9051 is displayed.

  FIG. 17C is a perspective view showing the portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different planes. For example, the user of the portable information terminal 9102 can check the display (information 9053 here) in a state where the portable information terminal 9102 is stored in the chest pocket of clothes. Specifically, the telephone number or name of the caller of the incoming call is displayed at a position where it can be observed from above portable information terminal 9102. The user can check the display and determine whether to receive a call without taking out the portable information terminal 9102 from the pocket.

  FIG. 17D is a perspective view showing a wristwatch-type portable information terminal 9200. The portable information terminal 9200 can execute various applications such as a mobile phone, electronic mail, text browsing and creation, music playback, Internet communication, and computer games. Further, the display portion 9001 is provided with a curved display surface, and can perform display along the curved display surface. In addition, the portable information terminal 9200 can execute short-range wireless communication with a communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication. In addition, the portable information terminal 9200 includes a connection terminal 9006 and can directly exchange data with other information terminals via a connector. Charging can also be performed through the connection terminal 9006. Note that the charging operation may be performed by wireless power feeding without using the connection terminal 9006.

  17E, 17F, and 17G are perspective views illustrating a foldable portable information terminal 9201. FIG. 17E is a perspective view of a state in which the portable information terminal 9201 is expanded, and FIG. 17F is a state in the middle of changing from one of the expanded state or the folded state of the portable information terminal 9201 to the other. FIG. 17G is a perspective view of the portable information terminal 9201 folded. The portable information terminal 9201 is excellent in portability in the folded state, and in the expanded state, the portable information terminal 9201 is excellent in display listability due to a seamless wide display area. A display portion 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. By bending between the two housings 9000 via the hinge 9055, the portable information terminal 9201 can be reversibly deformed from the expanded state to the folded state. For example, the portable information terminal 9201 can be bent with a curvature radius of 1 mm to 150 mm.

  The electronic device described in this embodiment includes a display portion for displaying some information. Note that the semiconductor device of one embodiment of the present invention can also be applied to an electronic device that does not include a display portion.

  The structure examples exemplified in this embodiment and the corresponding drawings can be implemented by combining at least part of the structure examples with other structure examples or the drawings as appropriate.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 5)
In this embodiment, an example of a television device to which a display device including the semiconductor device of one embodiment of the present invention can be applied will be described with reference to drawings.

  FIG. 18A shows a block diagram of the television device 600.

  In the drawings attached to the present specification, the components are classified by function and the block diagram is shown as an independent block. However, it is difficult to completely separate actual components by function. A component may be involved in multiple functions.

  The television apparatus 600 includes a control unit 601, a storage unit 602, a communication control unit 603, an image processing circuit 604, a decoder circuit 605, a video signal receiving unit 606, a timing controller 607, a source driver 608, a gate driver 609, a display panel 620, and the like. Have

  The display device described as an example in the above embodiment can be applied to the display panel 620 in FIG. Accordingly, the television device 600 having a large size and high resolution and excellent visibility can be realized.

  The control unit 601 can function as, for example, a central processing unit (CPU). For example, the control unit 601 has a function of controlling components such as the storage unit 602, the communication control unit 603, the image processing circuit 604, the decoder circuit 605, and the video signal receiving unit 606 via the system bus 630.

  A signal is transmitted between the control unit 601 and each component via the system bus 630. In addition, the control unit 601 has a function of processing a signal input from each component connected via the system bus 630, a function of generating a signal output to each component, and the like, thereby being connected to the system bus 630. Each component can be controlled centrally.

  The storage unit 602 functions as a register, a cache memory, a main memory, a secondary memory, or the like that can be accessed by the control unit 601 and the image processing circuit 604.

  As a storage device that can be used as the secondary memory, for example, a storage device to which a rewritable nonvolatile storage element is applied can be used. For example, a flash memory, an MRAM (Magnetostatic Random Access Memory), a PRAM (Phase change RAM), a ReRAM (Resistive RAM), an FeRAM (Ferroelectric RAM), or the like can be used.

  In addition, as a storage device that can be used as a temporary memory such as a register, a cache memory, or a main memory, a volatile storage element such as a DRAM (Dynamic RAM) or an SRAM (Static Random Access Memory) may be used.

  For example, as a RAM provided in the main memory, for example, a DRAM is used, and a memory space is virtually allocated and used as a work space of the control unit 601. The operating system, application program, program module, program data, etc. stored in the storage unit 602 are loaded into the RAM for execution. These data, programs, and program modules loaded in the RAM are directly accessed and operated by the control unit 601.

  On the other hand, the ROM can store BIOS (Basic Input / Output System), firmware and the like that do not require rewriting. As the ROM, a mask ROM, an OTPROM (One Time Programmable Read Only Memory), an EPROM (Erasable Programmable Read Only Memory), or the like can be used. Examples of EPROM include UV-EPROM (Ultra-Violet Erasable Programmable Read Only Memory) and EEPROM (Electrically Erasable Programmable Read Only Memory) capable of erasing stored data by ultraviolet irradiation.

  In addition to the storage unit 602, a removable storage device may be connected. For example, it has a terminal for connecting to a recording medium drive such as a hard disk drive (HDD) or a solid state drive (SSD) that functions as a storage device, a recording medium such as a flash memory, a Blu-ray disc, or a DVD. Is preferred. Thereby, a video can be recorded.

  The communication control unit 603 has a function of controlling communication performed via a computer network. For example, the control signal for connecting to the computer network is controlled in accordance with a command from the control unit 601, and the signal is transmitted to the computer network. As a result, the Internet, intranet, extranet, PAN (Personal Area Network), LAN (Local Area Network), CAN (Camper Area Network, and MAN (MetroApolNetwork), which are the foundations of the World Wide Web (WWW). Communication can be performed by connecting to a computer network such as Wide Area Network (GA) or GAN (Global Area Network).

  The communication control unit 603 has a function of communicating with a computer network or other electronic devices using a communication standard such as Wi-Fi (registered trademark), Bluetooth (registered trademark), or ZigBee (registered trademark). Also good.

  The communication control unit 603 may have a function of communicating wirelessly. For example, an antenna and a high frequency circuit (RF circuit) may be provided to transmit and receive an RF signal. The high-frequency circuit is a circuit for mutually converting an electromagnetic signal and an electric signal in a frequency band determined by the legislation of each country and performing communication with other communication devices wirelessly using the electromagnetic signal. Several tens of kHz to several tens of GHz is generally used as a practical frequency band. The high-frequency circuit connected to the antenna includes a high-frequency circuit unit corresponding to a plurality of frequency bands, and the high-frequency circuit unit includes an amplifier (amplifier), a mixer, a filter, a DSP, an RF transceiver, and the like. it can.

  The video signal receiving unit 606 includes, for example, an antenna, a demodulation circuit, an A / D conversion circuit (analog-digital conversion circuit), and the like. The demodulation circuit has a function of demodulating a signal input from the antenna. The A-D conversion circuit has a function of converting the demodulated analog signal into a digital signal. The signal processed by the video signal receiving unit 606 is sent to the decoder circuit 605.

  The decoder circuit 605 has a function of decoding video data included in a digital signal input from the video signal receiving unit 606 in accordance with the specification of a broadcast standard to be transmitted, and generating a signal to be transmitted to the image processing circuit. For example, as a broadcasting standard in 8K broadcasting, H.264 265 | MPEG-H High Efficiency Video Coding (abbreviation: HEVC).

  Examples of broadcast radio waves that can be received by the antenna included in the video signal receiving unit 606 include ground waves or radio waves transmitted from satellites. Broadcast radio waves that can be received by an antenna include analog broadcast and digital broadcast, and also includes video and audio, or audio-only broadcast. For example, broadcast radio waves transmitted in a specific frequency band in the UHF band (about 300 MHz to 3 GHz) or the VHF band (30 MHz to 300 MHz) can be received. In addition, for example, by using a plurality of data received in a plurality of frequency bands, the transfer rate can be increased and more information can be obtained. Accordingly, an image having a resolution exceeding full high-definition can be displayed on the display panel 620. For example, an image having a resolution of 4K2K, 8K4K, 16K8K, or higher can be displayed.

  Further, the video signal receiving unit 606 and the decoder circuit 605 may be configured to generate a signal to be transmitted to the image processing circuit 604 using broadcast data transmitted by a data transmission technique via a computer network. At this time, when the signal to be received is a digital signal, the video signal receiving unit 606 may not include a demodulation circuit, an A-D conversion circuit, and the like.

  The image processing circuit 604 has a function of generating a video signal to be output to the timing controller 607 based on the video signal input from the decoder circuit 605.

  The timing controller 607 also outputs a signal (a signal such as a clock signal or a start pulse signal) to be output to the gate driver 609 and the source driver 608 based on a synchronization signal included in the video signal or the like processed by the image processing circuit 604. It has a function to generate. The timing controller 607 has a function of generating a video signal to be output to the source driver 608 in addition to the above signals.

  The display panel 620 includes a plurality of pixels 621. Each pixel 621 is driven by signals supplied from the gate driver 609 and the source driver 608. Here, an example of a display panel having a resolution according to the 8K4K standard having the number of pixels of 7680 × 4320 is shown. Note that the resolution of the display panel 620 is not limited to this, and may be a resolution according to a standard such as full high-definition (pixel count 1920 × 1080) or 4K2K (pixel count 3840 × 2160).

  As the control unit 601 and the image processing circuit 604 illustrated in FIG. 18A, for example, a structure including a processor can be employed. For example, the control unit 601 can use a processor that functions as a central processing unit (CPU). Further, as the image processing circuit 604, for example, other processors such as a DSP (Digital Signal Processor) and a GPU (Graphics Processing Unit) can be used. In addition, the control unit 601 and the image processing circuit 604 may have a configuration in which the processor is realized by a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array) or an FPAA (Field Programmable Analog Array).

  The processor performs various data processing and program control by interpreting and executing instructions from various programs. The program that can be executed by the processor may be stored in a memory area of the processor, or may be stored in a storage device provided separately.

  In addition, two or more functions among the functions of the control unit 601, the storage unit 602, the communication control unit 603, the image processing circuit 604, the decoder circuit 605, the video signal receiving unit 606, and the timing controller 607 are provided. A system LSI may be configured by concentrating on one IC chip. For example, a system LSI including a processor, a decoder circuit, a tuner circuit, an A / D conversion circuit, a DRAM, and an SRAM may be used.

  Note that a transistor in which an oxide semiconductor is used for a channel formation region and an extremely low off-state current is realized can be used for the controller 601, an IC included in another component, or the like. Since the transistor has extremely low off-state current, the use of the transistor as a switch for holding charge (data) flowing into the capacitor functioning as a memory element can ensure a data holding period for a long time. it can. By using this characteristic for a register such as the control unit 601 or a cache memory, the control unit 601 is operated only when necessary, and in other cases, information on the immediately preceding process is saved in the storage element, so that it is normally. Off-computing becomes possible. Thereby, the power consumption of the television apparatus 600 can be reduced.

  Note that the structure of the television device 600 illustrated in FIG. 18A is an example, and it is not necessary to include all of the components. The television device 600 only needs to include necessary components from among the components illustrated in FIG. In addition, the television device 600 may include a component other than the components illustrated in FIG.

  For example, the television device 600 may include an external interface, an audio output unit, a touch panel unit, a sensor unit, a camera unit, and the like in addition to the configuration illustrated in FIG. For example, as an external interface, for example, a USB (Universal Serial Bus) terminal, a LAN (Local Area Network) connection terminal, a power receiving terminal, an audio output terminal, an audio input terminal, an image output terminal, an image input terminal, etc. External connection terminals, transceivers for optical communication using infrared rays, visible light, ultraviolet rays, etc., physical buttons provided on the housing, and the like. For example, the sound input / output unit includes a sound controller, a microphone, a speaker, and the like.

  Hereinafter, the image processing circuit 604 will be described in more detail.

  The image processing circuit 604 preferably has a function of executing image processing based on the video signal input from the decoder circuit 605.

  Examples of image processing include noise removal processing, gradation conversion processing, color tone correction processing, and luminance correction processing. Examples of color tone correction processing and luminance adjustment processing include gamma correction.

  The image processing circuit 604 preferably has a function of executing processing such as inter-pixel interpolation processing associated with resolution up-conversion and inter-frame interpolation processing associated with frame frequency up-conversion.

  For example, as noise removal processing, various noises such as mosquito noise generated around the outline of characters, block noise generated in high-speed moving images, flickering random noise, and dot noise generated by resolution up-conversion are removed.

  The gradation conversion process is a process for converting the gradation of an image into a gradation corresponding to the output characteristics of the display panel 620. For example, when the number of gradations is increased, a process for smoothing the histogram can be performed by interpolating and assigning gradation values corresponding to each pixel to an image input with a small number of gradations. Further, a high dynamic range (HDR) process for expanding the dynamic range is also included in the gradation conversion process.

  The inter-pixel interpolation process interpolates data that does not originally exist when the resolution is up-converted. For example, referring to pixels around the target pixel, the data is interpolated so as to display the intermediate colors.

  The color tone correction process is a process for correcting the color tone of an image. The brightness correction process is a process for correcting the brightness (brightness contrast) of the image. For example, the type, brightness, or color purity of the illumination arranged in the space in which the television apparatus 600 is provided is detected, and the brightness and color tone of the image displayed on the display panel 620 are corrected accordingly. . Or, it has a function to compare the image to be displayed with the images of various scenes in the image list stored in advance, and to correct the image displayed with the brightness and color tone suitable for the image of the closest scene. May be.

  Interframe interpolation generates an image of a frame (interpolation frame) that does not originally exist when the frame frequency of a video to be displayed is increased. For example, an interpolation frame image to be inserted between two images is generated from the difference between two images. Alternatively, an image of a plurality of interpolation frames can be generated between two images. For example, when the frame frequency of the video signal input from the decoder circuit 605 is 60 Hz, the frame frequency of the video signal output to the timing controller 607 is doubled by 120 Hz by generating a plurality of interpolation frames, or It can be increased to 4 times 240 Hz or 8 times 480 Hz.

  The image processing circuit 604 preferably has a function of executing image processing using a neural network. FIG. 18A illustrates an example in which the image processing circuit 604 includes a neural network 610.

  For example, the neural network 610 can perform feature extraction from image data included in a video, for example. Further, the image processing circuit 604 can select an optimal correction method according to the extracted feature, or can select a parameter used for correction.

  Alternatively, the neural network 610 itself may have a function of performing image processing. That is, the image data that has been subjected to image processing may be output by inputting the image data before being subjected to image processing to the neural network 610.

  In addition, weight coefficient data used for the neural network 610 is stored in the storage unit 602 as a data table. The data table including the weighting coefficient can be updated to the latest one via the computer network by the communication control unit 603, for example. Alternatively, the image processing circuit 604 may have a learning function so that a data table including a weighting factor can be updated.

  FIG. 18B shows a schematic diagram of a neural network 610 included in the image processing circuit 604.

  In this specification and the like, a neural network refers to a general model that imitates a biological neural network, determines the connection strength between neurons by learning, and has problem solving ability. The neural network has an input layer, an intermediate layer (also referred to as a hidden layer), and an output layer. A neural network having two or more intermediate layers is called deep learning (or deep neural network (DNN)).

  In this specification and the like, when describing a neural network, determining the connection strength (also referred to as a weighting factor) between neurons from existing information may be referred to as “learning”. Further, in this specification and the like, there is a case where “inference” refers to constructing a neural network using the connection strength obtained by learning and deriving a new conclusion therefrom.

  The neural network 610 includes an input layer 611, one or more intermediate layers 612, and an output layer 613. Input data is input to the input layer 611. Output data is output from the output layer 613.

  The input layer 611, the intermediate layer 612, and the output layer 613 each have a neuron 615. Here, the neuron 615 indicates a circuit element (product-sum operation element) capable of realizing product-sum operation. In FIG. 18B, the input / output direction of data between two neurons 615 included in two layers is indicated by arrows.

Arithmetic processing in each layer is executed by a product-sum operation between the output of the neuron 615 included in the previous layer and the weight coefficient. For example, if the output of the i-th neuron in the input layer is x _i and the connection strength (weight coefficient) between the output x _i and the j-th neuron in the next intermediate layer 612 is w _ji , The output y _j of the j-th neuron is y _j = f (Σw _ji · x _i ). Note that i and j are integers of 1 or more. Here, f (x) is an activation function, and a sigmoid function, a threshold function, or the like can be used. Similarly, the output of the neuron 615 of each layer is a value obtained by calculating the activation function on the product-sum operation result of the output of the neuron 615 of the previous layer and the weight coefficient. The connection between layers may be a total connection in which all neurons are connected, or a partial connection in which some neurons are connected. FIG. 18B shows the case of full coupling.

  FIG. 18B illustrates an example having three intermediate layers 612. Note that the number of the intermediate layers 612 is not limited to this, and it is only necessary to include one or more intermediate layers. In addition, the number of neurons included in one intermediate layer 612 may be changed as appropriate according to specifications. For example, the number of neurons 615 included in one intermediate layer 612 may be larger or smaller than the number of neurons 615 included in the input layer 611 or the output layer 613.

  A weighting factor that is an index of the strength of connection between the neurons 615 is determined by learning. The learning may be executed by a processor included in the television apparatus 600, but is preferably executed by a computer having an excellent arithmetic processing capability such as a dedicated server or a cloud. The weighting coefficient determined by learning is stored in the storage unit 602 as a table and is used by being read out by the image processing circuit 604. The table can be updated via a computer network as necessary.

  This completes the description of the neural network.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

DL_Y data line DL_1 data line DLa1 source line DLa2 source line DLb1 source line DLb2 source line GL_X gate line GL_1 gate line GL_2 gate line 100 transistor 100A transistor 100B transistor 100C transistor 102 substrate 104 insulating layer 106 conductive layer 108 semiconductor layer 108f metal oxide Film 108i region 108n region 108x region 110a insulating layer 110b insulating layer 110f insulating film 112 conductive layer 112f conductive film 114 metal oxide layer 114f metal oxide film 116 layer 117 metal oxide layer 118 insulating layer 120a conductive layer 120b conductive layer 141a opening Part 141b opening 142 opening 210 insulating layer 210f insulating film 312 conductive layer 312f conductive film 314 metal oxide layer 314f metal oxide film 316 insulation Layer 501 Pixel circuit 502 Pixel portion 504 Drive circuit portion 504a Gate driver 504b Source driver 506 Protection circuit 507 Terminal portion 550 Transistor 552 Transistor 554 Transistor 560 Capacitance element 562 Capacitance element 570 Liquid crystal element 572 Light emitting element 600 Television apparatus 601 Control portion 602 Storage Unit 603 communication control unit 604 image processing circuit 605 decoder circuit 606 video signal receiving unit 607 timing controller 608 source driver 609 gate driver 610 neural network 611 input layer 612 intermediate layer 613 output layer 615 neuron 620 display panel 621 pixel 630 system bus 700 display Device 700A Display device 701 Substrate 702 Pixel portion 704 Source driver circuit portion 705 Substrate 706 Gate dry Circuit portion 708 FPC terminal portion 710 signal line 710a a signal line 711 wiring portion 712 sealing material 716 FPC
721 Source Driver IC
722 Gate driver circuit 723 FPC
724 Printed circuit board 730 Insulating film 732 Sealing film 734 Insulating film 736 Colored film 738 Light shielding film 750 Transistor 752 Transistor 754 Transistor 760 Connection electrode 770 Flattened insulating film 772 Conductive film 773 Insulating film 774 Conductive film 775 Liquid crystal element 776 Liquid crystal layer 778 Structure Body 780 Anisotropic conductive film 782 Light emitting element 786 EL layer 788 Conductive film 791 Touch panel 792 Insulating film 793 Electrode 794 Electrode 795 Insulating film 796 Electrode 797 Insulating film 8000 Camera 8001 Housing 8002 Display unit 8003 Operation button 8004 Shutter button 8006 Lens 8100 Viewfinder 8101 Housing 8102 Display unit 8103 Button 8200 Head mounted display 8201 Mounting unit 8202 Lens 8203 Main body 8204 Display unit 8205 Cable 8206 Battery 8300 Head mounted display 8301 Case 8302 Display unit 8304 Fixture 8305 Lens 9000 Case 9001 Display unit 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9100 Television John apparatus 9101 portable information terminal 9102 portable information terminal 9200 portable information terminal 9201 portable information terminal

Claims (9)

A first transistor and a second transistor;
The first transistor includes a first semiconductor layer, a first insulating layer, a first conductive layer, and a sidewall insulating layer,
The first insulating layer is located between the first semiconductor layer and the first conductive layer;
The end portion of the first conductive layer is located inside the end portion of the first insulating layer,
The sidewall insulating layer is in contact with an upper surface of the first insulating layer and a side surface of the first conductive layer;
The second transistor includes a second semiconductor layer, a second insulating layer, and a second conductive layer,
The second insulating layer is located between the second semiconductor layer and the second conductive layer,
The second gate insulating layer is a semiconductor device having a thickness greater than that of the first gate insulating layer. In claim 1,
The sidewall insulating layer is a semiconductor device having the same material as the second insulating layer. In claim 1 or claim 2,
The sidewall insulating layer is a semiconductor device formed by processing the same insulating film as the second insulating layer. In any one of Claim 1 thru | or 3,
The second transistor further includes a third insulating layer,
The third insulating layer is located between the second semiconductor layer and the second insulating layer;
The third insulating layer and the second insulating layer are semiconductor devices having substantially the same top surface shape. In claim 4,
The third insulating layer is a semiconductor device having the same material as the first insulating layer. In claim 4 or claim 5,
The third insulating layer is a semiconductor device formed by processing the same insulating film as the first insulating layer. In any one of Claims 1 thru | or 6,
The width of the first conductive layer in the channel length direction is a semiconductor device smaller than the width of the second conductive layer in the channel length direction. In any one of Claim 1 or Claim 7,
The first semiconductor layer and the second semiconductor layer are semiconductor devices each having a metal oxide. A semiconductor device according to any one of claims 1 to 8,
A display device comprising: a liquid crystal element or a light emitting element electrically connected to the semiconductor device.

Images