JP2019071400A - Semiconductor device, display device and semiconductor device manufacturing method - Google Patents

Abstract

To provide a semiconductor device having good electrical characteristics.SOLUTION: In a semiconductor device, because a metal oxide layer 114 having high barrier properties is provided between a conductive layer 112 and an insulation layer 110, even when metal which is apt to absorb oxygen such as aluminum and copper is used for the conductive layer, diffusion of oxygen from the insulation layer to the conductive layer can be prevented. Alternatively, even when the conductive layer contains hydrogen, supply of hydrogen from the conductive layer to a semiconductor layer 108 via the insulation layer can be inhibited. As a result, carrier density of a region 108i as a channel formation region of the semiconductor layer 108 can be reduced. Alternatively, such a formation where a metal oxide film such as an aluminum oxide film and a hafnium oxide film which does not consist primarily of nitrogen is used between the semiconductor layer 108 and the conductive layer functioning as a gate electrode may be allowable. For that reason, the metal oxide layer 114 can be formed with very little amount of nitrogen oxide which is capable of forming a level in the film.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. One embodiment of the present invention relates to a display device and a method for manufacturing the display device.

  Note that one embodiment of the present invention is not limited to the above technical field. Semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, and driving methods thereof are given as technical fields of one embodiment of the present invention disclosed in this specification and the like Or their production methods can be mentioned as an example.

  Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor, a semiconductor circuit, an arithmetic device, a memory device, and the like are one embodiment of a semiconductor device. In addition, an imaging device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like), and an electronic device may include a semiconductor device.

  An oxide semiconductor using a metal oxide has attracted attention as a semiconductor material applicable to a transistor. For example, in Patent Document 1, a plurality of oxide semiconductor layers are stacked, and among the plurality of oxide semiconductor layers, the oxide semiconductor layer to be a channel contains indium and gallium, and the ratio of indium is the ratio of gallium A semiconductor device is disclosed in which the field effect mobility (simply referred to as mobility or μFE in some cases) is increased by making the size larger than that.

  A metal oxide that can be used for the semiconductor layer can be formed by a sputtering method or the like, and thus can be used for a semiconductor layer of a transistor included in a large display device. In addition, since it is possible to improve and use a part of a production facility of a transistor using polycrystalline silicon or amorphous silicon, facility investment can be suppressed. In addition, since a transistor using a metal oxide has higher field effect mobility than the case where amorphous silicon is used, a high-performance display device in which a display portion and a driver circuit are integrally formed can be realized.

  Further, as a transistor using an oxide semiconductor, a transistor with a self-aligned structure has been proposed. As a transistor having the self-aligned structure, a metal film is formed over the source region and the drain region, and heat treatment is performed on the metal film to increase the resistance of the metal film and to reduce the resistance of the source region and the drain region. Patent Document 2 discloses a method of

JP, 2014-7399, A JP, 2011-228622, A

  In Patent Document 2, when the resistance of the source region and the drain region is reduced, a metal film is formed on the source region and the drain region, and heat treatment is performed on the metal film in an oxygen atmosphere. By heat treatment, a constituent element of the metal film is introduced as a dopant into the source region and the drain region of the oxide semiconductor film to reduce resistance. Further, heat treatment is performed in an oxygen atmosphere to oxidize the conductive film and to increase the resistance of the conductive film. However, since heat treatment is performed in an oxygen atmosphere, the metal film has a low effect of extracting oxygen from the oxide semiconductor film.

  Further, Patent Document 2 describes the oxygen concentration in the channel formation region, but does not mention the concentration of impurities such as water and hydrogen. That is, there is a problem that the transistor characteristics of normally on are likely to be obtained because the channel formation region is not highly purified (reduction of impurities such as water and hydrogen, typically dehydration / dehydrogenation). . Note that the normally-on transistor characteristic is a state in which a channel is present even when a voltage is not applied to the gate, and current flows in the transistor. On the other hand, the normally-off transistor characteristic is a state in which no current flows in the transistor when no voltage is applied to the gate.

  In view of the above problems, one aspect of the present invention provides a semiconductor device having favorable electrical characteristics by stably reducing the resistance of the source region and the drain region of the transistor and by purifying the channel formation region. To be one of the issues.

  An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object is to provide a semiconductor device with stable electrical characteristics. Another object is to provide a highly reliable semiconductor device or a display device.

  Note that the descriptions of these objects do not disturb the existence of other objects. Note that in one embodiment of the present invention, it is not necessary to solve all of these problems. In addition, subjects other than these can be extracted from description of a specification, a drawing, a claim, etc.

  One embodiment of the present invention is a semiconductor device including a metal oxide layer, wherein the metal oxide layer includes a first metal element and a second metal element, and the metal oxide layer includes a first metal element. A first insulating layer on the first region, a conductor on the first insulating layer, a first insulating layer, a conductor, and a second region, each having a region and a second region And a third region is provided in the vicinity of the interface between the second region and the first layer, and the first region in the third region is provided. The concentration of the metal element is a semiconductor device larger than the concentration of the metal element in the second region.

  In the above, the first metal element is preferably In, and the second metal element is preferably any one or more selected from Ga, Sn, and Zn.

  One embodiment of the present invention is a semiconductor device having a metal oxide layer, and the metal oxide layer has a first metal element, a second metal element, and a third metal element, and is a metal oxide. The layer has a first region and a second region, and a first insulating layer on the first region, a conductor on the first insulating layer, a first insulating layer, a conductor, And a first layer provided to cover the second region, and a third region is provided in the vicinity of the interface between the second region and the first layer, The concentration of the first metal element in the second region is higher than the concentration of the metal element in the second region.

  In the above, it is preferable that the first metal element is In, the second metal element is Ga, and the third metal element is Zn.

  In the above, the atomic ratio of In is preferably larger than the atomic ratio of Ga.

  In the above, the first layer preferably comprises aluminum.

  In the above, the first layer preferably comprises aluminum nitride.

  In the above, the second region is preferably lower in resistance than the first region.

  In the above, the metal oxide layer preferably has crystallinity.

  In the above, the metal oxide layer preferably has a crystal part, and the crystal part preferably has c-axis orientation.

  According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided by stably reducing the resistance of the source region and the drain region of the transistor and by purifying the channel formation region. .

  According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, a semiconductor device with stable electrical characteristics can be provided. Alternatively, a highly reliable semiconductor device or display device can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description of the specification, drawings, claims and the like.

Configuration example of a transistor. Configuration example of a transistor. Configuration example of a transistor. Structural examples of a transistor, a capacitor, and the like. 7A to 7C illustrate a method for manufacturing a transistor, a capacitor, and the like. 7A to 7C illustrate a method for manufacturing a transistor, a capacitor, and the like. 7A to 7C illustrate a method for manufacturing a transistor, a capacitor, and the like. FIG. FIG. 2 is a cross-sectional view of a display device. FIG. 2 is a cross-sectional view of a display device. FIG. 2 is a cross-sectional view of a display device. FIG. 2 is a cross-sectional view of a display device. FIG. 2 is a cross-sectional view of a display device. 6A and 6B are a block diagram and a circuit diagram of a display device. FIG. 14 is a block diagram of a display device. FIG. Configuration example of display module. Configuration example of an electronic device. Configuration example of an electronic device. The structural example of a television apparatus. The figure explaining the resistivity and the transmittance | permeability of the sample in a present Example. The XPS spectrum of the sample in a present Example. The XPS spectrum of the sample in a present Example. The figure explaining the sheet resistance of the sample in a present Example. The figure explaining ESR signal of g value 1.93 of the sample in a present Example. The XPS spectrum of the sample in a present Example.

  Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be practiced in many different aspects and that the form and details can be variously changed without departing from the spirit and scope thereof . Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

Embodiment 1
In this embodiment, a structural example of a semiconductor device of one embodiment of the present invention and an example of a manufacturing method thereof will be described. The semiconductor device illustrated below can be particularly suitably used for a pixel portion or a driver circuit portion of a display device.

  One embodiment of the present invention is a transistor including a semiconductor layer in which a channel is formed, a gate insulating layer over the semiconductor layer, and a gate electrode over the gate insulating layer over a formation surface. The semiconductor layer is configured to include a metal oxide exhibiting semiconductor characteristics (hereinafter, also referred to as an oxide semiconductor). Hereinafter, the semiconductor layer may be referred to as a first metal oxide layer.

  The top surfaces of the gate electrode and the gate insulating layer preferably have substantially the same shape. In other words, the gate electrode and the gate insulating layer are preferably processed so that the side surfaces are continuous. For example, after laminating an insulating film to be a gate insulating layer and a conductive film to be a gate electrode, the gate insulating film can be formed by continuous processing using the same etching mask. Alternatively, the gate insulating layer may be formed by processing the insulating film using the previously processed gate electrode as a hard mask.

  Here, when a region overlapping with the gate electrode and the gate insulating layer of the semiconductor layer is a first region and a region not overlapping with these is a second region, the first region functions as a channel formation region, and The region 2 functions as a source region or a drain region. At this time, the second region is desired to have lower resistance than the first region.

  One embodiment of the present invention is a method for forming a second layer by forming a gate insulating layer and a gate electrode over a semiconductor layer, then forming a first layer so as to cover a second region of the semiconductor layer and performing heat treatment. Reduce the resistance of the area. In addition, the metal element contained in the semiconductor layer is deposited in the vicinity of the first layer in the formation of the first layer or by heat treatment. Here, the deposition of the metal element includes the case where the oxygen atom bonded to the metal element in the semiconductor layer is moved to the first layer to precipitate the metal element. The abundance ratio and concentration of oxygen atoms and metal elements in the semiconductor layer and the first layer may be determined using analysis methods such as X-ray photoelectron spectroscopy (XPS) or energy dispersive X-ray spectroscopy (EDX). it can. For example, when the amount of oxygen atoms relatively decreases with respect to the metal element contained in the semiconductor layer, the concentration of the metal element can be considered to be increased in the semiconductor layer.

  As the first layer, a film containing at least one of metal elements such as aluminum, titanium, tantalum, tungsten, chromium, and ruthenium can be used. In particular, it is preferable to contain at least one of aluminum, titanium, tantalum and tungsten. Alternatively, a nitride containing at least one of these metal elements, or an oxide containing at least one of these metal elements can be preferably used. In particular, a nitride film such as an aluminum nitride film, a titanium nitride film, or an aluminum titanium nitride film, an oxide film such as an aluminum titanium oxide film, or the like can be suitably used. Alternatively, a nitride containing silicon can be used as the first layer. For example, a silicon nitride film can be used as a nitride containing silicon.

In particular, since the aluminum nitride film has insulating properties and high transmittance to visible light, when the semiconductor device of this embodiment is used for a display device such as an EL display or a liquid crystal display, it is nitrided as the first layer. It is preferred to use an aluminum film. When an aluminum nitride film is used as the first layer, it is preferable to use a film whose composition formula satisfies AlN _x (x is a real number greater than 0 and 2 or less).

  Further, the higher the temperature of the heat treatment, the lower the resistance of the second region is promoted, which is preferable. The temperature of the heat treatment may be determined in consideration of the heat resistance of the gate electrode and the like. For example, the temperature can be 200 ° C. to 500 ° C., preferably 250 ° C. to 450 ° C., more preferably 300 ° C. to 400 ° C. For example, by setting the temperature of the heat treatment to about 350 ° C., semiconductor devices can be produced with high yield in a production facility using a large glass substrate.

  The thickness of the first layer can be, for example, 0.5 nm or more and 40 nm or less, preferably 3 nm or more and 30 nm or less, and more preferably 5 nm or more and 20 nm or less. Typically, it can be about 5 nm or about 20 nm. Even when the first layer is as thin as several nm (specifically, 0.5 nm or more and 10 nm or less), the resistance of the metal oxide film can be sufficiently reduced.

  On the other hand, for the first layer, it is preferable to use a material which is difficult to permeate hydrogen (a material having a hydrogen blocking property). Thus, the mixing and diffusion of hydrogen into the semiconductor layer from above the semiconductor layer can be suppressed. In addition, as the first layer, a material which hardly transmits oxygen (a material having an oxygen blocking property) is preferably used. Thus, desorption of oxygen from the semiconductor layer can be suppressed, and oxygen can be confined in the semiconductor layer. Therefore, the thickness of the first layer may be determined in consideration of the resistance reduction, the hydrogen blocking property, and the oxygen blocking property of the metal oxide film.

  The second region can also be referred to as a low resistance region because it has lower resistance than the first region. In addition, it is important to set a region with higher carrier density than the first region to be a channel formation region. For example, the low-resistance region can be a region containing more hydrogen than the channel formation region or a region containing more oxygen vacancies than the channel formation region. When an oxygen vacancy in the oxide semiconductor and a hydrogen atom are bonded to each other, a carrier is generated.

  By performing heat treatment in a state in which the first layer is provided in contact with the second region, oxygen in the second region is attracted to the first layer, and many oxygen vacancies are generated in the second region. It can be formed. Thereby, a very low resistance second region can be formed.

  The sheet resistance of the second region thus formed is preferably 1000 Ω / square (Ω / sq.) Or less, and 500 Ω / sq. The following are more preferable.

  The second region thus formed has a feature that it is difficult to increase the resistance in a later process. For example, even if heat treatment in an atmosphere containing oxygen or film formation treatment in an atmosphere containing oxygen is performed, there is no possibility that the conductivity of the second region is impaired, so that the electrical characteristics are excellent. And, a highly reliable transistor can be realized.

  Here, by applying the above-described method for reducing the resistance of the metal oxide film, one electrode of the capacitor can be manufactured at the same time. Hereinafter, a method for manufacturing an electrode of a capacitor is described.

  First, a second metal oxide layer is formed on the same plane as the first metal oxide layer. It is preferable to form the second metal oxide layer by processing the same metal oxide film as the first metal oxide layer because the number of steps is not increased. Subsequently, at the time of forming the first layer, the second layer is formed in contact with the second metal oxide layer, and heat treatment is performed to form the second metal oxide layer with low resistance. it can. Also in the second metal oxide layer, the metal element contained in the metal oxide layer may be precipitated in the vicinity of the first layer.

  As the other electrode of the capacitor, a conductive layer formed by processing the same conductive film as the conductive layer included in the transistor can be preferably used. For example, the other electrode of the capacitor can be formed by processing the same conductive film as the source electrode, the drain electrode, the second gate electrode, and the like of the transistor.

  Here, in the case where the same conductive film as the source electrode or the drain electrode of the transistor is processed to form the other electrode of the capacitor, an insulating first layer can be provided between the pair of electrodes. For example, since the above-described aluminum nitride film or the like is a material having a high insulating property and a relatively high dielectric constant, it can be suitably used as a dielectric of a capacitor.

  As described above, in one embodiment of the present invention, the transistor and the capacitor can be manufactured in the same process. For example, the transistor and the capacitor can be suitably applied to a pixel portion or a driver circuit portion of a display device provided with a liquid crystal element or a light emitting element. Thereby, a highly reliable display device can be realized.

  Hereinafter, more specific examples will be described with reference to the drawings.

[Configuration Example 1]
1A is a top view of the transistor 100, FIG. 1B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line A1-A2 in FIG. 1A, and FIG. 1A corresponds to a cross-sectional view taken along a dashed-dotted line B1-B2 shown in FIG. Note that in FIG. 1A, some of components of the transistor 100 (a gate insulating layer or the like) are omitted. In addition, the direction of the dashed-dotted line A1-A2 may be referred to as a channel length direction, and the direction of the dashed-dotted line B1-B2 may be referred to as a channel width direction. In the top view of the transistor, as in FIG. 1A, some of the components may be omitted and illustrated in the following drawings.

  The transistor 100 includes the insulating layer 104, the semiconductor layer 108, the insulating layer 110, the metal oxide layer 114, the conductive layer 112, the first layer 116, the insulating layer 118, and the like. The semiconductor layer 108 is provided over the insulating layer 104. The insulating layer 110, the metal oxide layer 114, and the conductive layer 112 are stacked in this order over the semiconductor layer 108. The first layer 116 is provided to cover the insulating layer 104, the top and side surfaces of the semiconductor layer 108, the side surface of the insulating layer 110, the side surface of the metal oxide layer 114, and the top and side surfaces of the conductive layer 112. An insulating layer 118 is provided to cover the first layer 116.

  A part of the conductive layer 112 functions as a gate electrode. A part of the insulating layer 110 functions as a gate insulating layer. The transistor 100 is a so-called top gate transistor in which a gate electrode is provided over the semiconductor layer 108.

  The semiconductor layer 108 preferably contains a metal oxide. The semiconductor layer 108 includes a region 108i in contact with the insulating layer 110 and a pair of regions 108n sandwiching the region 108i. The region 108 n is provided in contact with the first layer 116.

  A region 108 i of the semiconductor layer 108 which overlaps with the conductive layer 112 functions as a channel formation region of the transistor 100. The region 108 n has lower resistance than the region 108 i and functions as a source region or a drain region of the transistor 100.

  In addition, the top surfaces of the conductive layer 112, the metal oxide layer 114, and the insulating layer 110 substantially match each other.

  In the present specification and the like, “the top surface shapes substantially match” means that at least a part of the contours overlap between the stacked layers and the layers. For example, the case where the upper layer and the lower layer are processed by the same mask pattern or a part of the same mask pattern is included. However, strictly speaking, the outlines do not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer.

  The first layer 116 is provided in contact with the region 108 n of the semiconductor layer 108. Further, as shown in FIG. 1B, since the first layer 116 is in contact with both the semiconductor layer 108 and the conductive layer 112, the first layer 116 preferably has an insulating property.

  As the first layer 116, a film containing at least one of metal elements such as aluminum, titanium, tantalum, tungsten, chromium, and ruthenium can be used. In particular, it is preferable to contain at least one of aluminum, titanium, tantalum and tungsten. For example, a nitride containing at least one of these metal elements, or an oxide containing at least one of these metal elements can be suitably used. In particular, a nitride film such as an aluminum nitride film, a titanium nitride film, or an aluminum titanium nitride film, an oxide film such as an aluminum titanium oxide film, or the like can be suitably used. Alternatively, a nitride containing silicon can be used as the first layer 116. For example, a silicon nitride film can be used as a nitride containing silicon.

For example, in the case of using an aluminum nitride film as the first layer 116, a film whose composition formula satisfies AlN _x (x is a real number greater than 0 and 2 or less) is preferably used.

For example, when using a titanium nitride film, it is preferable to use a film whose composition formula satisfies TiN _x (x is a real number greater than 0 and 2 or less). When an aluminum titanium nitride film is used, the composition formula is AlTiN _x (x is a real number greater than 0 and 3 or less), or the composition formula is AlTi _x N _y (x is a real number greater than 0 and 2 or less, y is more than 0) It is preferable to use a film that largely satisfies 4 or less.

  The region 108 n is a part of the semiconductor layer 108 and has a lower resistance than the region 108 i which is a channel formation region. The region 108n is a region where the carrier density is higher than the region 108i, a region where the oxygen defect density is high, a region where the nitrogen concentration is high, a region which is n-type, or a region where the hydrogen concentration is high. In addition, the metal element included in the first layer 116 may be diffused in the region 108 n. FIG. 3 is an enlarged view of a region 150 surrounded by a dotted line in FIG. As shown in FIG. 3, in a region 115 shown in the vicinity of the first layer 116 in the region 108 n, the metal element contained in the semiconductor layer 108 is precipitated. For example, as the semiconductor layer 108, a metal oxide containing In, Ga, Zn, described later, such as a metal oxide containing In, M, Zn (M is gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium In the case where one or more elements selected from beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium are used, In Be done. Alternatively, in addition to In, one or more of Zn and a metal represented by M may be precipitated.

  Although the region 115 is illustrated as part of the region 108 n in FIG. 3, the region 115 may be provided between the region 108 n and the first layer 116. The region 115 may be provided on the region 108 n side, may be provided on the first layer 116 side, or may be provided on both the region 108 n and the first layer 116. That is, it can be expressed that the region 115 is provided in the vicinity of the interface between the region 108 n and the first layer 116. Note that the regions 115 preferably exist in layers. On the other hand, the region 115 may exist in an island shape or a dot shape. The thickness of the region 115 may be 0.1 nm or more and 10 nm or less, preferably 0.1 nm or more and 5 nm or less, more preferably 0.1 nm or more and 3 nm or less, and the interface between the region 108 n and the first layer 116 In some cases, the film does not necessarily have a constant film thickness. The region 115 may have lower resistance than the region 108 n because the concentration of the metal element is higher than the region 108 n.

  Note that the deposition of the metal element includes the case where the metal atom is deposited by the movement of the oxygen atom bonded to the metal element to the first layer 116 in the semiconductor layer 108. The abundance ratio and concentration of oxygen atoms and metal elements in the semiconductor layer 108 and the first layer 116 are determined using an analysis method such as X-ray photoelectron spectroscopy (XPS) or energy dispersive X-ray spectroscopy (EDX). be able to. For example, when the amount of oxygen atoms relatively decreases with respect to the metal element contained in the semiconductor layer 108, the concentration of the metal element in the semiconductor layer 108 can be considered to be increased.

  In addition, as illustrated in FIGS. 1A and 1B, the transistor 100 may include the conductive layer 120 a and the conductive layer 120 b over the insulating layer 118. The conductive layer 120a and the conductive layer 120b function as a source electrode or a drain electrode. The conductive layer 120 a and the conductive layer 120 b are electrically connected to the region 108 n through the opening 141 a or the opening 141 b provided in the first layer 116 and the insulating layer 118, respectively.

  One or both of the insulating layer 104 and the insulating layer 110 functioning as a gate insulating layer preferably contains oxygen. When the insulating layer 104 or the insulating layer 110 contains oxygen, oxygen can be supplied to the semiconductor layer 108. Therefore, oxygen may compensate for oxygen vacancies which may be formed in the semiconductor layer 108, and a highly reliable semiconductor device can be provided.

  The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 functions as a barrier film that prevents oxygen released from the insulating layer 110 from diffusing to the conductive layer 112 side. For the metal oxide layer 114, for example, a material which is less permeable to oxygen than at least the insulating layer 110 can be used.

  In this structure, since the metal oxide layer 114 with high barrier properties is provided between the conductive layer 112 and the insulating layer 110, the conductive layer 112 uses a metal that easily sucks in oxygen such as aluminum or copper. Even in this case, diffusion of oxygen from the insulating layer 110 to the conductive layer 112 can be prevented. Further, even when the conductive layer 112 contains hydrogen, supply of hydrogen from the conductive layer 112 to the semiconductor layer 108 through the insulating layer 110 is suppressed. As a result, the carrier density of the region 108i which is a channel formation region of the semiconductor layer 108 can be reduced.

  As the metal oxide layer 114, an insulating material or a conductive material can be used. When the metal oxide layer 114 has insulating properties, it functions as part of the gate insulating layer. On the other hand, in the case where the metal oxide layer 114 has conductivity, it functions as part of the gate electrode.

  In particular, as the metal oxide layer 114, an insulating material having a higher dielectric constant than silicon oxide is preferably used. In particular, it is preferable to use an aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, or the like.

Further, a metal oxide film which does not contain nitrogen as its main component, such as an aluminum oxide film or a hafnium oxide film, can be used between the semiconductor layer 108 and the conductive layer 112 which functions as a gate electrode. Therefore, a nitrogen oxide (NO _x , x is more than 0 and 2 or less, preferably 1 or more and 2 or less, typically NO ₂ or NO) which can form a level in the film. The content of H can be extremely small. Thus, a transistor with excellent electrical characteristics and reliability can be realized.

  Aluminum oxide film, hafnium oxide film, hafnium aluminate film, etc. have a sufficiently high barrier property even when the film thickness is thin (for example, about 5 nm thick), so they can be formed thin and productivity is improved. It can be done. For example, the thickness of the metal oxide layer 114 can be 1 nm to 50 nm, preferably 3 nm to 30 nm. Furthermore, the aluminum oxide film, the hafnium oxide film, and the hafnium aluminate film are characterized by having a dielectric constant higher than that of a silicon oxide film or the like. As described above, since a thin insulating film having a high dielectric constant can be formed as the metal oxide layer 114, the strength of the gate electric field applied to the semiconductor layer 108 can be increased as compared to the case of using a silicon oxide film or the like. As a result, the drive voltage can be lowered and power consumption can be reduced.

  Further, the metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, in the case of forming an aluminum oxide film using a sputtering apparatus, oxygen can be favorably added to the semiconductor layer 108 by forming in an atmosphere containing oxygen gas. In the case of forming an aluminum oxide film using a sputtering apparatus, the film density can be increased, which is preferable.

  In the case of using a conductive material for the metal oxide layer 114, an oxide conductive material such as indium oxide or indium tin oxide can be used. Alternatively, the above-described metal oxide which can be used for the semiconductor layer 108 may be applied. In particular, a material containing the same element as the semiconductor layer 108 is preferably used. At this time, it is preferable to use, for example, a sputtering method using the same metal oxide target as the semiconductor layer 108 because a deposition apparatus can be shared.

  Further, in the metal oxide layer 114, it is preferable that water and hydrogen do not easily diffuse. Thus, even when the conductive layer 112 uses a material which easily diffuses water or hydrogen, diffusion of water or hydrogen into the insulating layer 110 or the semiconductor layer 108 can be prevented. In particular, an aluminum oxide film or a hafnium oxide film is preferable because of its high barrier property to water and hydrogen.

  The first layer 116 not only has a function of forming the region 108 n functioning as a low resistance region in the semiconductor layer 108 and a function of depositing a metal element in the region 115, but also suppresses transmission of hydrogen and oxygen. It is preferable to have the following function. Accordingly, mixing of hydrogen into the semiconductor layer 108 from above the first layer 116 is suppressed by heat or the like applied in the process, oxygen is released from the semiconductor layer 108, the insulating layer 110, and the like, and the insulating layer 118 is formed. It can suppress the diffusion to the Therefore, the carrier density of the region 108i which functions as a channel formation region can be prevented from increasing, and a highly reliable transistor can be realized.

  By providing the first layer 116 and the metal oxide layer 114, the carrier density of the region 108i which functions as a channel formation region of the semiconductor layer 108 can be reduced more effectively.

  Here, oxygen vacancies that may be formed in the semiconductor layer 108 and the semiconductor layer 108 will be described.

  Oxygen vacancies formed in the semiconductor layer 108 are problematic because they affect transistor characteristics. For example, when oxygen vacancies are formed in the semiconductor layer 108, hydrogen is bonded to the oxygen vacancies and can be a carrier supply source. When a carrier supply source is generated in the semiconductor layer 108, a change in the electrical characteristics of the transistor 100, typically, a shift in threshold voltage occurs. Therefore, in the semiconductor layer 108, the less oxygen vacancies, the better.

  Thus, in the semiconductor device in one embodiment of the present invention, the insulating film in the vicinity of the semiconductor layer 108, specifically, the insulating layer 104 formed below the semiconductor layer 108 contains oxygen. By transferring oxygen from the insulating layer 104 to the semiconductor layer 108, oxygen vacancies in the semiconductor layer 108 can be reduced.

  Note that the insulating layer 110 located above the semiconductor layer 108 may contain oxygen. At this time, by moving oxygen from the insulating layer 110 to the semiconductor layer 108, oxygen vacancies in the semiconductor layer 108 may be further reduced.

  The semiconductor layer 108 preferably contains a metal oxide. For example, the semiconductor layer 108 is formed of In and M (M is gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, It is preferable to have Zn and one or more selected from hafnium, tantalum, tungsten, or magnesium. In particular, M is preferably Al, Ga, Y or Sn.

  In particular, an oxide containing In, Ga, and Zn is preferably used as the semiconductor layer 108.

  The semiconductor layer 108 preferably includes a region in which the atomic ratio of In is larger than the atomic ratio of M. As the atomic ratio of In is larger, the field-effect mobility of the transistor can be improved.

  Here, in the case of a metal oxide containing In, Ga, and Zn, the bonding force between In and oxygen is weaker than the bonding force between Ga and oxygen, and therefore, when the atomic ratio of In is large, the metal oxide film There is a tendency for oxygen deficiency to form. In addition, the same tendency is obtained when the metal element indicated by M is used instead of Ga. When many oxygen vacancies are present in the metal oxide film, the electrical characteristics of the transistor and the reliability thereof are degraded.

  However, in one embodiment of the present invention, a very large amount of oxygen can be supplied to the semiconductor layer 108 including a metal oxide; therefore, a metal oxide material with a large atomic ratio of In can be used. Thus, a transistor having extremely high field effect mobility, stable electrical characteristics, and high reliability can be realized.

  For example, a metal oxide in which the atomic ratio of In is at least 1.5 times, at least 2 times, at least 3 times, at least 3.5 times, or at least 4 times the atomic ratio of M It can be used suitably.

  In particular, the ratio of the number of In, M, and Zn in the semiconductor layer 108 is preferably In: M: Zn = 5: 1: 6 or in the vicinity thereof. Here, in the vicinity, when In is 5, M is 0.5 or more and 1.5 or less, and Zn includes 5 or more and 7 or less.

  Note that the semiconductor layer 108 is not limited to the above composition. For example, the ratio of the numbers of atoms of In, M, and Zn in the semiconductor layer 108 is: In: M: Zn = 4: 2: 3 or near, or In: M: Zn = 3: 1: 2 or near It is preferable then.

  In addition, as the composition of the semiconductor layer 108, the ratio of the number of In, M, and Zn atoms in the semiconductor layer 108 may be approximately equal. That is, the ratio of the number of atoms of In, M, and Zn is: In: M: Zn = 1: 1: 1 or around, or In: M: Zn = 1: 1: 0.5 or around May be included.

  The metal oxide used for the semiconductor layer 108 may further contain nitrogen. At this time, the concentration of nitrogen contained in the metal oxide is 0.1 atomic% or more and 10 atomic% or less, preferably 0.1 atomic% or more and 2.5 atomic% or less, more preferably 0.1 atomic% or more and less than 1 atomic% Is preferred. A metal oxide containing nitrogen can be suitably used in a channel formation region because it is difficult to reduce resistance unless a special resistance reduction process is performed. Such a metal oxide containing nitrogen can be formed by using a gas containing nitrogen as a deposition gas. Further, the metal oxide containing nitrogen preferably has the above-described CAAC structure.

When the semiconductor layer 108 has a region in which the atomic ratio of In is larger than the atomic ratio of M, the field-effect mobility of the transistor 100 can be increased. Specifically, the field-effect mobility of the transistor 100 can exceed 10 cm ² / Vs, more preferably, the field-effect mobility of the transistor 100 can exceed 30 cm ² / Vs.

  For example, by using the above-described transistor with high field-effect mobility for a gate driver for generating a gate signal, a display device with a narrow frame width (also referred to as a narrow frame) can be provided. In addition, a wiring connected to a display device can be obtained by using the above-described transistor with high field-effect mobility for a source driver of a display device (in particular, a demultiplexer connected to an output terminal of a shift register of the source driver). A small number of display devices can be provided.

  Note that even when the semiconductor layer 108 has a region in which the atomic ratio of In is larger than the atomic ratio of M, if the crystallinity of the semiconductor layer 108 is high, the field effect mobility may be low.

  The crystallinity of the semiconductor layer 108 can be analyzed, for example, by analysis using X-ray diffraction (XRD) or analysis using a transmission electron microscope (TEM). .

  Here, impurities such as hydrogen or moisture mixed in the semiconductor layer 108 cause problems because they affect transistor characteristics. Therefore, in the semiconductor layer 108, it is preferable that the amount of impurities such as hydrogen or moisture be as low as possible.

It is preferable to use a metal oxide film which has a low impurity concentration and a low density of defect states as the semiconductor layer 108 because a transistor having excellent electrical characteristics can be manufactured. Here, the fact that the impurity concentration is low and the density of defect states is low (the number of oxygen vacancies is low) is referred to as high purity intrinsic or substantially high purity intrinsic. The high purity intrinsic or substantially high purity intrinsic metal oxide film can lower the carrier density because there are few sources of carriers. Therefore, in the transistor in which the channel formation region is formed in the metal oxide film, the threshold voltage is less likely to be negative (also referred to as normally on). In addition, since the high purity intrinsic or the substantially high purity intrinsic metal oxide film has a low defect state density, the trap state density may also be low. In addition, high purity intrinsic or substantially high purity intrinsic metal oxide films have extremely low off-state current, and even when the device has a channel width of 1 × 10 ⁶ μm and a channel length of 10 μm, the source electrode and the drain are When the voltage between electrodes (drain voltage) is in the range of 1 V to 10 V, it is possible to obtain the characteristic that the off current is less than the measurement limit of the semiconductor parameter analyzer, that is, less than 1 × 10 ⁻¹³ A.

  The semiconductor layer 108 may have a stacked structure of two or more layers.

  For example, the semiconductor layer 108 in which two or more metal oxide films different in composition are stacked can be used.

  For example, in the case of using In—Ga—Zn oxide, the ratio of the number of atoms of In, M, and Zn is: In: M: Zn = 5: 1: 6, In: M: Zn = 4: 2: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 1: 1, In: M: Zn = 1: 1: 0.5, In: M: Zn = 1: 3: It is preferable to use two or more of the films formed with a sputtering target in the vicinity of 4, or In: M: Zn = 1: 3: 2, or them.

  Alternatively, the semiconductor layer 108 in which two or more metal oxide films having different crystallinity are stacked can be used.

  For example, in the case of forming the semiconductor layer 108 in which two metal oxide films different in crystallinity are stacked, the same oxide target is used, and the film formation conditions are changed to be continuously formed without being exposed to the air. Is preferred.

  For example, the oxygen flow ratio at the time of film formation of the first metal oxide film to be formed first is made smaller than the oxygen flow ratio at the time of film formation of the second metal oxide film to be formed later. Alternatively, oxygen is not flowed at the time of forming the first metal oxide film. Thus, oxygen can be effectively supplied at the time of film formation of the second metal oxide film. In addition, the first metal oxide film has lower crystallinity than the second metal oxide film, and can be a film having high electrical conductivity. On the other hand, when the second metal oxide film provided on the upper side is a film having higher crystallinity than the first metal oxide film, damage is caused when the semiconductor layer 108 is processed or when the insulating layer 110 is formed. Can be suppressed. For example, a CAC-OS film can be used for the first metal oxide film and a CAAC-OS film can be used for the second metal oxide film.

  More specifically, the oxygen flow ratio at the time of film formation of the first metal oxide film is 0% or more and less than 50%, preferably 0% or more and 30% or less, more preferably 0% or more and 20% or less, In fact, it is 10%. In addition, the oxygen flow rate ratio at the time of film formation of the second metal oxide film is 50% to 100%, preferably 60% to 100%, more preferably 80% to 100%, further preferably 90% or more 100% or less, typically 100%. In addition, although conditions such as pressure, temperature, and electric power at the time of film formation may be different between the first metal oxide film and the second metal oxide film, conditions other than the oxygen flow ratio are the same. This is preferable because the time required for the film formation process can be shortened.

  With such a stacked structure of the semiconductor layer 108, a transistor with excellent electrical characteristics and high reliability can be realized.

  The above is the description of the configuration example 1.

  Hereinafter, a structural example of a transistor whose structure is partially different from that of Structural Example 1 will be described. In the following, the same parts as those of Configuration Example 1 may not be described. Further, in the drawings shown below, hatching patterns may be the same for portions having the same functions as in Configuration Example 1 and there may be cases where reference numerals are not given.

[Configuration Example 2]
2A is a top view of the transistor 100A, FIG. 2B is a cross-sectional view of the transistor 100A in the channel length direction, and FIG. 2C is a cross-sectional view of the transistor 100A in the channel width direction. .

  The transistor 100A is mainly different from Structural Example 1 in that the conductive layer 106 is provided between the substrate 102 and the insulating layer 104. The conductive layer 106 has a portion overlapping with the semiconductor layer 108 with the insulating layer 104 interposed therebetween.

  In the transistor 100A, the conductive layer 106 has a function as a first gate electrode (also referred to as a bottom gate electrode), and the conductive layer 112 has a function as a second gate electrode (also referred to as a top gate electrode). . Further, part of the insulating layer 104 functions as a first gate insulating layer, and part of the insulating layer 110 functions as a second gate insulating layer.

  A portion of the semiconductor layer 108 which overlaps with at least one of the conductive layer 112 and the conductive layer 106 functions as a channel formation region. Note that in the following, a portion (a portion corresponding to the region 108i) of the semiconductor layer 108 overlapping with the conductive layer 112 may be referred to as a channel formation region in order to facilitate the description. Instead, a channel can be formed in a portion overlapping with the conductive layer 106 (a portion corresponding to the region 108 n).

  Further, as illustrated in FIG. 2C, the conductive layer 106 may be electrically connected to the conductive layer 112 through the opening 142 provided in the insulating layer 104 and the insulating layer 110. Accordingly, the same potential can be applied to the conductive layer 106 and the conductive layer 112.

  The conductive layer 106 can be formed using the same material as the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, the conductive layer 106 is preferably formed using a material containing copper because resistance can be reduced.

  Further, as shown in FIGS. 2A and 2C, the conductive layer 112 and the conductive layer 106 preferably protrude outward beyond the end portion of the semiconductor layer 108 in the channel width direction. At this time, as shown in FIG. 2C, the whole of the semiconductor layer 108 in the channel width direction is covered with the conductive layer 112 and the conductive layer 106 with the insulating layer 110 and the insulating layer 104 interposed therebetween.

  With such a structure, the semiconductor layer 108 can be electrically surrounded by an electric field generated by the pair of gate electrodes. At this time, in particular, the same potential is preferably applied to the conductive layer 106 and the conductive layer 112. Accordingly, an electric field for inducing a channel can be effectively applied to the semiconductor layer 108, so that the on-state current of the transistor 100A can be increased. Therefore, the transistor 100A can be miniaturized.

  Note that the conductive layer 112 and the conductive layer 106 may not be connected to each other. At this time, a constant potential may be supplied to one of the pair of gate electrodes, and a signal for driving the transistor 100A may be supplied to the other. At this time, the threshold voltage in driving the transistor 100A with the other electrode can also be controlled by the potential supplied to the one electrode.

  The above is the description of the configuration example 2.

  Hereinafter, a configuration example in the case where a metal oxide layer which is formed on the same surface as the semiconductor layer 108 in the above configuration example and has a low resistance is applied to one electrode of a capacitor is described.

[Configuration Example 1 of Capacitive Element]
FIG. 4A is a cross-sectional view of the transistor 100 illustrated in Structural Example 1 and a capacitor 130A which can be formed in the same step.

  The capacitor 130A includes a metal oxide layer 108C functioning as one electrode, a conductive layer 120b functioning as the other electrode, and a part of the first layer 116 located therebetween and functioning as a dielectric. And a part of the insulating layer 118.

  The metal oxide layer 108C is a layer formed by processing the same metal oxide film as the semiconductor layer 108. The metal oxide layer 108C is a layer whose resistance is reduced similarly to the region 108n of the semiconductor layer 108.

  4A shows an example in which the insulating layer 119 is provided to cover the conductive layer 120a, the conductive layer 120b, and the insulating layer 118, and the conductive layer 109 is provided over the insulating layer 119.

  The conductive layer 109 is a layer that can be used as one electrode (pixel electrode) of the display element. For the conductive layer 109, a material which reflects visible light, a material which transmits visible light, or the like can be used depending on the structure of the display element.

  The conductive layer 109 is electrically connected to the conductive layer 120 b through an opening provided in the insulating layer 119.

  The insulating layer 119 functions as a planarization film. Accordingly, the flatness of the surface on which the conductive layer 109 which functions as a pixel electrode is formed can be improved, so that optical characteristics of the display element can be improved.

[Configuration Example 2 of Capacitive Element]
FIG. 4B is a cross-sectional view of the transistor 100A exemplified in Structural Example 2 and a capacitor 130B which can be formed in the same step.

  Capacitive element 130B includes metal oxide layer 108C functioning as one electrode, conductive layer 106C functioning as the other electrode, and a part of insulating layer 104 located therebetween and functioning as a dielectric. Ru.

  The conductive layer 106C is a layer formed by processing the same conductive film as the conductive layer 106 which functions as a first gate electrode of the transistor 100A.

  The conductive layer 120 b is electrically connected to the metal oxide layer 108 C through an opening provided in the insulating layer 118 and the first layer 116. Thus, one of the source and the drain of the transistor 100A and the capacitor 130B are electrically connected.

[Configuration Example 3 of Capacitive Element]
FIG. 4C is a cross-sectional view of the transistor 100A illustrated in Structural Example 2 and a capacitor 130C which can be formed in the same step.

  The capacitor 130C functions as one of the electrodes of the semiconductor layer 108, a part of the region 108n of the semiconductor layer 108, the conductive layer 106C as another electrode, and the insulating layer 104 located between them and functioning as a dielectric. It consists of a part.

  A portion (specifically, the region 108n) of the semiconductor layer 108 of the transistor 100A extends to a region overlapping with the conductive layer 106C, and forms one electrode of the capacitor 130C. Thus, the transistor 100A and the capacitor 130C are electrically connected.

  Note that FIG. 4C illustrates an example in which the conductive layer 109 is electrically connected to the region 108n through the conductive layer 120b; however, without providing the conductive layer 120b, the conductive layer 109 and the region 108n and May be in direct contact with each other.

  The above is the description of the configuration example of the capacitor.

[Component of semiconductor device]
Next, components included in the semiconductor device of the present embodiment will be described in detail.

〔substrate〕
The material of the substrate 102 and the like are not particularly limited, but at least the heat resistance needs to be able to withstand the heat treatment to be performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. Further, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied, and semiconductor elements are provided on these substrates. The substrate may be used as the substrate 102. When a glass substrate is used as the substrate 102, the sixth generation (1500 mm × 1850 mm), the seventh generation (1870 mm × 2200 mm), the eighth generation (2200 mm × 2400 mm), the ninth generation (2400 mm × 2800 mm), the tenth A large-sized display device can be manufactured by using a large-sized substrate such as a generation (2950 mm × 3400 mm) or a 10.5th generation, an 11th generation, or a 12th generation.

  Alternatively, a flexible substrate may be used as the substrate 102, and the transistor 100 and the like may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100 or the like. The release layer can be used for separation from the substrate 102 and reprinting onto another substrate after a semiconductor device is partially or entirely completed thereon. At that time, the transistor 100 and the like can be transferred to a substrate with low heat resistance or a flexible substrate.

[Insulating layer 104]
The insulating layer 104 can be formed as appropriate using a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like. The insulating layer 104 can be formed, for example, as a single layer or a stack of an oxide insulating film or a nitride insulating film. Note that in order to improve interface characteristics with the semiconductor layer 108, at least a region in contact with the semiconductor layer 108 in the insulating layer 104 is preferably formed using an oxide insulating film. Further, by using an oxide insulating film which releases oxygen by heating as the insulating layer 104, oxygen contained in the insulating layer 104 can be moved to the semiconductor layer 108 by heat treatment.

  The thickness of the insulating layer 104 can be 50 nm or more, or 100 nm to 3000 nm, or 200 nm to 1000 nm. By thickening the insulating layer 104, the amount of oxygen released from the insulating layer 104 can be increased, and interface states at the interface between the insulating layer 104 and the semiconductor layer 108 and oxygen vacancies contained in the semiconductor layer 108 can be reduced. It is possible.

  As the insulating layer 104, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga-Zn oxide, or the like may be used, and a single layer or stacked layers can be provided. In this embodiment mode, a stacked structure of a silicon nitride film and a silicon oxynitride film is used as the insulating layer 104. Thus, oxygen can be efficiently introduced into the semiconductor layer 108 by using the insulating layer 104 as a stacked structure, using a silicon nitride film on the lower layer side, and using a silicon oxynitride film on the upper layer side.

  Alternatively, a film other than an oxide film such as a silicon nitride film can be used on the side of the insulating layer 104 in contact with the semiconductor layer 108. At this time, the surface of the insulating layer 104 in contact with the semiconductor layer 108 is preferably subjected to pretreatment such as oxygen plasma treatment to oxidize the surface of the insulating layer 104 or the vicinity of the surface.

[Conductive film]
The conductive layer 112 and the conductive layer 106 functioning as a gate electrode, the conductive layer 120 a functioning as a source electrode, and the conductive layer 120 b functioning as a drain electrode include chromium (Cr), copper (Cu), aluminum (Al), gold (gold) Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt (cobalt A metal element selected from Co), or an alloy containing the above-described metal element as a component, or an alloy in which the above-described metal element is combined can be used, respectively.

  In addition, an oxide (In-Sn oxide) containing indium and tin in the conductive layer 112 and the conductive layer 106 which function as a gate electrode, the conductive layer 120 a which functions as a source electrode, and the conductive layer 120 b which functions as a drain electrode. , An oxide having indium and tungsten (In-W oxide), an oxide having indium, tungsten and zinc (In-W-Zn oxide), an oxide having indium and titanium (In-Ti oxide) Oxide, an oxide having indium, titanium and tin (In-Ti-Sn oxide), an oxide having indium and zinc (In-Zn oxide), an oxide having indium, tin and silicon Oxide conductor such as In-Sn-Si oxide), oxide containing indium, gallium and zinc (In-Ga-Zn oxide) or gold It is also possible to apply the oxide film.

  Here, the oxide conductor is described. In the present specification and the like, the oxide conductor may be referred to as OC (Oxide Conductor). As an oxide conductor, for example, oxygen vacancies are formed in a metal oxide, and when hydrogen is added to the oxygen vacancies, donor levels are formed in the vicinity of the conduction band. As a result, the metal oxide becomes highly conductive and becomes conductive. A conductive metal oxide can be referred to as an oxide conductor. In general, metal oxides are translucent to visible light because of their large energy gap. On the other hand, the oxide conductor is a metal oxide having a donor level near the conduction band. Therefore, the oxide conductor has a small influence of absorption by the donor level, and has the same transparency to visible light as a metal oxide.

  Alternatively, the conductive layer 112 may have a stacked-layer structure of a conductive film containing the above-described oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. The wiring resistance can be reduced by using a conductive film containing a metal or an alloy. At this time, a conductive film including an oxide conductor is preferably applied to the side in contact with the insulating layer which functions as a gate insulating film.

  In addition, a Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) is applied to the conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b. It is also good. By using a Cu-X alloy film, processing can be performed by a wet etching process, which makes it possible to suppress the manufacturing cost.

  In addition, the conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b preferably include one or more selected from titanium, tungsten, tantalum, and molybdenum among the above-described metal elements. It is suitable. In particular, a tantalum nitride film is preferably used as the conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b. The tantalum nitride film is conductive and has high barrier properties to copper or hydrogen. Further, since the tantalum nitride film further emits less hydrogen from itself, the tantalum nitride film can be suitably used as a conductive film in contact with the semiconductor layer 108 or a conductive film in the vicinity of the semiconductor layer 108.

[Insulating layer]
A silicon oxide film is formed by plasma chemical vapor deposition (PECVD: (Plasma Enhanced Chemical Vapor Deposition)), sputtering, or the like as the insulating layer (insulating layer 104 and insulating layer 110) functioning as a gate insulating film of the transistor 100 or the like. Silicon oxynitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film And an insulating layer containing one or more of neodymium oxide films. Note that each of the insulating layer 104 and the insulating layer 110 may have a stacked structure of two layers or a stacked structure of three or more layers.

  In addition, an insulating layer in contact with the semiconductor layer 108 which functions as a channel formation region of the transistor 100 or the like is preferably an oxide insulating film, and contains oxygen in excess of the stoichiometric composition (an excess oxygen region It is more preferable to have the In other words, the insulating layer is an insulating film capable of releasing oxygen. Note that in order to provide an excess oxygen region in the insulating layer, for example, the insulating layer is formed in an oxygen atmosphere, the insulating layer after film formation is heat-treated in an oxygen atmosphere, or oxygen is formed on the insulating layer after film formation. Oxygen is implanted into the insulating layer by formation of the film included, or oxygen ions may be implanted into the insulating layer after film formation.

  When hafnium oxide is used as the insulating layer, the following effects can be obtained. Hafnium oxide has a higher dielectric constant than silicon oxide or silicon oxynitride. Therefore, since the thickness of the insulating layer can be increased as compared with the case of using silicon oxide, the leakage current due to the tunnel current can be reduced. That is, a transistor with small off current can be realized. Furthermore, hafnium oxide having a crystal structure has a high dielectric constant as compared to hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with low off current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include monoclinic system and cubic system. However, one embodiment of the present invention is not limited to these.

In addition, the insulating layer preferably has few defects, and typically, it is preferable that a signal observed by electron spin resonance (ESR) is small. For example, the above-mentioned signal includes the E ′ center observed at a g value of 2.001. The E 'center is due to dangling bonds of silicon. As the insulating layer, a silicon oxide film or a silicon oxynitride film having a spin density of 3 × 10 ¹⁷ spins / cm ³ or less, preferably 5 × 10 ¹⁶ spins / cm ³ or less due to the E ′ center may be used. .

[Semiconductor layer]
In the case where the semiconductor layer 108 is an In-M-Zn oxide, the atomic ratio of metal elements in a sputtering target used for forming the In-M-Zn oxide preferably satisfies In> M. The atomic ratio of the metal elements of such a sputtering target is In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 0.5, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5 1: 6, In: M: Zn = 5: 1: 7, In: M: Zn = 5: 1: 8, In: M: Zn = 6: 1: 6, In: M: Zn = 5: 2: 5 mag is listed.

  In the case where the semiconductor layer 108 is an In-M-Zn oxide, it is preferable to use a target including a polycrystalline In-M-Zn oxide as a sputtering target. With the use of a target including polycrystalline In-M-Zn oxide, the semiconductor layer 108 having crystallinity can be easily formed. Note that the atomic ratio of the semiconductor layer 108 to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the above sputtering target. For example, in the case where the composition of a sputtering target used for the semiconductor layer 108 is In: Ga: Zn = 4: 2: 4.1 [atomic ratio], the composition of the semiconductor layer 108 to be formed is In: Ga: Zn = It may be in the vicinity of 4: 2: 3 [atomic number ratio].

  In addition, the semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. Thus, by using a metal oxide with a wide energy gap, the off-state current of the transistor can be reduced.

  In addition, the semiconductor layer 108 preferably has a non-single-crystal structure. The non-single crystal structure includes, for example, a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), a polycrystalline structure, a microcrystalline structure, or an amorphous structure in which a crystal part has c-axis orientation. In the non-single crystal structure, the amorphous structure has the highest density of defect states, and CAAC-OS has the lowest density of defect states.

[Example of production method]
Hereinafter, a method for manufacturing the transistor and the capacitor of one embodiment of the present invention will be described. Here, the transistor 100A and the capacitor 130B illustrated in FIG. 4B will be described as an example.

  Note that thin films (insulating films, semiconductor films, conductive films, and the like) that constitute a semiconductor device are formed by sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulse laser deposition (PLD: Pulse Laser Deposition). ), Atomic layer deposition (ALD), or the like. Examples of the CVD method include plasma enhanced chemical vapor deposition (PECVD), thermal CVD and the like. In addition, one of the thermal CVD methods is metal organic chemical vapor deposition (MOCVD: Metal Organic CVD).

  In addition, thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be spin-coated, dip, spray-coated, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coat, roll coat, curtain coat , Knife coating or the like.

  In addition, when processing a thin film forming the semiconductor device, the thin film can be processed using a photolithography method or the like. Other than that, the thin film may be processed by a nanoimprint method, a sand blast method, a lift-off method or the like. Alternatively, the island-shaped thin film may be formed directly by a film formation method using a shielding mask such as a metal mask.

  As the photolithography method, there are typically the following two methods. One is a method of forming a resist mask on a thin film to be processed, processing the thin film by etching or the like, and removing the resist mask. The other is a method of processing the thin film into a desired shape by forming a thin film having photosensitivity, followed by exposure and development.

  In photolithography, light used for exposure may be, for example, i-ray (wavelength 365 nm), g-ray (wavelength 436 nm), h-ray (wavelength 405 nm), or a mixture of these. Besides, ultraviolet light, KrF laser light, ArF laser light or the like can also be used. Further, the exposure may be performed by the immersion exposure technique. Further, as light used for exposure, extreme ultraviolet (EUV: Extreme Ultra-violet) or X-rays may be used. Also, instead of light used for exposure, an electron beam can be used. The use of extreme ultraviolet light, X-rays or electron beams is preferable because extremely fine processing is possible. In the case where exposure is performed by scanning a beam such as an electron beam, a photomask is not necessary.

  For etching of the thin film, a dry etching method, a wet etching method, a sand blast method, or the like can be used.

  Each of FIGS. 5 to 7 is a cross-sectional view in the channel length direction, which illustrates the method for manufacturing the transistor 100A and the capacitor 130B.

[Formation of Conductive Layer 106, Conductive Layer 106C]
A conductive film is formed over the substrate 102 and processed by etching to simultaneously form a conductive layer 106 functioning as a gate electrode and a conductive layer 106C functioning as one electrode of a capacitor (FIG. 5A). ).

[Formation of Insulating Layer 104]
Subsequently, the insulating layer 104 is formed to cover the substrate 102, the conductive layer 106, and the conductive layer 106C (FIG. 5B). The insulating layer 104 can be formed by a plasma CVD method, an ALD method, a sputtering method, or the like.

[Formation of Semiconductor Layer 108, Metal Oxide Layer 108C]
Subsequently, a metal oxide film 108 f is formed over the insulating layer 104 (FIG. 5C).

  The metal oxide film 108 f is preferably formed by a sputtering method using a metal oxide target.

  Further, when forming the metal oxide film 108f, a gas containing nitrogen or an inert gas (eg, helium gas, argon gas, xenon gas, etc.) may be mixed in addition to the oxygen gas. As a gas containing nitrogen, a gas containing nitrogen gas or a nitrogen oxide such as dinitrogen monoxide can be used. Note that the ratio of oxygen gas to the whole of the deposition gas at the time of depositing the metal oxide film (hereinafter also referred to as oxygen flow ratio) is 0% or more and 100% or less, preferably 5% or more and 20% or less It is preferable to do. By reducing the oxygen flow ratio and forming the metal oxide film 108 f with relatively low crystallinity, a transistor in which the on-state current is increased can be obtained.

  Further, by mixing a gas containing nitrogen with a film formation gas, a metal oxide film containing nitrogen can be formed as the metal oxide film 108 f.

  In addition, as a film formation condition of the metal oxide film 108f, the substrate temperature may be higher than or equal to room temperature and less than or equal to 180 ° C., preferably, the substrate temperature may be higher than or equal to room temperature and less than or equal to 140 ° C. When the substrate temperature at the time of forming the metal oxide film 108 f is, for example, greater than or equal to room temperature and less than 140 ° C., productivity is preferably high. Further, by forming the metal oxide film 108 f with the substrate temperature set to room temperature or not intentionally heating, the metal oxide film 108 f having low crystallinity can be easily formed.

  The thickness of the metal oxide film 108f may be 3 nm to 200 nm, preferably 3 nm to 100 nm, and more preferably 3 nm to 60 nm.

  Note that in the case of using a large glass substrate (for example, the sixth to twelfth generations) as the substrate 102, the substrate temperature is 200 ° C. or more and 300 ° C. or less when forming the metal oxide film 108f. There are cases where the 102 is deformed (distorted or warped). Therefore, in the case of using a large-sized glass substrate, deformation of the glass substrate can be suppressed by setting the substrate temperature at the time of forming the metal oxide film 108 f at room temperature or more and less than 200 ° C.

  In addition, high purification of the sputtering gas is also required. For example, oxygen gas or argon gas used as a sputtering gas has a dew point of -40.degree. C. or less, preferably -80.degree. C. or less, more preferably -100.degree. C. or less, more preferably -120.degree. C. or less. By using the metal oxide film 108 f, it is possible to prevent moisture and the like from being taken in as much as possible.

In the case where the metal oxide film 108f is formed by sputtering, a chamber in the sputtering apparatus is an adsorption vacuum pump such as a cryopump in order to remove water and the like which become impurities for the metal oxide as much as possible. It is preferable to use a high vacuum (about 5 × 10 ⁻⁷ Pa to 1 × 10 ⁻⁴ Pa) to evacuate. In particular, the partial pressure of gas molecules corresponding to H ₂ O in the chamber (gas molecules corresponding to m / z = 18) is 1 × 10 ⁻⁴ Pa or less, preferably 5 × 10 ⁻⁵ during standby of the sputtering apparatus. It is preferable to set it as Pa or less.

  Further, before forming the metal oxide film 108 f, heat treatment is preferably performed to remove water or hydrogen adsorbed on the surface of the insulating layer 104. For example, heat treatment can be performed at a temperature of 70 ° C to 200 ° C in a reduced pressure atmosphere. At this time, it is preferable to form the metal oxide film 108 f continuously without exposing the surface of the insulating layer 104 to the air. For example, as a film formation apparatus, a heating chamber for heating a substrate and a film formation chamber for forming the metal oxide film 108 f are preferably connected via a gate valve or the like.

  Subsequently, the metal oxide film 108f is processed to simultaneously form the island-shaped semiconductor layer 108 and the metal oxide layer 108C (FIG. 5D).

  For processing of the metal oxide film 108f, either one or both of a wet etching method and a dry etching method may be used.

  After the metal oxide film 108 f is formed or processed into the semiconductor layer 108, heat treatment may be performed to perform dehydrogenation or dehydration of the metal oxide film 108 f or the semiconductor layer 108. The temperature of the heat treatment is typically 150 ° C to less than the strain point of the substrate, or 250 ° C to 450 ° C, or 300 ° C to 450 ° C.

  The heat treatment can be performed in a rare gas such as helium, neon, argon, xenon, krypton, or an inert gas atmosphere containing nitrogen. Alternatively, after heating in an inert gas atmosphere, heating may be performed in an oxygen atmosphere. Preferably, the inert gas atmosphere and the oxygen atmosphere do not contain hydrogen, water, and the like. The treatment time may be 3 minutes or more and 24 hours or less.

  For the heat treatment, an electric furnace, an RTA apparatus, or the like can be used. By using the RTA apparatus, heat treatment can be performed at a temperature higher than the strain point of the substrate for only a short time. Therefore, the heat treatment time can be shortened.

The film formation is performed while heating the metal oxide film 108f, or the metal oxide film 108f is formed, and then heat treatment is performed, whereby the hydrogen concentration in the metal oxide film 108f obtained by SIMS is 5 × 10 ¹⁹ atoms. / cm ³ or less, or 1 × ¹⁰ 19 atoms / cm ³ or less, 5 × ¹⁰ 18 atoms / cm ³ or less, or 1 × ¹⁰ 18 atoms / cm ³ or less, or 5 × ¹⁰ 17 atoms / cm ³ or less, or 1 It can be 10 ¹⁶ atoms / cm ³ or less.

[Formation of Insulating Film 110f]
Subsequently, an insulating film 110 f which is to be the insulating layer 110 is formed over the semiconductor layer 108, the metal oxide layer 108 C, and the insulating layer 104.

  As the insulating film 110f, for example, an oxide film such as a silicon oxide film or a silicon oxynitride film is preferably formed using a plasma enhanced chemical vapor deposition apparatus (referred to as a PECVD apparatus or simply referred to as a plasma CVD apparatus). In this case, as the source gas, it is preferable to use a deposition gas containing silicon and an oxidizing gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, fluorosilane and the like. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide.

  In addition, PECVD in which the flow rate of the oxidizing gas is greater than 20 times and less than 100 times, or 40 times to 80 times that of the deposition gas as the insulating film 110 f, and the pressure in the processing chamber is less than 100 Pa or 50 Pa or less By using the device, a silicon oxynitride film with a small amount of defects can be formed.

  In addition, the substrate placed in the vacuum-evacuated processing chamber of the PECVD apparatus is maintained at 280 ° C. to 350 ° C. as the insulating film 110 f, and the source gas is introduced into the processing chamber, and the pressure in the processing chamber is 20 Pa to 250 Pa. A dense silicon oxide film or a silicon oxynitride film can be formed as the insulating film 110 f under the condition of supplying the high frequency power to the electrode provided in the treatment chamber by setting the pressure to 100 Pa or more and 250 Pa or less.

  Alternatively, the insulating film 110 f may be formed by PECVD using microwaves. Microwave refers to the frequency range of 300 MHz to 300 GHz. The microwave has a low electron temperature and a small electron energy. Also, in the supplied electric power, the rate used for accelerating electrons is small, and it can be used for dissociation and ionization of more molecules, and can excite high density plasma (high density plasma) . Therefore, the insulating film 110 f with few defects can be formed with less plasma damage to the deposition surface and the deposit.

In addition, the insulating film 110 f can be formed by a CVD method using an organosilane gas. As organosilane gas, ethyl silicate (TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ), tetramethylsilane (TMS: chemical formula Si (CH ₃ ) ₄ ), tetramethyl cyclotetrasiloxane (TMCTS), octamethyl cyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane _{(SiH (OC 2 H 5)} 3), or trisdimethylaminosilane _{(SiH (N (CH 3)} 2) 3) be a silicon-containing compound such as it can. By using the CVD method using an organosilane gas, the insulating film 110f with high coverage can be formed.

[Formation of Metal Oxide Film 114f]
Subsequently, a metal oxide film 114 f to be the metal oxide layer 114 is formed over the insulating film 110 f.

  The metal oxide film 114 f is preferably formed, for example, in an atmosphere containing oxygen. In particular, sputtering is preferably performed in an atmosphere containing oxygen. Thus, oxygen can be supplied to the insulating film 110 f when the metal oxide film 114 f is formed.

  For example, as a film formation condition of the metal oxide film 114f, it is preferable to form the metal oxide film by a reactive sputtering method using a metal target by using oxygen as a film formation gas. When aluminum is used as the metal target, for example, an aluminum oxide film can be formed.

  When the metal oxide film 114f is formed, the ratio of the oxygen flow rate to the total flow rate of the film forming gas introduced into the film forming chamber of the film forming apparatus (oxygen flow ratio) or the oxygen partial pressure in the film forming chamber is higher. The oxygen supplied into the membrane 110f can be increased. The oxygen flow ratio or oxygen partial pressure is, for example, 50% to 100%, preferably 65% to 100%, more preferably 80% to 100%, and still more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow ratio to 100% and to bring the oxygen partial pressure as close as possible to 100%.

  By thus forming the metal oxide film 114f by sputtering in an atmosphere containing oxygen, oxygen is supplied to the insulating film 110f at the time of deposition of the metal oxide film 114f, and oxygen is supplied from the insulating film 110f. It is possible to prevent detachment. As a result, an extremely large amount of oxygen can be confined in the insulating film 110 f. Then, much heat can be supplied to the semiconductor layer 108 by heat treatment performed later. As a result, oxygen vacancies in the semiconductor layer 108 can be reduced, and a highly reliable transistor can be realized.

  In addition, after the metal oxide film 114f is formed, the metal oxide film 114f, the insulating film 110f, and part of the insulating layer 104 are etched to form an opening which reaches the conductive layer 106. Accordingly, the conductive layer 112 and the conductive layer 106 which are to be formed later can be electrically connected to each other through the opening.

[Formation of Conductive Film 112f]
Subsequently, a conductive film 112 f to be the conductive layer 112 is formed over the metal oxide film 114 f (FIG. 5E).

  The conductive film 112 f is preferably formed by a sputtering method using a sputtering target of metal or alloy.

[Etching of Conductive Film 112f, Metal Oxide Film 114f, and Insulating Film 110f]
Subsequently, the conductive film 112f, the metal oxide film 114f, and part of the insulating film 110f are etched to expose part of the semiconductor layer 108 and the metal oxide layer 108C (FIG. 5F).

  Here, the conductive film 112 f, the metal oxide film 114 f, and the insulating film 110 f are preferably processed using the same resist mask. Alternatively, the metal oxide layer 114 and the insulating layer 110 may be etched using the conductive layer 112 after etching as a hard mask.

  Thus, the island-shaped conductive layer 112, the metal oxide layer 114, and the insulating layer 110 whose top surface shapes are approximately the same can be formed.

  Note that when the conductive film 112 f, the metal oxide film 114 f, and the insulating film 110 f are etched, part of the semiconductor layer 108 which is not covered by the insulating layer 110 and the metal oxide layer 108 C may be etched and thinned. .

[Formation of First Layer 116]
Subsequently, a first layer 116 is formed (FIG. 6A).

  Here, a film having an insulating property is formed as the first layer 116. Note that the first layer 116 may have conductivity at the time of film formation in the case of insulating in a later step such as heat treatment.

  As the first layer 116, a film containing at least one of metal elements such as aluminum, titanium, tantalum, tungsten, chromium, and ruthenium is formed. In particular, it is preferable to contain at least one of aluminum, titanium, tantalum and tungsten. In particular, a nitride containing at least one of these metal elements, or an oxide containing at least one of these metal elements can be preferably used. As the film having an insulating property, a nitride film such as an aluminum nitride film, a titanium nitride film, or an aluminum titanium nitride film, an oxide film such as an aluminum titanium oxide film, or the like can be suitably used. Alternatively, a nitride containing silicon can be used as the first layer 116. For example, a silicon nitride film can be used as a nitride containing silicon.

  In particular, the aluminum nitride film has a light transmitting property with respect to visible light and does not adversely affect the light transmitted through the first layer 116; therefore, the semiconductor device described in this embodiment can be an EL display, a liquid crystal display, or the like. It is preferable to use an aluminum nitride film as the first layer 116 when using as a display device of In addition, the first layer 116 preferably has a transmittance of 80% or more to light with a wavelength of 400 nm.

  Here, the first layer 116 is preferably formed by a sputtering method using nitrogen gas or oxygen gas as a deposition gas. Thereby, even when the same sputtering target is used, control of the film quality becomes easy by controlling the flow rate of the film forming gas.

  In the case of forming an aluminum nitride film as the first layer 116, the aluminum nitride film is preferably formed by a sputtering method using a target containing aluminum or aluminum nitride, and using a deposition gas containing nitrogen. As the deposition gas, nitrogen or a mixed gas containing nitrogen and argon is preferably used, and the ratio of nitrogen contained in the deposition gas is 20% to 100%, preferably 30% to 60%, and more preferably Is 30% or more and 40% or less. This can be determined in consideration of the transmittance of the aluminum nitride film to visible light, the film stress, the film formation rate, and the like.

[Heat treatment]
Subsequently, heat treatment is performed (FIG. 6 (B)). By the heat treatment, a region of the semiconductor layer 108 in contact with the first layer 116 is lowered in resistance, so that a region 108 n which is lower in resistance than the region 108 i is formed in the semiconductor layer 108. At the same time, the resistance of the metal oxide layer 108C can be reduced.

  The heat treatment is preferably performed in an inert gas atmosphere such as nitrogen or a rare gas. The higher the temperature of the heat treatment is, the more preferable; however, the temperature can be set in consideration of the heat resistance of the substrate 102, the conductive layer 106, the conductive layer 112, and the like. For example, the temperature may be 120 ° C. to 500 ° C., preferably 150 ° C. to 450 ° C., more preferably 200 ° C. to 400 ° C., further preferably 250 ° C. to 400 ° C. For example, by setting the temperature of the heat treatment to about 350 ° C., semiconductor devices can be produced with high yield in a production facility using a large glass substrate.

  Note that the heat treatment may be performed at any stage after the formation of the first layer 116. The heat treatment may be combined with another heat treatment.

  By heat treatment, oxygen in the semiconductor layer 108 and the metal oxide layer 108 C is extracted into the first layer 116, whereby oxygen vacancies are generated. The carrier concentration is increased by bonding of the oxygen vacancy and hydrogen in the semiconductor layer 108 or in the metal oxide layer 108C, and a portion in contact with the first layer 116 is lowered in resistance. By the heat treatment, a metal element contained in the semiconductor layer 108 may be deposited in the vicinity of the first layer 116 of the semiconductor layer 108, whereby the region 115 may be formed.

  Further, in the case where the first layer 116 includes a metal element, the metal element included in the first layer 116 is diffused into the semiconductor layer 108 and the metal oxide layer 108C by heat treatment; There is also a case where a part of the oxide layer 108C is alloyed to reduce resistance.

  Alternatively, nitrogen or hydrogen contained in the first layer 116 or nitrogen contained in the atmosphere for heat treatment diffuses into the semiconductor layer 108 and the metal oxide layer 108C by heat treatment, whereby the resistance is reduced. There is also a case.

  The region 108 n of the semiconductor layer 108 and the metal oxide layer 108 C, which are reduced in resistance by such a combined action, become extremely stable and low-resistance regions. The region 108n and the metal oxide layer 108C formed in this manner have a feature that the resistance is not increased again even if the process of supplying oxygen is performed in the later step, for example.

[Formation of Insulating Layer 118]
Subsequently, the insulating layer 118 is formed to cover the first layer 116 (FIG. 6C).

  The insulating layer 118 can be formed by a plasma CVD method, a sputtering method, or the like.

[Formation of Openings 141a, 141b, 141c]
Subsequently, a mask is formed by lithography at a desired position of the insulating layer 118, and then the insulating layer 118 and a part of the first layer 116 are etched to form the opening 141a and the opening 141b which reach the region 108n. And an opening 141c reaching the metal oxide layer 108C.

[Formation of Conductive Layers 120a and 120b]
Subsequently, a conductive film is formed over the insulating layer 118 so as to cover the opening 141a, the opening 141b, and the opening 141c, and the conductive film is processed into a desired shape, whereby the conductive layer 120a and the conductive layer are formed. 120b are formed (FIG. 6 (D)).

  Through the above steps, the transistor 100A and the capacitor 130B which are electrically connected to each other can be manufactured. Hereinafter, the process of forming the pixel electrode of the display element will be further described.

[Formation of Insulating Layer 119]
Subsequently, the insulating layer 119 is formed to cover the conductive layer 120a, the conductive layer 120b, and the insulating layer 118 (FIG. 7A).

  It is preferable to use an organic resin as the insulating layer 119 because planarity is improved. Typically, the insulating layer 119 can be formed by a method such as spin coating, dispensing, screen printing, or slit coating.

  Note that an inorganic insulating material may be used as the insulating layer 119. In that case, the insulating layer 118 can be formed by the same method.

  Further, by using a photosensitive resin material for the insulating layer 119, an opening which reaches the conductive layer 120b can be formed at the same time as the insulating layer 119 is formed. Note that in the case where a non-photosensitive material is used for the insulating layer 119, the opening may be formed by etching.

[Formation of Conductive Layer 109]
Subsequently, a conductive layer 109 is formed (FIG. 7B). The conductive layer 109 can be formed by the same method as the conductive layer 112 or the like.

  Through the above steps, a pixel electrode, a transistor, and a capacitor can be formed. 7B is the same as FIG. 4B.

  Note that the capacitor 130A illustrated in FIG. 4A can be manufactured by processing the conductive layer 120b so as to overlap with the metal oxide layer 108C.

  Further, in the case of manufacturing the capacitor 130C illustrated in FIG. 4C, the photomask used in the processing of the semiconductor layer 108 and the metal oxide layer 108C in the above is changed, and these are processed into one island shape. Can be formed by

  The above is the description of the example of the manufacturing method.

  At least a part of the structural example, the manufacturing method, and the drawings and the like which are exemplified in this embodiment can be implemented in appropriate combination with another structural example, a manufacturing method, a drawing, and the like.

  This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.

Second Embodiment
In this embodiment, an example of a display device including the transistor described in the above embodiment will be described.

[Example of configuration]
FIG. 8A is a top view illustrating an example of a display device. A display device 700 illustrated in FIG. 8A includes a pixel portion 702 provided over a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided over the first substrate 701, and a pixel. A sealant 702 is provided so as to surround the portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706, and a second substrate 705 provided to face the first substrate 701. Note that the first substrate 701 and the second substrate 705 are attached to each other by a sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed by the first substrate 701, the sealant 712, and the second substrate 705. Although not illustrated in FIG. 8A, a display element is provided between the first substrate 701 and the second substrate 705.

  In addition, in the display device 700, an FPC terminal portion 708 (FPC: flexible printed circuit) is provided in a region which is different from a region which is surrounded by the sealant 712 on the first substrate 701. The FPC terminal portion 708 is electrically connected to each of the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706. An FPC 716 is connected to the FPC terminal portion 708, and various signals and the like are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716. Further, signal lines 710 are connected to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708, respectively. Various signals and the like supplied from the FPC 716 are supplied to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 through the signal line 710.

  In addition, a plurality of gate driver circuit portions 706 may be provided in the display device 700. In addition, although an example in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed over the same first substrate 701 as the pixel portion 702 is shown as the display device 700, the present invention is not limited to this structure. For example, only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, the first substrate 701 or the FPC 716 is provided with an IC including a substrate on which a source driver circuit, a gate driver circuit, or the like is formed (eg, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film). It is good also as composition. Note that there is no particular limitation on the method for connecting a driver circuit substrate which is separately formed, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

  The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 each include a plurality of transistors, and the transistor which is a semiconductor device of one embodiment of the present invention can be applied. .

  In addition, the display device 700 can have various elements. Examples of the element include electroluminescence (EL) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements, LEDs, etc.), light emitting transistor elements (transistors that emit light according to current), electrons Emitting element, liquid crystal element, electronic ink element, electrophoretic element, electrowetting element, plasma display panel (PDP), MEMS (micro electro mechanical system) display (for example, grating light valve (GLV), digital micro mirror Devices (DMDs), digital micro shutter (DMS) devices, interferometric modulation (IMOD) devices, etc.), piezoelectric ceramic displays and the like.

  In addition, an example of a display device using an EL element is an EL display. As an example of a display device using an electron emission element, there is a field emission display (FED) or a surface-conduction electron-emitter display (SED). Examples of a display device using a liquid crystal element include a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct view liquid crystal display, projection liquid crystal display) and the like. Examples of a display device using an electronic ink element or an electrophoretic element include electronic paper. In the case of realizing a semi-transmissive liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrodes may have a function as a reflective electrode. For example, some or all of the pixel electrodes may have aluminum, silver, or the like. In that case, it is also possible to provide a storage circuit such as an SRAM under the reflective electrode. This can further reduce power consumption.

  Note that as a display method in the display device 700, a progressive method, an interlace method, or the like can be used. In addition, color elements controlled by pixels in color display are not limited to three colors of RGB (R represents red, G represents green, B represents blue). For example, it may be composed of four pixels of an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, as in a pen tile array, one color element may be configured by two colors of RGB, and two different colors may be selected and configured depending on the color elements. Alternatively, one or more colors of yellow, cyan, magenta and the like may be added to RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to the display device for color display, and can be applied to a display device for monochrome display.

  In addition, a colored layer (also referred to as a color filter) is used to cause a display device to perform color display using white light (W) in a backlight or a front light (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.). You may use. The colored layer can be used by appropriately combining, for example, red (R), green (G), blue (B), yellow (Y) and the like. By using a colored layer, color reproducibility can be enhanced as compared to the case where no colored layer is used. At this time, white light in a region not having a colored layer may be directly used for display by arranging a region having a colored layer and a region not having a colored layer. By disposing a region not having a colored layer in part, in bright display, a decrease in luminance due to the colored layer can be reduced, and power consumption can be reduced by about 20% to about 30%. However, when full-color display is performed using a self light emitting element such as an organic EL element or an inorganic EL element, R, G, B, Y, and W may be emitted from elements having respective luminescent colors. In some cases, power consumption can be further reduced by using a self-luminous element than in the case of using a colored layer.

  Moreover, as a coloring method, in addition to a method (color filter method) in which a part of light emission from the above-mentioned white light emission is converted to red, green and blue by passing through a color filter, red, green and blue light emission A method (three-color method) to be used respectively or a method (color conversion method, quantum dot method) for converting part of light emission from blue light emission to red or green may be applied.

  The display device 700A illustrated in FIG. 8B is a display device which can be suitably used for an electronic device having a large screen. For example, it can be suitably used for a television device, a monitor device, digital signage and the like.

  The display device 700A includes a plurality of source driver ICs 721 and a pair of gate driver circuits 722.

  The plurality of source driver ICs 721 are attached to the FPC 723 respectively. In the plurality of FPCs 723, one terminal is connected to the substrate 701, and the other terminal is connected to the printed substrate 724. By bending the FPC 723, the printed substrate 724 can be provided on the back side of the pixel portion 702 and mounted on an electric device, so that space saving of the electronic device can be achieved.

  On the other hand, the gate driver circuit 722 is formed on the substrate 701. Thereby, an electronic device with a narrow frame can be realized.

  With such a configuration, a large-sized and high-resolution display device can be realized. For example, the present invention can be applied to a display having a screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more. In addition, a display device with extremely high resolution such as full high definition, 4K2K, or 8K4K can be realized.

[Example of section configuration]
Hereinafter, structures in which a liquid crystal element and an EL element are used as display elements will be described with reference to FIGS. 9 and 10 are cross-sectional views taken along the alternate long and short dash line Q-R shown in FIG. 8A, in which a liquid crystal element is used as a display element. FIG. 11 is a cross-sectional view taken along the dashed-dotted line Q-R shown in FIG. 8A, which is a configuration using an EL element as a display element.

  First, the common parts shown in FIGS. 9 to 11 will be described first, and then the different parts will be described below.

[Description of Common Part of Display Device]
The display device 700 illustrated in FIGS. 9 to 11 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. In addition, the routing wiring portion 711 has a signal line 710. The pixel portion 702 also includes a transistor 750 and a capacitor 790. In addition, the source driver circuit portion 704 includes a transistor 752.

  The transistors described in Embodiment 1 can be applied to the transistors 750 and 752.

  The transistor used in this embodiment has the oxide semiconductor film which is highly purified and in which the formation of oxygen vacancies is suppressed. The transistor can reduce off current. Therefore, the holding time of an electric signal such as an image signal can be extended, and the writing interval can be set long in the power on state. Thus, the frequency of the refresh operation can be reduced, which leads to an effect of suppressing power consumption.

  In addition, the transistor used in this embodiment can be driven at high speed because relatively high field-effect mobility can be obtained. For example, by using such a transistor which can be driven at high speed in a display device, the switching transistor in the pixel portion and the driver transistor used in the driver circuit portion can be formed over the same substrate. That is, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate drive circuit, the number of parts of the semiconductor device can be reduced. In addition, by using a transistor which can be driven at high speed also in the pixel portion, an image with high quality can be provided.

  The capacitor 790 includes a lower electrode formed through a process for processing the same metal oxide film as the semiconductor layer included in the transistor 750, and a conductive film identical to a conductive film serving as a source electrode or a drain electrode included in the transistor 750. And an upper electrode formed through the process of processing In addition, an insulating film formed through a step of forming an insulating film which is the same as an insulating film functioning as a first gate insulating film of the transistor 750 is formed between the lower electrode and the upper electrode; An insulating film formed through the step of forming the same insulating film as the insulating film which functions as a protective insulating film is provided. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is held between a pair of electrodes.

  Further, in FIGS. 9 to 11, a planarization insulating film 770 is provided over the transistor 750, the transistor 752, and the capacitor 790.

  In FIGS. 9 to 11, the transistor 750 included in the pixel portion 702 and the transistor 752 included in the source driver circuit portion 704 are illustrated using a transistor having the same structure; however, the present invention is not limited to this. For example, different transistors may be used for the pixel portion 702 and the source driver circuit portion 704. Specifically, a top gate transistor is used in the pixel portion 702, a bottom gate transistor is used in the source driver circuit portion 704, or a bottom gate transistor is used in the pixel portion 702, and the source driver circuit portion 704 is used. There is a structure using a top gate type transistor. Note that the above source driver circuit unit 704 may be read as a gate driver circuit unit.

  In addition, the signal line 710 is formed through the same process as a conductive film which functions as a source electrode and a drain electrode of the transistors 750 and 752. For example, in the case of using a material containing a copper element as the signal line 710, signal delay due to wiring resistance and the like can be reduced and display on a large screen can be performed.

  Further, the FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. Note that the connection electrode 760 is formed through the same process as a conductive film which functions as a source electrode and a drain electrode of the transistors 750 and 752. The connection electrode 760 is electrically connected to a terminal included in the FPC 716 through an anisotropic conductive film 780.

  For example, a glass substrate can be used as the first substrate 701 and the second substrate 705. Alternatively, a flexible substrate may be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate and the like.

  In addition, a structure body 778 is provided between the first substrate 701 and the second substrate 705. The structures 778 are columnar spacers, and are provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure 778.

  Further, on the second substrate 705 side, a light shielding film 738 functioning as a black matrix, a coloring film 736 functioning as a color filter, and an insulating film 734 in contact with the light shielding film 738 and the coloring film 736 are provided.

[Configuration Example of Display Device Using Liquid Crystal Element]
A display device 700 illustrated in FIG. 9 includes a liquid crystal element 775. The liquid crystal element 775 includes the conductive film 772, the conductive film 774, and the liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and has a function as a counter electrode. The display device 700 illustrated in FIG. 9 can display an image by controlling transmission and non-transmission of light by changing the alignment state of the liquid crystal layer 776 by a voltage applied to the conductive films 772 and 774.

  The conductive film 772 is electrically connected to a conductive film which functions as a source electrode or a drain electrode of the transistor 750. The conductive film 772 is formed over the planarization insulating film 770, and functions as a pixel electrode, that is, one electrode of a display element.

  As the conductive film 772, a conductive film which is translucent to visible light or a conductive film which is reflective to visible light can be used. As a conductive film which is translucent in visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) may be used. As a conductive film which is reflective in visible light, for example, a material containing aluminum or silver may be used.

  In the case of using a conductive film which is reflective to visible light as the conductive film 772, the display device 700 is a reflective liquid crystal display device. Further, in the case of using a conductive film which is translucent to visible light as the conductive film 772, the display device 700 is a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates which sandwich a liquid crystal element is provided.

  By changing the structure over the conductive film 772, the driving method of the liquid crystal element can be changed. An example of this case is shown in FIG. Further, the display device 700 illustrated in FIG. 10 is an example of a configuration using a lateral electric field method (for example, FFS mode) as a driving method of a liquid crystal element. In the structure shown in FIG. 10, the insulating film 773 is provided over the conductive film 772 and the conductive film 774 is provided over the insulating film 773. In this case, the conductive film 774 has a function as a common electrode (also referred to as a common electrode), and alignment of the liquid crystal layer 776 by an electric field generated between the conductive film 772 and the conductive film 774 through the insulating film 773. You can control the state.

  Although not shown in FIGS. 9 and 10, an alignment film may be provided on one or both of the conductive films 772 and 774 on the side in contact with the liquid crystal layer 776. Although not shown in FIGS. 9 and 10, an optical member (optical substrate) such as a polarization member, a retardation member, or an antireflective member may be provided as appropriate. For example, circularly polarized light by a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as a light source.

  When a liquid crystal element is used as the display element, thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, polymer network liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on conditions.

  In addition, in the case of employing the in-plane switching mode, liquid crystal exhibiting a blue phase which does not use an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase which appears immediately before the cholesteric liquid phase is changed to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which several weight% or more of a chiral agent is mixed is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic, so alignment processing is unnecessary. In addition, since it is not necessary to provide an alignment film, rubbing processing is also unnecessary, so electrostatic breakdown caused by rubbing processing can be prevented, and defects and breakage of the liquid crystal display device in the manufacturing process can be reduced. . In addition, liquid crystal materials exhibiting a blue phase have a small viewing angle dependency.

  When a liquid crystal element is used as a display element, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axially Symmetrically Aligned Micro-cell) mode, an OCB (Optical) A Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, an ECB (Electrically Controlled Birefringence) mode, a guest host mode, and the like can be used.

  Alternatively, a normally black liquid crystal display device, for example, a transmissive liquid crystal display device employing a vertical alignment (VA) mode may be used. Several examples of the vertical alignment mode include, but are not limited to, multi-domain vertical alignment (MVA) mode, patterned vertical alignment (PVA) mode, and ASV mode.

[Display device using light emitting element]
A display device 700 illustrated in FIG. 11 includes a light emitting element 782. The light-emitting element 782 includes the conductive film 772, the EL layer 786, and the conductive film 788. The display device 700 illustrated in FIG. 11 can display an image when the EL layer 786 included in the light emitting element 782 provided for each pixel emits light. Note that the EL layer 786 includes an organic compound or an inorganic compound such as a quantum dot.

  Materials usable for the organic compound include fluorescent materials and phosphorescent materials. Moreover, as a material which can be used for a quantum dot, a colloidal quantum dot material, an alloy type quantum dot material, a core-shell type quantum dot material, a core type quantum dot material, etc. are mentioned. Alternatively, a material containing group 12 and group 16, group 13 and group 15, or group 14 and group 16 may be used. Or cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As) The quantum dot material which has elements, such as aluminum (Al), may be used.

  In the display device 700 illustrated in FIG. 11, the insulating film 730 is provided over the planarization insulating film 770 and the conductive film 772. The insulating film 730 covers part of the conductive film 772. The light emitting element 782 has a top emission structure. Thus, the conductive film 788 has a light-transmitting property and transmits light emitted from the EL layer 786. Although the top emission structure is illustrated in the present embodiment, the present invention is not limited to this. For example, the invention can be applied to a bottom emission structure in which light is emitted to the conductive film 772 side, and a dual emission structure in which light is emitted to both the conductive film 772 and the conductive film 788.

  A coloring film 736 is provided at a position overlapping with the light emitting element 782, and a light shielding film 738 is provided at a position overlapping with the insulating film 730, the lead wiring portion 711, and the source driver circuit portion 704. The coloring film 736 and the light shielding film 738 are covered with an insulating film 734. Further, a sealing film 732 is filled between the light emitting element 782 and the insulating film 734. Note that the display device 700 illustrated in FIG. 11 exemplifies the structure in which the coloring film 736 is provided, but the present invention is not limited to this. For example, in the case where the EL layer 786 is formed in an island shape for each pixel, that is, in a case where the EL layer 786 is formed separately, the coloring film 736 may not be provided.

[Configuration Example of Providing Input / Output Device on Display Device]
Further, the display device 700 illustrated in FIGS. 9 to 11 may be provided with an input / output device. As the said input-output device, a touch panel etc. are mentioned, for example.

  A cross-sectional view of a configuration in which the touch panel 791 is provided in the display device 700 illustrated in FIG. A cross-sectional view of a structure in which the touch panel 791 is provided in the display device 700 shown in FIG. 11 is shown in FIG.

  First, the touch panel 791 shown in FIGS. 12 and 13 will be described below.

  The touch panel 791 illustrated in FIGS. 12 and 13 is a so-called in-cell touch panel provided between the substrate 705 and the coloring film 736. The touch panel 791 may be formed on the substrate 705 side before the light shielding film 738 and the coloring film 736 are formed.

  Note that the touch panel 791 includes a light shielding film 738, an insulating film 792, an electrode 793, an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797. For example, it is possible to detect a change in capacitance between the electrode 793 and the electrode 794 that may occur when a detected object such as a finger or a stylus approaches.

  Further, the intersection of the electrode 793 and the electrode 794 is clearly shown above the transistor 750 illustrated in FIGS. 12 and 13. The electrode 796 is electrically connected to two electrodes 793 sandwiching the electrode 794 through an opening provided in the insulating film 795. 12 and 13 illustrate the structure in which the region where the electrode 796 is provided is provided in the pixel portion 702, the invention is not limited to this. For example, the region may be formed in the source driver circuit portion 704.

  The electrode 793 and the electrode 794 are provided in a region overlapping with the light shielding film 738. In addition, as shown in FIG. 12, it is preferable that the electrode 793 be provided so as not to overlap with the liquid crystal element 775. In addition, as shown in FIG. 13, the electrode 793 is preferably provided so as not to overlap with the light emitting element 782. In other words, the electrode 793 has an opening in a region overlapping with the light-emitting element 782 or the liquid crystal element 775. That is, the electrode 793 has a mesh shape. With such a structure, the electrode 793 can have a structure in which light transmitted through the liquid crystal element 775 or light emitted from the light emitting element 782 is not blocked. Therefore, since the decrease in luminance due to the disposition of the touch panel 791 is extremely small, a display device with high visibility and reduced power consumption can be realized. Note that the electrode 794 may have a similar structure.

  Further, since the electrode 793 and the electrode 794 do not overlap with the liquid crystal element 775 or the light-emitting element 782, a metal material with low visible light transmittance can be used for the electrode 793 and the electrode 794. Therefore, the resistance of the electrode 793 and the electrode 794 can be reduced as compared with an electrode using an oxide material having high visible light transmittance, and sensor sensitivity of the touch panel can be improved.

  For example, conductive nanowires may be used for the electrodes 793, 794, and 796. The nanowire may have an average diameter of 1 nm to 100 nm, preferably 5 nm to 50 nm, more preferably 5 nm to 25 nm. In addition, as the nanowires, metal nanowires such as Ag nanowires, Cu nanowires, or Al nanowires, carbon nanotubes, or the like may be used. For example, in the case of using an Ag nanowire for any one or all of the electrodes 793, 794, and 796, the light transmittance in visible light is 89% or more, and the sheet resistance is 40 Ω / sq. 100 Ω / sq. The following can be made.

  Moreover, in FIG.12 and FIG.13, although it illustrated about the structure of the in-cell type touch panel, it is not limited to this. For example, a so-called on-cell touch panel formed on the display device 700 or a so-called out-cell touch panel used by being attached to the display device 700 may be used. Thus, the display device of one embodiment of the present invention can be used in combination with various types of touch panels.

  At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented in appropriate combination with other configuration examples, drawings, and the like.

  This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.

Third Embodiment
In this embodiment, a display device including the semiconductor device of one embodiment of the present invention is described with reference to FIG.

  The display device illustrated in FIG. 14A includes a region having a pixel (hereinafter referred to as a pixel portion 502) and a circuit portion provided outside the pixel portion 502 and having a circuit for driving the pixel (hereinafter referred to as a driver circuit). And a circuit having a protective function of the element (hereinafter referred to as a protective circuit 506) and a terminal portion 507. Note that the protective circuit 506 may not be provided.

  It is preferable that part or all of the driver circuit portion 504 be formed over the same substrate as the pixel portion 502. Thereby, the number of parts and the number of terminals can be reduced. When part or all of the driver circuit portion 504 is not formed over the same substrate as the pixel portion 502, part or all of the driver circuit portion 504 is formed by COG or TAB (Tape Automated Bonding). It can be implemented.

  The pixel portion 502 includes a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The driver circuit portion 504 outputs a signal (scanning signal) for selecting a pixel (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel (data signal). Hereinafter, a driver circuit such as a source driver 504 b) is included.

  The gate driver 504 a includes a shift register and the like. The gate driver 504 a receives a signal for driving the shift register through the terminal portion 507 and outputs the signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, and the like, and outputs a pulse signal. The gate driver 504a has a function of controlling the potentials of wirings (hereinafter referred to as gate lines GL_1 to GL_X) to which scan signals are supplied. Note that a plurality of gate drivers 504 a may be provided, and the gate lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504 a. Alternatively, the gate driver 504a has a function capable of supplying an initialization signal. However, without limitation thereto, the gate driver 504a can also supply another signal.

  The source driver 504 b includes a shift register and the like. The source driver 504 b receives a signal (image signal) which is a source of a data signal as well as a signal for driving the shift register through the terminal portion 507. The source driver 504 b has a function of generating a data signal to be written to the pixel circuit 501 based on an image signal. In addition, the source driver 504 b has a function of controlling output of a data signal in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, and the like. Further, the source driver 504 b has a function of controlling the potentials of wirings (hereinafter referred to as data lines DL_1 to DL_Y) to which data signals are supplied. Alternatively, the source driver 504 b has a function capable of supplying an initialization signal. However, without being limited to this, the source driver 504 b can also supply another signal.

  The source driver 504 b is configured using, for example, a plurality of analog switches. The source driver 504 b can output a signal obtained by time-dividing the image signal as a data signal by sequentially turning on the plurality of analog switches. Alternatively, the source driver 504 b may be configured using a shift register or the like.

  Each of the plurality of pixel circuits 501 receives a pulse signal through one of the plurality of scanning lines GL to which a scanning signal is applied, and receives a data signal through one of the plurality of data lines DL to which the data signal is applied. It is input. In each of the plurality of pixel circuits 501, writing and holding of data of a data signal are controlled by the gate driver 504a. For example, in the pixel circuit 501 in the m-th row and the n-th column, a pulse signal is input from the gate driver 504a via the scanning line GL_m (m is a natural number less than or equal to X), and the data line DL_n (n Is a natural number less than or equal to Y), and the data signal is input from the source driver 504 b.

  The protective circuit 506 illustrated in FIG. 14A is connected to, for example, a scan line GL which is a wiring between the gate driver 504 a and the pixel circuit 501. Alternatively, the protection circuit 506 is connected to a data line DL which is a wiring between the source driver 504 b and the pixel circuit 501. Alternatively, the protective circuit 506 can be connected to a wiring between the gate driver 504 a and the terminal portion 507. Alternatively, the protective circuit 506 can be connected to a wiring between the source driver 504 b and the terminal portion 507. Note that a terminal portion 507 refers to a portion provided with a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device.

  The protective circuit 506 is a circuit which brings a wiring and another wiring into conduction when the wiring to which the protection circuit 506 is connected is supplied with a potential outside the predetermined range.

  As illustrated in FIG. 14A, by providing protection circuits 506 in the pixel portion 502 and the driver circuit portion 504, the display device is more resistant to overcurrent generated by ESD (Electro Static Discharge) or the like. be able to. However, the configuration of the protection circuit 506 is not limited to this. For example, the protection circuit 506 may be connected to the gate driver 504 a or the protection circuit 506 may be connected to the source driver 504 b. Alternatively, the protective circuit 506 can be connected to the terminal portion 507.

  Although FIG. 14A illustrates an example in which the driver circuit portion 504 is formed by the gate driver 504 a and the source driver 504 b, the present invention is not limited to this configuration. For example, only the gate driver 504 a may be formed, and a substrate (for example, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) on which a separately prepared source driver circuit is formed may be mounted.

  Here, FIG. 15 shows a configuration different from that of FIG. In FIG. 15, a pair of source lines (for example, source line DLa1 and source line DLb1) are arranged so as to sandwich a plurality of pixels arranged in the source line direction. In addition, two adjacent gate lines (for example, the gate line GL_1 and the gate line GL_2) are electrically connected.

  The pixels connected to the gate line GL_1 are connected to one of the source lines (the source line DLa1, the source line DLa2, etc.), and the pixels connected to the gate line GL_2 are the other source line (the source line DLb1, the source Are connected to line DLb2 etc.).

  With such a configuration, two gate lines can be selected simultaneously. Thus, the length of one horizontal period can be doubled as compared with the configuration shown in FIG. Therefore, it is easy to increase the resolution and the screen size of the display device.

  In addition, the plurality of pixel circuits 501 illustrated in FIGS. 14A and 15 can be configured as illustrated in FIG. 14B, for example.

  The pixel circuit 501 illustrated in FIG. 14B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The transistor described in the above embodiment can be applied to the transistor 550.

  The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set in accordance with the specification of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the data to be written. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Further, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.

  For example, as a driving method of a display device including the liquid crystal element 570, a TN mode, an STN mode, a VA mode, an ASM (Axially Symmetric Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode , AFLC (Anti-Ferroelectric Liquid Crystal) mode, MVA mode, PVA (Pattered Vertical Alignment) mode, IPS mode, FFS mode, TBA (Transverse Bend Alignment) mode, or the like may be used. Further, as a driving method of the display device, in addition to the above-described driving method, there are an ECB (Electrically Controlled Birefringence) mode, a PDLC (Polymer Dispersed Liquid Crystal) mode, a PNLC (Polymer Network Liquid Crystal) mode, a guest host mode, and the like. However, the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.

  In the m-th row and n-th pixel circuit 501, one of the source and drain electrodes of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. Ru. Further, the gate electrode of the transistor 550 is electrically connected to the scan line GL_m. The transistor 550 has a function of controlling writing of data of the data signal.

  One of the pair of electrodes of capacitive element 560 is electrically connected to a wiring to which a potential is supplied (hereinafter, potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of liquid crystal element 570. Ru. Note that the value of the potential of the potential supply line VL is appropriately set in accordance with the specification of the pixel circuit 501. The capacitor element 560 has a function as a storage capacitor for storing written data.

  For example, in the display device including the pixel circuit 501 in FIG. 14B, for example, the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write data

  The pixel circuit 501 to which data is written is brought into the holding state by the transistor 550 being turned off. Images can be displayed by sequentially performing this on a row-by-row basis.

  In addition, the plurality of pixel circuits 501 illustrated in FIG. 14A can have a configuration illustrated in FIG. 14C, for example.

  The pixel circuit 501 illustrated in FIG. 14C includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572. The transistor described in the above embodiment can be applied to one or both of the transistor 552 and the transistor 554.

  One of the source electrode and the drain electrode of the transistor 552 is electrically connected to the data line DL_n, and the gate electrode is electrically connected to the scan line GL_m.

  The transistor 552 has a function of controlling writing of data of the data signal.

  One of the pair of electrodes of the capacitor 562 is electrically connected to the potential supply line VL_a, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

  The capacitor element 562 has a function as a storage capacitor for storing written data.

  One of the source electrode and the drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

  One of the anode and the cathode of the light emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

  As the light emitting element 572, an organic electroluminescent element (also referred to as an organic EL element) or the like can be used, for example. However, the light emitting element 572 is not limited to this, and an inorganic EL element containing an inorganic material may be used.

  Note that the high power supply potential VDD is applied to one of the potential supply line VL_a and the potential supply line VL_b, and the low power supply potential VSS is applied to the other.

  In the display device including the pixel circuit 501 in FIG. 14C, for example, the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. 14A, and the transistor 552 is turned on to output data signal data. Write.

  The pixel circuit 501 to which data is written is brought into the holding state by the transistor 552 being turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled in accordance with the potential of the written data signal, and the light emitting element 572 emits light with luminance according to the amount of current flowing. Images can be displayed by sequentially performing this on a row-by-row basis.

  At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented in appropriate combination with other configuration examples, drawings, and the like.

  This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.

Embodiment 4
Hereinafter, electronic devices to which the display device of one embodiment of the present invention can be applied will be described. Here, an electronic device including a power generation device and a power reception device will be described as an example.

  An example of a portable information terminal as an example of the electrical device will be described with reference to FIG.

  FIG. 16A is a perspective view showing the front and the side of the portable information terminal 8040. FIG. As an example, the portable information terminal 8040 can execute various applications such as mobile telephone, electronic mail, text browsing and creation, music reproduction, Internet communication, computer games, and the like. A portable information terminal 8040 has a display portion 8042, a camera 8045, a microphone 8046, and a speaker 8047 on the front of a housing 8041, and has a button 8043 for operation on the left side of the housing 8041 and a connection terminal 8048 on the bottom .

  The display module or the display panel of one embodiment of the present invention is used for the display portion 8042.

  A portable information terminal 8040 shown in FIG. 16A is an example in which one display portion 8042 is provided in a housing 8041. However, the present invention is not limited to this. The display portion 8042 may be provided on the back surface of the portable information terminal 8040. Alternatively, two or more display units may be provided as a foldable portable information terminal.

  Further, the display portion 8042 is provided with a touch panel which can input information by an instruction unit such as a finger or a stylus as an input unit. Thus, the icon 8044 displayed on the display unit 8042 can be easily operated by the instruction unit. In addition, since the area for arranging the keyboard in the portable information terminal 8040 becomes unnecessary due to the arrangement of the touch panel, the display portion can be arranged in a wide area. In addition, since information can be input using a finger or a stylus, a user-friendly interface can be realized. As the touch panel, various methods such as a resistive film method, a capacitance method, an infrared method, an electromagnetic induction method, a surface acoustic wave method and the like can be adopted, but since the display portion 8042 is curved, the resistance is particularly high. It is preferable to use a membrane method or a capacitance method. In addition, such a touch panel may be of a so-called in-cell type combined with the above-described display module or display panel as one unit.

  Further, the touch panel may function as an image sensor. In this case, personal identification can be performed, for example, by touching the display portion 8042 with a palm or finger to capture a palm print, a fingerprint, or the like. In addition, when a backlight which emits near-infrared light or a sensing light source which emits near-infrared light is used for the display portion 8042, an image of a finger vein, a palm vein, or the like can be taken.

  In addition, a keyboard may be provided in the display portion 8042 without providing a touch panel, or both of the touch panel and the keyboard may be provided.

  The operation button 8043 can have various functions in accordance with the application. For example, the home screen may be displayed on the display portion 8042 by using the button 8043 as a home button and pressing the button 8043. Alternatively, the main power supply of the portable information terminal 8040 may be turned off by pressing the button 8043 for a predetermined time. In addition, when transitioning to the sleep mode state, the button 8043 may be pressed to recover from the sleep mode state. In addition, it can be used as a switch for activating various functions by, for example, keeping pressing and pressing simultaneously with other buttons.

  Alternatively, the button 8043 may be a volume adjustment button or a mute button, and may have a function of adjusting the volume of the speaker 8047 for sound output. From the speaker 8047, various sounds such as sounds set during specific processing such as startup sound of operating system (OS), sounds by sound files executed in various applications such as music from music playback application software, ring tones of e-mail, etc. Output Although not shown, the sound output may be replaced with the speaker 8047 or in place of the speaker 8047, and a connector for outputting sound to a device such as a headphone, an earphone, or a headset may be provided.

  Thus, the button 8043 can be provided with various functions. Although FIG. 16A shows a portable information terminal 8040 provided with two buttons 8043 on the left side, it goes without saying that the number of buttons 8043 and the arrangement position thereof are not limited thereto, and may be designed appropriately. it can.

  The microphone 8046 can be used for voice input and recording. Further, an image acquired by the camera 8045 can be displayed on the display portion 8042.

  In addition to the touch panel and button 8043 provided in the display portion 8042 described above, the operation of the mobile information terminal 8040 uses the camera 8045, a sensor incorporated in the mobile information terminal 8040, and the like to recognize the user's operation (gesture) It is also possible to perform an operation (called a gesture input). Alternatively, the microphone 8046 can be used to recognize the user's voice and perform an operation (referred to as voice input). As described above, the operability of the portable information terminal 8040 can be further improved by implementing the NUI (Natural User Interface) technology for inputting to the electric device by natural human behavior.

  The connection terminal 8048 is a signal or power input terminal for communication with an external device or power supply. For example, the connection terminal 8048 can be used to drive an external memory in the portable information terminal 8040. As an external memory drive, for example, an external HDD (hard disk drive) or a flash memory drive, a DVD (Digital Versatile Disk), a DVD-R (DVD-Recordable), a DVD-RW (DVD-Rewritable), a CD (Compact Disc), a CD -Compact Disc Recordable (R), Compact Disc Rewritable (CD-RW), Magneto Optical Disc (MO), Floppy Disk Drive (FDD), or other non-volatile Solid State Drive (SSD) devices, etc. A recording media drive is mentioned. In addition, although the portable information terminal 8040 has a touch panel on the display portion 8042, a keyboard may be provided on the housing 8041 instead, or a keyboard may be externally attached.

  Although FIG. 16A illustrates a portable information terminal 8040 in which one connection terminal 8048 is provided on the bottom surface, the number and arrangement position of the connection terminals 8048 are not limited to this, and can be appropriately designed. .

  FIG. 16B is a perspective view showing the back and the side of the portable information terminal 8040. A portable information terminal 8040 has a solar cell 8049 and a camera 8050 on the surface of a housing 8041, and further has a charge / discharge control circuit 8051, a battery 8052, a DCDC converter 8053, and the like. The electric power generated by the solar cell 8049 by the outside light is boosted or stepped down by the DCDC converter 8053 to obtain a voltage necessary to charge the battery 8052. When the power from the solar cell 8049 is used for the operation of the display portion 8042, the charge / discharge control circuit 8051 boosts or steps down the voltage to the voltage required for the display portion 8042.

  Electric power can be supplied to the display portion, the touch panel, the video signal processing portion, or the like by the solar battery 8049 mounted on the back surface of the portable information terminal 8040. Note that the solar cell 8049 can be provided on one side or both sides of the housing 8041. By mounting the solar cell 8049 in the portable information terminal 8040, the battery 8052 of the portable information terminal 8040 can be charged even in a place where there is no means for supplying power such as outdoor. In addition, as shown in FIG. 16A, an image or the like indicating the charge state of the battery 8052 or the state being charged by the solar cell 8049 is displayed on the upper left (in the broken line frame) of the display portion 8042. Good.

  Although the solar cell 8049 is shown as an example of the power generation means, the present invention is not limited to this. The battery 8052 is charged using another power generation means such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element). May be Alternatively, a non-contact power transmission module may be used which wirelessly transmits and receives power to charge the battery, or the above charging methods may be combined.

  This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.

Fifth Embodiment
In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described.

  A display module 6000 illustrated in FIG. 17A includes a display device 6006 connected to an FPC 6005, a frame 6009, a printed substrate 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002.

  For example, the display device manufactured using one embodiment of the present invention can be used for the display device 6006. The display device 6006 can realize a display module with extremely low power consumption.

  The shape and size of the upper cover 6001 and the lower cover 6002 can be appropriately changed in accordance with the size of the display device 6006.

  In addition, a touch panel may be provided over the display device 6006. As a touch panel, a resistive touch panel or a capacitive touch panel can be superimposed on the display device 6006 and used. Alternatively, the display device 6006 can have a touch panel function without providing a touch panel. In addition, the display module 6000 may be provided with an optical touch sensor.

  The frame 6009 has a function as an electromagnetic shield for blocking an electromagnetic wave generated by the operation of the printed substrate 6010, in addition to the protective function of the display device 6006. The frame 6009 may also have a function as a heat sink.

  The printed circuit board 6010 has a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power supply for supplying power to the power supply circuit, an external commercial power supply may be used, or a power supply using a separately provided battery 6011 may be used. The battery 6011 can be omitted when using a commercial power supply.

  FIG. 17B is a schematic cross-sectional view of a display module 6000 including an optical touch sensor.

  The display module 6000 includes a light emitting unit 6015 and a light receiving unit 6016 provided on the printed circuit board 6010. A pair of light guide portions (light guide portions 6017 a and 6017 b) is provided in a region surrounded by the upper cover 6001 and the lower cover 6002.

  For example, plastic or the like can be used for the upper cover 6001 and the lower cover 6002. Further, the upper cover 6001 and the lower cover 6002 can be made thinner (for example, 0.5 mm or more and 5 mm or less). Therefore, the display module 6000 can be made extremely lightweight. Further, since the upper cover 6001 and the lower cover 6002 can be manufactured with a small amount of material, the manufacturing cost can be reduced.

  The display device 6006 is provided to overlap the printed circuit board 6010 and the battery 6011 with the frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to the light guide unit 6017 a and the light guide unit 6017 b.

  The light 6018 emitted from the light emitting unit 6015 passes through the upper portion of the display device 6006 by the light guiding unit 6017 a, passes through the light guiding unit 6017 b, and reaches the light receiving unit 6016. For example, when the light 6018 is blocked by a detection target such as a finger or a stylus, a touch operation can be detected.

  For example, a plurality of light emitting units 6015 are provided along two adjacent sides of the display device 6006. A plurality of light receiving units 6016 are provided at positions facing the light emitting units 6015. Thereby, information on the position where the touch operation has been performed can be acquired.

  The light emitting unit 6015 can use a light source such as an LED element, for example. In particular, it is preferable to use, as the light emitting portion 6015, a light source that emits infrared rays that is not visually recognized by the user and is harmless to the user.

  The light receiving unit 6016 can use a photoelectric element that receives light emitted by the light emitting unit 6015 and converts the light into an electric signal. Preferably, a photodiode capable of receiving infrared light can be used.

  As the light guide portion 6017a and the light guide portion 6017b, a member which transmits at least light 6018 can be used. By using the light guiding unit 6017a and the light guiding unit 6017b, the light emitting unit 6015 and the light receiving unit 6016 can be disposed below the display device 6006, and external light reaches the light receiving unit 6016 and the touch sensor malfunctions Can be suppressed. In particular, it is preferable to use a resin that absorbs visible light and transmits infrared light. Thereby, the malfunction of the touch sensor can be suppressed more effectively.

  This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.

Sixth Embodiment
In this embodiment, an electronic device provided with a display device manufactured using one embodiment of the present invention will be described.

  The electronic devices illustrated in FIGS. 18A to 18G include a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), a connection terminal 9006, a sensor 9007 (a power , Displacement, position, velocity, acceleration, angular velocity, number of rotations, distance, light, liquid, magnetism, temperature, chemicals, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, inclination, vibration , Including a function of measuring odor or infrared), a microphone 9008, and the like.

  The electronic devices illustrated in FIGS. 18A to 18G have various functions. For example, a function of displaying various information (still image, moving image, text image, etc.) on the display unit, a touch panel function, a calendar, a function of displaying date or time, etc., a function of controlling processing by various software (programs), A wireless communication function, a function of connecting to various computer networks using the wireless communication function, a function of transmitting or receiving various data using the wireless communication function, reading out and displaying a program or data recorded in a recording medium It can have a function of displaying on a unit, and the like. Note that the electronic device illustrated in FIGS. 18A to 18G can have various functions without limitation to the above. Although not illustrated in FIGS. 18A to 18G, the electronic device may have a plurality of display portions. In addition, a camera or the like is provided in the electronic device, a function of capturing a still image, a function of capturing a moving image, a function of saving a captured image in a recording medium (externally or incorporated in the camera), and displaying the captured image on a display portion And the like.

  The details of the electronic devices illustrated in FIGS. 18A to 18G will be described below.

  FIG. 18A is a perspective view showing a portable information terminal 9101. FIG. The portable information terminal 9101 has one or more functions selected from, for example, a telephone, a notebook, an information browsing apparatus, and the like. Specifically, it can be used as a smartphone. Note that the portable information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. In addition, the portable information terminal 9101 can display text and image information on the plurality of surfaces. For example, three operation buttons 9050 (also referred to as operation icons or simply icons) can be displayed on one surface of the display portion 9001. Further, information 9051 indicated by a dashed-line rectangle can be displayed on another surface of the display portion 9001. Note that examples of the information 9051 include a display for notifying an incoming call such as an email or SNS (social networking service) or a telephone, a title such as an email or SNS, a sender name such as an email or SNS, a date, time , Battery level, antenna reception strength, etc. Alternatively, instead of the information 9051, an operation button 9050 or the like may be displayed at the position where the information 9051 is displayed.

  FIG. 18B is a perspective view of the portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001. Here, an example is shown in which the information 9052, the information 9053, and the information 9054 are displayed on different sides. For example, the user of the portable information terminal 9102 can confirm the display (here, information 9053) in a state where the portable information terminal 9102 is stored in the chest pocket of the clothes. Specifically, the telephone number or the name or the like of the caller of the incoming call is displayed at a position where it can be observed from above the portable information terminal 9102. The user can check the display without taking out the portable information terminal 9102 from the pocket, and can judge whether or not to receive a call.

  FIG. 18C is a perspective view showing a wristwatch-type portable information terminal 9200. The portable information terminal 9200 can execute various applications such as mobile phone, electronic mail, text browsing and creation, music reproduction, Internet communication, computer games and the like. In addition, the display portion 9001 is provided with a curved display surface, and can perform display along the curved display surface. In addition, the portable information terminal 9200 can execute near-field wireless communication according to the communication standard. For example, it is possible to make a hands-free call by intercommunicating with a wireless communicable headset. In addition, the portable information terminal 9200 has a connection terminal 9006, and can directly exchange data with another information terminal through a connector. In addition, charging can be performed through the connection terminal 9006. Note that the charging operation may be performed by wireless power feeding without using the connection terminal 9006.

  18D, 18E, and 18F are perspective views showing a foldable portable information terminal 9201. FIG. FIG. 18D is a perspective view of the portable information terminal 9201 in an expanded state, and FIG. 18E shows a state in the middle of changing from one of the expanded or folded portable information terminal 9201 to the other. 18F is a perspective view of the portable information terminal 9201 in a folded state. The portable information terminal 9201 is excellent in portability in the folded state, and excellent in viewability of display due to a wide seamless display area in the expanded state. A display portion 9001 of the portable information terminal 9201 is supported by three housings 9000 connected by hinges 9055. By bending between the two housings 9000 via the hinge 9055, the portable information terminal 9201 can be reversibly deformed from the expanded state to the folded state. For example, the portable information terminal 9201 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

  FIG. 18G is an external view of the head mounted display 9300. As shown in FIG. The head mounted display 9300 includes a housing 9000, a display portion 9001, a band-like fixing tool 9304, and a pair of lenses 9305.

  The user can view the display of the display portion 9001 through the lens 9305. Note that the display portion 9001 is preferably curved and disposed. By arranging the display portion 9001 in a curved manner, the user can feel a high sense of reality. Note that although the present embodiment exemplifies a configuration in which one display portion 9001 is provided, the present invention is not limited to this. For example, two display portions 9001 may be provided. In this case, when one display unit is disposed in one eye of the user, it is possible to perform three-dimensional display or the like using parallax.

  The electronic device described in this embodiment is characterized by having a display portion for displaying some kind of information. Note that the semiconductor device of one embodiment of the present invention can also be applied to an electronic device that does not have a display portion.

  At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented in appropriate combination with other configuration examples, drawings, and the like.

  This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.

Seventh Embodiment
In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to the drawings.

  The electronic devices described below each include the display device of one embodiment of the present invention in a display portion. Therefore, it is an electronic device in which high resolution is realized. In addition, an electronic device in which a high resolution and a large screen are compatible can be provided.

  The display portion of the electronic device of one embodiment of the present invention can display an image having a resolution of, for example, full high definition, 4K2K, 8K4K, 16K8K, or higher. In addition, the screen size of the display unit may be 20 inches or more diagonally, 30 inches or more diagonally, 50 inches diagonally or more, 60 inches diagonally or more, or 70 inches diagonally or more.

  Examples of electronic devices include relatively large screens of television devices, desktop or notebook personal computers, monitors for computers, etc., large-sized game machines such as digital signage (Digital Signage), and pachinko machines. In addition to the electronic devices provided, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, sound reproduction devices, and the like can be given.

  The electronic device or lighting device of one embodiment of the present invention can be incorporated along the inner or outer wall of a house or building, or along the curved surface of the interior or exterior of a car.

  The electronic device of one embodiment of the present invention may have an antenna. By receiving the signal with the antenna, display of images, information, and the like can be performed on the display portion. In addition, when the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

  The electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow, humidity, inclination, vibration, odor or infrared.

  The electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function of displaying date or time, etc., a function of executing various software (programs), wireless communication A function, a function of reading a program or data recorded in a recording medium, or the like can be provided.

  FIG. 19A shows an example of a television set. In the television set 7100, a display portion 7500 is incorporated in a housing 7101. Here, a structure in which the housing 7101 is supported by the stand 7103 is shown.

  The display device of one embodiment of the present invention can be applied to the display portion 7500.

  The television set 7100 illustrated in FIG. 19A can be operated by an operation switch of the housing 7101 or a separate remote controller 7111. Alternatively, the display portion 7500 may be provided with a touch sensor or may be operated by touching the display portion 7500 with a finger or the like. The remote controller 7111 may have a display unit for displaying information output from the remote controller 7111. Channels and volume can be controlled with an operation key or a touch panel included in the remote controller 7111, and a video displayed on the display portion 7500 can be manipulated.

  Note that the television set 7100 is provided with a receiver, a modem, and the like. The receiver can receive a general television broadcast. In addition, by connecting to a wired or wireless communication network via a modem, one-way (from a sender to a receiver) or two-way (between a sender and a receiver, between receivers, etc.) information communication is performed. It is also possible.

  FIG. 19B shows a notebook personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. The display portion 7500 is incorporated in the housing 7211.

  The display device of one embodiment of the present invention can be applied to the display portion 7500.

  FIGS. 19C and 19D show an example of digital signage (digital signage: electronic signboard).

  A digital signage 7300 illustrated in FIG. 19C includes a housing 7301, a display portion 7500, a speaker 7303, and the like. Furthermore, an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be included.

  FIG. 19D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display 7500 provided along the curved surface of the column 7401.

  In FIGS. 19C and 19D, the display device of one embodiment of the present invention can be applied to the display portion 7500.

  As the display portion 7500 is wider, the amount of information that can be provided at one time can be increased. Also, the wider the display portion 7500 is, the easier it is for a person to notice, and for example, advertising effects can be enhanced.

  By applying a touch panel to the display portion 7500, not only an image or a moving image can be displayed on the display portion 7500, but also a user can operate intuitively, which is preferable. Moreover, when using for the application for providing information, such as route information or traffic information, usability can be improved by intuitive operation.

  In addition, as shown in FIGS. 19C and 19D, the digital signage 7300 or the digital signage 7400 can cooperate with the information terminal 7311 or information terminal 7411 such as a smartphone possessed by the user by wireless communication. Is preferred. For example, information of an advertisement displayed on the display portion 7500 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Further, the display of the display portion 7500 can be switched by operating the information terminal 7311 or the information terminal 7411.

  In addition, it is possible to make the digital signage 7300 or the digital signage 7400 execute a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller). Thus, an unspecified number of users can simultaneously participate in and enjoy the game.

  This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.

Eighth Embodiment
In this embodiment, an example of a television set to which a display device including the semiconductor device of one embodiment of the present invention can be applied is described with reference to drawings.

  A block diagram of the television set 600 is shown in FIG.

  In the drawings attached to this specification, components are classified according to functions and block diagrams are shown as blocks independent of each other. However, it is difficult to completely divide actual components according to functions, and A component may be involved in more than one function.

  The television device 600 includes a control unit 601, a storage unit 602, a communication control unit 603, an image processing circuit 604, a decoder circuit 605, a video signal reception unit 606, a timing controller 607, a source driver 608, a gate driver 609, a display panel 620, and the like. Have.

  The display device illustrated in the above embodiment can be applied to the display panel 620 in FIG. Thus, a television set 600 which is large and has high resolution and is excellent in visibility can be realized.

  The control unit 601 can function as, for example, a central processing unit (CPU). For example, the control unit 601 has a function of controlling components such as the storage unit 602, the communication control unit 603, the image processing circuit 604, the decoder circuit 605, and the video signal reception unit 606 via the system bus 630.

  Transmission of signals is performed between the control unit 601 and each component via a system bus 630. In addition, the control unit 601 has a function of processing a signal input from each component connected via the system bus 630, a function of generating a signal to be output to each component, and the like. Control each component.

  The storage unit 602 functions as a register accessible by the control unit 601 and the image processing circuit 604, a cache memory, a main memory, a secondary memory, and the like.

  As a storage device that can be used as a secondary memory, for example, a storage device to which a rewritable non-volatile storage element is applied can be used. For example, flash memory, MRAM (Magnetoresistive Random Access Memory), PRAM (Phase change RAM), ReRAM (Resistive RAM), FeRAM (Ferroelectric RAM) or the like can be used.

  In addition, as a storage device that can be used as a temporary memory such as a register, a cache memory, and a main memory, volatile storage elements such as DRAM (Dynamic RAM) and SRAM (Static Random Access Memory) may be used.

  For example, as a RAM provided in the main memory, a DRAM, for example, is used, and a memory space is virtually allocated and used as a work space of the control unit 601. The operating system, application programs, program modules, program data and the like stored in the storage unit 602 are loaded into the RAM for execution. These data, programs, and program modules loaded into the RAM are directly accessed and operated by the control unit 601.

  On the other hand, the ROM can store a BIOS (Basic Input / Output System), firmware and the like which do not require rewriting. As the ROM, a mask ROM, an OTP ROM (One Time Programmable Read Only Memory), an EPROM (Erasable Programmable Read Only Memory) or the like can be used. Examples of the EPROM include a UV-EPROM (Ultra-Violet Erasable Programmable Read Only Memory), an EEPROM (Electrically Erasable Programmable Read Only Memory), and a flash memory, which can erase stored data by ultraviolet irradiation.

  In addition to the storage unit 602, a removable storage device may be connectable. For example, it has a terminal connected to a recording medium drive such as a hard disk drive (HDD) or a solid state drive (solid state drive: SSD) functioning as a storage device, a flash memory, a Blu-ray disc, a DVD, etc. Is preferred. Thereby, the video can be recorded.

  The communication control unit 603 has a function of controlling communication performed via a computer network. For example, in response to an instruction from the control unit 601, a control signal for connecting to the computer network is controlled, and the signal is transmitted to the computer network. This enables connection to a computer network and communication.

  Also, the communication control unit 603 has a function of communicating with a computer network or another electronic device using a communication standard such as Wi-Fi (registered trademark), Bluetooth (registered trademark), ZigBee (registered trademark), etc. It is also good.

  The communication control unit 603 may have a function of communicating by wireless. For example, an antenna and a high frequency circuit (RF circuit) may be provided to transmit and receive an RF signal. The high frequency circuit connected to the antenna includes high frequency circuits corresponding to a plurality of frequency bands, and the high frequency circuit includes an amplifier, a mixer, a filter, a DSP, an RF transceiver, and the like. it can.

  The video signal reception unit 606 includes, for example, an antenna, a demodulation circuit, an AD conversion circuit (analog-digital conversion circuit), and the like. The demodulation circuit has a function of demodulating a signal input from the antenna. The AD conversion circuit also has a function of converting a demodulated analog signal into a digital signal. The signal processed by the video signal reception unit 606 is sent to the decoder circuit 605.

  The decoder circuit 605 has a function of decoding video data included in the digital signal input from the video signal reception unit 606 according to the specification of the broadcast standard to be transmitted, and generating a signal to be transmitted to the image processing circuit. For example, as a broadcast standard in 8K broadcast, H.264 and H.264 265 | MPEG-H High Efficiency Video Coding (abbreviation: HEVC) and the like.

  Examples of broadcast radio waves that can be received by the antenna of the video signal reception unit 606 include terrestrial waves, radio waves transmitted from satellites, and the like. Further, as broadcast radio waves that can be received by an antenna, there are analog broadcasting, digital broadcasting, etc., and also, there are broadcasting of only video and audio, or audio. For example, broadcast radio waves transmitted in a specific frequency band in the UHF band (about 300 MHz to 3 GHz) or the VHF band (30 MHz to 300 MHz) can be received. Further, for example, by using a plurality of data received in a plurality of frequency bands, the transfer rate can be increased, and more information can be obtained. Thus, an image having a resolution exceeding full high vision can be displayed on the display panel 620. For example, an image having a resolution of 4K2K, 8K4K, 16K8K, or higher can be displayed.

  Further, the video signal receiving unit 606 and the decoder circuit 605 may be configured to generate a signal to be transmitted to the image processing circuit 604 by using broadcast data transmitted by a data transmission technique via a computer network. At this time, when the signal to be received is a digital signal, the video signal receiving unit 606 may not have a demodulation circuit, an A-D conversion circuit, and the like.

  The image processing circuit 604 has a function of generating a video signal to be output to the timing controller 607 based on the video signal input from the decoder circuit 605.

  The timing controller 607 also outputs signals (such as clock signals and start pulse signals) to be output to the gate driver 609 and the source driver 608 based on synchronization signals included in video signals and the like processed by the image processing circuit 604. Has a function to generate. In addition to the above signals, the timing controller 607 has a function of generating a video signal to be output to the source driver 608.

  The display panel 620 has a plurality of pixels 621. Each pixel 621 is driven by a signal supplied from the gate driver 609 and the source driver 608. Here, an example of a display panel having a resolution according to the 8K4K standard, in which the number of pixels is 7680 × 4320, is shown. Note that the resolution of the display panel 620 is not limited to this, and may be a resolution according to a standard such as full high vision (the number of pixels 1920 × 1080) or 4K2K (the number of pixels 3840 × 2160).

  The control unit 601 and the image processing circuit 604 illustrated in FIG. 20 can be configured to include, for example, a processor. For example, the control unit 601 can use a processor that functions as a central processing unit (CPU). Further, as the image processing circuit 604, for example, another processor such as a digital signal processor (DSP) or a graphics processing unit (GPU) can be used. Further, the control unit 601 and the image processing circuit 604 may have a configuration in which the processor is realized by a PLD (Programmable Logic Device) such as a field programmable gate array (FPGA) or a field programmable analog array (FPAA).

  A processor performs various data processing and program control by interpreting and executing instructions from various programs. The program that can be executed by the processor may be stored in a memory area of the processor or may be stored in a separately provided storage device.

  In addition, two or more functions of the control unit 601, the storage unit 602, the communication control unit 603, the image processing circuit 604, the decoder circuit 605, the video signal reception unit 606, and the timing controller 607 have one or more functions. Two IC chips may be integrated to configure a system LSI. For example, a system LSI including a processor, a decoder circuit, a tuner circuit, an AD conversion circuit, a DRAM, an SRAM, and the like may be used.

  Note that an oxide semiconductor can be used for a channel formation region in the control portion 601 or an IC or the like included in another component, and a transistor with extremely low off-state current can be used. Since the transistor has extremely low off-state current, the data retention period can be secured for a long time by using the transistor as a switch for retaining charge (data) flowing into a capacitor functioning as a memory element. it can. By using this characteristic for a register or cache memory of the control unit 601 or the like, the control unit 601 is operated only when necessary, and in other cases, the information of the immediately preceding process is saved in the storage element. Off computing is possible. Thus, power consumption of the television set 600 can be reduced.

  Note that the structure of the television set 600 illustrated in FIG. 20 is an example, and it is not necessary to include all the components. The television device 600 may have necessary components of the components shown in FIG. In addition, the television set 600 may have components other than the components shown in FIG.

  For example, the television device 600 may have an external interface, an audio output unit, a touch panel unit, a sensor unit, a camera unit, and the like in addition to the configuration shown in FIG. For example, as an external interface, for example, a USB (Universal Serial Bus) terminal, a LAN (Local Area Network) connection terminal, a power supply reception terminal, an audio output terminal, an audio input terminal, an image output terminal, an image input terminal, etc. External communication terminals, a transmitter / receiver for optical communication using infrared light, visible light, ultraviolet light and the like, a physical button provided on a housing, and the like. Also, for example, as a sound input / output unit, there are a sound controller, a microphone, a speaker, and the like.

  Hereinafter, the image processing circuit 604 will be described in more detail.

  The image processing circuit 604 preferably has a function of executing image processing based on the video signal input from the decoder circuit 605.

  Examples of the image processing include noise removal processing, tone conversion processing, color tone correction processing, and luminance correction processing. Examples of the color tone correction process and the brightness adjustment process include gamma correction.

  Further, the image processing circuit 604 preferably has a function of executing processing such as inter-pixel interpolation processing accompanying resolution up-conversion and processing such as inter-frame interpolation accompanying frame frequency up conversion.

  For example, as noise removal processing, various noises such as mosquito noise generated around an outline of a character or the like, block noise generated in a high-speed moving image, random noise causing flicker, dot noise generated by resolution upconversion are removed.

  The gradation conversion process is a process of converting the gradation of an image into a gradation corresponding to the output characteristic of the display panel 620. For example, in the case where the number of gradations is increased, processing for smoothing the histogram can be performed by interpolating and allocating gradation values corresponding to respective pixels to an image input with a small number of gradations. In addition, dynamic range (HDR) processing that extends the dynamic range is also included in the tone conversion processing.

  Further, the inter-pixel interpolation process interpolates data that is not originally present when up-converting the resolution. For example, it references pixels around the target pixel and interpolates the data to display their intermediate colors.

  The color tone correction process is a process for correcting the color tone of an image. The luminance correction processing is processing for correcting the brightness (luminance contrast) of an image. For example, the type, brightness, color purity, and the like of the illumination provided in the space where the television device 600 is provided are detected, and the brightness and color tone of the image displayed on the display panel 620 are corrected accordingly. . Alternatively, it has a function to match the image to be displayed with the images of various scenes in the image list stored in advance, and correct the image to be displayed with the brightness and tone suitable for the image of the closest scene. May be

  Inter-frame interpolation generates an image of a frame (interpolated frame) which does not originally exist when increasing the frame frequency of a displayed image. For example, an image of an interpolation frame to be inserted between two images is generated from the difference between two images. Alternatively, images of a plurality of interpolation frames can be generated between two images. For example, when the frame frequency of the video signal input from the decoder circuit 605 is 60 Hz, the frame frequency of the video signal output to the timing controller 607 is doubled to 120 Hz by generating a plurality of interpolation frames. It can be increased to four times 240 Hz, or eight times 480 Hz, and so on.

  In addition, the image processing circuit 604 preferably has a function of executing image processing using a neural network. FIG. 20 shows an example in which the image processing circuit 604 has a neural network 610.

  For example, the neural network 610 can perform feature extraction from image data included in a video, for example. Further, the image processing circuit 604 can select an optimal correction method according to the extracted feature or select a parameter used for correction.

  Alternatively, the neural network 610 itself may have a function of performing image processing. That is, by inputting the image data before the image processing to the neural network 610, the image data subjected to the image processing may be output.

  Also, data of weighting factors used for the neural network 610 is stored in the storage unit 602 as a data table. The data table including the weighting factor can be updated to the latest one by the communication control unit 603 via the computer network, for example. Alternatively, the image processing circuit 604 may have a learning function, and the data table including the weighting factor may be updated.

  In the present specification and the like, a neural network refers to a whole model that imitates a neural network of an organism, determines the connection strength between neurons by learning, and has a problem solving ability. A neural network has an input layer, an intermediate layer (also called a hidden layer), and an output layer. Among neural networks, one having two or more intermediate layers is called deep learning (or deep neural network (DNN)).

  This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.

<Supplementary Notes on the Description of this Specification>
A description of each configuration in the above embodiment will be additionally described below.

  In the figures described herein, the size of each feature, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale.

  In addition, the ordinal numbers “first”, “second”, and “third” used in the present specification are given to avoid confusion of the constituent elements, and are not limited numerically.

  Further, in the present specification, the terms indicating the arrangement such as “above” and “below” are used for the sake of convenience to explain the positional relationship between the components with reference to the drawings. In addition, the positional relationship between the components is appropriately changed in accordance with the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification, and can be appropriately rephrased depending on the situation.

  Further, in this specification and the like, a transistor is an element having at least three terminals of a gate, a drain, and a source. A channel formation region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and between the source and the drain via the channel formation region. It is possible to flow a current. Note that in this specification and the like, a channel formation region refers to a region through which current mainly flows.

  In addition, the functions of the source and the drain may be switched when adopting transistors of different polarities or when the direction of current changes in circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” can be used interchangeably.

  Further, in the present specification and the like, the term "electrically connected" includes the case where they are connected via "something having an electrical function". Here, the “thing having an electrical function” is not particularly limited as long as it can transmit and receive electrical signals between connection targets. For example, “those having some electrical action” include electrodes, wirings, switching elements such as transistors, resistance elements, inductors, capacitors, elements having various other functions, and the like.

  Moreover, in this specification etc., the "parallel" means the state by which two straight lines are arrange | positioned by the angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "vertical" means that two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included.

  In the present specification and the like, the term "membrane" and the term "layer" can be interchanged with each other. For example, it may be possible to change the term "conductive layer" to the term "conductive film". Alternatively, for example, it may be possible to change the term "insulating film" to the term "insulating layer".

  In the present specification and the like, an off-state current is a drain current when the transistor is in an off state (also referred to as a non-conduction state or a cutoff state) unless otherwise specified. The off state is a state in which the voltage Vgs between the gate and the source is lower than the threshold voltage Vth in the n-channel transistor, and the voltage Vgs between the gate and the source in the p-channel transistor unless otherwise noted. Is higher than the threshold voltage Vth.

  The off current of the transistor may depend on Vgs. Therefore, that the off-state current of the transistor is less than or equal to I may mean that there is a value of Vgs at which the off-state current of the transistor is less than or equal to I. The off-state current of the transistor may refer to the off-state current in the off state at the given Vgs, the off state at the Vgs in the given range, or the off state at the Vgs at which a sufficiently reduced off current is obtained.

As an example, the threshold voltage Vth is 0.5 V, the drain current at Vgs of 0.5 V is 1 × 10 ⁻⁹ A, and the drain current at Vgs of 0.1 V is 1 × 10 ⁻¹³ A , And an n-channel transistor having a drain current of 1 × 10 ⁻¹⁹ A at a Vgs of −0.5 V and a drain current of 1 × 10 ⁻²² A at a Vgs of −0.8 V. Since the drain current of the transistor is 1 × 10 ⁻¹⁹ A or less at Vgs of −0.5 V or Vgs in the range of −0.5 V to −0.8 V, the off current of the transistor is 1 It may be said that x 10 ^-19 A or less. Since Vgs in which the drain current of the transistor is 1 × 10 ⁻²² A or less exists, it may be said that the off-state current of the transistor is 1 × 10 ⁻²² A or less.

  Further, in this specification and the like, the off-state current of a transistor having a channel width W may be expressed by a current value flowing around the channel width W. Also, it may be represented by a current value flowing around a predetermined channel width (for example, 1 μm). In the latter case, the unit of the off current may be represented by a unit having a dimension of current / length (for example, A / μm).

  The off current of the transistor may depend on temperature. In the present specification, the off current may represent an off current at room temperature, 60 ° C., 85 ° C., 95 ° C., or 125 ° C., unless otherwise specified. Alternatively, at a temperature at which the reliability of a semiconductor device or the like including the transistor is ensured, or at a temperature at which a semiconductor device or the like including the transistor is used (for example, any one of 5 ° C. to 35 ° C.). It may represent an off current. The off-state current of a transistor is less than or equal to I means room temperature, 60 ° C., 85 ° C., 95 ° C., 125 ° C., a temperature at which the reliability of a semiconductor device including the transistor is ensured, or the transistor It may indicate that there is a value of Vgs at which the off-state current of the transistor at a temperature at which a semiconductor device or the like is used (for example, any one of 5 ° C. to 35 ° C.) is less than or equal to I.

  The off current of the transistor may depend on the voltage Vds between the drain and the source. In the present specification, unless otherwise specified, the off current is 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V as Vds. Or may represent an off current at 20V. Alternatively, Vds may represent an off current in Vds for which reliability of a semiconductor device or the like including the transistor is ensured, or Vds used in a semiconductor device or the like including the transistor. The off-state current of the transistor is less than or equal to I if Vds is 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, 20 V There is a value of Vgs at which the off-state current of the transistor at Vds for which the reliability of a semiconductor device including the transistor is guaranteed or at Vds used in a semiconductor device or the like including the transistor is less than or equal to I. May point to

  In the above description of the off current, the drain may be read as a source. That is, the off current may refer to the current flowing through the source when the transistor is in the off state.

  In the present specification and the like, a leak current may be described in the same meaning as an off current. Further, in this specification and the like, an off-state current may indicate a current flowing between a source and a drain, for example, when the transistor is in the off state.

Further, in this specification and the like, the threshold voltage of a transistor refers to the gate voltage (Vg) when a channel is formed in the transistor. Specifically, the threshold voltage of a transistor is the maximum slope in a curve (Vg-√Id characteristic) in which the gate voltage (Vg) is plotted on the horizontal axis and the square root of the drain current (Id) is plotted on the vertical axis. In some cases, the gate voltage (Vg) at the intersection of a straight line obtained by extrapolating a certain tangent and the square root of the drain current (Id) may be 0 (Id is 0A). Alternatively, with respect to the threshold voltage of a transistor, a gate having a channel length of L and a channel width of W and a value of Id [A] × L [μm] / W [μm] of 1 × 10 ⁻⁹ [A] It may indicate voltage (Vg).

  In the present specification and the like, even when it is described as "semiconductor", for example, when the conductivity is sufficiently low, it may have characteristics as an "insulator". In addition, the boundaries between the “semiconductor” and the “insulator” may be vague and may not be strictly distinguishable. Therefore, the “semiconductor” and the “insulator” described in the present specification and the like may be paraphrased in some cases.

  In the present specification and the like, even when the term "semiconductor" is used, for example, when the conductivity is sufficiently high, it may have characteristics as a "conductor". In addition, the boundaries between the "semiconductor" and the "conductor" may be vague and may not be strictly distinguishable. Therefore, the “semiconductor” and the “conductor” described in the present specification and the like may be able to be rephrased with each other.

  In the present specification and the like, when the atomic ratio is In: Ga: Zn = 4: 2: 3 or in the vicinity thereof, the ratio of In to the total number of In, Ga, and Zn atoms is 4 It is assumed that the ratio of Ga is 1 or more and 3 or less, and the ratio of Zn is 2 or more and 4 or less. Further, that the atomic ratio is In: Ga: Zn = 5: 1: 6 or near is that when the ratio of In to the total number of atoms of In, Ga and Zn is 5, the ratio of Ga is It is assumed that the ratio is greater than 0.1 and less than or equal to 2, and the ratio of Zn is 5 or more and 7 or less. In addition, when the atomic ratio is In: Ga: Zn = 1: 1: 1 or near, the ratio of Ga is 1 when the ratio of In to the total number of atoms of In, Ga and Zn is 1. It is assumed that the ratio is greater than 0.1 and less than or equal to 2, and the ratio of Zn is greater than 0.1 and less than or equal to 2.

  In the present specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductor or simply OS), and the like. For example, in the case where a metal oxide is used for the active layer of the transistor, the metal oxide may be referred to as an oxide semiconductor. In addition, in the case of describing “OS FET”, it can be said to be a transistor having a metal oxide or an oxide semiconductor.

  In the present specification and the like, metal oxides having nitrogen may also be collectively referred to as metal oxides. In addition, a metal oxide having nitrogen may be referred to as metal oxynitride.

  Moreover, in this specification etc., it may describe as CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a structure of a material.

  Further, in this specification and the like, CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and the entire material is a semiconductor. Have the function of Note that in the case where CAC-OS or CAC-metal oxide is used for the active layer of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is electrons serving as carriers. Is a function that does not A function of switching (function of turning on / off) can be imparted to the CAC-OS or the CAC-metal oxide by causing the conductive function and the insulating function to be complementary to each other. By separating the functions of CAC-OS or CAC-metal oxide, both functions can be maximized.

  In the present specification and the like, a CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed as connected in a cloud shape with a blurred periphery.

  In addition, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in the material with a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less There is.

  Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap resulting from the insulating region and a component having a narrow gap resulting from the conductive region. In the case of this configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having the narrow gap acts complementarily to the component having the wide gap, and the carrier also flows to the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the above-described CAC-OS or CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on current, and high field effect mobility can be obtained in the on state of the transistor.

  That is, CAC-OS or CAC-metal oxide can also be called a matrix composite (matrix composite) or a metal matrix composite (metal matrix composite).

  An example of the crystal structure of the metal oxide is described. Note that, in the following, an example of a metal oxide film formed by a sputtering method using an In—Ga—Zn oxide target (In: Ga: Zn = 4: 2: 4.1 [atomic number ratio]) Explain as. A metal oxide formed by a sputtering method with a substrate temperature of 100 ° C. or more and 130 ° C. or less using the above target is referred to as sIGZO, and a substrate temperature of room temperature (R.T.) using the above target. The metal oxide formed by the method is called tIGZO. For example, sIGZO has a crystal structure of nc (nano crystal) and / or CAAC. In addition, tIGZO has a nc crystal structure. Note that the room temperature (R.T.) referred to here includes the temperature when the substrate is not intentionally heated.

  Note that a CAAC structure is one of crystal structures such as a thin film having a plurality of nanocrystals (crystal regions having a maximum diameter of less than 10 nm), and in each nanocrystal, the c-axis is oriented in a specific direction, that is, The crystal structure has c-axis orientation, and the a-axis and b-axis do not have orientation, and the nanocrystals are continuously connected without forming grain boundaries. In particular, a thin film having a CAAC structure is characterized in that the c-axis of each nanocrystal is easily oriented in the thickness direction of the thin film, the normal direction of the formation surface, or the normal direction of the surface of the thin film.

Here, in crystallography, it is general to take a unit cell with c-axis as a specific axis with respect to three axes (crystal axes) of a-axis, b-axis, and c-axis constituting the unit cell. . In particular, in a crystal having a layered structure, generally, two axes parallel to the plane direction of the layer are the a axis and b axis, and an axis intersecting the layer is the c axis. A typical example of a crystal having such a layered structure is graphite classified into a hexagonal system, and the a-axis and b-axis of the unit cell are parallel to the cleavage plane and the c-axis is orthogonal to the cleavage plane Do. For example, crystals of InGaZnO ₄ having a crystal structure of YbFe ₂ O ₄ type can be classified into a hexagonal system, and the a-axis and b-axis of the unit cell are parallel to the plane direction of the layer and the c-axis is a layer (ie, orthogonal to the a-axis and b-axis).

  In this specification and the like, a display panel which is one mode of a display device has a function of displaying (outputting) an image or the like on a display surface. Thus, the display panel is an aspect of the output device.

  Further, in this specification and the like, a substrate in which a connector such as a flexible printed circuit (FPC) or a TCP (Tape Carrier Package) is attached to a substrate of a display panel, or an IC by a COG (Chip On Glass) method or the like on a substrate What was implemented may be called a display panel module, a display module, or simply a display panel or the like.

  Further, in the present specification and the like, the touch sensor has a function of detecting that a detected object such as a finger or a stylus touches, presses, or approaches. Moreover, you may have the function to detect the positional information. Thus, the touch sensor is an aspect of the input device. For example, the touch sensor can be configured to have one or more sensor elements.

  Further, in this specification and the like, a substrate having a touch sensor may be referred to as a touch sensor panel or simply a touch sensor or the like. Further, in this specification and the like, a touch sensor panel module, a touch sensor in which a connector such as FPC or TCP is attached to the substrate of the touch sensor panel, or a IC in which the IC is mounted by the COG method etc. It may be called a module, a sensor module, or simply a touch sensor or the like.

  Note that in this specification and the like, a touch panel which is one mode of a display device has a function of displaying (outputting) an image or the like on a display surface and a detected object such as a finger or a stylus touches, presses, or approaches the display surface. And a function as a touch sensor that detects an object. Therefore, the touch panel is an aspect of the input / output device.

  The touch panel can also be called, for example, a display panel with a touch sensor (or a display device) or a display panel with a touch sensor function (or a display device).

  The touch panel can also be configured to have a display panel and a touch sensor panel. Alternatively, the inside or the surface of the display panel may have a function as a touch sensor.

  Further, in the present specification and the like, a touch panel with a connector such as FPC or TCP attached thereto, or a substrate with an IC mounted by a COG method, etc., is a touch panel module, a display module or simply a touch panel. It may be called etc.

In this example, the resistivity and the transmittance of the aluminum nitride film according to one embodiment of the present invention were evaluated. Samples A1 to A6 were produced in this example. In addition, sample A0 which is an elementary glass was prepared for comparison in the transmittance | permeability evaluation of an aluminum nitride film.

<Method of Producing Samples A1 to A6>
Hereinafter, methods for manufacturing the samples A1 to A6 will be described.

Samples A1 to A6 have a structure in which an aluminum nitride film having a thickness of 20 nm is formed on a glass substrate. The aluminum nitride film was formed by sputtering using an Al target under the conditions of a pressure in the chamber of 0.6 Pa, an applied voltage of 5 kW, and a substrate temperature of 70.degree. Each of the samples A1 to A6 has different ratios of gas flow rates supplied during formation. Specifically, the ratio of the N ₂ flow rate to the total of the Ar flow rate and the N ₂ flow rate is 0% for sample A1, 20% for sample A2, 40% for sample A3, 60% for sample A4, and 80% for sample A5 Sample A6 was 100%. Note that, in the sample A1, the film to be formed is an aluminum film because N ₂ is not contained in the film formation gas.

Resistivity
Next, the resistivity of the samples A1 to A6 was measured. As a resistivity measuring instrument, one having a measurement upper limit of 15 Ω · cm was used. The resistivity of each of the samples A1 to A6 is shown in FIG. The resistivity of the sample A1 was 8.2 × 10 ⁻⁶ Ω · cm, and the resistivity of the sample A2 was 4.1 × 10 ⁻² Ω · cm. Further, it was found that the resistivity of each of the samples A3 to A6 was equal to or higher than the upper limit of measurement.

<Transmittance>
Next, the transmittances of the samples A1 to A6 were measured. The transmittances of the samples A1 to A6 are shown in FIG. FIG. 21B also shows the transmittance of the sample A0 for comparison. In FIG. 21B, the horizontal axis indicates the wavelength [nm] and the vertical axis indicates the transmittance [%]. As shown in FIG. 21B, the transmittance of the samples A3 to A6 was 80% or more at a wavelength of 400 nm or more.

Note that the structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments or the other embodiments.

In this example, the chemical bonding state was evaluated when an aluminum nitride film was formed on a metal oxide. For the evaluation, Sample B1 in which an aluminum nitride film was stacked on a metal oxide was used. The state of chemical bonding was analyzed using X-ray photoelectron spectroscopy (XPS).

First, the method for producing the sample B1 will be described. A 40 nm-thick metal oxide was formed on a glass substrate by a sputtering method using a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio]. Next, the formed metal oxide is heat-treated at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere, and continuously subjected to a heat treatment at a temperature of 400 ° C. for 1 hour in a mixed atmosphere of oxygen and nitrogen. The Next, on a metal oxide, using a target of Al by sputtering, the ratio of the N ₂ flow rate to the sum of the Ar flow rate and the N ₂ flow rate is adjusted to be 40%, and an aluminum nitride film thickness of 20 nm A film was formed. After forming aluminum nitride, heat treatment was performed at a temperature of 350 ° C. for 1 hour in a nitrogen atmosphere. Sample B1 was produced by the above.

Next, measurement using X-ray photoelectron spectroscopy (XPS) of sample B1 (hereinafter referred to as XPS measurement) was performed. Note that by performing the XPS measurement while etching the sample B1 (specifically, alternately performing the ion sputtering and the XPS measurement), analysis in the depth direction of the sample B1 is possible. In this embodiment, in the depth direction of the sample B1, the depth D1 is near the center of the aluminum nitride film, the depth D2 near the interface between the aluminum nitride film and the metal oxide, and the depth D3 near the center of the metal oxide. I assume.

For XPS measurement, VersaProbe manufactured by ULVAC-PHI was used. Mg K α (1253.6 eV) was used as an X-ray source. The detection area was 8 mm square or less. The extraction angle was 45 °. The detection depth is considered to be about 4 nm to 5 nm.

XPS measurement was performed in an energy range in which a peak was obtained for each element of In, Ga, Zn, Al, and N. The results obtained by the XPS measurement are shown in FIG. 22 and FIG. In FIG. 22 and FIG. 23, the horizontal axis indicates binding energy (eV), and the vertical axis indicates photoelectron intensity (arbitrary unit).

22A shows the spectrum of In3d5 / 2, FIG. 22B shows the spectrum of Ga3d, FIG. 22C shows the spectrum of Zn3p, FIG. 23A shows the spectrum of Al2p, and FIG. 23B shows the N1s It is a spectrum. In each of FIGS. 22A to 22C and FIGS. 23B and 23C, a spectrum at depth D1, a spectrum at depth D2, and a spectrum at depth D3 are shown sequentially from the top. Furthermore, the intensity of photoelectrons in each spectrum is shown in arbitrary units in order to make the spectral shape more visible.

As shown in FIG. 22A, in the depth D2, in addition to a signal indicating the presence of In in the oxidized state (a peak located on a broken line indicated by In ₂ O ₃ ), In in the metal state is present A signal (peak located on a broken line indicated by In) indicating that the reaction was performed was observed. On the other hand, as shown in FIGS. 22 (B) and 22 (C), at depth D2, a signal indicating the presence of Ga in the metal state and a signal indicating the presence of Zn in the metal state are not detected. The Therefore, it was suggested that oxygen was insufficient near the interface between the metal oxide and the aluminum nitride film, and In in the metallic state was precipitated.

Note that the structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments or the other embodiments.

In this embodiment, when a silicon oxynitride film or a silicon nitride film is formed on a metal oxide, the sheet resistance of the metal oxide, the spin density in the metal oxide, the metal oxide and the silicon oxynitride film, or The composition state of the interface of the silicon nitride film was evaluated. In addition, evaluation of spin density was performed by electron spin resonance (ESR: Electron Spin Resonance) analysis, and evaluation of the composition state was performed by XPS analysis.

First, the method for manufacturing the sample C1 and the sample C2 used for measuring the sheet resistance of the metal oxide and the spin density in the metal oxide will be described. In sample C1, a metal oxide having a film thickness of 100 nm was formed on a quartz substrate by sputtering using a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio]. Next, a 300 nm thick silicon oxynitride film was formed over the metal oxide by a CVD method using SiH ₄ and N ₂ O as a deposition gas. After the silicon oxynitride film was formed, heat treatment was performed at 350 ° C. for one hour in an atmosphere containing nitrogen and oxygen. In sample C2, a metal oxide having a film thickness of 100 nm was formed on a quartz substrate by sputtering using a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio]. Next, a silicon nitride film was formed to a thickness of 100 nm over the metal oxide by a CVD method using SiH ₄ , N ₂ , and NH ₃ as a deposition gas. After forming the silicon nitride film, heat treatment was performed at 350 ° C. for one hour in an atmosphere containing nitrogen and oxygen.

<Sheet resistance>
The sheet resistances of the metal oxides in the samples C1 and C2 prepared as described above were measured. As the sheet resistance measuring instrument, one having a measurement upper limit of 1.0E + 07 Ω was used. The sheet resistances of sample C1 and sample C2 are shown in FIG.

In FIG. 24, in the sample C1 in which the silicon oxynitride film was formed on the metal oxide, the sheet resistance of the metal oxide was 1.0E + 07 Ω or more, which is the measurement upper limit of the sheet resistance measuring device. On the other hand, in the sample C2 in which the silicon nitride film was formed on the metal oxide, the sheet resistance of the metal oxide was lower than that of the sample C1, and was 3.5E + 02Ω.

<Spin density>
Next, the spin density in the metal oxide was measured in sample C1 and sample C2. Evaluation of spin density was performed by ESR analysis. In the measurement of each sample, the measurement temperature was room temperature, the high frequency power of 8.9 GHz (microwave power) was 20 mW, and the direction of the magnetic field was parallel to the film surface of the manufactured sample. Note that when the oxide semiconductor has hydrogen taken into an oxygen vacancy, a signal having symmetry appears in the vicinity of a g value of 1.93 in ESR measurement. Therefore, the higher the spin density (hereinafter referred to as the spin density (g value = 1.93)) calculated from the signal that appears near the g value of 1.93, the larger the amount of hydrogen taken into the oxygen vacancies It can be said. The calculation lower limit of the spin density (g value = 1.93) was 3.7E + 16 spins / cm ³ . The spin densities of sample C1 and sample C2 are shown in FIG.

In FIG. 25, in the sample C1 in which the silicon oxynitride film was formed on the metal oxide, the spin density in the metal oxide was 1.60E + 17 spins / cm ³ . On the other hand, in the sample C2 in which the silicon nitride film was formed on the metal oxide, the spin density in the metal oxide was higher than the sample C1, and was 1.09E + 19 spins / cm ³ . This indicates that sample C2 has a larger amount of hydrogen incorporated into the oxygen vacancy.

<Composition state>
Next, a method for manufacturing Sample C3 and Sample C4 used for evaluating the composition state of the interface between the metal oxide and the silicon oxynitride film or the silicon nitride film will be described. The sample C3 was formed using a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio] on a metal oxide formed by sputtering by a CVD method using SiH ₄ as a deposition gas. And N ₂ O are used to form a silicon oxynitride film with a thickness of 100 nm. The sample C 4 was formed using a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio] on a metal oxide formed by a sputtering method, using SiH ₄ as a deposition gas by a CVD method. , in which _{N 2,} and a silicon nitride film using NH ₃ to 100nm formed.

The composition state of the interface between the metal oxide and the silicon oxynitride film or the silicon nitride film in the samples C3 and C4 manufactured as described above was evaluated. XPS analysis was used to evaluate the composition state. An evaluation result is shown in FIG.

As shown in FIG. 26A, in Sample C3, precipitation of metallic indium (In) is not observed at the interface between the metal oxide and the silicon oxynitride film and in the vicinity thereof, but is shown in FIG. 26B. Thus, in sample C4, precipitation of metallic indium and silicon oxide (SiOx) were confirmed at the interface between the metal oxide and the silicon nitride film and in the vicinity thereof. This is because, in the sample C4, oxygen is transferred between the metal oxide and the silicon nitride film, oxygen is released from indium which is most likely to cause oxygen deficiency in the metal oxide, and part of the silicon nitride film is It is thought that it is because it has oxidized. It is considered that the delivery of oxygen as described above and the deposition of metallic indium lower the resistance of the metal oxide.

Note that the structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments or the other embodiments.

Reference Signs List 100 transistor, 100A transistor, 102 substrate, 104 insulating layer, 106 conductive layer, 106C conductive layer, 108 semiconductor layer, 108C metal oxide layer, 108f metal oxide film, 108i region, 108n region, 109 conductive layer, 110 insulating layer , 110f insulating film, 112 conductive layer, 112f conductive film, 114 metal oxide layer, 114f metal oxide film, 115 region, 116 layer, 118 insulating layer, 119 insulating layer, 120a conductive layer, 120b conductive layer, 130A capacitance element , 130 B capacitive element, 130 C capacitive element, 141 a opening, 141 b opening, 141 c opening, 142 opening, 150 area

Claims (10)

A semiconductor device having a metal oxide layer,
The metal oxide layer has a first metal element and a second metal element,
The metal oxide layer has a first region and a second region,
An insulating layer on the first region;
A conductor on the insulating layer,
The insulating layer, the conductor, and a first layer provided to cover the second region;
A third region is provided in the vicinity of the interface between the second region and the first layer,
The semiconductor device according to claim 1, wherein a concentration of the first metal element in the third region is larger than a concentration of the metal element in the second region. In claim 1,
The first metal element is In,
The semiconductor device according to claim 1, wherein the second metal element is one or more selected from Ga, Sn, and Zn. A semiconductor device having a metal oxide layer,
The metal oxide layer includes a first metal element, a second metal element, and a third metal element.
The metal oxide layer has a first region and a second region,
An insulating layer on the first region;
A conductor on the insulating layer,
The insulating layer, the conductor, and a first layer provided to cover the second region;
A third region is provided in the vicinity of the interface between the second region and the first layer,
The semiconductor device according to claim 1, wherein a concentration of the first metal element in the third region is larger than a concentration of the metal element in the second region. In claim 3,
The first metal element is In,
The second metal element is Ga,
The semiconductor device characterized in that the third metal element is Zn. In claim 4,
A semiconductor device characterized in that the atomic ratio of In is larger than the atomic ratio of Ga; In any one of claims 1 to 5,
The semiconductor device according to claim 1, wherein the first layer comprises aluminum. In any one of claims 1 to 6,
The semiconductor device according to claim 1, wherein the first layer comprises aluminum nitride. In any one of claims 1 to 7,
A semiconductor device characterized in that the second region has a lower resistance than the first region. In any one of claims 1 to 8,
The said metal oxide layer has crystallinity, The semiconductor device characterized by the above-mentioned. In any one of claims 1 to 8,
The metal oxide layer has a crystal part,
The semiconductor device according to claim 1, wherein the crystal part has c-axis alignment.

Images