CN117855305A - Silicon-based thin film back contact solar cell, manufacturing method thereof and battery module - Google Patents
Silicon-based thin film back contact solar cell, manufacturing method thereof and battery module Download PDFInfo
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- CN117855305A CN117855305A CN202410257512.XA CN202410257512A CN117855305A CN 117855305 A CN117855305 A CN 117855305A CN 202410257512 A CN202410257512 A CN 202410257512A CN 117855305 A CN117855305 A CN 117855305A
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Abstract
The invention belongs to the technical field of back contact solar cells, and particularly relates to a silicon-based film back contact solar cell, a manufacturing method thereof and a cell module, which comprises a substrate, wherein an anti-reflection layer, a back passivation layer, a silicon film absorption layer, a semiconductor distribution layer and a metal electrode are sequentially arranged on the back of the substrate, the semiconductor distribution layer comprises a first semiconductor layer and a second semiconductor layer which are alternately arranged, the metal electrode is arranged on the outer surfaces of part of the first semiconductor layer and part of the second semiconductor layer, the silicon film absorption layer is an intrinsic monocrystalline silicon or doped polycrystalline silicon layer, and the thickness of the silicon film absorption layer is 400-8000nm; the ratio of the thicknesses of the first semiconductor layer, the second semiconductor layer and the silicon thin film absorption layer is 0.15-30:0.15-30:100. the silicon-based thin film back contact solar cell provided by the invention has the advantages that the process flow is simple, the cell conversion efficiency is high, and the production yield is high.
Description
Technical Field
The invention belongs to the technical field of back contact solar cells, and particularly relates to a silicon-based thin film back contact solar cell, a manufacturing method thereof and a battery module.
Background
At present, a silicon substrate back contact solar cell needs to use a silicon wafer as a substrate, a passivation layer and an anti-reflection layer are formed on the front surface of the silicon wafer, and an alternating P-type semiconductor layer, an alternating N-type semiconductor layer and a metal electrode are formed on the back surface of the silicon wafer. And the method for manufacturing the silicon substrate back contact solar cell into a module comprises the following steps: providing a back plate, sequentially laminating a back adhesive film, a welding strip, a silicon substrate battery, a front adhesive film and a front plate above the back plate, and then forming a module after lamination, namely, respectively laying the adhesive film, the front plate and the back plate on the front and back surfaces of the battery.
In addition, although there are also silicon thin film batteries in the prior art, the silicon thin film battery structure is generally: the transparent conductive film (first electrode), the first semiconductor layer, the silicon film absorption layer, the second semiconductor layer, the metal electrode or the transparent conductive film (second electrode) is arranged on the back surface of the glass substrate in sequence, and the transparent conductive film needs to be used as an electrode and is required to be kept at a large thickness, so that the absorption of incident light of the battery is reduced, the formation of electron hole pairs is reduced, and the battery conversion efficiency is reduced.
It should be noted that this section of the disclosure only provides a background related to the present disclosure, and does not necessarily constitute prior art or known technology.
Disclosure of Invention
The invention aims to overcome the defects of complex process and low battery conversion efficiency of a silicon substrate back contact solar battery in the prior art, and provides a silicon-based thin film back contact solar battery, a manufacturing method thereof and a battery module.
In order to achieve the above object, in a first aspect, the present invention provides a silicon-based thin film back contact solar cell, including a substrate, an anti-reflection layer, a back passivation layer, a silicon thin film absorption layer, a semiconductor distribution layer, and a metal electrode sequentially disposed on the back of the substrate, where the semiconductor distribution layer includes a first semiconductor layer and a second semiconductor layer that are alternately arranged, the metal electrode is disposed on the outer surfaces of a part of the first semiconductor layer and a part of the second semiconductor layer, and the silicon thin film absorption layer is an intrinsic monocrystalline silicon or doped polycrystalline silicon layer, and the thickness of the silicon thin film absorption layer is 400-8000nm; the ratio of the thicknesses of the first semiconductor layer, the second semiconductor layer and the silicon thin film absorption layer is 0.15-30:0.15-30:100.
in some preferred embodiments of the present invention, the silicon thin film absorber layer is a doped polysilicon layer having an effective doping concentration of less than 1e17cm -3 。
In some preferred embodiments of the present invention, the doped polysilicon layer is N-type or P-type.
In some preferred embodiments of the present invention, the ratio of the thickness of the silicon thin film absorption layer to the thickness of the anti-reflection layer and the thickness of the back passivation layer is 100:4-200:0.05-2.
In some preferred embodiments of the invention, the thickness of the anti-reflection layer is 40-150nm.
In some preferred embodiments of the invention, the backside passivation layer has a thickness of 1-20nm.
In some preferred embodiments of the present invention, the anti-reflection layer is at least one of silicon nitride, silicon oxynitride, and silicon oxide.
In some preferred embodiments of the present invention, the back passivation layer is at least one of silicon oxide, aluminum oxide, polysilicon.
In some preferred embodiments of the invention, the substrate has a light transmittance of 90% or more and a softening point of greater than 900 ℃.
In some preferred embodiments of the present invention, the substrate is at least one of a hard material and a flexible material. Further preferably, the substrate is at least one of quartz glass, borosilicate glass, and sodium-potassium glass.
In some preferred embodiments of the invention, the thickness of the substrate is in the range of 1-5mm.
In some preferred embodiments of the present invention, the first semiconductor layer includes a passivation structure selected from the group consisting of a first intrinsic amorphous layer and a first doped crystalline silicon layer, or a passivation structure selected from the group consisting of a first tunneling oxide layer and a first doped polysilicon layer.
In some preferred embodiments of the present invention, the second semiconductor layer includes a passivation structure selected from the group consisting of a second intrinsic amorphous layer and a second doped crystalline silicon layer, or a passivation structure selected from the group consisting of a second tunneling oxide layer and a second doped polysilicon layer.
In some preferred embodiments of the present invention, the thickness of the first and second intrinsic amorphous layers is each independently 5-15nm.
In some preferred embodiments of the present invention, the first doped crystalline silicon layer has a thickness of 8-16nm and an effective doping concentration of 1e19cm -3 -5e20cm -3 。
In some preferred embodiments of the present invention, the second doped crystalline silicon layer has a thickness of 8-20nm and an effective doping concentration of 1e19cm -3 -5e20cm -3 。
In some preferred embodiments of the present invention, the thickness of the first tunneling oxide layer and the second tunneling oxide layer is 1-2nm, respectively.
In some preferred embodiments of the present invention, the first doped polysilicon layer and the second doped polysilicon layer each independently have a thickness of 30-120nm and an effective doping concentration of 1e19cm -3 -5e20cm -3 。
In some preferred embodiments of the present invention, the first semiconductor layer includes a passivation structure selected from the group consisting of a first tunneling oxide layer and a first doped polysilicon layer, and the second semiconductor layer includes a passivation structure selected from the group consisting of a second intrinsic amorphous layer and a second doped crystalline silicon layer.
In the combined passivation structure, it is further preferable that the ratio of the thicknesses of the first tunneling oxide layer, the second intrinsic amorphous layer and the silicon thin film absorption layer is 0.0125-0.75:0.0625-3.75:100.
in some preferred embodiments of the present invention, two ends of the second semiconductor layer extend outwards to cover part of the back surface of the adjacent first semiconductor layer, and a first semiconductor opening area which does not cover the second semiconductor layer is reserved on the back surface of the first semiconductor layer, a second semiconductor opening area is formed between the adjacent first semiconductor layers, a region between the second semiconductor opening area and the first semiconductor opening area is a spacing area, the width W1 of the second semiconductor opening area is 0.3-0.8mm, and the sum W2 of the widths of the first semiconductor layer adjacent to one side of the second semiconductor opening area is 0.8-2mm, preferably 0.8-1.5mm.
In some preferred embodiments of the present invention, the second semiconductor layer includes a passivation structure selected from a second intrinsic amorphous layer and a second doped crystalline silicon layer, and the semiconductor distribution layer further includes a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and a portion of the conductive film layer located in the spacer is provided with an isolation trench; the metal electrode is arranged on the outer surfaces of the second semiconductor opening area and the first semiconductor opening area, which correspond to the conductive film layers respectively.
In some other preferred embodiments of the present invention, the second semiconductor layer includes a passivation structure selected from the group consisting of a second tunneling oxide layer and a second doped polysilicon layer, the semiconductor distribution layer further includes passivation film layers laid on outer surfaces of the first semiconductor layer and the second semiconductor layer, and the metal electrode is disposed on outer surfaces of the second semiconductor opening region and the respective corresponding passivation film layers of the first semiconductor opening region.
In a second aspect, the present invention provides a method for manufacturing a silicon-based thin film back contact solar cell, which is used for manufacturing the silicon-based thin film back contact solar cell in the first aspect.
The manufacturing method of the silicon-based thin film back contact solar cell comprises the following steps: and sequentially depositing an antireflection layer, a back passivation layer, a silicon film absorption layer, a semiconductor distribution layer and a metal electrode on the back of the substrate.
In some preferred embodiments of the present invention, the deposition process of the semiconductor distribution layer, the metal electrode, comprises:
depositing a first semiconductor layer on the back of the silicon film absorption layer;
etching part of the first semiconductor layer in a first preset area on the back surface to form a second semiconductor opening area;
depositing a second semiconductor layer on the back surface;
etching part of the second semiconductor layer in a second preset area on the back surface to form a first semiconductor opening area;
depositing a conductive film layer or a passivation film layer on the back surface, and forming an isolation groove on the conductive film layer after depositing the conductive film layer;
and then forming metal electrodes outside the corresponding back surfaces of the first semiconductor opening area and the second semiconductor opening area respectively.
In a third aspect, the present invention provides a battery module, which includes the silicon-based thin film back contact solar cell of the first aspect, and a solder strip, a glue film and a back plate sequentially disposed on the back surface of a substrate in the silicon-based thin film back contact solar cell.
The beneficial effects are that:
according to the technical scheme, particularly, the anti-reflection layer, the back passivation layer, the silicon film absorption layer, the semiconductor distribution layer and the metal electrode are directly formed on the back of the substrate, a silicon wafer is not required, all the film layers are arranged on a single surface of the substrate, double-sided deposition is not required, the process flow is simpler, the production yield of the battery is improved, good battery conversion efficiency is considered, and meanwhile, the material cost can be greatly reduced when the battery module is manufactured; and the front surface of the substrate is not required to be plated with a transparent conductive film (the conductive film is equivalent to a front electrode), so that the light absorption of the transparent conductive film can be reduced, and the battery conversion efficiency can be improved by matching the structures of the layers. The silicon-based thin film back contact solar cell can keep higher cell conversion efficiency while the process flow is concise.
Compared with the prior art that the silicon thin film absorption layer is made of amorphous silicon material, the silicon thin film absorption layer is smaller in forbidden bandwidth, can utilize longer-wavelength light, is better in conductivity, can improve the current of a battery and reduce the internal resistance of the battery, is more suitable for preparing a back contact battery, is matched with a back contact structure, and further reduces parasitic absorption, so that the battery conversion efficiency is higher than that of the silicon thin film battery in the prior art. And moreover, the silicon film absorption layer with proper thickness is adopted, so that the conversion efficiency and the manufacturing cost of the battery can be balanced, and the production yield of the battery can be improved.
When the silicon-based film back contact solar cell is used for manufacturing a cell module, only a single-layer adhesive film and a back plate are needed, so that the material cost can be greatly reduced. In addition, the front plate of the current battery module has a size of about 1.1 m×2.4 m, and the silicon wafer has a size of typically 0.2 m×0.2 m, and 60-70 silicon wafers are typically required to be packaged into a module when the silicon substrate battery is packaged into a module. Compared with the silicon wafer, the silicon-based thin film back contact solar cell provided by the invention has the advantages that the size of the adopted substrate (such as glass and the like) can be larger and the strength is higher, for example, the size of the substrate can be about 1.1 m multiplied by 2.4 m, and the cell can be directly formed on the surface of the substrate with the same size as that of the cell module, so that the productivity can be greatly improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of one embodiment of a prior art silicon substrate back contact heterojunction solar cell;
fig. 2 is a schematic view illustrating the structure of the battery module of fig. 1.
FIG. 3 is a process flow diagram of one embodiment of a method for fabricating a silicon-based thin film back contact solar cell according to the present invention.
Fig. 4 is a schematic structural diagram of a glass substrate according to embodiment 1 of the present invention;
FIG. 5 is a schematic diagram of a structure in which an anti-reflection layer, a back passivation layer, a silicon thin film absorption layer, and a first semiconductor layer are sequentially deposited on the back surface of a glass substrate in embodiment 1;
FIG. 6 is a schematic diagram of a structure of a portion of a first semiconductor layer etched away according to embodiment 1 of the present invention;
FIG. 7 is a schematic diagram of a structure of depositing a second semiconductor layer according to embodiment 1 of the present invention;
FIG. 8 is a schematic diagram of a structure of a portion of a second semiconductor layer etched away from a surface of a first semiconductor layer according to embodiment 1 of the present invention;
FIG. 9 is a schematic diagram of a deposited conductive film layer according to embodiment 1 of the present invention;
fig. 10 is a schematic diagram of a structure of a first semiconductor layer and a second semiconductor layer of a deposited conductive film layer according to embodiment 1 of the present invention.
FIG. 11 is a schematic structural view of a silicon-based thin film back contact solar cell according to an embodiment of the present invention.
Fig. 12 is a schematic structural diagram of a silicon-based thin film back contact solar cell fabricated into a cell module according to embodiment 1 of the present invention.
Description of the reference numerals
1. The device comprises a glass substrate, 2, an antireflection layer, 3, a back passivation layer, 4, a silicon film absorption layer, 5, a first semiconductor layer, 6, a second semiconductor layer, 7, a conductive film layer, 8 and a metal electrode; 100. 200 parts of silicon-based film back contact solar cell, 300 parts of welding strip, 300 parts of adhesive film, 400 parts of back plate.
500. The silicon substrate back contact heterojunction solar cell, 51, silicon wafer, 52, first semiconductor layer, 53, second mask layer, 54, front amorphous layer, 55, a front anti-reflection layer 56, a second semiconductor layer 57, a silver paste thin grid line electrode 58, insulating ink 59 and a silver paste main grid; 600. front plate, 700, front glued membrane layer.
Detailed Description
In the present disclosure, the terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying a number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
The endpoints and any values of the ranges disclosed herein are not limited to the precise range or value, and are understood to encompass values approaching those ranges or values. For numerical ranges, one or more new numerical ranges may be found between the endpoints of each range, between the endpoint of each range and the individual point value, and between the individual point value, in combination with each other, and are to be considered as specifically disclosed herein. Wherein the terms "optional" and "optionally" mean either comprising or not comprising (or may not be present).
The front surface is also referred to as a light receiving surface in the present invention, and the back surface is the back surface of the light receiving surface.
The invention provides a silicon-based thin film back contact solar cell, which comprises a substrate, wherein an anti-reflection layer, a back passivation layer, a silicon thin film absorption layer, a semiconductor distribution layer and a metal electrode are sequentially arranged on the back of the substrate, the semiconductor distribution layer comprises a first semiconductor layer and a second semiconductor layer which are alternately arranged, the metal electrode is arranged on the outer surfaces of part of the first semiconductor layer and part of the second semiconductor layer, the silicon thin film absorption layer is an intrinsic monocrystalline silicon or N-type doped polycrystalline silicon layer, and the thickness of the silicon thin film absorption layer is 400-8000nm; the ratio of the thicknesses of the first semiconductor layer, the second semiconductor layer and the silicon thin film absorption layer is 0.15-30:0.15-30:100. preferably 6-30:1-30: 100. more preferably 13-30:2-30:100.
in some preferred embodiments of the present invention, the silicon thin film absorber layer is a doped polysilicon layer having an effective doping concentration of less than 1e17cm -3 . The adoption of the silicon film absorption layer with proper doping concentration can reduce electron hole pair recombination, ensure passivation effect and improve current at the same time, thereby further improving battery conversion efficiency.
In some preferred embodiments of the present invention, the doped polysilicon layer is N-type or P-type, more preferably N-type. The N-type doped polysilicon layer is simpler and more convenient to manufacture and has higher reliability. The doped polysilicon layer may have the same or different conductivity polarity as the first semiconductor layer.
In some preferred embodiments of the present invention, the ratio of the thickness of the silicon thin film absorption layer to the thickness of the anti-reflection layer and the thickness of the back passivation layer is 100:4-200:0.05-2, preferably 100:10-200:0.5-2. The three-layer structure of the specific silicon film absorption layer, the antireflection layer and the back passivation layer with proper thickness ratio is adopted, so that the reflection of light can be reduced, parasitic absorption is reduced, and the current density and the conversion efficiency of the battery are improved.
In some preferred embodiments of the invention, the thickness of the anti-reflection layer is 40-150nm, preferably 50-150nm.
In some preferred embodiments of the invention, the thickness of the backside passivation layer is 1-20nm, preferably 5-20nm.
In some preferred embodiments of the present invention, the anti-reflection layer is at least one of silicon nitride, silicon oxynitride, and silicon oxide. Of these, silicon oxide is preferably silicon dioxide.
In some preferred embodiments of the present invention, the back passivation layer is at least one of silicon oxide, aluminum oxide, polysilicon. Of these, silicon oxide is preferably silicon dioxide.
In some preferred embodiments of the invention, the substrate has a light transmittance of 90% or more and a softening point of greater than 900 ℃.
The substrate of the present invention may be made of at least one of a hard material and a flexible material as long as it satisfies the high temperature resistance and transmittance in the above range indicated by the above softening point range. Further preferably, the substrate is glass. The glass may be, for example, quartz glass, borosilicate glass, sodium-potassium glass, or the like.
In some preferred embodiments of the invention, the thickness of the substrate is in the range of 1-5mm.
The shape of the substrate can be selected according to actual requirements.
In the present invention, the polarities of the first semiconductor layer and the second semiconductor layer are opposite.
In some preferred embodiments of the present invention, the first semiconductor layer includes a passivation structure selected from the group consisting of a first intrinsic amorphous layer and a first doped crystalline silicon layer, or a passivation structure selected from the group consisting of a first tunneling oxide layer and a first doped polysilicon layer.
In some preferred embodiments of the present invention, the second semiconductor layer includes a passivation structure selected from the group consisting of a second intrinsic amorphous layer and a second doped crystalline silicon layer, or a passivation structure selected from the group consisting of a second tunneling oxide layer and a second doped polysilicon layer.
Wherein, the first doped crystalline silicon layer or the first doped polycrystalline silicon layer and the second doped crystalline silicon layer or the second doped polycrystalline silicon layer are respectively N-type and P-type. The first doped crystalline silicon layer and the second doped crystalline silicon layer may each independently be a respective doped layer that is amorphous or microcrystalline.
In some preferred embodiments of the present invention, the thickness of the first and second intrinsic amorphous layers is each independently 5-15nm.
In some preferred embodiments of the present invention, the first doped crystalline silicon layer has a thickness of 8-16nm and an effective doping concentration of 1e19cm -3 -5e20cm -3 。
In some preferred embodiments of the present invention, the second doped crystalline silicon layer has a thickness of 8-20nm and an effective doping concentration of 1e19cm -3 -5e20cm -3 。
In some preferred embodiments of the present invention, the thickness of the first tunneling oxide layer and the second tunneling oxide layer is each independently 1-3nm, preferably 1-2nm.
In some preferred embodiments of the present invention, the first doped polysilicon layer and the second doped polysilicon layer each independently have a thickness of 30-120nm and an effective doping concentration of 1e19cm -3 -5e20cm -3 。
In some preferred embodiments of the present invention, the first semiconductor layer includes a passivation structure selected from the group consisting of a first tunneling oxide layer and a first doped polysilicon layer, and the second semiconductor layer includes a passivation structure selected from the group consisting of a second intrinsic amorphous layer and a second doped crystalline silicon layer. The semiconductor distribution layer with the combined passivation structure is matched with the silicon film absorption layer, the antireflection layer and the back passivation layer, so that a preparation process window of a rear graphical opening (namely slotting or etching) can be improved, and the production yield of the battery can be improved.
In the combined passivation structure, it is further preferable that the ratio of the thicknesses of the first tunneling oxide layer, the second intrinsic amorphous layer and the silicon thin film absorption layer is 0.0125-0.75:0.0625-3.75:100. preferably 0.075-0.35:0.35-1.5:100, more preferably 0.075-0.25:0.35-1.2:100. In the combined passivation structure, the specific layer structures with proper preferable thickness ratio are adopted, so that the series resistance can be reduced while the good passivation effect is maintained, the filling factor of the battery is facilitated, and the conversion efficiency of the battery is further improved.
In some preferred embodiments of the present invention, two ends of the second semiconductor layer extend outwards to cover part of the back surface of the adjacent first semiconductor layer, and a first semiconductor opening area which does not cover the second semiconductor layer is reserved on the back surface of the first semiconductor layer, a second semiconductor opening area is formed between the adjacent first semiconductor layers, and a region between the second semiconductor opening area and the first semiconductor opening area is a spacer.
A mask layer may or may not be provided between the first semiconductor layer and the second semiconductor layer within the spacer, and may be selected by those skilled in the art according to actual requirements.
Further preferably, the width W1 of the second semiconductor opening region is 0.3-0.8mm, and the sum W2 of the widths of the first semiconductor layers of the second semiconductor opening region adjacent to one side thereof is 0.8-2mm, preferably 0.8-1.5mm. W2 is also the etching period of the second semiconductor opening region. By adopting a proper etching period, the battery production process window and the battery conversion efficiency can be well balanced, and the production yield can be improved.
Further preferably, the width W3 of the first semiconductor opening region is 0.3 to 0.8mm.
In some preferred embodiments of the present invention, the second semiconductor layer includes a passivation structure selected from a second intrinsic amorphous layer and a second doped crystalline silicon layer, and the semiconductor distribution layer further includes a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and a portion of the conductive film layer located in the spacer is provided with an isolation trench; the metal electrode is arranged on the outer surfaces of the second semiconductor opening area and the first semiconductor opening area, which correspond to the conductive film layers respectively.
The material of the conductive film layer can be selected by those skilled in the art according to actual requirements, for example, an indium oxide-based film doped with tin, zinc, tungsten or titanium, or a zinc oxide-based film doped with aluminum, boron or gallium.
Further preferably, the thickness of the conductive film layer may be, for example, 40 to 80nm.
Further preferably, the width W4 of the isolation groove is 30-150 μm.
In some preferred embodiments of the present invention, the second semiconductor layer includes a passivation structure selected from the group consisting of a second tunneling oxide layer and a second doped polysilicon layer, the semiconductor distribution layer further includes passivation film layers laid on outer surfaces of the first semiconductor layer and the second semiconductor layer, and the metal electrode is disposed on outer surfaces of the second semiconductor opening region and the respective corresponding passivation film layers of the first semiconductor opening region.
In a second aspect, the present invention provides a method for manufacturing a silicon-based thin film back contact solar cell, which is used for manufacturing the silicon-based thin film back contact solar cell in the first aspect.
The manufacturing method of the silicon-based thin film back contact solar cell comprises the following steps: and sequentially depositing an antireflection layer, a back passivation layer, a silicon film absorption layer, a semiconductor distribution layer and a metal electrode on the back of the substrate. The structure and composition of the anti-reflection layer, the back passivation layer, the silicon thin film absorption layer, the semiconductor distribution layer and the metal electrode are respectively the same as those of the layers in the first aspect, and are not described herein again.
The semiconductor distribution layer comprises a first semiconductor layer and a second semiconductor layer. In some preferred embodiments of the present invention, the deposition process of the semiconductor distribution layer, the metal electrode, comprises:
depositing a first semiconductor layer on the back of the silicon film absorption layer;
etching part of the first semiconductor layer in a first preset area on the back surface to form a second semiconductor opening area;
depositing a second semiconductor layer on the back surface;
etching part of the second semiconductor layer in a second preset area on the back surface to form a first semiconductor opening area;
depositing a conductive film layer or a passivation film layer on the back surface, and forming an isolation groove on the conductive film layer after depositing the conductive film layer;
and then forming metal electrodes outside the corresponding back surfaces of the first semiconductor opening area and the second semiconductor opening area respectively.
The first semiconductor layer of the anti-reflection layer, the back passivation layer, the silicon thin film absorption layer and the semiconductor distribution layer can be formed by using a Chemical Vapor Deposition (CVD) process, low Pressure CVD (LPCVD), normal pressure CVD (APCVD), plasma Enhanced CVD (PECVD), thermal growth, sputtering and any other existing techniques, so long as a target layer with required parameters can be obtained, and a preparation method of each layer can be selected according to requirements by a person skilled in the art. The second semiconductor layer may be formed using a Chemical Vapor Deposition (CVD) process, low Pressure CVD (LPCVD), atmospheric Pressure CVD (APCVD), plasma Enhanced CVD (PECVD), thermal growth, sputtering, and any other existing techniques. The corresponding doped layers in the first semiconductor layer and the second semiconductor layer can be formed by depositing an intrinsic crystal silicon layer, printing doping slurry, and then laser etching doping.
The etching of the first semiconductor opening region and the second semiconductor opening region may be formed using laser etching, mask etching, chemical etching, and other prior art techniques, preferably using laser etching.
The deposition of the passivation film layer may be formed using a Chemical Vapor Deposition (CVD) process, low Pressure CVD (LPCVD), atmospheric Pressure CVD (APCVD), plasma Enhanced CVD (PECVD), thermal growth, sputtering, and any other existing techniques, so long as a desired target layer is obtained.
The conductive film layer may be formed by a Physical Vapor Deposition (PVD) process, an activated plasma deposition (RPD) process, an electron beam evaporation (E-gun) process, a Chemical Vapor Deposition (CVD) process, and any other prior art technique.
The isolation groove can be formed by etching modes such as laser, mask etching, chemical etching and the like.
The metal electrode may be formed by printing, ink jet printing, electroplating, or any other prior art technique.
In a third aspect, the present invention provides a battery module, which includes the silicon-based thin film back contact solar cell of the first aspect, and a solder strip, a glue film and a back plate sequentially disposed on the back surface of a substrate in the silicon-based thin film back contact solar cell.
The battery module is prepared by laminating according to the required layer structure and then laminating, wherein the laminating condition is the same as that of the prior art.
The corresponding arrangement of the solder strip, the adhesive film and the back plate in the invention is respectively referred to the corresponding arrangement in the prior art, and the purpose of the invention can be achieved, and the description is omitted.
In the battery module, the front surface of the substrate is not required to be provided with the adhesive film and the front plate, so that the process is simple.
The following detailed description of the embodiments of the invention is exemplary and is merely illustrative of the invention and not to be construed as limiting the invention.
Example 1
A silicon-based thin film back contact solar cell 100 is prepared by a method shown in FIG. 3, and specifically comprises the following steps:
s1, as shown in FIG. 4, providing a glass substrate 1; the glass substrate 1 is quartz glass, and has a thickness of 3mm.
S2, as shown in FIG. 5, sequentially depositing an antireflection layer 2, a back passivation layer 3, a silicon thin film absorption layer 4 and a first semiconductor layer 5 on the back surface of the glass substrate 1;
the anti-reflection layer 2 is silicon nitride and has the thickness of 80nm. The back passivation layer 3 is silicon dioxide and has a thickness of 10nm. The silicon film absorption layer 4 is an intrinsic monocrystalline silicon layer and has a thickness of 800nm. The first semiconductor layer 5 is a first tunneling oxide layer (thickness 1.5 nm) and an N-type first doped polysilicon layer (thickness 120nm, effective doping concentration 1e20 cm) -3 ). The anti-reflection layer 2, the back passivation layer 3, the silicon thin film absorption layer 4, and the first semiconductor layer 5 are formed using a Chemical Vapor Deposition (CVD) process.
S3, as shown in FIG. 6, etching away part of the first semiconductor layer 5 by using laser to form second semiconductor opening regions which are arranged at intervals;
the width W1 of the second semiconductor opening area is 0.5mm, the etched areas and the unetched areas are arranged at intervals, and the etching period W2 is arranged according to 1 mm.
S4, as shown in FIG. 7, depositing a second semiconductor layer 6;
the second semiconductor layer 6 is a second intrinsic amorphous layer (with thickness of 7 nm) and a second P-type doped crystalline silicon layer (amorphous silicon layer with thickness of 15nm and effective doping concentration of 5e19 cm) -3 ). The second semiconductor layer 6 is formed using a Chemical Vapor Deposition (CVD) process.
S5, as shown in FIG. 8, etching away part of the second semiconductor layer 6 on the surface of the first semiconductor layer 5 by using laser to form a first semiconductor opening region; the width W3 of the first semiconductor opening region is 0.3mm.
S6, as shown in FIG. 9, depositing a conductive film layer 7 with the thickness of 60nm, wherein the conductive film layer 7 is a tin-doped indium oxide-based film; the conductive film layer 7 is formed by a Physical Vapor Deposition (PVD) process.
As shown in fig. 10, the first semiconductor layer 5 is isolated from the conductive film layer 7 on the second semiconductor layer 6 by laser etching, and the isolation groove width W4 is 60 μm.
S7, as shown in FIG. 11, forming metal electrodes 8 on the outer surfaces of the corresponding conductive film layers 7 of the first semiconductor opening region and the second semiconductor opening region respectively; the metal electrode 8 is formed by printing.
The schematic structure of the silicon-based thin film back contact solar cell 100 of the present invention corresponding to the battery module is shown in fig. 12, a back plate 400 is provided, a glue film 300, a solder strip 200 and the silicon-based thin film back contact solar cell 100 of the present invention are sequentially laminated above the back plate 400, and then the battery module is formed by lamination.
Example 2
The method of example 1 is performed with the difference that the silicon thin film absorption layer is an N-type doped polysilicon layer with an effective doping concentration of 3e16cm -3 。
Example 3
The method according to example 1 was carried out, except that the thickness of the silicon thin film absorption layer was 600nm.
Example 4
The method according to example 1 was performed with the difference that the thickness of the silicon thin film absorption layer was 2000nm.
Example 5
The process according to example 1 was carried out, except that the thickness of the antireflection layer was adjusted to 40nm so that the ratio of the thickness of the silicon thin film absorption layer to that of the antireflection layer was 100:5.
example 6
The process according to example 1 was performed, except that the thickness of the back passivation layer was adjusted to 2nm such that the ratio of the thickness of the silicon thin film absorption layer to the back passivation layer was 100:0.25.
example 7
The process of example 1 was followed with the difference that the total thickness of the back passivation layer was constant, the back passivation layer being a composite stack of polysilicon and silicon dioxide, the ratio of polysilicon to silicon dioxide thickness being 5:1.
example 8
The process according to example 1 is performed with the difference that the thickness of the first tunnel oxide layer is adjusted to 2.5nm such that the ratio of the thickness of the first tunnel oxide layer to the thickness of the silicon thin film absorption layer is 0.3:100.
example 9
The process according to example 1 was performed, except that the thickness of the second intrinsic amorphous layer was adjusted to 12nm such that the ratio of the thickness of the second intrinsic amorphous layer to the thickness of the silicon thin film absorption layer was 1.5:100.
example 10
The method of example 1 was performed with the difference that the thickness of the first doped polysilicon layer was adjusted to 80nm so that the ratio of the thickness of the first semiconductor layer to the thickness of the silicon thin film absorption layer was 10:100.
example 11
The method of example 1 was performed with the difference that the thickness of the second doped crystalline silicon layer was adjusted to 8nm so that the ratio of the thickness of the second semiconductor layer to that of the silicon thin film absorption layer was 1.88:100.
example 12
The process according to example 1 is performed with the difference that the first semiconductor layer is a first intrinsic amorphous layer (thickness 8 nm) and a doped amorphous silicon layer (thickness 15nm, effective doping concentration 2e20cm -3 ）。
Example 13
The method of example 1 was performed with the difference that the thickness of the first doped polysilicon layer was adjusted to 50nm so that the ratio of the thickness of the first semiconductor layer to the thickness of the silicon thin film absorption layer was 6.4:100.
comparative example 1
The structure of a silicon substrate back contact heterojunction solar cell 500 in the prior art is shown in fig. 1, and the preparation process flow is as follows:
s101, double-sided polishing of a silicon wafer 51;
s102, plating a first mask layer on the back surface of the silicon wafer 51 for protection, wherein the first mask layer is silicon nitride;
s103, performing texturing cleaning on the silicon wafer 51, forming pyramid textured surfaces on the opposite sides of the first mask layer, and removing the first mask layer to form the silicon wafer 51 with a single-sided texturing and single-sided polishing structure;
s104, plating a first semiconductor layer 52 (the first semiconductor layer with the same composition as that of the embodiment 10) and a second mask layer 53 on the back surface of the silicon wafer 51 in sequence, wherein the second mask layer 53 is silicon nitride and has a thickness of 70nm;
s105, forming a second semiconductor opening area by laser opening on the back surface of the silicon wafer 51 and removing the second mask layer 53 and part of the first semiconductor layer 52;
s106, cleaning to remove the first semiconductor layer 52 in the second semiconductor opening area;
s107, forming a front amorphous layer 54 with a thickness of 6nm and a front antireflection layer 55 (specifically, silicon nitride) with a thickness of 80nm on the front surface of the silicon wafer 51 in sequence, and forming a second semiconductor layer 56 (the second semiconductor layer having the same composition as that of the embodiment 1) on the back surface;
s108, forming first semiconductor opening areas alternately arranged with the second semiconductor opening areas through laser openings on the back surface of the silicon wafer 51;
s109, cleaning the silicon wafer 51, and removing the second mask layer 53 in the first semiconductor opening area;
s110, depositing a conductive film layer 7 on the back surface of the silicon wafer 51;
s111, forming an isolation groove between the first semiconductor opening area and the second semiconductor opening area in a laser mode;
s112, forming silver paste thin gate line electrodes 57 on a first semiconductor opening area and a second semiconductor opening area of the silicon wafer 51, alternately forming insulating ink 58 on the first semiconductor opening area and the second semiconductor opening area, and forming silver paste main gates 59 on the insulating ink area;
the silicon substrate back contact heterojunction solar cell 500 is manufactured into a cell module, the corresponding structure is shown in fig. 2, a back plate 400 is provided, a glue film 300, a welding strip 200, the silicon substrate back contact heterojunction solar cell 500, a front glue film layer 700 and a front plate 600 are sequentially laminated above the back plate 400, and then the cell module is formed after lamination.
Comparative example 2
The structure of the silicon-based thin film battery adopting the prior art comprises: the method comprises the steps of providing a glass substrate, and sequentially arranging a first electrode, an N-type amorphous silicon layer (with the thickness of 15 nm), an intrinsic amorphous silicon layer (with the thickness of 500 nm), a P-type amorphous silicon layer (with the thickness of 15 nm) and a second electrode on the back surface of the glass substrate, wherein the first electrode is a transparent conductive film with the thickness of 500nm, and the second electrode is a metal film with the thickness of 100nm.
Comparative example 3
The process according to example 1 is carried out with the difference that the silicon-based film has a relatively thin thickness, in particular 200nm.
Comparative example 4
The process of example 1 is followed with the difference that the silicon thin film absorber layer is intrinsic amorphous silicon.
Test case
The battery modules obtained in the above examples and comparative examples were subjected to performance tests, and the results are shown in table 1. The performance indexes of each example and comparative example were obtained by scaling with the reference of example 1, the data of example 1 being normalized reference 1, and the other examples were scaled based on example 1, for example, the current density of example 2/the current density of example 1 being 0.99. The unit of the battery module cost is W, and the unit is converted based on the W.
TABLE 1
Compared with the comparative example, the embodiment of the invention has the advantages of simple process flow, high battery conversion efficiency, improvement of current density and production yield and low production cost.
Furthermore, according to the embodiments 1, 2-11 and 13, the silicon-based thin film back contact solar cell scheme with the preferred structure of the invention can further improve the current density and the cell conversion efficiency and increase the production yield while keeping the cost low.
The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited thereto. Within the scope of the technical idea of the invention, a number of simple variants of the technical solution of the invention are possible, including combinations of the individual technical features in any other suitable way, which simple variants and combinations should likewise be regarded as being disclosed by the invention, all falling within the scope of protection of the invention.
Claims (14)
1. The silicon-based thin film back contact solar cell comprises a substrate and is characterized by further comprising an anti-reflection layer, a back passivation layer, a silicon thin film absorption layer, a semiconductor distribution layer and a metal electrode which are sequentially arranged on the back of the substrate, wherein the semiconductor distribution layer comprises a first semiconductor layer and a second semiconductor layer which are alternately arranged, the metal electrode is arranged on the outer surfaces of part of the first semiconductor layer and part of the second semiconductor layer, the silicon thin film absorption layer is an intrinsic monocrystalline silicon or doped polycrystalline silicon layer, and the thickness of the silicon thin film absorption layer is 400-8000nm; the ratio of the thicknesses of the first semiconductor layer, the second semiconductor layer and the silicon thin film absorption layer is 0.15-30:0.15-30:100.
2. the silicon-based thin film back contact solar cell of claim 1, wherein the silicon thin film absorber layer is a doped polysilicon layer having an effective doping concentration of less than 1e17cm -3 ；
And/or the number of the groups of groups,
the doped polysilicon layer is of N type or P type.
3. The silicon-based thin film back contact solar cell of claim 1, wherein the ratio of the thickness of the silicon thin film absorber layer to the thickness of the anti-reflective layer and the thickness of the back passivation layer is 100:4-200:0.05-2.
4. The silicon-based thin film back contact solar cell of claim 3, wherein the thickness of the anti-reflective layer is 40-150nm and the thickness of the back passivation layer is 1-20nm;
and/or the number of the groups of groups,
the anti-reflection layer is at least one of silicon nitride, silicon oxynitride and silicon oxide, and the back passivation layer is at least one of silicon oxide, aluminum oxide and polysilicon.
5. The silicon-based thin film back contact solar cell of claim 1, wherein the substrate has a light transmittance of 90% or more and a softening point of greater than 900 ℃;
and/or the number of the groups of groups,
the thickness of the substrate is 1-5mm.
6. The silicon-based thin film back contact solar cell of claim 5, wherein the substrate is at least one of quartz glass, borosilicate glass, sodium potassium glass.
7. The silicon-based thin film back contact solar cell of claim 1, wherein the first semiconductor layer comprises a passivation structure selected from the group consisting of a first intrinsic amorphous layer and a first doped crystalline silicon layer, or a passivation structure selected from the group consisting of a first tunneling oxide layer and a first doped polysilicon layer;
the second semiconductor layer comprises a passivation structure selected from a second intrinsic amorphous layer and a second doped crystalline silicon layer, or a passivation structure selected from a second tunneling oxide layer and a second doped polysilicon layer.
8. The silicon-based thin film back contact solar cell of claim 7, wherein the thickness of the first and second intrinsic amorphous layers is 5-15nm independently, the thickness of the first doped crystalline silicon layer is 8-16nm, and the effective doping concentration is 1e19cm -3 -5e20cm -3 The thickness of the second doped crystal silicon layer is 8-20nm, and the effective doping concentration is 1e19cm -3 -5e20cm -3 The thicknesses of the first tunneling oxide layer and the second tunneling oxide layer are respectively and independently 1-3nm, the thicknesses of the first doped polysilicon layer and the second doped polysilicon layer are respectively and independently 30-120nm, and the effective doping concentrations are respectively and independently 1e19cm -3 -5e20cm -3 。
9. The silicon-based thin film back contact solar cell of claim 7, wherein the first semiconductor layer comprises a passivation structure selected from the group consisting of a first tunneling oxide layer and a first doped polysilicon layer, and the second semiconductor layer comprises a passivation structure selected from the group consisting of a second intrinsic amorphous layer and a second doped crystalline silicon layer; wherein the ratio of the thicknesses of the first tunneling oxide layer, the second intrinsic amorphous layer and the silicon thin film absorption layer is 0.0125-0.75:0.0625-3.75:100.
10. the silicon-based thin film back contact solar cell of claim 7, wherein both ends of the second semiconductor layer extend outwards to cover part of the back surface of the adjacent first semiconductor layer, a first semiconductor opening area which does not cover the second semiconductor layer is reserved on the back surface of the first semiconductor layer, a second semiconductor opening area is formed between the adjacent first semiconductor layers, a region between the second semiconductor opening area and the first semiconductor opening area is a spacing area, the width W1 of the second semiconductor opening area is 0.3-0.8mm, and the sum W2 of the widths of the first semiconductor layers adjacent to one side of the second semiconductor opening area is 0.8-2mm.
11. The silicon-based thin film back contact solar cell of claim 10, wherein the second semiconductor layer comprises a passivation structure selected from the group consisting of a second intrinsic amorphous layer and a second doped crystalline silicon layer, the semiconductor distribution layer further comprises a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and isolation trenches are opened on portions of the conductive film layer located in the spacers; the metal electrode is arranged on the outer surfaces of the second semiconductor opening area and the first semiconductor opening area, which correspond to the conductive film layers respectively;
or,
the second semiconductor layer comprises a passivation structure selected from a second tunneling oxide layer and a second doped polysilicon layer, the semiconductor distribution layer further comprises passivation film layers paved on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and the metal electrode is arranged on the outer surfaces of the second semiconductor opening area and the outer surfaces of the passivation film layers corresponding to the first semiconductor opening area.
12. A method for manufacturing a silicon-based thin film back contact solar cell, characterized in that it is used for manufacturing a silicon-based thin film back contact solar cell according to any one of claims 1 to 11, and the method for manufacturing a silicon-based thin film back contact solar cell comprises: and sequentially depositing an antireflection layer, a back passivation layer, a silicon film absorption layer, a semiconductor distribution layer and a metal electrode on the back of the substrate.
13. The method of claim 12, wherein the deposition of the semiconductor distribution layer and the metal electrode comprises:
depositing a first semiconductor layer on the back of the silicon film absorption layer;
etching part of the first semiconductor layer in a first preset area on the back surface to form a second semiconductor opening area;
depositing a second semiconductor layer on the back surface;
etching part of the second semiconductor layer in a second preset area on the back surface to form a first semiconductor opening area;
depositing a conductive film layer or a passivation film layer on the back surface, and forming an isolation groove on the conductive film layer after depositing the conductive film layer;
and then forming metal electrodes outside the corresponding back surfaces of the first semiconductor opening area and the second semiconductor opening area respectively.
14. A battery module, characterized in that it comprises the silicon-based thin film back contact solar cell according to any one of claims 1 to 11, and a solder strip, a glue film and a back plate which are sequentially arranged on the back surface of a substrate in the silicon-based thin film back contact solar cell.
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