CN110690308A - Back contact heterojunction solar cell and module thereof - Google Patents
Back contact heterojunction solar cell and module thereof Download PDFInfo
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- CN110690308A CN110690308A CN201810723548.7A CN201810723548A CN110690308A CN 110690308 A CN110690308 A CN 110690308A CN 201810723548 A CN201810723548 A CN 201810723548A CN 110690308 A CN110690308 A CN 110690308A
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- 239000002184 metal Substances 0.000 claims abstract description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 39
- 239000010703 silicon Substances 0.000 claims abstract description 39
- 238000002955 isolation Methods 0.000 claims abstract description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 107
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 27
- 229910052802 copper Inorganic materials 0.000 claims description 27
- 239000010949 copper Substances 0.000 claims description 27
- 238000004806 packaging method and process Methods 0.000 claims description 17
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 12
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 12
- 239000003292 glue Substances 0.000 claims description 12
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 12
- 229910052709 silver Inorganic materials 0.000 claims description 12
- 239000004332 silver Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910044991 metal oxide Inorganic materials 0.000 claims description 6
- 150000004706 metal oxides Chemical group 0.000 claims description 6
- 239000011241 protective layer Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 239000011787 zinc oxide Substances 0.000 claims description 6
- -1 ITO Chemical compound 0.000 claims description 3
- 229910018487 Ni—Cr Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 claims description 3
- YOCUPQPZWBBYIX-UHFFFAOYSA-N copper nickel Chemical compound [Ni].[Cu] YOCUPQPZWBBYIX-UHFFFAOYSA-N 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 229910003437 indium oxide Inorganic materials 0.000 claims description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 3
- ORUIBWPALBXDOA-UHFFFAOYSA-L magnesium fluoride Chemical compound [F-].[F-].[Mg+2] ORUIBWPALBXDOA-UHFFFAOYSA-L 0.000 claims description 3
- 229910001635 magnesium fluoride Inorganic materials 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
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- 239000000126 substance Substances 0.000 claims description 3
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- 235000012431 wafers Nutrition 0.000 description 23
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/05—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
- H01L31/0504—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/048—Encapsulation of modules
- H01L31/049—Protective back sheets
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/05—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
- H01L31/0504—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
- H01L31/0516—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module specially adapted for interconnection of back-contact solar cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
The invention discloses a back contact heterojunction solar cell, which comprises an N-type monocrystalline silicon wafer, a second intrinsic amorphous silicon layer, an anti-reflection layer, two or more groups of N regions, P regions and N/P overlapped regions, wherein the second intrinsic amorphous silicon layer and the anti-reflection layer are sequentially arranged on the front surface of the silicon wafer, the two or more groups of N regions, P regions and N/P overlapped regions are arranged on the back surface of the silicon wafer in a finger-like cross manner, an isolation groove is formed in the N/P overlapped regions, a first intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a conductive film layer and a metal grid line layer are sequentially arranged on the surface of the P region, a third intrinsic amorphous silicon layer, an N-type amorphous silicon layer, a conductive film layer and a metal grid line layer are sequentially arranged on the surface of the N region, and a first intrinsic amorphous silicon layer, a P-. According to the invention, two or more batteries are connected in series on one silicon chip, so that the short-circuit current of the batteries is reduced, the power loss of the batteries and the modules thereof is reduced, and the conversion efficiency of the batteries and the modules is finally improved.
Description
Technical Field
The invention relates to the technical field of crystalline silicon solar cells, in particular to a back contact heterojunction solar cell and a module thereof.
Background
The photovoltaic industry is rapidly developed under the energy crisis, and the key for further popularization of photovoltaic application is to improve the photoelectric conversion efficiency of the solar cell and reduce the manufacturing cost of the cell. Back contact heterojunction solar cells are a good combination of back contact structure cells and silicon-based heterojunction cells. The back contact structure is that the electrodes are concentrated on the back of the solar cell, and the cell has high short-circuit current because the front grid line electrode is not shielded from light; the silicon-based heterojunction cell has the advantages that the passivation of high-quality hydrogenated amorphous silicon can reduce the phenomenon that holes and electrons generated under illumination are compounded and disappear in the cell, the cell has high open-circuit voltage, and the back contact heterojunction cell combines the advantages of the two cells and has high photoelectric conversion efficiency.
However, the battery with the structure has relatively large current, and the transmission distance of the current on the grid line is long, so that the internal loss of the battery is very high, the back contact heterojunction solar battery is mainly manufactured by adopting a five-inch silicon wafer in order to reduce the internal loss caused by grid line transmission, when the battery is manufactured by adopting a six-inch silicon wafer, because the current is obviously promoted, the transmission distance of the grid line is obviously lengthened, the internal loss of the battery can be obviously improved, and the efficiency of the battery is reduced. Meanwhile, when the corresponding battery is manufactured into an assembly, large power loss can be caused due to the introduction of external resistors such as assembly welding strips and bus bars.
Disclosure of Invention
In order to solve the problems, the invention provides a back contact heterojunction solar cell and a module thereof, wherein a silicon wafer is divided into a plurality of cells, so that the short-circuit current of the cells is reduced, the power loss of the cells and the module thereof is further reduced, and the conversion efficiency of the cells and the module is finally improved.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows: a back contact heterojunction solar cell comprises an N-type monocrystalline silicon wafer with double-sided texture etching to form a pyramid, a second intrinsic amorphous silicon layer, an anti-reflection layer, two or more groups of N-shaped regions, P-shaped regions and N/P overlapping regions arranged on the back of the silicon wafer and crossed in finger-like manner, the N/P overlapping area is provided with an isolation groove, the surface of the P area on the back of the silicon wafer is sequentially provided with a first intrinsic amorphous silicon layer, a P type amorphous silicon layer, a conductive film layer and a metal grid line layer, a third intrinsic amorphous silicon layer, an N-type amorphous silicon layer, a conductive film layer and a metal grid line layer are sequentially arranged on the surface of the N region on the back surface of the silicon wafer, and the surface of the N/P overlapping region on the back surface of the silicon wafer is sequentially provided with a first intrinsic amorphous silicon layer, a P-type amorphous silicon layer, an insulating layer, a third intrinsic amorphous silicon layer, an N-type amorphous silicon layer, a conductive film layer and an insulating groove.
Furthermore, the thicknesses of the first intrinsic amorphous silicon layer, the P-type amorphous silicon layer, the second intrinsic amorphous silicon layer, the N-type amorphous silicon layer and the third intrinsic amorphous silicon layer are 1-15nm, and the amorphous silicon film layer is formed by deposition through a PECVD (plasma enhanced chemical vapor deposition) or hot wire method.
Furthermore, the area of the two or more different interdigital N regions and P regions is equivalent, the different interdigital N regions and P regions are mutually isolated, and the width of the isolation region is 0.1-3 mm.
Further, the anti-reflection layer is at least one of silicon nitride, silicon oxynitride, magnesium fluoride, ITO, silicon oxide, aluminum oxide and zinc oxide, the thickness of the anti-reflection layer is 40-200nm, and the anti-reflection layer is formed through PECVD or PVD deposition.
Further, the insulating layer is at least one of silicon nitride, silicon oxynitride, silicon oxide and amorphous silicon, the thickness of the insulating layer is 40-200nm, and the insulating layer is formed through PECVD or PVD deposition.
Further, the conductive film layer is at least one of a transparent conductive film layer and a metal film layer, the transparent conductive film layer is a metal oxide, the metal oxide is one of an indium tin oxide film, an aluminum-doped zinc oxide film and a tungsten-doped indium oxide film, the metal film layer is one of copper, nickel copper and nickel chromium, the thickness of the conductive film layer is 50-300nm, and the conductive film layer is deposited by PVD.
Further, the metal grid lines are silver paste grid lines or copper grid lines, the silver paste grid lines are formed through screen printing, the width of each silver paste grid line is 30-600um, and the thickness of each silver paste grid line is 10-100 um; the copper grid line is formed by electroplating or chemical plating, the copper grid line comprises a copper grid line layer and a copper grid line protective layer, the copper grid line protective layer is a tin layer, the width of the copper grid line is 30-600um, and the thickness of the copper grid line is 10-100 um.
Further, the width of the P region is 200-700um, the width of the N region is 100-700um, and the width of the N/P overlapping region is 50-500 um.
Furthermore, the metal grid lines on the surface of the P region and the surface of the N region are in a finger-shaped cross pattern, and the distance between the metal grid lines of the P region and the metal grid lines of the N region is 30-700 um.
A back contact heterojunction solar cell module comprises a back plate body, first packaging glue arranged on the back plate body, at least one solar cell which is formed on the first packaging glue and is cut into multiple equal parts according to claim 1, second packaging glue arranged on the solar cell and a front plate body arranged on the second packaging glue, wherein the solar cells are connected through metal grid line electrodes arranged on a first side face and a second side face of the solar cells, and the solar cells are wrapped by the first packaging glue and the second packaging glue.
From the above description of the structure of the present invention, compared with the prior art, the present invention has the following advantages:
according to the invention, two or more batteries are connected in series on one silicon chip, so that the short-circuit current of the batteries is obviously reduced, and the open-circuit voltage of the batteries is increased, thereby greatly reducing the power loss of the batteries and components, increasing the conversion efficiency of the batteries and the components, simultaneously reducing the requirements on the resistance of electrode grid lines, and reducing the consumption of metal materials, thereby reducing the internal stress of the battery chip, improving the product stability and reducing the production cost.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a back contact heterojunction solar cell of the present invention;
fig. 2 is a schematic side view of a back contact heterojunction solar cell in accordance with embodiment 1 of the present invention;
fig. 3 is a schematic structural diagram of a back-contact heterojunction solar cell in which two cells are connected in series on a silicon wafer before a metal electrode is formed on the back side of the back-contact heterojunction solar cell in embodiment 1 of the invention;
fig. 4 is a schematic structural diagram of a back-contact heterojunction solar cell in which two cells are connected in series on a silicon wafer and a metal electrode is formed on the back of the back-contact heterojunction solar cell in embodiment 1 of the present invention;
fig. 5 is a schematic structural diagram of a silicon wafer after two batteries are cut according to embodiment 1 of the present invention;
fig. 6 is a schematic structural diagram of a cut solar cell after series welding in embodiment 1 of the present invention;
fig. 7 is a schematic structural diagram of a back-contact heterojunction solar cell in which two cells are connected in series on a silicon wafer before a metal electrode is formed on the back side of the back-contact heterojunction solar cell in embodiment 2 of the invention;
fig. 8 is a schematic structural diagram of a back-contact heterojunction solar cell in which two cells are connected in series on a silicon wafer and a metal electrode is formed on the back of the back-contact heterojunction solar cell in embodiment 2 of the present invention;
fig. 9 is a schematic structural view of a solar cell after series welding in embodiment 2 of the present invention;
FIG. 10 is a schematic view of a module structure according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Example 1
As shown in fig. 1, the back contact heterojunction solar cell includes an N-type single crystal silicon wafer 10 with pyramids formed by texturing on both sides, a second intrinsic amorphous silicon layer 21, an anti-reflection layer 22 sequentially disposed on the front side of the silicon wafer, a first intrinsic amorphous silicon layer 31, a P-type amorphous silicon layer 32, a conductive film layer 33, and a metal gate line layer 34 sequentially disposed on the back side of the silicon wafer 10, and a third intrinsic amorphous silicon layer 41, an N-type amorphous silicon layer 42, a conductive film layer 43, and a metal gate line layer 44 sequentially disposed on the back side of the silicon wafer 10. The first intrinsic amorphous silicon layer 31, the P-type amorphous silicon layer 32, the insulating layer 33, the third intrinsic amorphous silicon layer 41, the N-type amorphous silicon layer 42, the conductive film layer 43 and the insulating groove 1C are sequentially arranged on the surface of the N/P overlapping region C on the back surface of the silicon wafer. As shown in FIG. 2 and FIG. 3, two sets of 1, 2 interdigitated N, P, and N/P overlapped regions on the back surface of the silicon wafer 10 are respectively the N region 11N, P region 11P, N/P overlapped region 1C of the 1 st set, the N region 21N, P region 21P, N/P overlapped region 2C of the 2 nd set, and the isolation region 12C, and the width W1 of the isolation region 12C is 0.1-3 mm. As shown in fig. 4, two sets of 1, 2 finger-like N-region metal gate lines, P-region metal gate lines, and N/P overlapping regions on the back side of the silicon wafer 10 are respectively the N-region metal gate line 12N, P region 12P, N/P overlapping region 1C of the 1 st set, and the N-region metal gate line 22N, P region metal gate line 22P, N/P overlapping region 2C of the 2 nd set. As shown in fig. 5, the silicon wafer 10 forming the metal grid line is cut into two pieces by laser or mechanical means to form a battery 1 and a battery 2.
The pyramid size on the surface of the silicon wafer 10 is 2-12 um. The thicknesses of the first intrinsic amorphous silicon layer 31, the P-type amorphous silicon layer 32, the second intrinsic amorphous silicon layer 21, the N-type amorphous silicon layer 42 and the third intrinsic amorphous silicon layer 41 are 1-15nm, and the amorphous silicon film layer is formed by deposition through a PECVD (plasma enhanced chemical vapor deposition) or hot wire method. The two different interdigitated N and P regions are of comparable area and are spaced apart from one another to form cell 1 and cell 2, with the spacing region 12C having a width W1 of 0.1-3 mm. The anti-reflection layer 22 is at least one of silicon nitride, silicon oxynitride, magnesium fluoride, ITO, silicon oxide, aluminum oxide and zinc oxide, the thickness is 40-200nm, and the anti-reflection layer 22 is formed through PECVD or PVD deposition. The insulating layer 33 is at least one of silicon nitride, silicon oxynitride, silicon oxide and amorphous silicon, the thickness is 40-200nm, and the insulating layer 33 is formed by PECVD or PVD deposition. The conductive film layer 43 is at least one of a transparent conductive film layer and a metal film layer, the transparent conductive film layer is a metal oxide, the metal oxide is one of an indium tin oxide film, an aluminum-doped zinc oxide film and a tungsten-doped indium oxide film, the metal film layer is one of copper, nickel copper and nickel chromium, the thickness of the conductive film layer 43 is 50-300nm, and the conductive film layer 43 is deposited by PVD. The width of the insulation groove 1C and the width of the insulation groove 2C are 0.02-0.2 mm. The metal grid lines 34 and 44 are silver paste grid lines or copper grid lines, the silver paste grid lines are formed through screen printing, the width of each silver paste grid line is 30-600um, and the thickness of each silver paste grid line is 10-100 um. The copper grid line is formed by electroplating or chemical plating, the copper grid line comprises a copper grid line layer and a copper grid line protective layer, the copper grid line protective layer is a tin layer, the width of the copper grid line is 30-600um, and the thickness of the copper grid line is 10-100 um. The widths of the P regions 11P and 12P are 200-700um, the widths of the N regions 11N and 12N are 100-700um, and the widths 1C and 2C of the N/P overlapped regions are 50-500 um. The metal grid lines on the surface of the P region and the surface of the N region are in a finger-shaped cross pattern, and the distance between the metal grid lines 34 and 44 in the P region and the N region is 30-700 um.
As shown in fig. 6, a plurality of cut batteries 1 and 2 are welded in series and parallel by using a welding tape 103A. As shown in fig. 10, a backboard body 101 is provided; a first packaging adhesive 102 disposed on the backplane body 101; a plurality of equally-cut solar cells 1 and cells 2 arranged on the first packaging adhesive 102, wherein the plurality of solar cells 1 and the cells 2 are welded together through solder strips 103A; the second packaging adhesive 104 is arranged on the solar cell, and the first packaging adhesive 102 and the second packaging adhesive 104 are coated on the periphery of the solar cell 1/2; and a front plate 105 disposed on the second encapsulant 104.
Example 2
The difference from example 1 is: as shown in fig. 7, a complete metal electrode grid line is reserved on the isolation region 12C, as shown in fig. 8, a P-region metal grid line 12P of the battery 1 on the upper surface of the isolation region 12C is connected with an N-region metal grid line 22N of the battery 2, as shown in fig. 9, a plurality of silicon wafers 10 forming the metal grid line are connected in series and in parallel by welding with a solder strip 103A.
According to the invention, two or more batteries are connected in series on one silicon chip, so that the short-circuit current of the batteries is obviously reduced, and the open-circuit voltage of the batteries is increased, thereby greatly reducing the power loss of the batteries and components, increasing the conversion efficiency of the batteries and the components, simultaneously reducing the requirements on the resistance of electrode grid lines, and reducing the consumption of metal materials, thereby reducing the internal stress of the battery chips, improving the product stability and reducing the production cost.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A back contact heterojunction solar cell, comprising: the silicon wafer comprises an N-type monocrystalline silicon wafer with two surfaces textured to form a pyramid, a second intrinsic amorphous silicon layer and an anti-reflection layer which are sequentially arranged on the front surface of the silicon wafer, two or more groups of N regions, P regions and N/P overlapped regions which are arranged on the back surface of the silicon wafer and are crossed in finger-like mode, wherein an isolation groove is formed in the N/P overlapped regions, a first intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a conductive film layer and a metal grid line layer are sequentially arranged on the surface of the P region on the back surface of the silicon wafer, a third intrinsic amorphous silicon layer, an N-type amorphous silicon layer, a conductive film layer and a metal grid line layer are sequentially arranged on the surface of the N region on the back surface of the silicon wafer, and a first intrinsic amorphous silicon layer, a P-type amorphous silicon layer, an insulating layer, a third intrinsic amorphous silicon layer, an N.
2. The back contact heterojunction solar cell of claim 1, wherein: the thicknesses of the first intrinsic amorphous silicon layer, the P-type amorphous silicon layer, the second intrinsic amorphous silicon layer, the N-type amorphous silicon layer and the third intrinsic amorphous silicon layer are 1-15nm, and the amorphous silicon film layer is formed by deposition through a PECVD (plasma enhanced chemical vapor deposition) or hot wire method.
3. The back contact heterojunction solar cell of claim 1, wherein: the area of the two or more different interdigital N regions and P regions is equivalent, the different interdigital N regions and P regions are mutually isolated, and the width of the isolation region is 0.1-3 mm.
4. The back contact heterojunction solar cell of claim 1, wherein: the anti-reflection layer is at least one of silicon nitride, silicon oxynitride, magnesium fluoride, ITO, silicon oxide, aluminum oxide and zinc oxide, the thickness of the anti-reflection layer is 40-200nm, and the anti-reflection layer is formed by PECVD or PVD deposition.
5. The back contact heterojunction solar cell of claim 1, wherein: the insulating layer is at least one of silicon nitride, silicon oxynitride, silicon oxide and amorphous silicon, the thickness of the insulating layer is 40-200nm, and the insulating layer is formed by PECVD or PVD deposition.
6. The back contact heterojunction solar cell of claim 1, wherein: the conductive film layer is at least one of a transparent conductive film layer and a metal film layer, the transparent conductive film layer is a metal oxide, the metal oxide is one of an indium tin oxide film, an aluminum-doped zinc oxide film and a tungsten-doped indium oxide film, the metal film layer is one of copper, nickel-copper and nickel-chromium, the thickness of the conductive film layer is 50-300nm, and the conductive film layer is deposited by PVD.
7. The back contact heterojunction solar cell of claim 1, wherein: the metal grid lines are silver paste grid lines or copper grid lines, the silver paste grid lines are formed by screen printing, the width of each silver paste grid line is 30-600um, and the thickness of each silver paste grid line is 10-100 um; the copper grid line is formed by electroplating or chemical plating, the copper grid line comprises a copper grid line layer and a copper grid line protective layer, the copper grid line protective layer is a tin layer, the width of the copper grid line is 30-600um, and the thickness of the copper grid line is 10-100 um.
8. The back contact heterojunction solar cell of claim 1, wherein: the width of the P area is 200-700um, the width of the N area is 100-700um, and the width of the N/P overlapping area is 50-500 um.
9. The back contact heterojunction solar cell of claim 1, wherein: the metal grid lines on the surfaces of the P region and the N region are in a finger-shaped cross pattern, and the distance between the metal grid lines of the P region and the metal grid lines of the N region is 30-700 um.
10. The back contact heterojunction solar cell module of claim 1, wherein: the solar cell comprises a back plate body, first packaging glue arranged on the back plate body, at least one multi-equal-part cut solar cell arranged on the first packaging glue, second packaging glue arranged on the solar cell and a front plate body arranged on the second packaging glue, wherein the solar cells are connected through metal grid line electrodes arranged on a first side face and a second side face of each solar cell, and the first packaging glue and the second packaging glue wrap the periphery of the solar cell.
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