CN117423757A - Solar cell and photovoltaic module - Google Patents
Solar cell and photovoltaic module Download PDFInfo
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- CN117423757A CN117423757A CN202210811367.6A CN202210811367A CN117423757A CN 117423757 A CN117423757 A CN 117423757A CN 202210811367 A CN202210811367 A CN 202210811367A CN 117423757 A CN117423757 A CN 117423757A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/048—Encapsulation of modules
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/05—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Development (AREA)
- Sustainable Energy (AREA)
- Manufacturing & Machinery (AREA)
- Photovoltaic Devices (AREA)
Abstract
The invention discloses a solar cell and a photovoltaic module, comprising: a substrate having a front surface and a back surface; the first doping layer is positioned on the back surface of the substrate, the first doping layer comprises a main body part and a plurality of protruding parts protruding from the main body part, the main body part is closer to the substrate than the protruding parts, the protruding parts extend along a first direction, the protruding parts are arranged at equal intervals along a second direction, and a plane where the second direction is located is perpendicular to a plane where the first direction is located. Compared with the prior art, the first doping layer is arranged as the main body part and the plurality of protruding parts protruding out of the main body part, the thickness of the first doping layer of the coverage area of the first grid line electrode is not changed, the thickness of the first doping layer of the coverage area of the back surface non-first grid line electrode is thinned, parasitic absorption of the first doping layer to light is reduced, short-circuit current is improved, and the metal grid line is prevented from burning through the first doping layer.
Description
Technical Field
The invention relates to the technical field of photovoltaic cells, in particular to a solar cell and a photovoltaic module.
Background
TOPCon (Tunnel Oxide Passivating Contacts) the cell is a solar cell based on the selective carrier principle where the tunneling oxide layer passivates contacts. The back surface of the semiconductor device is generally in a structure of combining ultra-thin tunneling silicon oxide and doped polycrystalline silicon layers, so that a passivation contact effect is realized, a metal electrode and c-Si are not in direct contact, the recombination of carriers is reduced, and the separation and collection of the carriers are realized. However, the conventional solar cell passivation structure has certain limitations for reducing reverse saturation current and improving short current and open voltage of the cell.
Disclosure of Invention
The invention aims to provide a solar cell and a photovoltaic module so as to solve the technical problems in the prior art.
The present invention provides a solar cell comprising:
a substrate having a front surface and a back surface, the front surface and the back surface being disposed opposite in a first direction;
the first doping layer is positioned on the back surface of the substrate and comprises a main body part and a plurality of protruding parts protruding out of the main body part, the main body part is closer to the substrate than the protruding parts, the protruding parts extend along the first direction, the protruding parts are arranged at equal intervals along a second direction, and the plane in which the second direction is positioned is perpendicular to the plane in which the first direction is positioned;
a dielectric layer between the substrate and the first doped layer;
a second doped layer located on the front surface of the substrate;
a first gate line electrode electrically contacting the protrusion;
and a second gate line electrode electrically contacting the second doped layer.
In the solar cell as described above, it is preferable that the protruding portion has a protruding distance of 5 to 200nm in the first direction.
In the solar cell as described above, preferably, the width of the protruding portion in the second direction is 50 to 200um.
In the solar cell as described above, it is preferable that the ratio of the width of the protruding portion to the width of the main body portion in the second direction is 0.03% to 0.12%.
In the solar cell as described above, it is preferable that a ratio of the width of the protrusion to the width of the first gate line electrode in the second direction is 1.5 to 5.
In the solar cell as described above, it is preferable that the thickness of the main body portion in the first direction is 1 to 100nm.
In the solar cell as described above, preferably, the second doped layer includes a first region and a second region, the second doped layer has a doping concentration at the first region greater than a doping concentration at the second region, and the second gate line electrode is electrically connected at the first region.
A solar cell as described above, wherein preferably the doping concentration at said first region comprises between 5e+18 and 5E-19, the junction depth being between 1.5 and 2.5 um.
A solar cell as described above, wherein preferably the dielectric layer comprises at least one of silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, silicon oxynitride.
In the solar cell as described above, it is preferable that the dielectric layer and the first doped layer each have a plurality of layers, the dielectric layer and the first doped layer are alternately arranged in sequence along the first direction, and the protrusion is disposed on the first doped layer farthest from the substrate.
In the solar cell as described above, preferably, a surface of the first doped layer facing away from the substrate is formed with a first passivation layer, and the first gate electrode penetrates through the first passivation layer and is in electrical contact with the first doped layer, and the first passivation layer includes at least one of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, and a silicon oxynitride layer.
In the solar cell as described above, preferably, a second passivation layer is formed on a surface of the second doped layer on a side facing away from the substrate, and the second gate electrode penetrates through the second passivation layer to be in electrical contact with the second doped layer, and the second passivation layer includes at least one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.
In the solar cell as described above, preferably, the number of the first gate line electrodes is 80-200, and the width is 30-40um.
In the solar cell as described above, preferably, the number of the second gate line electrodes is 100-150, and the width is 20-30um.
The application also provides a photovoltaic module, comprising:
the battery string is formed by connecting the solar batteries;
an encapsulation layer for covering the surface of the battery string;
and the cover plate is used for covering the surface, far away from the battery strings, of the packaging layer.
Compared with the prior art, the first doping layer is arranged as the main body part and the plurality of protruding parts protruding out of the main body part, the thickness of the first doping layer of the coverage area of the first grid line electrode is not changed, the thickness of the first doping layer of the coverage area of the back surface non-first grid line electrode is thinned, parasitic absorption of the first doping layer to light is reduced, short-circuit current is improved, and the metal grid line is prevented from burning through the first doping layer.
Drawings
Fig. 1 is a schematic structural view of a solar cell of a first structure provided in the present application;
fig. 2 is a schematic structural view of a solar cell of a second structure provided herein;
fig. 3 is a schematic structural view of the photovoltaic module provided by the present application.
Reference numerals illustrate: 1-substrate, 2-front surface, 3-back surface, 4-dielectric layer, 5-first doped layer, 51-body portion, 52-protrusion, 6-first gate electrode, 7-first passivation layer, 8-second doped layer, 81-first region, 82-second region, 9-second passivation layer, 10-second gate electrode, 11-cell string, 12-encapsulation layer, 13-cap plate.
D1-a first direction, D2-a second direction.
Detailed Description
The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
In the prior art, most of the first doped layer technology on the back surface of TOPCon (Tunnel Oxide Passivating Contacts) is a single-layer uniform thickness structure, the thickness of the first doped layer is basically more than 100nm, light can be reflected again into the cell after reaching the back surface of the cell, and the reflected light can be absorbed due to the existence of the first doped layer, so that short-circuit current is lower.
In order to solve the above technical problems, referring to fig. 1 and 2, an embodiment of the present invention provides a solar cell, including:
the substrate 1 has a front surface 2 and a back surface 3, where the front surface 2 and the back surface 3 are disposed opposite to each other along a first direction D1, in this embodiment, the first direction D1 is a direction extending along gravity as shown in fig. 1, the front surface 2 is a light receiving surface facing a direction of sunlight irradiation, the back surface 3 is a surface opposite to the front surface 2, and the back surface 3 may also be a light receiving surface for a double-sided battery. The substrate 1 may be, for example, a semiconductor including a crystal (e.g., crystalline silicon) containing a first conductivity type dopant. The crystalline semiconductor may be single crystal silicon, and the first conductivity type dopant may be an N-type dopant such As a V group element including phosphorus (P), arsenic (As), bismuth (Bi), antimony (Sb), or a P-type dopant including a III group element including boron (B), aluminum (Al), gallium (Ga), indium (In), or the like.
A first doped layer 5 on the back surface 3 of the substrate 1, the first doping element of the first doped layer 5 being compatible with the first conductivity type dopant of the substrate 1; in a possible embodiment, when the substrate 1 is an N-type crystalline silicon substrate 1, the first doping element of the first doping layer 5 is phosphorus; when the substrate 1 is a P-type crystalline silicon substrate 1, the first doping element of the first doping layer 5 is boron.
In the embodiment provided herein, the first doping layer 5 is formed by doping amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like with an N-type dopant. The N-type dopant may be any dopant having the same conductivity type as the substrate 1. That is, a group V element such As phosphorus (P), arsenic (As), bismuth (Bi), or antimony (Sb) may be used. Further, the first doped layer 5 is a phosphorus doped polysilicon layer. The crystal structure of the first doped layer 5 is different from that of the substrate 1.
And the dielectric layer 4 is positioned between the substrate 1 and the first doping layer 5, and the dielectric layer 4 is used for carrying out interface passivation on the back surface 3 of the substrate 1, so that the recombination of carriers at the interface is reduced, and the transmission efficiency of the carriers is ensured.
A second doped layer 8 located on the front surface 2 of the substrate 1, the second doping element of the second doped layer 8 being opposite to the first conductivity type dopant of the substrate 1; in a possible embodiment, when the substrate 1 is an N-type crystalline silicon substrate 1, the second doping element of the second doping layer 8 is boron; when the substrate 1 is a P-type crystalline silicon substrate 1, the second doping element of the second doping layer 8 is phosphorus.
The first gate line electrode 6, which is in electrical contact with the first doped layer 5, in some embodiments, the material of the first gate line electrode 6 comprises at least one conductive metal material of silver, aluminum, copper, nickel, etc.
A second gate line electrode 10 in electrical contact with the second doped layer 8, the material of the second gate line electrode 10 in some embodiments comprising at least one conductive metallic material of silver, aluminum, copper, nickel, and the like.
The first doped layer 5 includes a main body portion 51 and a plurality of protruding portions 52 protruding from the main body portion 51, the shape of the protruding portions 52 is not fixed, which may be trapezoidal or rectangular, the main body portion 51 is closer to the substrate 1 than the protruding portions 52, the first gate electrode 6 and the protruding portions 52 form electrical contact, the protruding portions 52 extend along a first direction D1, the protruding portions 52 are arranged at equal intervals along a second direction D2, a plane of the second direction D2 is perpendicular to a plane of the first direction D1, the second direction D2 is a horizontal extending direction shown in fig. 1, and the second direction D2 and the first direction D1 respectively form an X axis and a Y axis of a rectangular coordinate system.
In the above embodiment, by setting the first doped layer 5 as the main body 51 and the protruding portion 52 protruding from the main body 51, the first doped layer 5 is thicker in the area connected to the first gate electrode 6, and the first doped layer 5 is thinner in the area not connected to the first gate electrode 6, so that the purposes of low metal contact recombination, low non-metal contact area recombination and low contact resistivity can be achieved, and the method is particularly suitable for the thinner first doped layer 5, and can further reduce the thickness of the first doped layer 5 and reduce the dosage of the first doped element, thereby reducing the cost, and meanwhile, the overall thickness of the protruding portion 52 is larger, so that the condition of metal-semiconductor contact can be well satisfied, and good ohmic contact with metal paste can be ensured in the metallization process.
In the embodiment provided in the present application, the protruding distance of the protruding portion 52 along the first direction D1 is 5-200nm, specifically, the protruding distance may be 5nm, 25nm, 45nm, 65nm, 85nm, 100nm, 120nm, 140nm, 160nm, 180nm, 200nm, or the like, but other values within the above range are also possible, and are not limited herein. In this range, parasitic absorption of the first doped layer 5 to current can be reduced, short-circuit current can be increased, and the metal gate line is ensured not to burn through the first doped layer 5.
In the embodiment provided in the present application, the width of the protruding portion 52 along the second direction D2 is 50-200um, and the width of the protruding portion 52 is matched with the width of the first gate line electrode 6 and the width of the light spot, specifically, the width may be 50um, 100um, 150um, 200um, etc., but may also be other values within the above range, which is not limited herein. Within this range, the width of the projection 52 is wider than the width of the first gate line electrode 6 and the spot, but not too wide, which increases the dose of the first doping element required, increases the cost, and may result in a reduction of the short-circuit current.
In the embodiment provided in this application, the ratio of the width of the protruding portion 52 to the width of the main body portion 51 along the second direction D2 is 0.03% -0.12%, specifically, the width may be 0.03%, 0.06%, 0.09%, 0.12%, or the like, which may be, of course, other values within the above range, which are not limited herein, and in this interval range, not only can ensure good electrical contact between the protruding portion 52 and the first gate line electrode 6, but also can ensure good ohmic contact with the metal paste in the metallization process, without excessively large ratio, thereby enhancing parasitic absorption of light. When the ratio is out of this range, if the ratio is too small, the improvement effect is not obvious, and if the ratio is too large, the effective area of the main body 51 is wasted, thereby degrading the battery performance.
In the embodiment provided in this application, the ratio of the width of the protruding portion 52 to the width of the first gate line electrode 6 along the second direction D2 is between 1.5 and 5, specifically, the width ratio may be 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, or the like, and of course, other values within the above range may also be used, which is not limited herein, and in a possible embodiment, on a battery sheet with a size of 166×166mm, the number of the first gate line electrodes 6 is 80-200, the width is 30-40um, the width of the protruding portion 52 is 50-200um, and the width of the protruding portion 52 is wider than the width of the first gate line electrode 6, so as to facilitate the forming process of the first gate line electrode 6, but not too wide, which may increase the dosage of the required first doping element, increase the cost, and may result in a reduction in the short-circuit current. In one possible embodiment, the method of forming the first gate line electrode 6 includes printing a conductive paste on the surface of the protrusion 52, wherein the conductive material in the conductive paste may be at least one of silver, aluminum, copper, tin, gold, lead, or nickel; the conductive paste is subjected to a sintering process, for example, a peak temperature of 780 ℃ to 880 ℃ may be used to form the first gate line electrode 6.
In the embodiment provided in this application, the thickness of the main body portion 51 along the first direction D1 is 1-100nm, specifically, the width ratio may be 1nm, 10nm, 30nm, 50nm, 70nm, 80nm, 100nm, or the like, and of course, other values within the above range may also be used, which is not limited herein, and the thickness of the main body portion 51 is thinner than that of the back doped layer in the prior art, so that parasitic absorption of the first doped layer 5 to current can be reduced, short-circuit current can be improved, and meanwhile, the usage amount of the first doped element can be reduced, thereby achieving the purpose of reducing cost.
In the prior art, the conventional front boron diffusion technology of the TopCon battery cannot give consideration to unified improvement of open-circuit voltage and filling factor; if the boron diffusion square resistance is lower, the contact resistance is smaller and the filling factor is higher; but can lead to higher internal recombination of the battery piece and lower open circuit voltage; if the square resistance is higher, the internal recombination of the battery piece is lower, and the open circuit voltage is higher; but the contact resistance is larger and the fill factor is lower.
In order to solve the above-mentioned problems, in the embodiment provided in the application, the second doped layer 8 includes a first region 81 and a second region 82, the doping concentration of the second doped layer 8 at the first region 81 is greater than the doping concentration at the second region 82, and the second gate electrode 10 is electrically connected at the first region 81. Thereby forming a selective emitter structure on the surface of the second doped layer 8, wherein the second area 82 without the metal grid line has larger sheet resistance, lower surface doping concentration and less recombination, and can improve the open-circuit voltage and short-circuit current of the battery piece; the doping concentration of the first region 81 where the metal gate line is located is higher, the junction depth is deeper, the contact resistance can be effectively reduced, and the filling factor is improved.
In the embodiment provided in the application, the doping concentration at the first region 81 is between 5e+18 and 5e-19, the junction depth is between 1.5 um and 2.5um, the first region 81 is heavily doped, the second gate line electrode 10 is in contact with the heavily doped first region 81, the contact resistivity is greatly reduced, and the resistance loss is reduced. The second region 82 is lightly doped and very low non-contact region recombination can be achieved.
In the embodiment provided in this application, the concentration of the second region 82 is lower, resulting in a larger lateral resistance, and if the area of the second gate electrode 10 is smaller, the electron collection efficiency will be lower, and the filling factor will be lower, so that the area of the second gate electrode 10 needs to be increased; however, after the area of the second gate line electrode 10 is large, the shading becomes serious, and the short-circuit current becomes low; the metal recombination is also increased, and the open circuit voltage is reduced; but the contact resistance becomes small and the fill factor becomes large.
In a possible implementation manner, referring to fig. 1, fig. 1 is a schematic structural diagram of a solar cell with a first structure provided in the present application, where the number of first grid electrodes 6 is greater than that of second grid electrodes 10, and the number of first grid electrodes 6 and the number of second grid electrodes 10 are all thin grid lines, and on a 166 x 166mm size cell sheet, the number of first grid electrodes 6 is 80-200, the width is 30-40um, the number of second grid electrodes 10 is 100-150, and the width is 20-30um, so that light shielding is not only serious, but also open-circuit voltage can be increased, contact resistance is reduced, and electron collection efficiency is improved.
In another possible embodiment, referring to fig. 2, fig. 2 is a schematic structural diagram of a solar cell of a second structure provided in the present application; the solar cell of the second structure is different from the solar cell of the first structure in that the number of the first gate line electrodes 6 is equal to the number of the second gate line electrodes 10, the number of the first gate line electrodes 6 corresponds to the position of the second gate line electrodes 10, and the position and size of the protruding portion 52 also correspond to the position and size of the first region 81, so that the shielding areas of the front surface 2 and the back surface 3 of the substrate 1 are maintained to be substantially uniform, the electron collection efficiency is improved, and the filling factor is increased.
In the embodiments provided herein, the thickness of the dielectric layer 4 is between 0.5nm and 2nm. Specifically, the thickness of the dielectric layer 4 is 0.5nm, 0.9nm, 1.0nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm, 2.0nm, etc., but other values within the above range are also possible, and the present invention is not limited thereto.
As an alternative solution to the present application, the dielectric layer 4 comprises one or more of silicon oxide, aluminum oxide, hafnium oxide, silicon nitride or silicon oxynitride. The dielectric layer 4 allows multi-photon tunneling to enter the first doped layer 5 and simultaneously blocks minority carriers from passing through, so that the majority carriers are transported transversely in the first doped layer 5 and collected by the first grid line electrode 6, the dielectric layer 4 and the first doped layer 5 form a tunneling oxide passivation contact structure, excellent interface passivation and selective collection of carriers can be achieved, recombination of the carriers is reduced, and photoelectric conversion efficiency of the solar cell is improved. It is noted that the dielectric layer 4 may in fact not have a perfect tunnel barrier, as it may for example contain defects such as pinholes, which may lead to other charge carrier transport mechanisms (e.g. drift, diffusion) being dominant with respect to tunneling.
The dielectric layers 4 and the first doped layers 5 are all provided with a plurality of layers, the plurality of dielectric layers 4 and the plurality of first doped layers 5 are alternately arranged in sequence along the first direction D1, and the protruding portions 52 are arranged on the first doped layers 5 farthest from the substrate 1. By depositing multiple first doping layers 5, the level passivation of the substrate 1 is realized, the field effect passivation effect is improved, the carrier recombination at the interface of the substrate 1 is reduced, minority carriers are blocked from passing through by multiple dielectric layers 4, the selective transmission of the carriers is realized, and the carrier recombination at the interface of the substrate 1 is reduced.
In the embodiment provided herein, the surface of the first doped layer 5 facing away from the substrate 1 is formed with a first passivation layer 7, the shape of the first passivation layer 7 is matched with the shape of the first doped layer 5, the first gate line electrode 6 penetrates through the first passivation layer 7 and then forms electrical contact with the protruding portion 52, and the first passivation layer 7 includes at least one of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer and a silicon oxynitride layer.
The first passivation layer 7 can passivate the back surface 3 of the battery, reduce the carrier recombination velocity of the back surface 3, improve the photoelectric conversion efficiency, the first passivation layer 7 is positioned on the surface of the first doped layer 5, and the first gate line electrode 6 penetrates through the first passivation layer 7 and is in electrical contact with the first doped layer 5. As an alternative solution of the present application, the first passivation layer 7 may be provided with an opening, so that the first gate line electrode 6 is electrically contacted with the first doped layer 5 after passing through the opening, thereby reducing the contact area between the metal electrode and the first doped layer 5, further reducing the contact resistance, and improving the open circuit voltage.
Alternatively, the first passivation layer 7 includes a stacked structure of at least one or more of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, and a silicon oxynitride layer.
In some embodiments, the thickness of the first passivation layer 7 ranges from 10nm to 120nm, specifically, may be 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm or 120nm, or the like, but may be other values within the above range, which is not limited herein.
Optionally, a second passivation layer 9 is formed on the surface of the second doped layer 8 facing away from the substrate 1, and the second gate line electrode 10 is in electrical contact with the second doped layer 8 after penetrating the second passivation layer 9. The second passivation layer 9 can play a role in passivating the front surface 2 of the substrate 1, so that the recombination of carriers at the interface is reduced, the transmission efficiency of the carriers is improved, and the photoelectric conversion efficiency of the battery piece is further improved.
Optionally, the second passivation layer 9 includes a stacked structure of at least one or more of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, and a silicon oxynitride layer.
The application also provides a preparation method of the solar cell, which comprises the following steps,
double-sided texturing of an N-type substrate 1, placing the substrate in a solution of KOH and an additive for reaction, wherein the reflectivity after texturing is generally 8-12%;
2. placing the substrate 1 after texturing into a furnace tube, using a boron source and oxygen to diffuse at a high temperature (> 800 ℃), wherein the diffusion rear resistance is between 100 and 250 ohm/sq; the diffusion can be double-sided diffusion or single-sided diffusion;
3. forming a SE pattern on one side of the sheet after boron diffusion (serving as a front side), wherein the sheet resistance of a laser area is generally between 50 and 150 ohm/sq; the light spot can be a square light spot or a round light spot; the light spots can be overlapped or not overlapped;
4. placing the substrate 1 after SE in a mixed solution of HF and HCL for cleaning, and removing borosilicate glass and dust on the surface;
5. placing the substrate 1 into a furnace tube again, and performing high-temperature (> 900 ℃) oxidation reaction by using oxygen to generate an oxide layer with the thickness of 50-150nm, so as to protect the front surface from being corroded by alkali; can be single-sided oxidation or double-sided oxidation;
6. firstly, placing the back surface of a substrate 1 in an HF solution, and removing a back surface BSG; immersing the substrate 1 in KOH solution, changing the back surface of the substrate 1 into a polished surface, and ensuring that the reflectivity is between 40 and 60 percent;
7. placing the substrate 1 into a high-temperature (500-700 ℃) furnace tube, and generating an ultrathin oxide layer (1-3 nm) and amorphous silicon (5-200 nm) with a multilayer structure on the surface of the substrate 1 by using oxygen and silane;
8. the substrate 1 is put into a high-temperature (750-950 ℃) furnace tube, a phosphorus source and oxygen are used for diffusing at the back, and the ECV surface concentration after diffusion is more than 3E+20;
9. forming an INK structure on the surface of the substrate 1 by using wax, and protecting the phosphosilicate glass of the structure from acid corrosion;
10. firstly, HF is used for washing out phosphosilicate glass outside the INK structure, and then the substrate 1 is placed in KOH mixed solution to remove wax and poly silicon outside the INK structure; the poly silicon at the bottom layer is reserved, so that passivation is not influenced;
11. a mask layer is formed on the back surface by PECVD or high-temperature furnace tube oxidation, so that the back surface is protected from acid-base corrosion;
12. etching poly silicon on the front side of the substrate 1 by using acid or alkali solution to leak out of the structure of the substrate 1, and forming a second doped layer 8; removing the mask on the back surface, leaking the polysilicon, and forming a first doped layer 5;
13. depositing a layer of alumina with the thickness of 2-5nm on the front surface to form a second passivation layer 9, so as to improve the passivation effect of the front surface;
14. depositing a SINx film with the thickness of 50-150nm and the refractive index of 1.8-2.5 on the front surface of the substrate 1 by PECVD as an anti-reflection layer;
15. depositing a SINx film with the thickness of 50-150nm and the refractive index of 1.8-2.5 on the back surface of the substrate 1 by PECVD as a first passivation layer 7;
16. printing Ag/Al sizing agent on the fixed positions of the front and back surfaces of the substrate 1 by screen printing, and forming good ohmic contact by high-temperature sintering; h passivation is carried out through light injection, broken covalent bonds are repaired by H bonds, and passivation effect is improved; and finishing the manufacture of the solar cell.
The thickness of the first doped layer 5 of the coverage area of the first grid line electrode 6 of the manufactured solar cell is not changed, and the thickness of the first doped layer 5 of the coverage area of the non-first grid line electrode 6 on the back is thinned, so that parasitic absorption of light of the first doped layer 5 is reduced, short-circuit current is improved, and the metal grid line is ensured not to burn through the first doped layer 5.
Based on the above embodiment, referring to fig. 3, the present application further provides a photovoltaic module, including: a cell string 11 formed by connecting the solar cells, wherein adjacent cell strings 11 are connected to each other via a conductive tape such as a solder tape; an encapsulation layer 12, wherein the encapsulation layer 12 is used for covering the surface of the battery string 11; a cover plate 13, the cover plate 13 is used for covering the surface of the encapsulation layer 12 away from the battery strings 11.
In some embodiments, the number of battery strings 11 is at least two, and the battery strings 11 are electrically connected in parallel and/or in series.
In some embodiments, the encapsulation layer 12 includes an encapsulation layer 12 disposed on the front and back sides of the battery string 11, and the material of the encapsulation layer 12 includes, but is not limited to, EVA, POE, or PET, among others, adhesive films.
In some embodiments, the cover 13 includes cover 13 disposed on the front and back sides of the battery string 11, the cover 13 being selected from materials having good light transmission capabilities, including but not limited to glass, plastic, and the like.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (15)
1. A solar cell, comprising:
a substrate having a front surface and a back surface, the front surface and the back surface being disposed opposite in a first direction;
the first doping layer is positioned on the back surface of the substrate and comprises a main body part and a plurality of protruding parts protruding out of the main body part, the main body part is closer to the substrate than the protruding parts, the protruding parts extend along the first direction, the protruding parts are arranged at equal intervals along a second direction, and the plane in which the second direction is positioned is perpendicular to the plane in which the first direction is positioned;
a dielectric layer between the substrate and the first doped layer;
a second doped layer located on the front surface of the substrate;
a first gate line electrode electrically contacting the protrusion;
and a second gate line electrode electrically contacting the second doped layer.
2. The solar cell of claim 1, wherein: the protruding distance of the protruding portion along the first direction is 5-200nm.
3. The solar cell of claim 1, wherein: the width of the protruding part along the second direction is 50-200um.
4. The solar cell of claim 1, wherein: the ratio of the width of the protruding portion to the width of the main body portion in the second direction is 0.03% -0.12%.
5. The solar cell of claim 1, wherein: the ratio of the width of the protruding portion to the width of the first gate line electrode in the second direction is 1.5-5.
6. The solar cell of claim 1, wherein: the thickness of the main body part along the first direction is 1-100nm.
7. The solar cell of claim 1, wherein: the second doped layer comprises a first region and a second region, the doping concentration of the second doped layer at the first region is larger than that at the second region, and the second grid line electrode is electrically connected at the first region.
8. The solar cell of claim 5, wherein: the doping concentration at the first region is comprised between 5E+18 and 5E-19, and the junction depth is between 1.5 and 2.5 um.
9. The solar cell of claim 1, wherein: the dielectric layer includes at least one of silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, silicon oxynitride.
10. The solar cell of claim 1, wherein: the dielectric layers and the first doping layers are respectively provided with a plurality of layers, the dielectric layers and the first doping layers are sequentially and alternately arranged along the first direction, and the protruding parts are arranged on the first doping layers which are farthest from the substrate.
11. The solar cell of claim 1, wherein: the surface of the first doped layer, which is far away from one side of the substrate, is provided with a first passivation layer, the first grid line electrode penetrates through the first passivation layer and then is in electrical contact with the first doped layer, and the first passivation layer comprises at least one of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer and a silicon oxynitride layer.
12. The solar cell of claim 1, wherein: the surface of one side of the second doped layer, which is far away from the substrate, is provided with a second passivation layer, the second gate line electrode penetrates through the second passivation layer and then is in electrical contact with the second doped layer, and the second passivation layer comprises at least one of a silicon nitride layer, a silicon oxide layer and a silicon oxynitride layer.
13. The solar cell of claim 1, wherein: the number of the first grid line electrodes is 80-200, and the width is 30-40um.
14. The solar cell of claim 1, wherein: the number of the second grid line electrodes is 100-150, and the width is 20-30um.
15. A photovoltaic module, comprising:
a cell string formed by connecting the solar cells according to any one of claims 1 to 14;
an encapsulation layer for covering the surface of the battery string;
and the cover plate is used for covering the surface, far away from the battery strings, of the packaging layer.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117913164A (en) * | 2024-01-23 | 2024-04-19 | 滁州捷泰新能源科技有限公司 | Photovoltaic module containing TOPCon batteries and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117913164A (en) * | 2024-01-23 | 2024-04-19 | 滁州捷泰新能源科技有限公司 | Photovoltaic module containing TOPCon batteries and preparation method thereof |
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