CN114068740A

CN114068740A - Solar cell and battery pack

Info

Publication number: CN114068740A
Application number: CN202111390822.1A
Authority: CN
Inventors: 邱开富; 林文杰; 许文理; 王永谦; 陈刚
Original assignee: Zhejiang Aiko Solar Energy Technology Co Ltd; Guangdong Aiko Technology Co Ltd; Tianjin Aiko Solar Energy Technology Co Ltd; Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
Current assignee: Zhejiang Aiko Solar Energy Technology Co Ltd; Guangdong Aiko Technology Co Ltd; Tianjin Aiko Solar Energy Technology Co Ltd; Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
Priority date: 2021-11-23
Filing date: 2021-11-23
Publication date: 2022-02-18

Abstract

The solar cell comprises a silicon substrate, a first doping area and a first conducting layer which are sequentially arranged on the front surface of the silicon substrate, and a back surface passivation contact structure and a second conducting layer which are sequentially arranged on the back surface of the silicon substrate; the number of the first doping regions is multiple, the multiple first doping regions are spaced from each other, the doping polarity of the first doping regions is the same as that of the silicon substrate, the first conductive layer is in electric contact with the first doping regions, and the second conductive layer is in electric contact with the back passivation contact structure. Therefore, the first doping region with the same polarity as the silicon substrate adopts a local design, and most carriers can be transmitted to the first doping region through the body region of the silicon substrate, so that the first doping region does not need to be in contact with the whole surface of the silicon substrate, and the Auger recombination or parasitic absorption can be reduced. Meanwhile, the body region of the silicon substrate can be enabled to transport carriers more fully.

Description

Solar cell and battery pack

Technical Field

The application belongs to the technical field of solar cells, and particularly relates to a solar cell and a cell module.

Background

The electricity generated by the solar cell is a sustainable clean energy source, and the solar cell can convert sunlight into electric energy by utilizing the photovoltaic effect of a semiconductor p-n junction, so that the photoelectric conversion efficiency is an important index for measuring the performance of the solar cell. In a solar cell, the loss of photoelectric conversion efficiency includes both electrical loss and optical loss. The electrical loss mainly comprises recombination loss and resistance loss caused by metal-semiconductor contact, and the optical loss mainly comprises shielding of a light receiving surface metal grid line.

The double-sided contact back junction solar cell in the related art is generally designed to have an emitter in full-sided contact with a surface field to perform carrier transport, so as to reduce electrical loss and improve the photoelectric conversion efficiency of the solar cell.

However, this causes a large auger recombination or parasitic absorption, and leads to insufficient carrier transport in the bulk region of the silicon wafer, which makes it impossible to fully utilize the advantage of high quality of the existing silicon wafer. Based on this, how to make the body region of the silicon substrate fully transmit carriers and reduce auger recombination or parasitic absorption becomes a technical problem to be solved urgently.

Disclosure of Invention

The embodiment of the application provides a solar cell and a cell module, and aims to solve the problem of how to enable a body region of a silicon substrate to fully transmit carriers and reduce Auger recombination or parasitic absorption.

The solar cell of the embodiment of the application comprises: the semiconductor device comprises a silicon substrate, a first doping area and a first conducting layer which are sequentially arranged on the front surface of the silicon substrate, and a back passivation contact structure and a second conducting layer which are sequentially arranged on the back surface of the silicon substrate; the number of the first doping regions is multiple, the first doping regions are spaced from one another, the doping polarity of the first doping regions is the same as that of the silicon substrate, the first conductive layer is in electrical contact with the first doping regions, and the second conductive layer is in electrical contact with the back passivation contact structure.

Furthermore, the first doped region is provided with a conductive contact region, the first conductive layer is arranged on the conductive contact region, and the orthographic projection of the first conductive layer on the silicon substrate is completely overlapped with the conductive contact region.

Furthermore, the first doped region is further provided with a non-conductive contact region, and the area ratio of the non-conductive contact region to the first doped region ranges from 5% to 80%.

Furthermore, the area ratio of the non-conductive contact region to the first doped region ranges from 30% to 60%.

Furthermore, the first doped region is provided with a conductive contact region, the first conductive layer is arranged on the conductive contact region, and the orthographic projection of the first conductive layer on the silicon substrate covers and exceeds the conductive contact region.

Furthermore, the first conductive layer includes a first conductive portion and a second conductive portion, the first conductive portion protrudes from the second conductive portion to the first doped region, an orthographic projection of the first conductive portion on the silicon substrate is completely overlapped with the first doped region or is located in the first doped region, and a width of the orthographic projection of the second conductive portion on the silicon substrate is greater than a width of the orthographic projection of the first conductive portion on the silicon substrate.

Further, the width of the orthographic projection of the first conductive part on the silicon substrate ranges from 5 μm to 100 μm, and the width of the orthographic projection of the second conductive part on the silicon substrate ranges from 10 μm to 250 μm.

Further, the first conductive part, the second conductive part and the silicon substrate enclose a gap, and the height of the gap ranges from 5 μm to 50 μm.

Further, a first surface passivation layer is disposed in the gap.

Still further, the first surface passivation layer covers an area of the front surface area of the solar cell except for an orthographic projection of the first conductive portion on the silicon substrate.

Furthermore, the first conductive layer includes a third conductive portion and a fourth conductive portion, the third conductive portion at least partially covers the first doped region, the fourth conductive portion is disposed on the silicon substrate outside the first doped region, and the first surface passivation layer covers a region of the front surface region of the solar cell except for an orthographic projection of the first conductive layer on the silicon substrate.

Further, the back passivation contact structure is in full-face contact with the back of the silicon substrate.

Furthermore, the first conductive layer is disposed on the first doped region, and a non-doped region is disposed between the first doped regions.

Further, the first doped region is a monocrystalline doped layer.

Further, the first doped region includes a front passivation contact structure.

Further, the front passivation contact structure comprises a first doped layer, a first passivation layer and a second doped layer which are sequentially stacked on the silicon substrate.

Furthermore, the first passivation layer is a porous structure having the first doping layer and/or the second doping layer in a hole region, and the second doping layer is connected to the first doping layer through the doped hole region.

Still further, the porous structure has an average pore size of less than 1000 nm.

Further, the porous structure is prepared by means of thermal diffusion impact.

Further, the holes of the porous structure are distributed sparsely on the first passivation layer.

Further, the ratio of the area of the pore region of the porous structure to the overall area of the porous structure is less than 20%.

Furthermore, the first doping layer is discretely and locally distributed in each hole region of the passivation layer.

Still further, the first doped layer is disposed entirely continuously between the silicon substrate and the passivation layer.

Further, the front passivation contact structure comprises a second passivation layer and a third doped layer which are sequentially stacked on the silicon substrate.

The battery module of the embodiment of the application comprises the solar battery of any one of the above-mentioned.

The solar cell and the cell module of the embodiment of the application have the advantages that the first doping area with the same polarity as the silicon substrate adopts a local design, and most current carriers can be transmitted to the first doping area through the body area of the silicon substrate, so that the first doping area does not need to be in full-area contact with the silicon substrate, Auger recombination caused by the fact that a diffusion process is adopted to prepare a full-area surface field can be reduced, or parasitic absorption caused by the fact that a passivation contact structure is adopted as the full-area front surface field can be reduced. In one embodiment, the first doped region is provided with a conductive contact region and a non-conductive contact region, and the area ratio of the non-conductive contact region to the first doped region ranges from 30% to 60%, so that the difficulty of the metallization alignment process can be reduced. Meanwhile, the method can adapt to the trend that the quality of the silicon substrate is higher and higher, and the advantage of high quality of the silicon substrate is utilized, so that the body region of the silicon substrate can transport carriers more fully, and the method is favorable for simplifying the process flow and improving the conversion efficiency.

Drawings

Fig. 1-10 are schematic structural diagrams of various implementations of a solar cell according to an embodiment of the present disclosure.

Description of the main element symbols:

the solar cell comprises a solar cell 100, a silicon substrate 10, a first doped region 20, a conductive contact region 201, a non-conductive contact region 202, a non-doped region 21, a first doped layer 221, a first passivation layer 222, a second doped layer 223, a second passivation layer 231, a third doped layer 232, a first conductive layer 30, a first conductive portion 31, a second conductive portion 32, a third conductive portion 33, a fourth conductive portion 34, a back passivation contact structure 40, a second conductive layer 50, a first surface passivation layer 60 and a second surface passivation layer 70.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

In this application, unless expressly stated or limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, or integral connections; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

According to the method, the local design is adopted for the first doping area with the same polarity as the silicon substrate, and majority carriers can be transmitted to the first doping area through the body area of the silicon substrate, so that the first doping area does not need to be in contact with the whole surface of the silicon substrate, auger recombination caused by the fact that a diffusion process is adopted to prepare a full-area surface field can be reduced, or parasitic absorption caused by the fact that a passivation contact structure is adopted as the full-area front surface field can be reduced. Meanwhile, the method can adapt to the trend that the quality of the silicon substrate is higher and higher, and the advantage of high quality of the silicon substrate is utilized, so that the body region of the silicon substrate can transport carriers more fully, and the method is favorable for simplifying the process flow and improving the conversion efficiency.

Example one

The first embodiment of the present application provides a solar cell, and for convenience of illustration, only the portions related to the first embodiment of the present application are shown.

Referring to fig. 1, a solar cell 100 provided in an embodiment of the present application includes: the semiconductor device comprises a silicon substrate 10, a first doping region 20 and a first conducting layer 30 which are sequentially arranged on the front surface of the silicon substrate 10, and a back passivation contact structure 40 and a second conducting layer 50 which are sequentially arranged on the back surface of the silicon substrate 10; the number of the first doped regions 20 is plural, the plural first doped regions 20 are spaced apart from each other, the doping polarity of the first doped regions 20 is the same as that of the silicon substrate 10, the first conductive layer 30 is in electrical contact with the first doped regions 20, and the second conductive layer 50 is in electrical contact with the rear passivation contact structure 40.

In the solar cell 100 of the embodiment of the present application, since the first doped region 20 having the same polarity as the silicon substrate 10 adopts a local design, and most carriers can be transmitted to the first doped region 20 through the body region of the silicon substrate 10, the first doped region 20 does not need to be in contact with the entire surface of the silicon substrate 10, so that auger recombination caused by preparing a full-area surface field by using a diffusion process can be reduced, or parasitic absorption caused by using a passivation contact structure as a full-area front surface field can be reduced. Meanwhile, the method can adapt to the trend that the quality of the silicon substrate 10 is higher and higher, and the advantage of high quality of the silicon substrate 10 is utilized, so that the body region of the silicon substrate 10 can transport carriers more fully, and the method is favorable for simplifying the process flow and improving the conversion efficiency.

Specifically, the front surface is a light receiving surface of the solar cell 100, and the back surface is disposed on the other side of the silicon substrate 10 away from the front surface. That is, the front surface and the back surface are located on opposite sides of the silicon substrate 10. In the present embodiment, the silicon substrate 10 is an N-type single crystal silicon wafer. It is understood that in other embodiments, the silicon substrate 10 may be a polysilicon wafer or a quasi-monocrystalline silicon wafer, and the silicon substrate 10 may also be P-type. In this manner, the silicon substrate 10 may be provided according to actual use requirements, and the specific form of the silicon substrate 10 is not limited herein.

Specifically, the front surface of the silicon substrate 10 may be formed with an anti-reflection structure. Such as random pyramid structures, inverted pyramid structures, spherical cap structures, V-groove structures. The anti-reflection structure may be formed by texturing on the front surface of the silicon substrate 10. Therefore, the reflection of sunlight from the front can be reduced, and the photoelectric conversion efficiency can be improved.

Specifically, the back surface of the silicon substrate 10 may be a polished surface. For example, an alkaline polishing surface, an acid polishing surface, a mechanical polishing surface, and the like.

Specifically, "the doping polarity of the first doping region 20 is the same as the polarity of the silicon substrate 10" means that: in the case where the polarity of the silicon substrate 10 is N-type, the doping polarity of the first doping region 20 is also N-type; in the case where the polarity of the silicon substrate 10 is P-type, the doping polarity of the first doping region 20 is also P-type.

Specifically, the number of the first doping regions 20 may be 2, 3, 4, 5 or other values, and the specific number of the first doping regions 20 is not limited herein.

Specifically, referring to fig. 1, in the present embodiment, the orthographic projection of the first doped region 20 on the silicon substrate 10 covers and exceeds the orthographic projection of the first conductive layer 30 on the silicon substrate 10. In other embodiments, the orthographic projection of the first doped region 20 on the silicon substrate 10 may completely overlap with the orthographic projection of the first conductive layer 30 on the silicon substrate 10; the orthographic projection of the first doped region 20 on the silicon substrate 10 can also be partially overlapped with the orthographic projection of the first conductive layer 30 on the silicon substrate 10; it is also possible that the orthographic projection of the first doped region 20 on the silicon substrate 10 is located within the orthographic projection of the first conductive layer 30 on the silicon substrate 10. The specific positional relationship of the first doped region 20 and the first conductive layer 30 is not limited herein. In addition, the relationship between the first doped regions 20 and the corresponding first conductive layers 30 may be the same, different, or partially the same.

Specifically, referring to fig. 1, in the present embodiment, the lengths, widths, and thicknesses of the first doping regions 20 are the same, that is, the sizes of the first doping regions 20 are the same. In other embodiments, the lengths of the first doping regions 20 may all be different or partially the same; the widths of the first doping regions 20 may all be different or partially the same; the thicknesses of the plurality of first doping regions 20 may all be different or partially the same. The specific dimensional relationship of the plurality of first doping regions 20 is not limited herein.

Specifically, the width of the first doping region 20 is 20 μm to 200 μm. Examples thereof include 20 μm, 21 μm, 25 μm, 30 μm, 50 μm, 100 μm, 150 μm, 198 μm and 200 μm.

Specifically, the thickness of the first doped region 20 is 0.1 μm to 10 μm. For example, 0.1. mu.m, 0.15. mu.m, 0.2. mu.m, 1. mu.m, 3. mu.m, 5. mu.m, 8. mu.m, 9. mu.m, 10 μm.

Specifically, the distance between two adjacent first doping regions 20 is 0.1mm to 10 mm. For example, 0.1mm, 0.11mm, 0.15mm, 0.5mm, 1mm, 2mm, 5mm, 8mm, 10 mm.

Referring to fig. 1, optionally, a backside passivation contact structure 40 is in full-face contact with the backside of the silicon substrate 10. In this way, a good passivation effect is provided for the back surface of the silicon substrate 10.

Specifically, the back passivation contact structure 40 includes a back passivation layer and a back doped layer sequentially disposed on the silicon substrate 10. Further, the back passivation layer includes one or more of a tunneling oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer. Further, the back side doping layer comprises one or more of a doped silicon carbide layer and a doped amorphous silicon layer. Thus, the back passivation layer is disposed between the silicon substrate 10 and the back doped layer, and is used as a tunneling structure, the back passivation layer enables one type of carriers to realize selective transmission through a tunneling principle, and the other type of carriers is difficult to tunnel through the back passivation layer due to the existence of the potential barrier and the field effect of the back doped layer. Therefore, the back passivation layer can enable one type of carrier to tunnel into the back doping layer and block the other type of carrier from passing through, the recombination of an interface can be obviously reduced, the solar cell has high open-circuit voltage and short-circuit current, and the photoelectric conversion efficiency is improved.

Referring to fig. 1, optionally, the first conductive layer 30 is disposed on the first doped regions 20, and the non-doped regions 21 are disposed between the first doped regions 20. It is understood that the undoped region 21 refers to a region that is not doped on the silicon substrate 10. Therefore, the interval between two adjacent first doping regions 20 is realized through the non-doping region 21, and a groove, a boss, a groove or an insulating part is not required to be arranged between two adjacent first doping regions 20, so that the production efficiency is improved. Further, the plurality of first doped regions 20 may be formed by high temperature diffusion, and a surface passivation layer such as a silicon nitride layer may be formed on the undoped region 21 before the high temperature diffusion, thereby improving minority carrier lifetime.

Specifically, referring to fig. 2, a plurality of grooves may be formed at intervals on the front surface of the silicon substrate 10, a plurality of first doped regions 20 are disposed in each groove, and a boss-shaped undoped region 21 is formed in a region between two adjacent grooves. In this way, the spacing of the first doping regions 20 disposed in two adjacent grooves can be achieved. Further, the recess may be formed by laser ablation or by a combination of a mask (e.g., a hard mask, a silicon oxide mask, a silicon nitride mask, a photoresist mask, etc.) and wet/dry etching. Further, the groove may be rectangular, circular arc, trapezoidal, or square. The plurality of grooves may all be the same shape, all be different, or be partially the same and partially different.

Referring to fig. 3, in another embodiment, a plurality of grooves are formed at intervals on the front surface of the silicon substrate 10, a boss is formed in a region between two adjacent grooves, one of two adjacent first doping regions 20 is disposed in the groove, and the other is disposed on the boss. Thus, the interval between the adjacent two first doping regions 20 is realized by the height difference between the groove and the boss.

Referring to fig. 4, in another embodiment, a plurality of grooves are formed at intervals on the front surface of the silicon substrate 10, a boss is formed in a region between two adjacent grooves, and a plurality of first doping regions 20 are disposed on each boss. Thus, the spacing between two adjacent first doping regions 20 is achieved by the groove between the bumps.

In other embodiments, a trench may be disposed between two adjacent first doping regions 20. In this way, the spacing of two adjacent first doping regions 20 is achieved by the trench.

In other embodiments, an insulating member may be disposed between two adjacent first doping regions 20. In this way, the spacing of two adjacent first doping regions 20 is achieved by the insulating member. Further, the insulator includes at least one of EPE (pearl wool), EVA (ethylene-vinyl acetate copolymer), and PET (polyethylene glycol terephthalate). Therefore, the buffer function can be achieved while insulation is achieved, and battery protection is facilitated.

Referring to fig. 1, the first doped region 20 is optionally a monocrystalline doped layer. It is understood that the first doped region 20 is a diffusion structure formed on the silicon substrate 10 by doping different types of diffusion sources, and the first doped region 20 is not formed by growing on the basis of the silicon substrate 10, but the silicon substrate 10 is partially diffused into the first doped region 20. Thus, the first doping region 20 has a simple structure, which is beneficial to improving the production efficiency.

In particular, the monocrystalline doped layer may be formed by diffusion, ion implantation, source diffusion, or other processes.

Specifically, when the polarity of the silicon substrate 10 is N-type, the doping polarity of the first doping region 20 is also N-type, and a single crystal doping layer may be formed by doping nitrogen, phosphorus, arsenic, or the like on the silicon substrate 10. In this way, the N-type single crystal doped layer is an N + + layer with respect to the N-type silicon substrate 10, and the single crystal doped layer and the silicon substrate 10 form a high-low junction.

Specifically, when the polarity of the silicon substrate 10 is P-type, the doping polarity of the first doping region 20 is also P-type, and boron, aluminum, gallium, or the like may be doped on the silicon substrate 10 to form a single crystal doping layer. In this way, the P-type single crystal doped layer is a P + + layer with respect to the P-type silicon substrate 10, and the single crystal doped layer and the silicon substrate 10 form a high-low junction.

Referring to fig. 5 and 6, the first doped region 20 may optionally include a front passivation contact structure. In this way, contact resistivity and surface recombination can be reduced.

Referring to fig. 5, optionally, the front passivation contact structure includes a first doped layer 221, a first passivation layer 222 and a second doped layer 223 sequentially stacked on the silicon substrate 10. Thus, the arrangement of the front passivation contact structure is realized, and double gettering can be performed through the first doping layer 221 and the second doping layer 223, so that the gettering effect is better.

Specifically, in the case where the polarity of the silicon substrate 10 is N-type, the doping polarities of the first doping layer 221 and the second doping layer 223 are also N-type; in the case where the polarity of the silicon substrate 10 is P-type, the doping polarities of the first and second doping layers 221 and 223 are also P-type.

Specifically, the thickness of the first doping layer 221 ranges from 50nm to 2000 nm. For example, 50nm, 51nm, 60nm, 100nm, 500nm, 1000nm, 1500nm, 1900nm, 2000 nm. In this way, contact resistance can be reduced and a field passivation effect can be provided.

Specifically, the first doping layer 221 is a doped monocrystalline silicon layer. Further, the first doping layer 221 may be formed by diffusion, ion implantation, source diffusion, or other processes; the first doping layer 221 may also be formed in the silicon substrate 10 by making a doping source directly through the first passivation layer 222 or through a hole in the porous structure when the second doping layer 223 is prepared.

Specifically, the thickness of the first passivation layer 222 is 0.5nm to 20 nm. For example, 0.5nm, 0.6nm, 1nm, 1.5nm, 5nm, 10nm, 12nm, 15nm, 18nm, 20 nm.

Specifically, the first passivation layer 222 includes one or more of an oxide layer, a nitride oxide layer, a silicon carbide layer, and an amorphous silicon layer. Further, the oxide layer comprises one or more of a silicon oxide layer and an aluminum oxide layer. Thus, an excellent interface passivation effect can be provided.

Further, the silicon carbide layer comprises a hydrogenated silicon carbide layer. Thus, hydrogen in the hydrogenated silicon carbide layer enters the silicon substrate 10 under the action of a diffusion mechanism and a thermal effect, dangling bonds on the back surface of the silicon substrate 10 can be neutralized, and defects of the silicon substrate 10 are passivated, so that defect energy levels in forbidden bands are reduced, and the probability that carriers enter the second doping layer 223 through the first passivation layer 222 is improved.

Specifically, the first passivation layer 222 is a porous structure having the first doping layer 221 and/or the second doping layer 223 in the hole region, and the second doping layer 223 is connected to the first doping layer 221 through the doped hole region. Further, the second doping layer 223 is connected to the silicon substrate 10 through the doped hole region and the first doping layer 221.

In this manner, a conductive channel is formed in the hole region of the first passivation layer 222, such that the first passivation layer 222 forms a good resistivity, and the sensitivity of the thickness of the first passivation layer 222 to the effect of resistance is reduced, thereby reducing the control requirement for the thickness of the first passivation layer 222. Meanwhile, the first doping layer 221 disposed between the silicon substrate 10 and the first passivation layer 222 may form a separation electric field for enhancing surface electron holes, thereby improving a field passivation effect. Meanwhile, since the first doping layer 221 has a different fermi level from that of the silicon substrate 10, the first doping layer 221 changes the fermi level, increases the solid concentration of impurities (transition group metals), and may form an additional gettering effect. Meanwhile, the second doping layer 223 is connected with the silicon substrate 10 through the doped hole region and the first doping layer 221 on the porous structure, so that the overall resistance of the prepared battery is further reduced, and the conversion efficiency of the battery is finally improved.

In one example, the hole region has the first doping layer 221 therein and does not have the second doping layer 223; in another example, the hole region has the second doping layer 223 therein, without the first doping layer 221; in yet another example, the hole region has a first doping layer 221 and a second doping layer 223 therein. In addition, the first doping layer 221 and/or the second doping layer 223 may fill one or more holes, or may fill a part of one or more holes, or some holes may not fill the first doping layer 221 and the second doping layer 223. The specific doping profile of the void region is not limited herein.

It is understood that in other embodiments, the first passivation layer 222 may also be a completely continuous structure. In other words, the first passivation layer 222 may not include a hole.

Further, the average pore size of the porous structure is less than 1000 nm. Examples thereof include 4nm, 10nm, 16nm, 50nm, 480nm, 830nm, 960nm and 999 nm. As such, the average pore diameter of the porous structure is in the order of nanometers, so that the overall contact area of the second doping layer 223 and the silicon substrate 10 is greatly reduced, and recombination loss can be reduced. Still further, the porous structure has an average pore size of less than 500 nm. As such, the overall contact area of the second doped layer 223 and the silicon substrate 10 is further reduced, thereby further reducing recombination losses. Still further, 90% of the through-holes may have an average pore size of less than 1000 nm. Therefore, a certain floating space is provided, the product yield can be guaranteed under the condition of ensuring small composite loss, the production efficiency is improved, extra processes such as laser hole opening are not needed to be added, and the preparation process is simple.

Further, the porous structure is prepared by means of thermal diffusion impact. Specifically, the temperature range of the thermal diffusion impact is 500 ℃ to 1200 ℃. For example, 500 deg.C, 510 deg.C, 550 deg.C, 600 deg.C, 700 deg.C, 800 deg.C, 820 deg.C, 900 deg.C, 950 deg.C, 1000 deg.C, 1050 deg.C, 1100 deg.C, 1150 deg.C, 1200 deg.C. Preferably, the thermal diffusion impact temperature is from 800 ℃ to 1100 ℃. For example, 800 deg.C, 820 deg.C, 900 deg.C, 950 deg.C, 1000 deg.C, 1050 deg.C, 1100 deg.C. Therefore, the formed porous structure has smaller holes, the average pore diameter is less than 1000nm, and the composite loss is favorably reduced. Moreover, the surface density of the holes is higher and can reach 10⁶-10⁸/cm²The transverse transport distance can be reduced, the current crowding effect is eliminated, the resistance loss is reduced, and the resistance reducing effect is better. It is understood that in other embodiments, the porous structure may be formed by chemical etching, dry etching, or other means.

Further, the holes of the porous structure are sparsely distributed on the first passivation layer 222. Therefore, the distribution state of the holes does not need to be strictly controlled, and the production efficiency is favorably improved.

Further, the ratio of the area of the pore region of the porous structure to the overall area of the porous structure is less than 20%. In this way, the total area of the hole region is controlled by the area ratio of the hole region, so that the total contact area between the second doping layer 223 and the silicon substrate 10 is small, and the recombination loss is reduced under the condition of ensuring low contact resistance.

Further, the first doping layer 221 is discretely and locally distributed in each hole region of the first passivation layer 222. Thus, even in the case that the first doping layer 221 is discretely distributed, the orthographic projection of the hole of the first passivation layer 222 on the silicon substrate 10 can be covered by the orthographic projection of the first doping layer 221 on the silicon substrate 10, so that the second doping layer 223 cannot directly contact the silicon substrate 10, and the serious recombination caused by the second doping layer 223 directly contacting the silicon substrate 10 is avoided.

Further, the first doping layer 221 is completely continuously disposed between the silicon substrate 10 and the first passivation layer 222. Thus, since the first doping layer 221 is completely and continuously disposed, the orthographic projection of the hole of the first passivation layer 222 on the silicon substrate 10 is inevitably covered by the orthographic projection of the first doping layer 221 on the silicon substrate 10, and the second doping layer 223 cannot be in direct contact with the silicon substrate 10, thereby avoiding the serious recombination caused by the direct contact of the second doping layer 223 with the silicon substrate 10.

Further, the profile of the first doping layer 221 can be controlled by the doping duration. The longer the doping time, the more the doping amount, the higher the proportion of the first doping layer 221 that continues until a completely covered layer of the first doping layer 221 is formed on the silicon substrate 10. Further, the junction depth of the first doped layer 221 is less than 1.5 um. Thus, contact resistance can be reduced, and field effect passivation can be improved.

Specifically, the thickness of the second doped layer 223 ranges from 0nm to 500 nm. For example, 0.1nm, 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500 nm. Thus, the thickness range of the second doped layer 223 is wide, and the second doped layer can meet different requirements in actual production.

Preferably, the thickness of the second doped layer 223 ranges from 100nm to 500 nm. Examples thereof include 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm and 500 nm. Thus, the thicker second doping layer 223 can prevent the conducting layer from burning through the second doping layer 223, reduce contact recombination, improve open-circuit voltage, improve process width and ensure product yield.

Specifically, the second doping layer 223 includes a doped polysilicon layer, a doped silicon carbide layer, or a doped amorphous silicon layer. Preferably, the second doped layer 223 comprises a doped silicon carbide layer. Thus, the silicon carbide material has wide optical band gap and low absorption coefficient, so that parasitic absorption can be reduced, and the short-circuit current density can be effectively improved. Further, the doped silicon carbide layer is composed of at least one doped silicon carbide film having different refractive indexes, and the refractive indexes of the doped silicon carbide films are sequentially decreased from the silicon substrate 10 to the outside. Thus, a gradient of refractive index can be formed, and a gradient extinction effect can be formed. Further, the doped silicon carbide layer in the second doped layer 223 includes a doped hydrogenated silicon carbide layer having a conductivity of greater than 0.01S-cm and a thickness of greater than 10 nm. Thus, the conductivity requirement of the second doped layer 223 can be satisfied, and the parasitic absorption is lower, thereby increasing the short-circuit current.

Referring to fig. 6, optionally, the front passivation contact structure includes a second passivation layer 231 and a third doped layer 232 sequentially stacked on the silicon substrate 10.

Thus, the arrangement of the front passivation contact structure is realized. It is understood that the second passivation layer 231 is disposed between the silicon substrate 10 and the third doped layer 232, and when used as a tunneling structure, the second passivation layer 231 allows selective transport of one carrier through the tunneling principle, while the other carrier is difficult to tunnel through the second passivation layer 231 due to the potential barrier and the field effect of the third doped layer 232. Thus, one carrier can tunnel into the third doping layer 232 and block the other carrier from passing through, and recombination of the interface can be significantly reduced, so that the solar cell 100 has higher open-circuit voltage and short-circuit current, and the photoelectric conversion efficiency is improved.

Specifically, the thickness of the second passivation layer 231 ranges from 0.1nm to 20 nm. For example, 0.1nm, 0.2nm, 0.5nm, 1nm, 5nm, 10nm, 15nm, 19nm, 20 nm.

Specifically, the second passivation layer 231 includes one or more of intrinsic amorphous silicon, intrinsic silicon carbide. Preferably, the second passivation layer 231 is an intrinsic silicon carbide layer. Thus, the silicon carbide material has wide optical band gap and low absorption coefficient, so that parasitic absorption can be reduced, and the short-circuit current density can be effectively improved.

Further, when the second passivation layer 231 is an intrinsic silicon carbide layer, it can be prepared by a Hot Wire Chemical Vapor Deposition (HWCVD) method, wherein the temperature of the Hot Wire is preferably 1500-H₃(CH₃) And H₂Or may also include N₂At this time N₂Does not participate in the reaction at a temperature lower than 1800 ℃.

Further, when the second passivation layer 231 is an intrinsic silicon carbide layer, it can be prepared by Plasma Enhanced Chemical Vapor Deposition (PECVD), wherein the Deposition temperature is 100-₄And CH₄And CH thereof₄Flow rate of (1) and SiH₄And CH₄Total flow ratio of CH₄/(SiH₄+CH₄) Is 0.1-1.

Specifically, the thickness of the third doped layer 232 ranges from 10nm to 300 nm. For example, 10nm, 11nm, 15nm, 20nm, 50nm, 100nm, 150nm, 180nm, 200nm, 250nm, 290nm, 300 nm.

Specifically, third doped layer 232 includes one or more of doped amorphous silicon, doped silicon carbide. Preferably, third doped layer 232 is a doped silicon carbide layer. Because the silicon carbide material has wide optical band gap and low absorption coefficient, the parasitic absorption can be reduced, and the short-circuit current density can be effectively improved. Further, the doped silicon carbide layer is composed of at least one doped silicon carbide film having different refractive indexes, and the refractive indexes of the doped silicon carbide films are sequentially decreased from the silicon substrate 10 to the outside. Thus, a gradient of refractive index can be formed, and a gradient extinction effect can be formed. Further, the doped silicon carbide layer in third doped layer 232 comprises a doped hydrogenated silicon carbide layer having a conductivity greater than 0.01S-cm and a thickness greater than 10 nm. Therefore, the conductivity requirement of the third doped layer 232 can be met, the parasitic absorption is lower, and the short-circuit current is improved.

Specifically, the surface of the silicon substrate 10 in contact with the second passivation layer 231 forms a plurality of inter-diffusion regions corresponding to the third doped layer 232. It can be understood that, during the process of preparing the third doping layer 232, due to the high temperature process, the thinner second passivation layer 231 may be partially broken, and at this time, the second passivation layer 231 and the silicon substrate 10 may be attached at the broken position during the high temperature diffusion process, so that a plurality of inner diffusion regions corresponding to the third doping layer 232 are formed on the surface of the silicon substrate 10 in contact with the second passivation layer 231.

Specifically, a tunnel oxide layer may be further disposed between the second passivation layer 231 and the silicon substrate 10.

Further, the thickness of the tunneling oxide layer is less than 3 nm. For example, 0.1nm, 0.5nm, 0.8nm, 1nm, 1.2nm, 1.5nm, 2nm, 2.3nm, 2.8nm, 3 nm.

Further, the tunneling oxide layer comprises one or more of a silicon oxide layer and an aluminum oxide layer. Preferably, the tunneling oxide layer is a silicon oxide layer. As such, the silicon oxide layer and the second passivation layer 231 may reduce the interface state density between the silicon substrate 10 and the third doped layer 232 through chemical passivation.

Further, the tunnel oxide layer may be prepared by thermal oxidation and solution oxidation. Further, in the case of preparing the tunnel oxide layer by thermal oxidation, oxygen and nitrogen may be introduced at 800 ℃ and 500 ℃ for thermal oxidation for 5-30min, thereby forming a silicon oxide layer on the silicon substrate 10. In the case of preparing a tunnel oxide layer by solution oxidation, H in a solution ratio of 4:1 to 1:4 may be used₂SO₄And H₂O₂The mixed solution of the solutions is subjected to oxidation preparation, thereby forming a silicon oxide layer on the silicon substrate 10.

Referring to fig. 1, the first conductive layer 30 may optionally include a Transparent Conductive Oxide (TCO). Thus, the TCO can effectively collect the current of the solar cell 100, and ensure the normal operation of the solar cell 100. Moreover, the TCO has high permeability and can reflect light, so that the loss of sunlight can be reduced. Thus, the photoelectric conversion efficiency is advantageously improved.

Further, the TCO includes one or more of fluorine-doped tin oxide (FTO), Indium Zinc Oxide (IZO), Indium Tin Oxide (ITO), aluminum-doped zinc oxide (AZO), aluminum-doped tin oxide (ATO), and IGO-indium-doped gallium oxide (IGO). It is understood that the first conductive layer 30 may also include metals such as silver, gold, aluminum, copper, molybdenum, tungsten, nickel, magnesium, tin, tantalum, and the like. The first conductive layer 30 may also include TCO and metal electrodes.

Note that the explanation and description of the second conductive layer 50 can refer to the explanation and description of the first conductive layer 30, and are not repeated herein to avoid redundancy.

Referring to fig. 7, optionally, the solar cell 100 may further include a first surface passivation layer 60 and a second surface passivation layer 70, wherein the first surface passivation layer 60 is disposed between the plurality of first conductive layers 30, and the second surface passivation layer 70 is disposed between the plurality of second conductive layers 50. Thus, it is possible to reduce reflection and reduce the surface recombination rate.

Specifically, the first surface passivation layer 60 includes one or more of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, an amorphous silicon layer, and a silicon oxide layer. Similarly, the second surface passivation layer 70 includes one or more of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, an amorphous silicon layer, and a silicon oxide layer.

Specifically, the first surface passivation layer 60 may be composed of at least one passivation film having different refractive indexes, and the refractive indexes of the passivation films are sequentially decreased from the silicon substrate 10 outward. Similarly, the second surface passivation layer 70 may be composed of at least one passivation film having different refractive indexes, and the refractive indexes of the passivation films are sequentially decreased from the silicon substrate 10 outward. Thus, a gradient of refractive index can be formed, and a gradient extinction effect can be formed.

Referring to fig. 7, optionally, the first doped region 20 is provided with a conductive contact region 201, the first conductive layer 30 is disposed on the conductive contact region 201, and the orthographic projection of the first conductive layer 30 on the silicon substrate 10 completely overlaps the conductive contact region 201. In this way, by providing the conductive contact region 201, the position of the metal contact region between the first conductive layer 30 and the first doped region 20 is more accurate. Moreover, since the orthographic projection of the first conductive layer 30 on the silicon substrate 10 is completely overlapped with the conductive contact region 201, the material consumption of the first conductive layer 30 is less and the light shielding area is smaller while better metal contact is ensured.

Specifically, the first doped region 20 is further provided with a non-conductive contact region 202, and the area ratio of the non-conductive contact region 202 to the first doped region 20 is in the range of 5% -80%. For example, 5%, 5.2%, 8%, 10%, 15%, 20%, 28%, 30%, 40%, 55%, 60%, 68%, 70%, 78%, 80%. Therefore, the difficulty of the metallization alignment process can be reduced, and the production efficiency is improved.

Preferably, the area ratio of the non-conductive contact region 202 to the first doped region 20 ranges from 30% to 60%. For example, 30%, 32%, 35%, 38%, 40%, 41%, 45%, 47%, 50%, 55%, 59%, 60%. Therefore, the difficulty of the metallization aligning process can be further reduced, and the production efficiency is further improved.

Referring to fig. 8 and 10, optionally, the first doped region 20 is provided with a conductive contact region 201, the first conductive layer 30 is disposed on the conductive contact region 201, and the first conductive layer 30 covers and exceeds the conductive contact region 201 in the orthographic projection of the silicon substrate 10. Therefore, the width of the first conductive layer 30 is wider, so as to provide tolerance for the alignment of the first conductive layer 30 and the conductive contact region 201, which is beneficial to improving the yield of the battery.

Referring to fig. 8, optionally, the first conductive layer 30 includes a first conductive portion 31 and a second conductive portion 32, the first conductive portion 31 protrudes from the second conductive portion 32 to the first doped region 20, an orthogonal projection of the first conductive portion 31 on the silicon substrate 10 is completely overlapped with the first doped region 20 or is located in the first doped region 20, and a width of the orthogonal projection of the second conductive portion 32 on the silicon substrate 10 is greater than a width of the orthogonal projection of the first conductive portion 31 on the silicon substrate 10. Thus, the width of the second conductive portion 32 is wider, which facilitates the fabrication of the first conductive layer 30. It is understood that the region where the first conductive portion 31 contacts the first doped region 20 is a conductive contact region 201.

Specifically, "the first conductive parts 31 completely overlap with the first doped regions 20 or are located in the first doped regions 20 in the orthographic projection of the silicon substrate 10" means that all the first conductive parts 31 completely overlap with the corresponding first doped regions 20 in the orthographic projection of the silicon substrate 10; or, all the first conductive parts 31 are located in the corresponding first doped regions 20 in the orthographic projection of the silicon substrate 10; or, a part of the first conductive part 31 completely overlaps the corresponding first doped region 20 in the orthographic projection of the silicon substrate 10, and a part of the first conductive part 31 is located in the corresponding first doped region 20 in the orthographic projection of the silicon substrate 10.

Specifically, the width of the orthographic projection of the first conductive part 31 on the silicon substrate 10 ranges from 5 μm to 100 μm. Examples thereof include 5 μm, 6 μm, 10 μm, 15 μm, 30 μm, 50 μm, 80 μm, 95 μm and 100 μm.

Preferably, the width of the orthographic projection of the first conductive part 31 on the silicon substrate 10 is 30 μm.

Specifically, the width of the orthogonal projection of the second conductive portion 32 on the silicon substrate 10 ranges from 10 μm to 250 μm. For example, 10 μm, 12 μm, 15 μm, 20 μm, 50 μm, 86 μm, 100 μm, 125 μm, 150 μm, 200 μm, 250 μm.

Preferably, the width of the orthogonal projection of the second conductive portion 32 on the silicon substrate 10 is 86 μm.

Specifically, the first conductive portion 31, the second conductive portion 32, and the silicon substrate 10 enclose a gap, and the height of the gap ranges from 5 μm to 50 μm. Examples thereof include 5 μm, 8 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 45 μm and 50 μm.

Specifically, a first surface passivation layer 60 is disposed in the gap. In this way, the gap may be filled with the first surface passivation layer 60 for spacing, thereby preventing leakage.

Further, the first surface passivation layer 60 covers a region of the front surface area of the solar cell 100 except for an orthographic projection of the first conductive part 31 on the silicon substrate 10. Thus, electric leakage can be sufficiently avoided, reflection can be sufficiently reduced, and the surface recombination rate can be reduced.

Specifically, the thickness of the first conductive layer 30 ranges from 30 μm to 60 μm. Examples thereof include 30 μm, 32 μm, 35 μm, 38 μm, 40 μm, 41 μm, 44 μm, 50 μm, 55 μm and 60 μm.

Preferably, the thickness of the first conductive layer 30 is 44 μm.

Specifically, in fig. 8, the first conductive portion 31 is located at the middle position of the second conductive portion 32. It is understood that in other embodiments, the first conductive portion 31 may be located at an edge position of the second conductive portion 32.

Specifically, in fig. 8, the second conductive portion 32 contacts the first surface passivation layer 60. In other words, the first surface passivation layer 60 completely fills the gap enclosed by the first conductive part 31, the second conductive part 32 and the silicon substrate 10. Thus, accumulation of dust, moisture, and the like in the gap is prevented.

Referring to fig. 9, optionally, a gap may be formed between the second conductive portion 32 and the first surface passivation layer 60. In other words, the first surface passivation layer 60 partially fills the gap enclosed by the first conductive part 31, the second conductive part 32 and the silicon substrate 10. Thus, the reflected sunlight can be reflected back to the silicon substrate 10 through the first conductive layer 30, thereby improving the photoelectric conversion efficiency.

Specifically, the heights of the gaps corresponding to the plurality of second conductive portions 32 may be the same or different. And are not limited herein.

Referring to fig. 10, the first conductive layer 30 includes a third conductive portion 33 and a fourth conductive portion 34, the third conductive portion 33 at least partially covers the first doped region 20, the fourth conductive portion 34 is disposed on the silicon substrate 10 outside the first doped region 20, and the first surface passivation layer 60 covers a front surface area of the solar cell 100 except for an orthographic projection of the first conductive layer 30 on the silicon substrate 10. Thus, the projection of the first conductive layer 30 on the silicon substrate and the first doped region 20 have an overlapping portion, which ensures the contact between the first conductive layer 30 and the first doped region 20.

Specifically, "the third conductive portion 33 at least partially covers the first doped region 20" means that the third conductive portion 33 partially covers the first doped region 20, as shown in the right first conductive layer 30 in fig. 10; alternatively, the third conductive portion 33 entirely covers the first doped region 20, as shown in the left and middle first conductive layers 30 in fig. 10.

In this embodiment, since the first doped region 20 having the same polarity as the silicon substrate 10 is designed locally, and most carriers can be transmitted to the first doped region 20 through the body region of the silicon substrate 10, the first doped region 20 does not need to be in contact with the entire surface of the silicon substrate 10, so that auger recombination caused by preparing a full-area surface field by using a diffusion process can be reduced, or parasitic absorption caused by using a passivation contact structure as a full-area front surface field can be reduced. Meanwhile, the method can adapt to the trend that the quality of the silicon substrate 10 is higher and higher, and the advantage of high quality of the silicon substrate 10 is utilized, so that the body region of the silicon substrate 10 can transport carriers more fully, and the method is favorable for simplifying the process flow and improving the conversion efficiency.

Example two

The second embodiment of the present application further provides a battery assembly, which includes the solar cell 100 of the first embodiment.

In the second cell module of the embodiment of the present application, the first doping region 20 having the same polarity as the silicon substrate 10 in the solar cell 100 is designed locally, and most carriers can be transmitted to the first doping region 20 through the body region of the silicon substrate 10, so that the first doping region 20 does not need to be in full-surface contact with the silicon substrate 10, thereby reducing auger recombination caused by preparing a full-area surface field by using a diffusion process, or reducing parasitic absorption caused by using a passivation contact structure as a full-area front surface field. Meanwhile, the method can adapt to the trend that the quality of the silicon substrate 10 is higher and higher, and the advantage of high quality of the silicon substrate 10 is utilized, so that the body region of the silicon substrate 10 can transport carriers more fully, and the method is favorable for simplifying the process flow and improving the conversion efficiency.

For further explanation and explanation of this section, reference is made to the foregoing description, and further explanation is omitted here to avoid redundancy.

The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

Claims

1. A solar cell, comprising: the semiconductor device comprises a silicon substrate, a first doping area and a first conducting layer which are sequentially arranged on the front surface of the silicon substrate, and a back passivation contact structure and a second conducting layer which are sequentially arranged on the back surface of the silicon substrate; the number of the first doping regions is multiple, the first doping regions are spaced from one another, the doping polarity of the first doping regions is the same as that of the silicon substrate, the first conductive layer is in electrical contact with the first doping regions, and the second conductive layer is in electrical contact with the back passivation contact structure.

2. The solar cell of claim 1, wherein the first doped region is provided with an electrically conductive contact region, the first conductive layer being provided on the electrically conductive contact region, the first conductive layer completely overlapping the electrically conductive contact region in an orthographic projection of the silicon substrate.

3. The solar cell of claim 2, wherein the first doped region is further provided with a non-conductive contact region, and an area ratio of the non-conductive contact region to the first doped region ranges from 5% to 80%.

4. The solar cell of claim 3, wherein an area ratio of the non-conductive contact region to the first doped region ranges from 30% to 60%.

5. The solar cell of claim 1, wherein the first doped region is provided with an electrically conductive contact region, the first conductive layer being disposed on the electrically conductive contact region, the first conductive layer covering and extending beyond the electrically conductive contact region in an orthographic projection of the silicon substrate.

6. The solar cell according to claim 1, wherein the first conductive layer includes a first conductive portion and a second conductive portion, the first conductive portion protrudes from the second conductive portion toward the first doped region, an orthographic projection of the first conductive portion on the silicon substrate completely overlaps with or is located within the first doped region, and a width of the orthographic projection of the second conductive portion on the silicon substrate is larger than a width of the orthographic projection of the first conductive portion on the silicon substrate.

7. The solar cell according to claim 6, wherein a width of an orthogonal projection of the first conductive portion on the silicon substrate is in a range of 5 μm to 100 μm, and a width of an orthogonal projection of the second conductive portion on the silicon substrate is in a range of 10 μm to 250 μm.

8. The solar cell of claim 7, wherein the first conductive portion, the second conductive portion, and the silicon substrate enclose a gap having a height in a range of 5 μ ι η to 50 μ ι η.

9. The solar cell of claim 8, wherein a first surface passivation layer is disposed in the gap.

10. The solar cell of claim 6, wherein the first surface passivation layer covers an area of the front surface area of the solar cell other than an orthographic projection of the first conductive portion on the silicon substrate.

11. The solar cell of claim 1, wherein the first conductive layer comprises a third conductive portion and a fourth conductive portion, the third conductive portion at least partially covering the first doped region, the fourth conductive portion being disposed on the silicon substrate outside the first doped region, the first surface passivation layer covering an area of the front surface area of the solar cell other than an orthographic projection of the first conductive layer on the silicon substrate.

12. The solar cell of claim 1, wherein the backside passivation contact structure is in full-side contact with the backside of the silicon substrate.

13. The solar cell of claim 1, wherein the first conductive layer is disposed on the first doped region, and a non-doped region is disposed between the first doped regions.

14. The solar cell of claim 13, wherein a lightly doped region is further disposed between the first doped region and the undoped region.

15. The solar cell of claim 1, wherein the first doped region is a single crystal doped layer.

16. The solar cell of claim 1, wherein the first doped region comprises a front side passivation contact structure.

17. The solar cell of claim 16, wherein the front side passivation contact structure comprises a first doped layer, a first passivation layer, and a second doped layer sequentially stacked on the silicon substrate.

18. The solar cell according to claim 17, wherein the first passivation layer is a porous structure having the first doped layer and/or the second doped layer in a hole region, and the second doped layer is connected to the first doped layer through the doped hole region.

19. The solar cell of claim 17, wherein the porous structure has an average pore size of less than 1000 nm.

20. The solar cell of claim 19, wherein the porous structure is formed by thermal diffusion bombardment.

21. The solar cell of claim 18, wherein the pores of the porous structure are sparsely distributed on the first passivation layer.

22. The solar cell of claim 18, wherein the ratio of the area of the pore region of the porous structure to the total area of the porous structure is less than 20%.

23. The solar cell of claim 18, wherein the first doped layer is discretely locally distributed in each hole region of the passivation layer.

24. The solar cell of claim 18, wherein the first doped layer is disposed entirely continuously between the silicon substrate and the passivation layer.

25. The solar cell of claim 16, wherein the front side passivation contact structure comprises a second passivation layer and a third doped layer sequentially stacked on the silicon substrate.

26. A battery module comprising the solar cell of any one of claims 1-25.