CN114171385A - Low-voltage transient suppression diode and manufacturing method thereof - Google Patents
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- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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Abstract
A low-voltage transient suppression diode and a manufacturing method thereof are disclosed, the manufacturing method comprises the following steps: providing a substrate; forming grooves on two surfaces of the substrate respectively; oxidizing the substrate with the groove to form a silicon dioxide layer with a preset thickness on the surface of the groove, forming a second doped region on one side of the substrate close to the silicon dioxide layer in the oxidation process, forming a third doped region on one side of the first doped layer close to the silicon dioxide layer, and forming a second PN junction between the second doped region and the third doped region; and forming a glass passivation layer on the groove. The silicon dioxide layer is formed by adopting a thermal oxidation process, the second doped region and the third doped region are formed in the forming process, and a narrow second PN junction is formed on the inner surface of the groove; because of the low breakdown voltage of the second PN junction, the total area of the second PN junction is smaller, and therefore the leakage current in the chip body is reduced.
Description
Technical Field
The invention relates to the technical field of transient suppression diodes, in particular to a low-voltage transient suppression diode and a manufacturing method thereof.
Background
The existing transient suppression diode (TVS for short) mainly has two chip structures of a mesa structure and a planar structure in the low voltage field (defined in the industry that VR is greater than or equal to 5V and less than or equal to 10V and reverse maximum voltage), wherein the low leakage current product generally adopts the planar structure.
The mesa process generally adopts a glass passivation process, and the groove is passivated by adopting the glass passivation process, and the glass has the characteristics of high insulation, moisture resistance and voltage resistance, has certain mechanical strength, has the advantage of passivation protection effect far superior to that of a silicon dioxide layer, and belongs to a high-quality passivation protection layer. However, the surface leakage current of the PN junction of the chip is increased in the glass sintering process, so that the leakage current control of the low-voltage product is a process difficulty of the glass passivation process of the low-voltage TVS chip.
The technical problem that leakage current is increased exists in the existing low-voltage TVS chip adopting a glass passivation layer.
Disclosure of Invention
The invention mainly solves the technical problem that the leakage current of the existing low-voltage TVS chip adopting a glass passivation layer is increased.
According to a first aspect, there is provided in an embodiment a method of manufacturing a low voltage transient suppression diode, comprising:
providing a base, wherein the base comprises a substrate and first doping layers formed on two surfaces of the substrate, the substrate is monocrystalline silicon doped with a first conductive type material, the first doping layers are doped with a second conductive type material, and a first PN junction is formed between the substrate and the first doping layers; the first conductivity type and the second conductivity type are of different semiconductor conductivity types;
forming grooves on two surfaces of the substrate respectively, wherein the grooves penetrate through the first doping layer and part of the substrate; the groove corresponds to a scribing region of the low-voltage transient suppression diode;
oxidizing the substrate with the groove to form a silicon dioxide layer with a preset thickness on the surface of the groove, and forming a second doped region on one side, close to the silicon dioxide layer, of the substrate in the oxidation process, wherein the first doped layer forms a third doped region on one side, close to the silicon dioxide layer, of the first doped layer, the second doped region is of the first conductivity type, the third doped region is of the second conductivity type, and a second PN junction is formed between the second doped region and the third doped region; the doping concentration of the second doping region is smaller than that of the substrate, and the doping concentration of the third doping region is larger than that of the first doping layer; or the doping concentration of the second doping region is greater than that of the substrate, and the doping concentration of the third doping region is less than that of the first doping layer;
and forming a glass passivation layer on the groove.
According to a second aspect, there is provided in an embodiment a low voltage transient suppression diode comprising:
the substrate is doped with a first conductive type material;
the semiconductor device comprises a substrate, a first doping layer, a second doping layer, a first PN junction, a second PN junction and a second doping layer, wherein the first doping layer is formed on two surfaces of the substrate and is doped with a second conductive type material;
the groove is formed on the surface of the first doping layer, is positioned at the edge of the first doping layer and penetrates through the first doping layer and part of the substrate;
a silicon dioxide layer formed on the surface of the trench;
a second doped region formed on one side of the substrate close to the silicon dioxide layer, wherein the second doped region has a second conductive type;
a third doped region is formed on one side, close to the silicon dioxide layer, of the first doped layer, the third doped region is provided with a first conductivity type, and a second PN junction is formed between the second doped region and the third doped region; the doping concentration of the second doping region is smaller than that of the substrate, and the doping concentration of the third doping region is larger than that of the first doping layer; or the doping concentration of the second doping region is greater than that of the substrate, and the doping concentration of the third doping region is less than that of the first doping layer;
and a glass passivation layer formed on the silicon dioxide layer.
According to the low-voltage transient suppression diode and the manufacturing method thereof of the above embodiment, a silicon dioxide layer is formed on the surface of the trench by oxidation, during the oxidation process, since the solid solubility of silicon dioxide to phosphorus atoms is lower than that of silicon to phosphorus atoms, and the solid solubility of silicon dioxide to boron atoms is higher than that of silicon to boron atoms, when the substrate and the first doped layer are oxidized to form the silicon dioxide layer, phosphorus atoms in silicon dioxide are pushed out of the substrate or the first doped layer, boron atoms in the substrate or the first doped layer are absorbed into the silicon dioxide layer, the doping concentrations of the substrate and the region of the first doped layer close to the silicon dioxide layer are changed, so as to form the second doped region and the third doped region, the second doped region and the third doped region form a narrow second PN junction on the inner surface of the trench, and since the phosphorus-removing effect of silicon dioxide is greater than the boron-absorbing effect, therefore, the breakdown voltage of the second PN junction is lower than that of the first PN junction; because of the low breakdown voltage of the second PN junction, the total area of the second PN junction is smaller, and therefore the leakage current in the chip body is reduced.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a low-voltage transient suppression diode according to an embodiment;
fig. 2 to 5 are process diagrams of a method for manufacturing a low voltage transient suppression diode according to an embodiment;
fig. 6 is a schematic structural diagram of a low-voltage transient suppression diode according to an embodiment.
Reference numerals: 10-a substrate; 11-a second doped region; 20-a first doped layer; 21-a third doped region; 30-a trench; 40-a silicon dioxide layer; 50-glass passivation layer.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
The TVS chip mainly includes two chip structures, i.e., a mesa structure and a planar structure, wherein the interface of the PN junction of the planar TVS chip is exposed on the surface of the substrate, and the TVS chip generally uses silicon dioxide as a passivation layer and has a relatively thin thickness (generally <20K angstroms). The silicon dioxide layer is easy to be damaged under the influence of factors such as subsequent metal surface photoetching and mechanical impact, or the silicon dioxide layer is damaged in the packaging process; there is also a short circuit caused by metal overflowing to the cut surface during the welding process. Therefore, the TVS chip with a planar structure is required to be higher than the mesa structure in the soldering and packaging processes.
The PN junction interface of the TVS chip with the mesa structure is arranged on the side wall of the groove, silicon dioxide is not generally adopted as a passivation layer, and the passivation performance of the silicon dioxide in mechanical shock protection and electrical insulation passivation is inferior to that of a glass passivation layer, so that the glass passivation layer is commonly used for the TVS chip with the existing mesa structure, and the glass powder is generally lead-based glass powder.
In the low voltage field of TVS, the high leakage current has been a difficult process due to the high doping concentration required for the substrate material (e.g., single crystal silicon). Meanwhile, by adopting a glass passivation process, the leakage current on the surface of the PN junction at the groove can be increased in the sintering process, the leakage current is generally at the level of 200uA-600uA in a low-voltage chip with the specification of 5V, and the leakage current is generally at the level of 1 uA-5 uA in a low-voltage chip with the specification of 10V.
Because the TVS chip is not structurally complex, the use of the glass passivation process for the mesa-structured TVS chip has been a normal state in the industry, and therefore, further reducing the leakage current of the low-voltage TVS chip has become a technical difficulty, and is also important for enhancing the competitiveness of the product.
In the present application, the first conductivity type and the second conductivity type belong to different semiconductor conductivity types, and the first conductivity type and the second conductivity type are P-type and N-type, and when the first conductivity type is N-type, the second conductivity type is P-type, and vice versa.
In the embodiment of the invention, the influence of the sintering process of glass passivation on the PN junction of the groove is isolated by forming the silicon dioxide layer in the groove before the glass passivation process is carried out. The silicon dioxide layer is formed in an oxidation mode, so that mutual diffusion of doping elements occurs between the silicon dioxide layer and the monocrystalline silicon, the concentration of donor impurities in the monocrystalline silicon close to the silicon dioxide layer is improved, the concentration of acceptor impurities is reduced, a second PN junction is formed on the inner surface of the silicon dioxide layer, and the leakage current in the TVS chip is reduced.
The first embodiment is as follows:
referring to fig. 1, the present embodiment provides a method for manufacturing a low voltage transient suppression diode, which is described below by taking an NPN-type TVS chip as an example, wherein a substrate 10 is a P-type monocrystalline silicon substrate, and a doping element of the substrate 10 is a trivalent element, such as boron; the N-type doping element is a pentavalent element, such as a phosphorus element. The manufacturing method comprises the following steps:
step 1: as shown in fig. 2, a base is provided, the base includes a substrate 10 and first doped layers 20 formed on two surfaces of the substrate 10, the substrate 10 may be monocrystalline silicon doped with a first conductive type material, the first doped layers 20 are doped with a second conductive type material, and a first PN junction is formed between the substrate 10 and the first doped layers 20; the first conductivity type and the second conductivity type are of different semiconductor conductivity types.
Specifically, step 1 may include the steps of:
step 1.1: a P-type single crystal silicon substrate is provided. For example, a single crystal abrasive sheet having a P-type <111> crystal orientation and a resistivity in the range of 0.002 to 0.018 is used.
Step 1.2: the baked substrate 10 is cleaned. For example, the surface is cleaned by RCA cleaning, spun-dried, and baked in a clean oven at 140 deg.C/15 min at 130-.
Step 1.3: the substrate 10 is doped N-type on the surface to form a first doped layer 20. For example, phosphorus oxychloride is pre-diffused for 3-6H at 1100-.
Step 1.4: and cleaning the substrate. For example, HF or BOE is used for soaking for 10 minutes to remove phosphorosilicate glass grown on the surface of the silicon wafer, RCA cleaning is used for cleaning the surface of the silicon wafer, the silicon wafer is dried by drying, and the silicon wafer is baked in a clean oven at the temperature of 140 ℃/15 min.
Step 1.5: and (4) surface oxidation. For example, an oxide layer is grown on the surface by passing through high temperature of 1000-1100 ℃/30-120min and oxygen of 5-7.5LPM, and then the temperature is reduced to 600 ℃ at the speed of 5 ℃/min, and the product is taken out of the furnace. The silicon dioxide layer on the surface of the substrate can be used as a hard mask for subsequent groove etching to protect the area outside the scribing area from being etched.
Step 2: as shown in fig. 3, trenches 30 are formed on two surfaces of the substrate, respectively, and the trenches 30 penetrate through the first doping layer 20 and a portion of the substrate 10; trench 30 corresponds to the scribe area of the low voltage transient suppression diode. The scribe region is provided according to the shape of the chip, and is not limited to a specific shape in this embodiment, and is generally square.
Specifically, step 2 may include the steps of:
step 2.1: and (6) photoetching. And coating photoresist on the surface of the substrate, and carrying out patterning treatment, wherein the shape of the pattern corresponds to the shape of the scribing area.
Step 2.2: and (5) etching the groove. The monocrystalline silicon can be etched by a wet method or a dry method, and when the wet method is used, the oxide layer formed in the step 1.5 is etched by the wet method or the dry method, and finally the monocrystalline silicon is etched. The first doped layer 20 and part of the substrate 10 are etched under the mask of the photoresist, resulting in a trench 30.
Step 2.3: and removing the photoresist and cleaning. The photoresist on the surface of the substrate is subjected to photoresist stripping treatment by using sulfuric acid or other photoresist stripping agents, and then RCA cleaning can be carried out.
And step 3: as shown in fig. 4, taking one trench 30 as an example for description, a substrate having the trench 30 is oxidized to form a silicon dioxide layer 40 with a predetermined thickness on the surface of the trench 30, and a second doped region 11 is formed on a side of the substrate 10 close to the silicon dioxide layer 40 during the oxidation process, a third doped region 21 is formed on a side of the first doped layer 20 close to the silicon dioxide layer 40, the second doped region 11 has a first conductivity type, the third doped region 21 has a second conductivity type, and a second PN junction is formed between the second doped region 11 and the third doped region 21; wherein, the doping concentration of the second doping region 11 is less than that of the substrate 10, and the doping concentration of the third doping region 21 is greater than that of the first doping layer 20; alternatively, the doping concentration of the second doping region 11 is greater than the doping concentration of the substrate 10, and the doping concentration of the third doping region 21 is less than the doping concentration of the first doping layer 20.
Specifically, the predetermined thickness may be 4 kilo-angstroms to 12 kilo-angstroms, and the substrate may be oxidized by thermal oxidation, which includes dry oxygen oxidation, water vapor oxidation, wet oxygen oxidation, and the like. In the embodiment of the present invention, the silicon dioxide layer 40 is formed using a hydrogen-oxygen synthetic oxidation process in wet oxygen oxidation.
For example, the process temperature of the hydrogen-oxygen synthesis oxidation can be 950 ℃ to 1100 ℃, and the process time can be 2 hours to 4 hours.
Oxyhydrogen synthesis during the growth of the silicon dioxide layer 40, since the solid solubility of silicon dioxide for phosphorus atoms is low relative to the solid solubility of silicon for phosphorus atoms, and the solid solubility of silicon dioxide for boron atoms is high relative to the solid solubility of silicon for boron atoms. When the silicon dioxide layer 40 on the surface of the substrate is formed by oxidizing silicon on the surface of the single crystal silicon substrate, phosphorus atoms in the silicon dioxide layer 40 are pushed into the first doped layer 20, boron atoms in the substrate 10 are sucked into the silicon dioxide layer 40, so that the phosphorus concentration on the surface of the N-type first doped layer 20 below the silicon dioxide layer 40 is higher than that in other regions, the boron concentration on the surface of the P-type substrate 10 is lower than that in other regions, and a narrow second PN junction is formed on the surface of the trench 30.
Under the process condition of silicon dioxide growth, the phosphorus removal effect of silicon dioxide is greater than the boron absorption effect, so that an N + -type third doped region 21 is formed in the region of the first doped layer 20 close to the silicon dioxide layer 40 (or the groove 30) due to phosphorus removal of the silicon dioxide layer 40, a P-type second doped region 11 is formed in the region of the substrate 10 close to the silicon dioxide layer 40 (or the groove 30) due to boron absorption of the silicon dioxide layer 40, and the breakdown voltage of a second PN junction (P-N + -type PN junction) formed between the second doped region 11 and the third doped region 21 is lower than the breakdown voltage of an internal first PN junction; the total area of the second PN junction is smaller, so that the leakage current in the chip body is reduced. The silicon dioxide layer 40 grown by hydrogen and oxygen synthesis has excellent compactness and few defects, and the silicon dioxide is an insulating passivation layer, so that movable electrons on the surface of the groove 30 can be well bound, and the leakage current on the surface of the second PN junction is reduced, so that the whole leakage current of the chip is smaller.
It should be understood that the filling colors of the first doped layer 20, the second doped region 11 and the third doped region 21 shown in fig. 4 do not represent the uniformity of the doping concentration or the local concentration relationship, and the shape or the edge is only illustrative and does not limit the edge flatness or the specific shape of the actual semiconductor structure. For example, when the first doping layer 20 is formed on the substrate 10 using thermal diffusion, the closer to the substrate 10, the lower the doping concentration thereof. For another example, the thickness of the second PN junction is not equal everywhere, and through experimental testing and analysis, the thickness of the interface closer to the second PN junction is narrower.
And 4, step 4: as shown in fig. 5, a glass passivation layer 50 is formed on the trench 30.
Specifically, step 5 may include the steps of:
step 5.1: the glass paste is coated on the surface of the substrate and the surface of the trench 30.
For example, the glass paste may be applied by a doctor blade method, the glass powder may be mixed with the binder in a predetermined ratio, and the glass paste may be applied to the surface of the substrate and the surface of the groove 30 by a doctor blade method. Wherein, the glass slurry preparation proportion can be as follows: glass powder: ethyl cellulose: butyl carbitol in a ratio of about 1 KG: 12.0 g: preparing 500 ml; when in preparation, the butyl carbitol is heated to 80 +/-5 ℃, then the ethyl cellulose is dissolved in the butyl carbitol, then the glass powder is poured in, the stirring is carried out for more than 10 minutes to form glass slurry, then the ball milling is carried out for more than 2H, and the glass is poured out for use in required amount after being uniform. The glass frit may be a lead-based glass frit corresponding to the chip.
Then horizontally placing the silicon wafer on a circular rotatable sucker, and then carrying out blade coating on the glass slurry in a manner that a proper amount (about 5-10 g) of glass slurry is dipped in the middle of the silicon wafer, and a blade forms an angle of about 45 degrees with the surface of the silicon wafer, so that the glass slurry is uniformly coated on the surface of the silicon wafer; the coated silicon wafer is then placed in a basket and the next coating is performed.
Step 5.2: the substrate is sintered to form a glass passivation layer 50 on the trench 30, the glass passivation layer 50 being formed on the silicon dioxide layer 40.
In particular, sintering may include pre-sintering as well as sintering steps.
Pre-sintering, pre-sintering at a first preset temperature, and removing the adhesive. For example, a silicon wafer coated with a glass paste is transferred into a diffusion quartz furnace tube, and ethyl cellulose in the glass paste is decomposed and carbonized by pre-firing at 500 ℃ for 30 minutes.
And sintering at a second preset temperature to form a glass passivation layer 50 on the trench 30. For example, after sintering the glass at the temperature of 820-.
The thickness of the glass passivation layer 50 after sintering is 10-25um, the high-quality silicon dioxide layer 40 isolates the direct action of the glass passivation layer 50 on the second PN junction, the buffer layer action is achieved, the damage of the glass on the low-voltage breakdown layer structure of the second PN junction is avoided, and therefore the leakage current after glass sintering can be still maintained near the leakage current level before glass sintering.
Step 6: as shown in fig. 6, dicing is performed along the center line of the trench 30, and a transient suppression diode chip is obtained.
The leakage current of the low-voltage TVS chip manufactured by the manufacturing method is reduced compared with that of a TVS chip manufactured by the similar glass passivation process, and the leakage current of a 5V chip can be controlled to be less than 100uA, and the leakage current of a 10V chip can be controlled to be less than 1 uA. Effectively reduce the leakage current of low pressure TVS chip, improve the long time competitiveness of product. Meanwhile, the silicon dioxide layer is formed by oxyhydrogen synthesis oxidation before the glass passivation process, so that complicated process steps are not required to be added, and the method is easy to realize. The silica layer formed by oxyhydrogen synthesis oxidation isolates the direct action of the sintering process of the glass passivation layer on the second PN junction, plays the role of a buffer layer, and avoids the damage of glass on the low-voltage breakdown layer structure on the surface of the second PN junction, so that the leakage current after the glass sintering can be still maintained near the leakage current level before the glass sintering.
Example two:
referring to fig. 6, the present embodiment provides a low voltage transient suppression diode, including: a substrate 10, a first doping layer 20, a trench 30, a silicon dioxide layer 40, a second doping region 11, a third doping region 21 and a glass passivation layer 50.
Wherein the substrate 10 is doped with a first conductivity type material. The first doping layer 20 is formed on both surfaces of the substrate 10, the first doping layer 20 is doped with a second conductive type material, a first PN junction is formed between the substrate 10 and the first doping layer 20, and the first conductive type and the second conductive type belong to different semiconductor conductive types.
Specifically, the substrate 10 may be single crystal silicon doped with a first conductive type material, and the first doping layer 20 is formed on both surfaces of the substrate 10 by doping of a second conductive type element.
For example, the low-voltage transient suppression diode may be an NPN-type low-voltage transient suppression diode, the substrate 10 is a P-type single crystal silicon substrate, and the doping element is a trivalent element, such as boron; the first doping layer 20 is formed on both surfaces of the substrate 10 by N-type doping, and the doping element is a pentavalent element such as phosphorus.
The trench 30 is formed on the surface of the first doped layer 20, the trench 30 is located at the edge of the first doped layer 20, and the trench 30 penetrates the first doped layer 20 and a portion of the substrate 10 along the thickness direction of the substrate (the up-down direction in the figure) corresponding to the scribe region of the manufacturing method in the first embodiment.
A silicon dioxide layer 40 is formed on the surface of the trench 30; wherein, the silicon dioxide layer 40 is formed on the trench 30 by thermal oxidation, during the formation of the silicon dioxide layer 40, the second doped region 11 is formed between the silicon dioxide layer 40 and the substrate 10, and the third doped region 21 is formed between the first doped layer 20 and the silicon dioxide layer 40. The thermal oxidation may be specifically hydrogen-oxygen synthesis oxidation.
The second doped region 11 is formed on one side of the substrate 10 close to the silicon dioxide layer 40, and the second doped region 11 has a second conductive type; the third doped region 21 is formed on one side of the first doped layer 20 close to the silicon dioxide layer 40, the third doped region 21 has the first conductivity type, and a second PN junction is formed between the second doped region 11 and the third doped region 21; wherein, the doping concentration of the second doping region 11 is less than that of the substrate 10, and the doping concentration of the third doping region 21 is greater than that of the first doping layer 20; alternatively, the doping concentration of the second doping region 11 is greater than the doping concentration of the substrate 10, and the doping concentration of the third doping region 21 is less than the doping concentration of the first doping layer 20.
For example, when the low-voltage transient suppression diode is an NPN-type low-voltage transient suppression diode, the doping concentration of the second doping region 11 (corresponding to P-type) is less than that of the substrate 10 (corresponding to P-type), and the doping concentration of the third doping region 21 (corresponding to N + -type) is greater than that of the first doping layer 20 (corresponding to N-type).
A glass passivation layer 50 is formed on the silicon dioxide layer 40.
For example, the glass passivation layer 50 may be formed by performing glass passivation using a knife-blade method using a lead-based glass frit.
The low voltage transient suppression diode provided in this embodiment has the technical effects of the low voltage transient suppression diode manufactured by the manufacturing method described in the first embodiment, and details are not repeated herein.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (10)
1. A method of manufacturing a low voltage transient suppression diode, comprising:
providing a base, wherein the base comprises a substrate (10) and first doping layers (20) formed on two surfaces of the substrate (10), the substrate (10) is monocrystalline silicon doped with a first conduction type material, the first doping layers (20) are doped with a second conduction type material, and a first PN junction is formed between the substrate (10) and the first doping layers (20); the first conductivity type and the second conductivity type are of different semiconductor conductivity types;
forming grooves (30) on two surfaces of the base respectively, wherein the grooves (30) penetrate through the first doping layer (20) and a part of the substrate (10); the groove (30) corresponds to a scribing region of the low-voltage transient suppression diode;
oxidizing a substrate with a groove (30) to form a silicon dioxide layer (40) with a preset thickness on the surface of the groove (30), and forming a second doped region (11) on one side, close to the silicon dioxide layer (40), of the substrate (10) in an oxidation process, forming a third doped region (21) on one side, close to the silicon dioxide layer (40), of the first doped layer (20), wherein the second doped region (11) is of a first conductivity type, the third doped region (21) is of a second conductivity type, and a second PN junction is formed between the second doped region (11) and the third doped region (21); wherein the doping concentration of the second doping region (11) is less than the doping concentration of the substrate (10), and the doping concentration of the third doping region (21) is greater than the doping concentration of the first doping layer (20); or the doping concentration of the second doping region (11) is greater than that of the substrate (10), and the doping concentration of the third doping region (21) is less than that of the first doping layer (20);
forming a glass passivation layer (50) on the trench (30).
2. The method of claim 1, wherein the oxidizing the substrate having the trench (30) to form a silicon dioxide layer (40) of a predetermined thickness on the surface of the trench (30) comprises:
and forming a silicon dioxide layer (40) with a preset thickness on the surface of the groove (30) through thermal oxidation.
3. The method of claim 2, wherein the predetermined thickness is 4 kilo-angstroms to 12 kilo-angstroms, and/or the thermal oxidation is oxyhydrogen synthesis oxidation at a process temperature of 950 ℃ to 1100 ℃ for 2 hours to 4 hours.
4. The method of manufacturing of claim 1, wherein the low voltage transient suppression diode is an NPN type low voltage transient suppression diode, the providing a substrate comprising:
providing a P-type monocrystalline silicon substrate (10), wherein the doping element of the substrate (10) is a trivalent element;
and N-type doping is carried out on the substrate (10), the first doping layers (20) are formed on two surfaces of the substrate (10), and the doping elements are pentavalent elements.
5. The manufacturing method according to claim 1, wherein the forming a glass passivation layer (50) on the trench (30) comprises:
coating glass slurry on the surface of the substrate and the surface of the groove (30);
sintering the substrate to form a glass passivation layer (50) on the trench (30), the glass passivation layer (50) being formed on the silicon dioxide layer (40).
6. The manufacturing method according to claim 1, wherein the forming a glass passivation layer (50) on the trench (30) comprises:
coating glass slurry, mixing glass powder and a bonding agent according to a preset proportion, and coating the glass slurry on the surface of the substrate and the surface of the groove (30) by adopting a knife scraping method;
pre-sintering, performing pre-sintering at a first preset temperature, and removing the adhesive;
and sintering at a second preset temperature to form a glass passivation layer (50) on the groove (30).
7. A low voltage transient suppression diode, comprising:
a substrate (10), the substrate (10) being doped with a first conductivity type material;
a first doped layer (20) formed on both surfaces of the substrate (10), the first doped layer (20) being doped with a second conductivity type material, a first PN junction being formed between the substrate (10) and the first doped layer (20), the first and second conductivity types being of different semiconductor conductivity types;
a trench (30) formed on the surface of the first doped layer (20), the trench (30) being located at the edge of the first doped layer (20), the trench (30) extending through the first doped layer (20) and a portion of the substrate (10);
a silicon dioxide layer (40) formed on the surface of the trench (30);
a second doped region (11) formed on a side of the substrate (10) adjacent to the silicon dioxide layer (40), the second doped region (11) having a second conductivity type;
a third doped region (21) formed on a side of the first doped layer (20) adjacent to the silicon dioxide layer (40), the third doped region (21) having the first conductivity type, a second PN junction being formed between the second doped region (11) and the third doped region (21); wherein the doping concentration of the second doping region (11) is less than the doping concentration of the substrate (10), and the doping concentration of the third doping region (21) is greater than the doping concentration of the first doping layer (20); or the doping concentration of the second doping region (11) is greater than that of the substrate (10), and the doping concentration of the third doping region (21) is less than that of the first doping layer (20);
and a glass passivation layer (50) formed on the silicon dioxide layer (40).
8. The low voltage transient suppression diode of claim 7, wherein said substrate (10) is single crystal silicon doped with a first conductivity type material, said first doped layer (20) being formed by doping at both surfaces of said substrate (10);
the silicon dioxide layer (40) is formed on the groove (30) through thermal oxidation, the second doped region (11) is formed between the silicon dioxide layer (40) and the substrate (10) in the forming process of the silicon dioxide layer (40), and the third doped region (21) is formed between the first doped layer (20) and the silicon dioxide layer (40).
9. The low voltage transient suppression diode of claim 8, wherein said low voltage transient suppression diode is an NPN type low voltage transient suppression diode, said substrate (10) is a P-type single crystal silicon substrate, and the doping element is a trivalent element;
the first doping layers (20) are formed on two surfaces of the substrate (10) through N-type doping, and doping elements are pentavalent elements.
10. The low voltage transient suppression diode of claim 9, wherein said second doped region (11) has a doping concentration less than a doping concentration of said substrate (10), and said third doped region (21) has a doping concentration greater than a doping concentration of said first doped layer (20).
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| JPS5633845A (en) * | 1979-08-29 | 1981-04-04 | Toshiba Corp | Manufacture of semiconductor device |
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| US20020175391A1 (en) * | 2001-05-22 | 2002-11-28 | Einthoven Willem G. | Low-voltage punch-through bi-directional transient-voltage suppression devices and methods of making the same |
| CN101621002A (en) * | 2009-08-05 | 2010-01-06 | 百圳君耀电子（深圳）有限公司 | Manufacturing method of low-voltage transient voltage suppression diode chip |
| CN103972305A (en) * | 2014-04-18 | 2014-08-06 | 苏州固锝电子股份有限公司 | Method for manufacturing low-voltage transient voltage suppression diode chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS5633845A (en) * | 1979-08-29 | 1981-04-04 | Toshiba Corp | Manufacture of semiconductor device |
| US4980315A (en) * | 1988-07-18 | 1990-12-25 | General Instrument Corporation | Method of making a passivated P-N junction in mesa semiconductor structure |
| US20020175391A1 (en) * | 2001-05-22 | 2002-11-28 | Einthoven Willem G. | Low-voltage punch-through bi-directional transient-voltage suppression devices and methods of making the same |
| CN101621002A (en) * | 2009-08-05 | 2010-01-06 | 百圳君耀电子（深圳）有限公司 | Manufacturing method of low-voltage transient voltage suppression diode chip |
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