CN111755529A - Bidirectional symmetrical TVS diode and manufacturing method thereof - Google Patents
Bidirectional symmetrical TVS diode and manufacturing method thereof Download PDFInfo
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- CN111755529A CN111755529A CN201910251215.3A CN201910251215A CN111755529A CN 111755529 A CN111755529 A CN 111755529A CN 201910251215 A CN201910251215 A CN 201910251215A CN 111755529 A CN111755529 A CN 111755529A
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- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 52
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 48
- 239000000758 substrate Substances 0.000 claims description 26
- 235000012239 silicon dioxide Nutrition 0.000 claims description 24
- 239000000377 silicon dioxide Substances 0.000 claims description 24
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 18
- 238000002161 passivation Methods 0.000 claims description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 238000000407 epitaxy Methods 0.000 claims description 6
- 239000003292 glue Substances 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- -1 2000A titanium Chemical class 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims description 3
- 230000035515 penetration Effects 0.000 claims description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000001312 dry etching Methods 0.000 description 7
- 230000001052 transient effect Effects 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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Abstract
The invention relates to a bidirectional symmetrical TVS diode and a manufacturing method thereof, which reduces the thermal process by using a low-pressure chemical vapor deposition method, realizes transverse bidirectional TVS, and has stable performance and consistent bidirectional symmetry; the etching method of dry method and wet method is used to ensure that the silicon in the window is not over-etched and the window has good appearance, which is beneficial to metal covering and improves the reliability of the device. One end of the TVS is connected to the back of the chip through the through area, so that the area of the chip is saved.
Description
Technical Field
The present invention relates to a TVS diode, and more particularly, to a bidirectional symmetrical TVS diode and a method for manufacturing the same.
Background
Transient interference of voltage and current is a main cause of damage to electronic circuits and devices, and often brings immeasurable loss to people. These disturbances typically result from start-stop operation of the electrical equipment, instability of the ac power grid, lightning disturbances, electrostatic discharge, and the like. Transient interference is almost ubiquitous and untimely, so that people feel defenses and fortunate, and the transient interference is effectively controlled due to the occurrence of the TVS which is a high-efficiency circuit protection device. When the two ends of TVS tube are subjected to instantaneous high energy impact, it can make its impedance reduce suddenly at a very high speed, and at the same time absorb a large current, and clamp the voltage between its two ends at a preset value, so as to ensure that the following circuit elements are not damaged by the impact of transient high energy. TVSs can be classified into unidirectional and bidirectional TVSs according to polarity. Unidirectional TVS is generally suitable for dc circuits, whereas in ac circuits, bidirectional protection TVS diodes are required. If the TVS is made into a lateral bidirectional diode, the performance of the TVS is greatly influenced by a thermal process because the TVS is a surface device. Therefore, the conventional bidirectional TVS is generally made into a longitudinal bidirectional diode, and the process generally adopts a mesa process to make the bidirectional TVS diode or a substrate of hetero-epitaxy, and an NPN or PNP structure is formed by doping impurities of the same type as the substrate on the epitaxy. The traditional bipolar TVS has a great limitation, the consistency of the bidirectional voltage of the traditional bipolar TVS is difficult to control, and the voltage in two directions is greatly influenced by the fluctuation of the process. In addition, some bidirectional TVS protection circuits are formed by combining a plurality of packaged separated TVSs, and the independent chip combination results in low integration level, large size and waste of chip area.
Disclosure of Invention
Accordingly, the present invention is directed to a bidirectional symmetrical TVS diode and a method for manufacturing the same, which overcome the shortcomings of the prior art.
In order to achieve the purpose, the invention is realized by the following technical scheme:
in one aspect, a bidirectional symmetrical TVS diode is provided, including:
a P-type substrate;
the N-type epitaxial layer is formed on the P-type substrate;
the P + doped region is formed on the surface of the N-type epitaxial layer;
the P + through area penetrates through the N-type epitaxial layer, and the bottom of the P + through area is connected with the P-type substrate;
the oxide layer is formed on the N-type epitaxial layer, and the surface of the P + through region is connected with the P + doped region through the oxide layer;
a metal hole formed on the P + penetration region, the P + doping region and between the oxide layers;
a passivation layer formed on the metal layer; and
and the back metal layer is formed on the back of the P-type substrate.
In the above-mentioned bidirectional symmetrical TVS diode, the passivation layer includes an oxide layer and silicon nitride, the oxide layer is in contact with the metal, and the silicon nitride is formed on the oxide layer.
In the bidirectional symmetrical TVS diode, the back metal layer sequentially includes a titanium layer, a nickel layer, and a silver layer.
In another aspect, a method for manufacturing a bidirectional symmetrical TVS diode is provided, including:
s1, providing a P-type substrate, and growing an N-type epitaxy on the P-type substrate;
s2, growing a silicon dioxide layer of 800A on the N-type epitaxy by dry thermal oxidation, then growing a TEOS silicon dioxide layer of 8000A by a low-pressure chemical vapor deposition method at the low temperature of 650-750 ℃, and then densifying the TEOS silicon dioxide by 850 ℃ for 40 minutes;
s3, forming a window of a P + through region on the surface silicon dioxide through photoetching and wet etching, and then doping the P + through region in a boron injection mode, wherein the doping amount is 2.5E16KEV, and the energy is 120 KEV; after doping, a layer of 6000A TEOS silicon dioxide is grown by low pressure chemical vapor deposition at the low temperature of 650-750 ℃, and then N is at 1250 DEG C2Advancing for 1 hour under the condition;
s4, photoetching to open a window of a P + active region, etching 10000A of silicon dioxide by a dry method, carrying out wet etching on the rest oxide layer after glue solidification, carrying out 5E15 injection metering after etching, injecting boron with 90KEV injection energy, growing a layer of 6000A of TEOS silicon dioxide by an LPCVD method after injection, and then carrying out 1000 ℃ N2Advancing the condition;
s5, dry etching the 4500A oxide layer, curing the tape adhesive at 90 ℃ for 1 hour, and wet etching the rest oxide layer by a method combining the dry method and the wet method. Simultaneously, opening holes on a 12000A TEOS oxide layer of a P + through area and a 6000A TEOS oxide layer of a P + active area;
s6, depositing metal ALSiCu on the surface, wherein the thickness is 3 um;
s7, growing a passivation layer on the metal layer, wherein the passivation layer has a two-layer structure, one layer is a PSG (patterned silicon germanium) oxide layer, the second layer is silicon nitride, and holes are formed in the passivation layer through photoetching to expose metal lead holes;
and S8, grinding the back of the P-type substrate to 150um, and then depositing three layers of metals, namely 2000A titanium, 3000A nickel and 8000A silver, on the back of the P-type substrate.
Compared with the prior art, the invention has the beneficial effects that:
the invention reduces the thermal process by using the low-pressure chemical vapor deposition method, realizes the transverse bidirectional TVS, has stable performance and consistent bidirectional symmetry; by using the dry-method and wet-method etching method, the silicon in the window is not over-etched, the window is ensured to have good appearance, metal coverage is facilitated, and the reliability of the device is improved; one end of the TVS is connected to the back of the chip through the through area, so that the area of the chip is saved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 shows a schematic structural diagram of the present invention;
figure 2 shows a flow diagram of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
Referring to fig. 1, the bidirectional symmetrical TVS diode of the present invention includes a P-type substrate 1, an N-type epitaxial layer 2, a P + doped region 3, a P + punch-through region 4, an oxide layer 5, a metal hole 6, a passivation layer 7 and a back metal layer 8, the N-type epitaxial layer 2 is formed on the P-type substrate 1, the P + doped region 3 is formed on the surface of the N-type epitaxial layer 2, the P + punch-through region 4 penetrates the N-type epitaxial layer 2, the bottom of the P + punch-through region 4 is connected to the P-type substrate 1, the oxide layer 5 is formed on the N-type epitaxial layer 2, and the surface of the P + punch-through region 4 is connected to the P + doped region 3 through the. The metal hole 6 is formed on the P + penetration region 4 and the P + doping region 3 and between the oxide layers 5, the passivation layer 7 is formed on the metal layer 6, and the back metal layer 8 is formed on the back of the P-type substrate 1. In this technical solution, the passivation layer 7 includes an oxide layer and silicon nitride, the oxide layer is in contact with the metal, and the silicon nitride is formed on the oxide layer. The back metal layer 8 comprises a titanium layer, a nickel layer and a silver layer in sequence.
Referring to fig. 2, the process flow of the method for manufacturing the diode is as follows:
s1, providing a P-type substrate, and growing an N-type epitaxy on the P-type substrate;
s2, growing a silicon dioxide layer of 800A on the surface by dry thermal oxidation, then growing a TEOS silicon dioxide layer of 8000A by low-pressure chemical vapor deposition at 650-750 ℃, and then densifying the TEOS silicon dioxide by 850 ℃ for 40 minutes;
s3, forming a window of a P + through region on the surface silicon dioxide through photoetching and wet etching, and then doping the P + through region in a boron injection mode, wherein the doping amount is 2.5E16KEV, and the energy is 120 KEV; after doping, a layer of 6000A TEOS silicon dioxide is grown by low pressure chemical vapor deposition at the low temperature of 650-750 ℃, and then N is at 1250 DEG C2Advancing for 1 hour under the condition;
s4, the thickness of the oxide layer of the surface except the P + through region is 14800A, the oxide layer is very thick, and the thick oxide layer is etched out by wet etchingThe edge morphology of (2) is very oblique, which can affect the reliability of the device. If dry etching is used, the dry etching time is long because the oxide layer is thicker, the utilization rate of equipment is greatly reduced, and the cost of the dry process is higher. The invention uses a dry-wet method mode, 10000A of silicon dioxide is etched by a dry method, the rest oxide layer is etched by a wet method, and glue curing is carried out at 90 ℃ for one hour after the dry etching, which is beneficial to enhancing the adhesive property of the glue. After the window is etched, the implantation dosage of 5E15 and the boron implantation with the implantation energy of 90KEV are carried out, after the implantation is finished, a layer of 6000A TEOS silicon dioxide is grown by an LPCVD method, and then 1000 ℃ N is carried out2Advancing the condition;
and S5, the thickness of the oxide layer on the surface is different in each area, the thickness of the oxide layer on the P + through area is 12000A, the thickness of the oxide layer on the P + active area is 6000A, the thickness of the oxide layer on the area needing isolation on the surface is 20800A (the oxide layer is thick and has a good isolation effect), and holes are required to be formed on the 12000 ATOOS oxide layer of the P + through area and the 6000A TEOS oxide layer of the P + active area at the same time. If the dry etching is used, 12000A of oxide layer is etched clean, and the area of 6000A is over-etched. The normal dry equipment etches silicon dioxide and also etches some Si unless the dry equipment with high selectivity is selected. According to the invention, by a dry-wet method, an oxide layer of 4500A is etched in a dry method, and then 100C is cured with glue, so that wet etching is carried out. By a dry-method and wet-method corrosion method, the P + through area and the P + active area form a very good step shape, and the P + active area does not have an over-etching phenomenon;
and S6, depositing metal ALSiCu on the surface, wherein the thickness is 3 um. Due to the step shape of the hole, the metal step covering shape is particularly good, and the reliability of the device is enhanced;
s7, growing a passivation layer on the metal layer, wherein the passivation layer has a two-layer structure, one layer is a PSG (patterned silicon germanium) oxide layer, the second layer is silicon nitride, and holes are formed in the passivation layer through photoetching to expose metal lead holes;
s8, grinding the back of the P-type substrate to 150um, and then depositing three layers of metals, namely 2000A titanium, 3000A nickel and 8000A silver, on the back of the P-type substrate, wherein the titanium is used as an adhesion layer.
The surface dielectric layer in the invention uses TEOS silicon dioxide produced by low-pressure chemical vapor deposition to replace silicon dioxide produced by thermal oxidation, thereby greatly reducing the thermal process in the process, reducing the production cost and improving the stability of the device. The window is corroded by a method combining dry etching and wet etching, the window appearance with good step performance is obtained, the following metal has good step coverage performance, the reliability of a device is improved, and the photoresist is solidified by one step after the dry etching, so that the photoresist has a good protection effect in the later wet process.
As can be seen from the above embodiments, the advantages of the present invention are:
the invention reduces the thermal process by using the low-pressure chemical vapor deposition method, realizes the transverse bidirectional TVS, has stable performance and consistent bidirectional symmetry; by using the dry-method and wet-method etching method, the silicon in the window is not over-etched, the window is ensured to have good appearance, metal coverage is facilitated, and the reliability of the device is improved; one end of the TVS is connected to the back of the chip through the through area, so that the area of the chip is saved.
The embodiments of the present invention have been described in detail, but the present invention is not limited to the above-described embodiments, which are only examples. Any equivalent modifications and substitutions for those skilled in the art are also within the scope of the present invention. Accordingly, equivalent changes and modifications made without departing from the spirit and scope of the present invention should be covered by the present invention.
Claims (4)
1. A bilaterally symmetric TVS diode, comprising:
a P-type substrate;
the N-type epitaxial layer is formed on the P-type substrate;
the P + doped region is formed on the surface of the N-type epitaxial layer;
the P + through area penetrates through the N-type epitaxial layer, and the bottom of the P + through area is connected with the P-type substrate;
the oxide layer is formed on the N-type epitaxial layer, and the surface of the P + through region is connected with the P + doped region through the oxide layer;
a metal hole formed on the P + penetration region, the P + doping region and between the oxide layers;
a passivation layer formed on the metal layer; and
and the back metal layer is formed on the back of the P-type substrate.
2. The bilaterally symmetric TVS diode of claim 1, wherein said passivation layer comprises an oxide layer and a silicon nitride, said oxide layer in contact with a metal, said silicon nitride formed on said oxide layer.
3. The bilaterally symmetric TVS diode of claim 1, wherein said back side metal layer comprises, in order, a titanium layer, a nickel layer, and a silver layer.
4. A method for manufacturing a bidirectional symmetrical TVS diode is characterized by comprising the following steps:
s1, providing a P-type substrate, and growing an N-type epitaxy on the P-type substrate;
s2, growing a silicon dioxide layer of 800A on the surface of the N-type epitaxy by dry thermal oxidation, then growing a TEOS silicon dioxide layer of 8000A by a low-pressure chemical vapor deposition method at the low temperature of 650-750 ℃, and then densifying the TEOS silicon dioxide by 850 ℃ for 40 minutes;
s3, forming a window of a P + through region on the surface silicon dioxide through photoetching and wet etching, and then doping the P + through region in a boron injection mode, wherein the doping amount is 2.5E16KEV, and the energy is 120 KEV; after doping, a layer of 6000A TEOS silicon dioxide is grown by low pressure chemical vapor deposition at the low temperature of 650-750 ℃, and then N is at 1250 DEG C2Advancing for 1 hour under the condition;
s4, photoetching to open a window of a P + active region, etching 10000A of silicon dioxide by a dry method, and curing with glue at 90 ℃ for 1 hourThen, wet etching the rest oxide layer, 5E15 implantation metering, boron implantation with 90KEV implantation energy, growing a 6000A TEOS silicon dioxide layer by LPCVD method, and then carrying out 1000 deg.C N2Advancing the condition;
s5, through a method combining a dry method and a wet method, firstly etching an oxide layer of 4500A by a dry method, then carrying out glue curing for 1 hour at 90 ℃, then etching the rest oxide layer by a wet method, and simultaneously opening holes on a 12000A TEOS oxide layer of a P + through area and a 6000A TEOS oxide layer of a P + active area;
s6, depositing metal ALSiCu on the surface, wherein the thickness is 3 um;
s7, growing a passivation layer on the metal layer, wherein the passivation layer has a two-layer structure, one layer of structure is PSG, the second layer of structure is silicon nitride, and holes are formed in the passivation layer through photoetching to expose the metal lead holes;
and S8, grinding the back of the P-type substrate to 150um, and then depositing three layers of metals, namely 2000A titanium, 3000A nickel and 8000A silver, on the back of the P-type substrate.
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| CN201910251215.3A CN111755529A (en) | 2019-03-29 | 2019-03-29 | Bidirectional symmetrical TVS diode and manufacturing method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112366231A (en) * | 2020-11-20 | 2021-02-12 | 济南新芯微电子有限公司 | Voltage stabilizing diode and manufacturing method thereof |
| CN113113324A (en) * | 2021-04-07 | 2021-07-13 | 捷捷半导体有限公司 | Passivation layer manufacturing method |
| CN117174760A (en) * | 2023-11-02 | 2023-12-05 | 江西信芯半导体有限公司 | TVS chip with field ring structure and manufacturing method thereof |
-
2019
- 2019-03-29 CN CN201910251215.3A patent/CN111755529A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112366231A (en) * | 2020-11-20 | 2021-02-12 | 济南新芯微电子有限公司 | Voltage stabilizing diode and manufacturing method thereof |
| CN113113324A (en) * | 2021-04-07 | 2021-07-13 | 捷捷半导体有限公司 | Passivation layer manufacturing method |
| CN113113324B (en) * | 2021-04-07 | 2024-02-06 | 捷捷半导体有限公司 | Passivation layer manufacturing method |
| CN117174760A (en) * | 2023-11-02 | 2023-12-05 | 江西信芯半导体有限公司 | TVS chip with field ring structure and manufacturing method thereof |
| CN117174760B (en) * | 2023-11-02 | 2024-04-05 | 江西信芯半导体有限公司 | TVS chip with field ring structure and manufacturing method thereof |
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