CN105938848A - Schottky chip used for chip scale packaging - Google Patents
Schottky chip used for chip scale packaging Download PDFInfo
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- CN105938848A CN105938848A CN201610075433.2A CN201610075433A CN105938848A CN 105938848 A CN105938848 A CN 105938848A CN 201610075433 A CN201610075433 A CN 201610075433A CN 105938848 A CN105938848 A CN 105938848A
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- 238000004806 packaging method and process Methods 0.000 title abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 107
- 239000002184 metal Substances 0.000 claims abstract description 107
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 94
- 239000010703 silicon Substances 0.000 claims abstract description 94
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 81
- 230000004888 barrier function Effects 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000011049 filling Methods 0.000 claims abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 67
- 238000000407 epitaxy Methods 0.000 claims description 44
- 235000012239 silicon dioxide Nutrition 0.000 claims description 33
- 239000000377 silicon dioxide Substances 0.000 claims description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 31
- 238000007789 sealing Methods 0.000 claims description 17
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 230000000737 periodic effect Effects 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 150000003376 silicon Chemical class 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 239000000945 filler Substances 0.000 abstract 2
- 238000000034 method Methods 0.000 description 16
- 238000009792 diffusion process Methods 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 7
- 238000001259 photo etching Methods 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 238000005260 corrosion Methods 0.000 description 6
- 230000007797 corrosion Effects 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
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- 230000002441 reversible effect Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 206010037660 Pyrexia Diseases 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 239000007792 gaseous phase Substances 0.000 description 3
- 230000012010 growth Effects 0.000 description 3
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- 239000007924 injection Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000005036 potential barrier Methods 0.000 description 3
- 229910021484 silicon-nickel alloy Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- XRZCZVQJHOCRCR-UHFFFAOYSA-N [Si].[Pt] Chemical compound [Si].[Pt] XRZCZVQJHOCRCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- -1 boron ion Chemical class 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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- 238000005530 etching Methods 0.000 description 1
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- 238000009413 insulation Methods 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a Schottky chip used for chip scale packaging. The Schottky chip comprises a highly doped silicon substrate, a lowly doped silicon epitaxial layer formed on the front surface of the highly doped silicon substrate, a Schottky electrode and an ohmic electrode which are formed on the silicon epitaxial layer, an insulating layer formed on the silicon epitaxial layer for isolating the Schottky electrode and the ohmic electrode, and a protection ring arranged around the periphery of the Schottky electrode, wherein the silicon substrate and the silicon epitaxial layer are of a first conductivity type; the protection ring is of a second conductivity type; the Schottky electrode comprises a Schottky barrier metal formed on the front surface of the silicon epitaxial layer and an anode metal overlapped on the barrier metal; and the ohmic electrode comprises a plurality of grooves running through the epitaxial layer, a groove filler for filling the grooves, and a cathode connecting metal formed on the top of the ohmic electrode. The groove filler is of the first conductivity type, and is electrically connected with the front surface of the silicon substrate. According to the Schottky chip, the two electrodes of the Schottky chip are arranged on the same main surface of the silicon epitaxial layer, so that the requirement of the chip scale packaging that a packaging device is of dimensions approximate to those of a semiconductor element is reached.
Description
Technical field
The present invention relates to semiconductor device, particularly for the schottky device chip of wafer-level package.
Background technology
Due to energy-conservation, the needs of lightness small-sized with equipment, the application of high frequency switch power is the most universal.Compared with junction diode, Schottky diode has that forward voltage is lower and the higher advantage of operating frequency, and therefore, Schottky diode being widely used in high frequency switch power, it is mainly used in PC
Power, solar energy, LED streetlamp power source, industrial power, adapter etc., the application of current Schottky diode accounts for position leading in the application of all commutation diodes, and its utility ratio has the trend continuing to raise.
Along with customer demand integrated more multi-functional and increase of requirement to electronic component smallerization in small portable device, exploitation new device uses joint space-efficient wafer-level package (Chip
Scale Package: CSP), it is applied to the hand-held of limited space and portable equipment, such as panel computer, smart phone, PDA and miniature hard disk drive, range of application includes electric current regulation, boosting and freewheeling circuit etc..Wide variety of Schottky diode in electronic circuit, wishes have the Schottky chip that can be applied to wafer-level package so that the miniaturization realizing electronic circuit naturally.
Wafer-level package requires that chip area and package area, close to the ideal situation of 1:1, thus take the area on less circuit board than traditional semiconductor packages.Using the Schottky chip of conventional package technique, be arranged on by the electrode of tube core on positive and negative two surfaces, wafer-level package device approximates the size of semiconductor element in order to ensure having, and is provided only on by the electrode of tube core on a surface, if notification number is CN
The patent of invention of 100380679C proposes the schottky device structure of a kind of wafer-level package, it is simply that negative electrode and anode are simultaneously located at the example on same surface.But, in this patent of invention, negative electrode is to form a sinker area by injection and follow-up diffusion-driven in epitaxial region to electrically connect to be formed, the negative electrode of this structure has high conducting resistance, simultaneously its sinker area also can take bigger chip area, and the negative electrode conducting resistance how reducing device is the main bugbear of the chip development being applied to wafer-level package at present.
Summary of the invention
For the technical problem of the Schottky chip being currently used for wafer-level package, it is desirable to provide a kind of negative electrode has less conducting resistance and takies the Schottky chip of less chip area.
The invention provides a kind of Schottky chip for wafer-level package, including:
Highly doped silicon substrate；
The low-doped silicon epitaxy layer being formed on the front surface of highly doped silicon substrate；
It is formed at the Schottky electrode on this silicon epitaxy layer, Ohmic electrode；
The insulating barrier for isolating Schottky electrode and Ohmic electrode being formed on silicon epitaxy layer；
And the protection ring of the periphery setting around Schottky electrode；
Described silicon substrate and described silicon epitaxy layer have the first conduction type；It is contrary that described protection ring has the second conduction type, the second conduction type and the first conduction type electric conductivity；
Described Schottky electrode includes the Schottky barrier metal being formed on the front surface of silicon epitaxy layer and covers the anode metal on barrier metal；
The composition of described Ohmic electrode includes: the groove of some through-silicon epitaxial layers, fill the trench filling of described groove, and the negative electrode being formed at Ohmic electrode top layer couples metal；Described trench filling is conducted electricity and has the first conduction type, and described trench filling couples the front surface formation of metal and silicon substrate and electrically connects with described negative electrode.
Preferably, groove and the Schottky electrode number of Ohmic electrode is arranged one to one；It is to be formed at the cathodic metal on trench filling that described negative electrode connects metal.
Preferably, Ohmic electrode be some through-silicon epitaxial layers trench cycle arrangement form；Described negative electrode couples metal and includes: is formed at the barrier metal on the gap epitaxial layer between the groove of periodic arrangement and is formed at the cathodic metal of whole Ohmic electrode top layer, this barrier metal and cover cathodic metal thereon and trench gap epitaxial layer and formed and electrically connect.The width of each groove of periodic arrangement is 0.6～1.2 μm, and the gap epitaxial layer width between two grooves is 0.5～2 μm.
Further, described trench filling 61 is conductive polycrystalline silicon.
Further, the square resistance of described conductive polycrystalline silicon is 14～20 Ω/sq.
Further, described Schottky chip also includes sealing coat, is arranged between the lateral margin of described trench filling and described groove.
Further, described sealing coat is the silicon dioxide layer that thickness is 400～600A using thermal oxide to be formed；Or use the silicon dioxide layer that thickness is 1000～3000A that wet-oxygen oxidation is formed.
Preferably, described Schottky barrier metal is Ni, and described anode metal and cathodic metal are TiNiAg or TiWNiVAl.
Preferably, described Schottky barrier metal is Cr, and described anode metal and cathodic metal are CrNiAu or CrTiWNiVAl.
Beneficial effects of the present invention:
1) both by the two of Schottky chip electrode Schottky electrodes (anode) and Ohmic electrode (negative electrode) are arranged on the same first type surface of silicon epitaxy layer, reached wafer-level package and required that packaging has the size requirements of approximation semiconductor element.
2) if groove-shaped sinker area and negative electrode by the highly doped conductive polycrystalline silicon of dry-packing couple metal and constitute Ohmic electrode.Heavy doping conductive polycrystalline silicon has good conduction property, the conducting resistance of chip can be effectively reduced and the thickness of cathodic metal can be reduced further, thus improve its reverse-conducting characteristic, and further reduce the chip area that Ohmic electrode takies, the more efficient miniaturization realizing electronic circuit.
3) conductive polycrystalline silicon and groove lateral margin have been carried out the isolation of further insulant, Schottky electrode and the Ohmic electrode of chip are effectively isolated it, decrease the diffusion of dopant ion in subsequent high temperature processes of highly doped conductive polycrystalline silicon simultaneously, reduce further the reverse leakage current of this Schottky chip, make its reverse blocking capability strong, good reliability.
Accompanying drawing explanation
Fig. 1 is the structural representation of the Schottky chip using traditional packaged type.
Fig. 2 be notification number be the Schottky chip structure chart in the patent of invention of CN 100380679C.
The cross sectional representation of the Schottky chip 11 in Fig. 3 first embodiment of the invention.
The cross sectional representation of the Schottky chip 12 in Fig. 4 first embodiment of the invention.
Fig. 5 is the flow chart of the manufacture method of Schottky chip 11 in first embodiment of the invention.
Fig. 6 is the cross sectional representation of Schottky chip 20 in second embodiment of the invention.
The flow chart of the manufacture method of Schottky chip 20 in Fig. 7 second embodiment of the invention.
In each figure: silicon substrate 2, the front surface 2a of silicon substrate, the back surface 2b of silicon substrate; silicon epitaxy layer 3, the front surface 3a of silicon epitaxy layer, Schottky electrode 4; protection ring 41, Schottky barrier metal 42, anode metal 43; Ohmic electrode 6, trench filling 61, sealing coat 62; cathodic metal 63, injects sinker area 64, insulating barrier 7; once oxidation layer 71, secondary oxidation layer 72, three oxide layers 73.
Detailed description of the invention
Hereinafter based on accompanying drawing, embodiment of the present invention will be described.In following figure, identical or corresponding parts are presented with like reference characters, and the description that they will not be repeated.
Existing market mainly uses the Schottky chip using traditional packaged type, its structure such as Fig. 1, two electrodes i.e. Schottky electrode 4(anode of this chip) and Ohmic electrode 6(negative electrode) the front surface 3a and the back surface 2b of silicon substrate 2 of the silicon epitaxy layer 3 that is placed in so that it is the volume of packaging and package thickness are all difficult to meet further the limited space demand of small portable device.
nullNotification number is Schottky chip structure such as Fig. 2 of the wafer-level package provided in the patent of invention of CN 100380679C，Its negative electrode (Ohmic electrode 6) is because being by injecting and follow-up diffusion-driven forms a sinker area to be formed and the electrically connecting of silicon epitaxy layer in epitaxial region，Owing to being limited by injection technology and follow-up diffusion，The negative electrode of this structure is formed as injected the structure wide at the top and narrow at the bottom shown in sinker area 64 in Fig. 2 in diffusion process，And doping content forms gradient from high to low along diffusion path to its lower surface from the upper surface of injection region，The Ohmic electrode being consequently formed has high conducting resistance、It is difficult to reach and the conduction property of Fig. 1 traditional structure、Need bigger area so the Ohmic electrode of device can take bigger chip area simultaneously as it injects sinker area at silicon epitaxy layer front surface.
(first embodiment)
Comparing both above Schottky chip, Fig. 3 is the cross-sectional view schematically showing the Schottky chip 11 in first embodiment of the invention.As shown in Figure 3; Schottky chip 11 includes having the highly doped silicon substrate 2 of the first conduction type, the low-doped silicon epitaxy layer 3 being formed on the front surface 2a of highly doped silicon substrate 2, this silicon epitaxy layer 3 also have the first conduction type, the Schottky electrode 4 being formed on this silicon epitaxy layer 3, Ohmic electrode 6, be formed on silicon epitaxy layer 3 for the insulating barrier 7 isolating Schottky electrode 4 and Ohmic electrode 6, the protection ring 41 that arranges around the periphery of Schottky electrode 4, this protection ring 41 has and the second conduction type of the first conduction type opposite conductivities；Wherein said Schottky electrode 4 includes the Schottky barrier metal 42 being formed on silicon epitaxy layer 3 and covers the anode metal 43 on barrier metal 42；The composition of Ohmic electrode 6 includes: for some through-silicon epitaxial layers 3 groove and be formed at Ohmic electrode top layer negative electrode couple metal, and in groove, it being filled with the trench filling 61 with the first conduction type, this trench filling 61 couples metal formation and electrically connects with described silicon substrate 2 front surface 2a and negative electrode.The most described preferred heavy doping conductive polycrystalline silicon of trench filling 61, the preferably first conduction type is the N-type of the adulterant such as Doping Phosphorus or arsenic, and therefore the second conduction type of protection ring 41 is preferably the p-type of the adulterants such as doped with boron；As preferably, the Schottky barrier metal 42 of the present invention selects schottky barrier metal layer such as Ni, Ti, Cr etc. that potential barrier is relatively low, to reduce device forward cut-in voltage, the thickness of anode metal layer can also be reduced simultaneously, so can be substantially improved device forward conduction characteristic, and noble metal such as Pt equal proportion contained by the metal that generally potential barrier is relatively low is low or does not contains noble metal, therefore schottky barrier metal layer low cost, it is possible to decrease the cost of whole device；As preferably, the present invention uses silicon dioxide as isolation Schottky electrode 4 and the insulating barrier 7 of Ohmic electrode 6.Preferred as one, groove and the Schottky electrode number of Ohmic electrode are arranged one to one, and it is to be formed at the cathodic metal 63 on trench filling that negative electrode couples metal, and the square resistance of trench filling heavy doping conductive polycrystalline silicon is 14～20 Ω/sq.
Preferred as another, another arrangement of Ohmic electrode as shown in Schottky chip 12 in Fig. 4, Ohmic electrode is that the trench cycle arrangement of some through-silicon epitaxial layers 3 forms, the width h1 of the groove of periodic arrangement is 0.6～1.2 μm, gap epitaxial layer width h2 between two grooves is 0.5～2 μm, certainly, Fig. 4 simply illustrates the periodic arrangement pattern of groove and gap epitaxial layer thereof, being not offered as the groove number being limited to shown in figure, concrete groove number determines according to width h1, gap width h2 and the groove overall width of groove；Thus, it is the barrier metal 42 being formed on the epitaxial layer of gap and the cathodic metal 63 being formed at whole Ohmic electrode top layer that the negative electrode of the Ohmic contact forming Ohmic electrode 6 couples metal, this barrier metal and cover cathodic metal 63 thereon and trench gap epitaxial layer and formed and electrically connect.
The Schottky chip of the present invention, both by the two of Schottky chip electrode Schottky electrodes (anode) and Ohmic electrode (negative electrode) are arranged on the same first type surface of silicon epitaxy layer, reach wafer-level package and required that packaging has the size requirements of approximation semiconductor element, also improve the design of Ohmic electrode, if groove-shaped sinker area and anode metal by the highly doped conductive polycrystalline silicon of dry-packing constitute Ohmic electrode.Heavy doping conductive polycrystalline silicon has good conduction property, the conducting resistance of chip can be effectively reduced and the thickness of cathodic metal can be reduced further, thus improve its reverse-conducting characteristic, and further reduce the chip area that Ohmic electrode takies, the more efficient miniaturization realizing electronic circuit.
Describe the method for Schottky chip in the present embodiment that manufactures below with reference to Fig. 5, Fig. 5 is by the method flow diagram of Schottky chip in the manufacture the present embodiment shown in order of steps.
With reference to Fig. 5, silicon substrate preparation process (S10) is first carried out.In this substrate preparation process, prepared silicon substrate 2, monocrystalline silicon piece prepared by any preparation method all can be as this silicon substrate 2, such as: prepare the N-type silicon substrate with the heavy doping phosphorus that crystal orientation is<111>.
It follows that perform silicon epitaxy layer forming step (S20).In this step, silicon substrate 2 is formed silicon epitaxy layer 3, the relative silicon substrate of epitaxial layer 3 is for being lightly doped and having conduction type as silicon substrate, such as silicon substrate has a N-type silicon substrate of the heavy doping phosphorus that crystal orientation is<111>, then silicon epitaxy layer is the single-crystal Si epitaxial layers in<111>crystal orientation of N-type conduction of light p-doped.
It follows that perform insulating barrier part forming step (S30).In this step, the front surface 3a of silicon epitaxy layer 3 forms a silicon dioxide layer part as insulating barrier 7.Concrete, such as: to be deposited on silicon epitaxy layer surface deposition layer of silicon dioxide layer or by the silicon layer of thermal oxide epi-layer surface, form this silicon dioxide layer in epi-layer surface by performing chemical gaseous phase.The silicon dioxide of thermal oxide growth has more excellent film quality, stability and reliability to device performance are more favourable, but its speed of growth is slow, therefore, the present invention perform this insulating barrier part forming step preferably employ first pass through thermal oxide epi-layer surface formed one layer of i.e. once oxidation layer 71 of thin silicon dioxide layer, continue to deposit second layer silicon dioxide layer i.e. secondary oxidation layer 72 on first time silicon dioxide layer by chemical gaseous phase deposition again, the gross thickness of twice silicon dioxide layer reaches the thickness of the silicon dioxide layer required by this step, the most both ensure that the insulation characterisitic that insulating barrier is good, guarantee stability and the reliability of resulting devices performance, also ensure that the efficiency of production technology simultaneously, but this step is not limited to the described method carrying out twice oxidation.
It follows that perform groove forming step (S40).Concrete, this step, with the silicon dioxide layer that formed in previous step as hard mask, runs through the groove of whole silicon epitaxy layer by etching of photoetching and Etch selectivity.As preferably, according to Fig. 3, groove and the Schottky electrode number of Ohmic electrode are arranged one to one；Preferred as another, according to Fig. 4, the trench cycle arrangement that groove arrangement is some through-silicon epitaxial layers 3 of Ohmic electrode forms, therefore in this groove forming step, the A/F h1 of each groove is preferably 0.6～1.2 μm, and the gap epitaxial layer width h2 between two grooves is preferably 0.5～2 μm.Latter groove arrangement optimal way, the more easy to control and saving process time in production technology.
It follows that fill polysilicon step (S50).In this step, filling heavily doped polysilicon 61 in the groove formed above, this polysilicon 61 has the first conduction type as silicon epitaxy layer 3, such as, fill the polysilicon of heavy doping phosphorus, its conduction type is N-type, and the preferably square resistance of this heavily doped polysilicon is 14～20 Ω/sq.Concrete execution step is: first clean total layer surface；Afterwards at the polysilicon of total layer surface deposition of heavily doped, it is ensured that whole groove is filled；Selective removal partial polysilicon afterwards, makes the most only to be filled with polysilicon and polysilicon in groove concordant with epitaxial layer 3 front surface 3a.
It follows that the protection ring 41 forming step (S60) of Schottky electrode.Protection ring 41 uses ion implantation to be formed, and the conduction type of protection ring 41 is the second conduction type, contrary with the first conduction type, such as: the first conduction type is N-type, then protection ring uses ion implantation to inject boron ion, has conduction type p-type.Concrete, such as: etch oxide layer opening by photoresist so that it is expose silicon epitaxy layer；Then by ion implantation doping agent；Remove photoresist and clean total layer surface.
Formed and ion diffusing step (S70) it follows that perform insulating barrier another part.In this step; by chemical vapor deposition layer of silicon dioxide as three oxide layers 73 of insulating barrier another part, while three oxide layer 73 growths, by high temperature action during oxidation; carry out injecting the thermal diffusion of ion, thus ultimately form protection ring 41.Concrete, first clean the surface of total layer；Afterwards on total layer surface by that is three times oxide layer 73 of chemical vapor deposition layer of silicon dioxide layer; in deposition process; by controlling temperature and time during oxidation; meet the formation of requisite oxygen SiClx layer thickness simultaneously and injected the control of ion diffusion length, thus having formed final anode protection ring while forming silicon oxide layer.
It follows that perform barrier metal and top-level metallic forming step (S80).In this step, at anode openings, complete the formation of barrier metal 42, thus form barrier metal 42 and the Schottky contacts of silicon epitaxy layer 3 at anode；In this step, also complete top layer anode metal 43 and the formation of cathodic metal 63, anode metal and cathodic metal can select same metal the most all to select TiNiAg, or all select CrNiAu etc.；Different metals can also be selected to make anode and negative electrode respectively, but two electrodes select different metals, a photoetching and the technique of metal formation can be increased, device cost can increase therewith, therefore, the most same metal of the present invention is as two electrode matel material, but the invention is not restricted to this selection.Concrete, first carry out the photoetching corrosion step (S81) of insulating barrier, selective removal is as the silicon dioxide layer of insulating barrier, open negative electrode and anode openings, anode exposes the front surface 3a of silicon epitaxy layer 3, negative electrode exposes the upper surface (when forming the Schottky chip 12 of Fig. 4, also can expose the front surface of each trench gap epitaxial layer at this) of conductive polycrystalline silicon 61；Then carrying out barrier metal deposition step (S82), the method for barrier metal deposition can be magnetron sputtering or metal fever evaporation etc.；Then carry out negative electrode and anode metal forms (S83) step；Finally carry out metal lithographic corrosion step (S84), to open opening, the electrically connecting between cut-out anode metal and cathodic metal exposing insulating barrier 7.Preferably, such as barrier metal is Ni, and corresponding anode and cathodic metal select TiNiAg, because Ti and Ni has good adhesive force, it is ensured that contact good between metal, lowers conducting resistance, also reduces the risk that surface metal comes off；For another example: barrier metal is Ni, corresponding anode and cathodic metal select TiWNiVAl；For another example: barrier metal is Cr, corresponding anode and cathodic metal select CrNiAu or CrTiWNiVAl.But the selection of barrier metal of the present invention and negative electrode and anode metal is not limited to listed herein.Preferably, after carrying out barrier metal deposition step (S82), once make annealing treatment, it is made to form metal alloy with silicon epitaxy layer 3 surface silicon, to increase barrier height, reducing reverse leakage current, the barrier height of metal alloy is the most stable simultaneously, such as: barrier metal is NiPt alloy, after forming barrier metal NiPt, make annealing treatment, in this annealing process, at anode openings, barrier metal NiPt forms nickel silicon alloy and platinum silicon alloy on silicon epitaxy layer 3 surface with monocrystal silicon.
(the second embodiment)
Fig. 6 is to schematically show the cross-sectional view of Schottky chip 20 in the present embodiment.As shown in Figure 6, Schottky chip 20 in the present embodiment is with the difference of Schottky chip in first embodiment 11: Schottky chip farther includes: at the lateral margin of the groove of some through-silicon epitaxial layers 3, be provided with sealing coat 62 between conductive polycrystalline silicon 61 and groove lateral margin；Preferably, the insulant that sealing coat 62 is identical with insulating barrier selection, such as the same with insulating barrier 71 all use silicon dioxide, thus can be while insulating barrier 71 be formed, complete the formation of this sealing coat 62, decrease processing step, the manufacturing cost of saving components；The preferably thickness of this silicon dioxide sealing coat is 400～3000A.But the present invention is not limited to sealing coat 62 must select the same material with insulating barrier 7, it is possible to use different insulant respectively, but both use different materials, primary insulation material can be increased and formed and chemical wet etching step, device cost increase.The Schottky chip 20 of the present embodiment is relative to the Schottky chip 11 of first embodiment, because conductive polycrystalline silicon and groove lateral margin to have been carried out the isolation of further insulant, Schottky electrode and the Ohmic electrode of chip the most further it are effectively isolated, decrease the diffusion of dopant ion in subsequent high temperature processes of highly doped conductive polycrystalline silicon simultaneously, reduce further the reverse leakage current of this Schottky chip, its reverse blocking capability is made to strengthen, good reliability.
Fig. 7 is by the flow chart of the method for Schottky chip 20 in the manufacture the present embodiment shown in order of steps.
With reference to Fig. 7, silicon substrate preparation process (S10) being first carried out, this step is identical with first embodiment.
It follows that perform silicon epitaxy layer forming step (S20), this step is identical with first embodiment.
It follows that perform insulating barrier part forming step (S30).This step is identical with first embodiment.
It follows that perform groove forming step (S40).This step is identical with first embodiment.
It follows that perform sealing coat forming step (S90).In this step, the making of sealing coat 62 between conductive polycrystalline silicon 61 and groove lateral margin is completed.Concrete, such as: first carry out oxidation step (S91), it is deposited on total surface deposition layer of silicon dioxide layer by chemical gaseous phase, this step can use thermal oxide, its thickness is preferably 400～600A, or uses wet-oxygen oxidation, and its thickness is 1000～3000A；Then sealing coat photoetching corrosion step (S92) is performed, the silicon dioxide layer of channel bottom is optionally removed by photoetching corrosion, expose the front surface 3a of the silicon epitaxy layer 3 of channel bottom, and it being retained in the silicon dioxide layer that groove lateral margin is formed, the silicon dioxide layer of this groove lateral margin i.e. constitutes described sealing coat 62.
It follows that perform to fill polysilicon step (S50), the protection ring 41 forming step (S60) of Schottky electrode, the formation of insulating barrier another part and ion diffusing step (S70), barrier metal and top-level metallic forming step (S80).These steps are identical with first embodiment.
Certainly, in the present embodiment, the groove arrangement of Schottky chip 20 equally uses such as the periodic arrangement mode of Schottky chip 12 in first embodiment, its alternative approach equivalent and the change of Schottky chip 11 to Schottky chip 12 in first embodiment.
Hereinafter, the example of the present invention will be described.
Example 1
The manufacture method of Schottky chip 11, the Schottky chip of this example produced in the first embodiment of the invention that this example illustrates according to Fig. 5.
Concrete, silicon substrate preparation process, employ the N-type silicon substrate of the heavy doping phosphorus that crystal orientation is<111>, resistivity is 0.0010 Ω cm.
It follows that silicon epitaxy layer is formed, define the silicon epitaxy layer in<111>crystal orientation of the N-type conduction of light p-doped, silicon epitaxy layer thickness 3.6 μm, resistivity 0.56 Ω cm.
It follows that first pass through thermal oxide first grow the silicon dioxide of one layer of once oxidation layer 500A, then formed the silicon dioxide of secondary oxidation layer 5000A by wet-oxygen oxidation.
It follows that to form silicon dioxide layer above as hard mask, optionally etch a rectangular groove by photoetching and dry etching, and expose the front surface 3a of silicon epitaxy layer at channel bottom.
It follows that by LPCVD deposition process in the groove formed above, fill the conductive polycrystalline silicon of Doping Phosphorus in the trench, the square resistance of conductive polycrystalline silicon is 18 Ω/sq.
It follows that etch oxide layer opening by photoresist so that it is expose silicon epitaxy layer；Then by ion implantation doping agent boron, the protection ring 41 of Schottky electrode is formed；Remove photoresist and clean total layer surface.
It follows that formed the silicon dioxide of three i.e. thickness 3300A of oxide layer by chemical vapor deposition, simultaneously by high temperature action during oxidation, carry out injecting the thermal diffusion of ion, thus ultimately formed protection ring 41.
It follows that form barrier metal and two electrode metals.Concrete, first carry out the photoetching corrosion of insulating barrier silicon dioxide, optionally remove silicon dioxide layer, open negative electrode and anode openings；Then carrying out having carried out barrier metal Ni by metal fever evaporation to deposit, the thickness of Ni is 500A；Then carry out at a temperature of 450 degree, N2 protects the annealing under atmosphere; in this annealing process, at anode openings, barrier metal Ni defines nickel silicon alloy on silicon epitaxy layer 3 surface with monocrystal silicon; nickel silicon alloy and silicon epitaxy layer constitute Schottky contacts, form potential barrier；Use metal fever evaporation afterwards, at total layer forming metal layer on surface TiNiAg；Finally carry out metal lithographic corrosion, with the connection opening the opening exposing silicon dioxide layer, cut off between anode metal and cathodic metal.
Example 2
The manufacture method of Schottky chip 20, the Schottky chip of this example produced in the embodiment of the present invention two that this example illustrates according to Fig. 7.The Schottky chip of this example and example 1 difference are the silicon dioxide sealing coat adding between groove lateral margin and conductive polycrystalline silicon, this silicon dioxide sealing coat is formed by wet-oxygen oxidation, its thickness is 1500A, and remaining is as all identical with example 1 in silicon substrate, silicon epitaxy layer, conductive polycrystalline silicon, barrier metal, two electrode metals etc..
Claims (10)
1. for a Schottky chip for wafer-level package, including:
Highly doped silicon substrate (2)；
It is formed at the low-doped silicon epitaxy layer (3) on the front surface (2a) of highly doped silicon substrate (2)；
The Schottky electrode (4) that is formed on this silicon epitaxy layer (3), Ohmic electrode (6)；
It is formed at being used on silicon epitaxy layer (3) and isolates the insulating barrier (7) of Schottky electrode (4) and Ohmic electrode (6)；
And the protection ring (41) of the periphery setting around Schottky electrode (4)；
Described silicon substrate (2) and described silicon epitaxy layer (3) have the first conduction type；It is contrary that described protection ring (41) has the second conduction type, the second conduction type and the first conduction type electric conductivity；
Described Schottky electrode (4) includes the Schottky barrier metal (42) being formed on the front surface (3a) of silicon epitaxy layer and covers the anode metal (43) on barrier metal (42)；
The composition of described Ohmic electrode (6) including: the groove of some through-silicon epitaxial layers (3), fills the trench filling (61) of described groove, and the negative electrode being formed at Ohmic electrode top layer couples metal；Described trench filling (61) is conducted electricity and has the first conduction type, and described trench filling (61) couples front surface (2a) formation of metal and silicon substrate and electrically connects with described negative electrode.
A kind of Schottky chip for wafer-level package the most according to claim 1, it is characterised in that:
Groove and the Schottky electrode number of Ohmic electrode are arranged one to one；
It is to be formed at the cathodic metal (63) on trench filling (61) that described negative electrode couples metal.
A kind of Schottky chip for wafer-level package the most according to claim 1, it is characterised in that:
Ohmic electrode is that the trench cycle arrangement of some through-silicon epitaxial layers (3) forms；
Described negative electrode couples metal and includes: the barrier metal (42) being formed on the gap epitaxial layer between the groove of periodic arrangement and the cathodic metal (63) being formed at whole Ohmic electrode top layer, this barrier metal and cover cathodic metal thereon (63) and trench gap epitaxial layer and formed and electrically connect.
A kind of Schottky chip for wafer-level package the most according to claim 3, it is characterised in that: the width of each groove of periodic arrangement is 0.6～1.2 μm, and the gap epitaxial layer width between two grooves is 0.5～2 μm.
5. according to a kind of Schottky chip for wafer-level package described in any one of Claims 1 to 4, it is characterised in that: described trench filling (61) is conductive polycrystalline silicon.
A kind of Schottky chip for wafer-level package the most according to claim 5, it is characterised in that: the square resistance of described conductive polycrystalline silicon is 14～20 Ω/sq.
7. according to a kind of Schottky chip for wafer-level package described in any one of Claims 1 to 4, it is characterized in that: described Schottky chip also includes that sealing coat (62), described sealing coat (62) are arranged between described trench filling (61) and the lateral margin of described groove.
A kind of Schottky chip for wafer-level package the most according to claim 7, it is characterised in that: described sealing coat is the silicon dioxide layer that thickness is 400～600A using thermal oxide to be formed；Or use the silicon dioxide layer that thickness is 1000～3000A that wet-oxygen oxidation is formed.
A kind of Schottky chip for wafer-level package the most according to claim 1, it is characterised in that: described Schottky barrier metal (42) is Ni, and described anode metal (43) and cathodic metal (63) they are TiNiAg or TiWNiVAl.
A kind of Schottky chip for wafer-level package the most according to claim 1, it is characterised in that: described Schottky barrier metal (42) is Cr, and described anode metal (43) and cathodic metal (63) they are CrNiAu or CrTiWNiVAl.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10615292B2 (en) | 2018-03-27 | 2020-04-07 | Hong Kong Applied Science And Technology Research Institute Co., Ltd. | High voltage silicon carbide Schottky diode flip chip array |
| CN111430468A (en) * | 2020-03-06 | 2020-07-17 | 江阴新顺微电子有限公司 | Double-core isolation structure of double-cell packaged Schottky diode chip and manufacturing method |
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| CN1708850A (en) * | 2002-11-06 | 2005-12-14 | 国际整流器公司 | Chip-scale schottky device |
| US20060030142A1 (en) * | 2004-08-03 | 2006-02-09 | Grebs Thomas E | Semiconductor power device having a top-side drain using a sinker trench |
| CN205428934U (en) * | 2016-02-03 | 2016-08-03 | 杭州立昂微电子股份有限公司 | A schottky chip for encapsulation of chip level |
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| CN1708850A (en) * | 2002-11-06 | 2005-12-14 | 国际整流器公司 | Chip-scale schottky device |
| US20060030142A1 (en) * | 2004-08-03 | 2006-02-09 | Grebs Thomas E | Semiconductor power device having a top-side drain using a sinker trench |
| CN205428934U (en) * | 2016-02-03 | 2016-08-03 | 杭州立昂微电子股份有限公司 | A schottky chip for encapsulation of chip level |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10615292B2 (en) | 2018-03-27 | 2020-04-07 | Hong Kong Applied Science And Technology Research Institute Co., Ltd. | High voltage silicon carbide Schottky diode flip chip array |
| CN111430468A (en) * | 2020-03-06 | 2020-07-17 | 江阴新顺微电子有限公司 | Double-core isolation structure of double-cell packaged Schottky diode chip and manufacturing method |
| CN111430468B (en) * | 2020-03-06 | 2023-06-20 | 江苏新顺微电子股份有限公司 | Dual-core isolation structure of dual-cell packaged Schottky diode chip and manufacturing method |
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