CN104124151B - A trench-structure of a Schottky barrier diode and the manufacturing method - Google Patents

A trench-structure of a Schottky barrier diode and the manufacturing method Download PDF

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CN104124151B
CN104124151B CN 201410333547 CN201410333547A CN104124151B CN 104124151 B CN104124151 B CN 104124151B CN 201410333547 CN201410333547 CN 201410333547 CN 201410333547 A CN201410333547 A CN 201410333547A CN 104124151 B CN104124151 B CN 104124151B
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CN 201410333547
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CN104124151A (en )
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郭涵
郑晨焱
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中航(重庆)微电子有限公司
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本发明提供一种沟槽结构肖特基势垒二极管及其制作方法,所述制作方法包括步骤:1)于N型重掺杂的硅衬底表面形成N型轻掺杂的硅外延层;2)于所述硅外延层形成多个间隔排列的沟槽;3)对各所述沟槽的底部进行刻蚀,形成预设形状的沟槽底部结构,于各所述沟槽底部结构表面形成介质层;4)于所述沟槽底部结构及沟槽内填充P型硅;5)于所述硅外延层表面形成金属硅化物;6)于所述金属硅化物表面形成阳电极;7)减薄所述硅衬底,并于所述硅衬底背面形成阴电极。 The present invention provides a trench Schottky barrier diode structure and fabrication method, the manufacturing method comprising the steps of: 1) a heavily doped N-type silicon substrate surface lightly doped N-type silicon epitaxial layer; 2) a plurality of spaced grooves formed in said silicon epitaxial layer; 3) of the bottom of each trench is etched to form a predetermined shape of the bottom of the trench structure, the trench bottom to the respective surface structure forming a dielectric layer; 4) to the bottom of the trench structure and the P-type silicon trench fill; 5) surface of the silicon epitaxial layer forming a metal silicide; 6) an anode electrode is formed on the surface of the metal silicide; 7 ) thinning the silicon substrate, and forming a cathode electrode on the back surface of the silicon substrate. 与现有技术相比较,本发明利用新型沟槽型结构,制作出性能更优的肖特基势垒二极管器件,在保证所需反向击穿电压的同时,降低正向导通压降,并且减小器件面积。 Compared with the prior art, the present invention utilizes a novel trench structure, to produce a better performance of the Schottky barrier diode device, to ensure the required reverse breakdown voltage while reducing the forward voltage drop, and reduced device area.

Description

一种沟槽结构肖特基势垒二极管及其制作方法 A trench-structure of a Schottky barrier diode and the manufacturing method

技术领域 FIELD

[0001]本发明属于半导体及半导体制造领域,特别是涉及一种沟槽结构肖特基势垒二极管及其制作方法。 [0001] The present invention belongs to the field of semiconductors and semiconductor manufacturing, particularly to a structure of a trench Schottky barrier diode and a manufacturing method thereof.

背景技术 Background technique

[0002] 随着半导体技术的不断发展,功率器件作为一种新型器件,被广泛地应用于磁盘驱动、汽车电子等领域。 [0002] With the continuous development of semiconductor technology, the power device as a new device, it is widely used in disk drives, automotive electronics. 功率器件需要能够承受较大的电压、电流以及功率负载。 Power devices need to be able to withstand a large voltage, current and power load. 而现有M0S 晶体管等器件无法满足上述需求,因此,为了满足应用的需要,各种功率器件成为关注的焦点。 M0S transistor, the existing device can not meet the above requirements, therefore, in order to meet the needs of the application, various power devices into focus.

[0003]肖特基势垒二极管一般是以金属(金、银、铝、铂等)为正极,以N型半导体为负极, 利用二者接触面上形成的势垒具有整流特性而制成的金属-半导体器件。 [0003] Usually a Schottky barrier diode is a metal (gold, silver, aluminum, platinum, etc.) is made as a positive electrode, a negative electrode of N-type semiconductor, the potential barrier formed by using both a contact surface having a rectifying property metal - semiconductor device. 因为N型半导体中存在着大量的电子,金属中仅有极少量的自由电子,所以电子便从浓度高的N型半导体中向浓度低的金属中扩散。 Since there are a lot of electrons, only a very small amount of metal free electrons in the N-type semiconductor, it begins with a high electron concentration N-type semiconductor having a low concentration is diffused metal. 显然,金属中没有空穴,也就不存在空穴自金属向N型半导体的扩散运动。 Clearly, there is no hole in the metal, there would be no movement of holes from diffusing metal into the N-type semiconductor. 随着电子不断从N型半导体扩散到金属,N型半导体表面电子浓度逐渐降低,表面电中性被破坏,于是就形成势垒,其电场方向为N型半导体—金属。 As the electrons from the N-type semiconductor continued to spread to the metal, the N-type semiconductor surface electron concentration gradually decreases, neutral surface is damaged, so they form a barrier, which is the direction of the electric field N-type semiconductor - metal. 但在该电场作用之下,金属中的电子也会产生从金属—N型半导体的漂移运动,从而削弱了由于扩散运动而形成的电场。 However, under the electric field, the electrons in the metal from the metal will drift motion -N-type semiconductor, thus weakening the electric field formed by the motion due to diffusion. 当建立起一定宽度的空间电荷区后,电场引起的电子漂移运动和浓度不同引起的电子扩散运动达到相对的平衡,便形成了肖特基势垒。 When the space charge region to establish a certain width, different electric field induced electron drift motion and equilibrium concentration relative movement caused by electron diffusion, it will form a Schottky barrier. 肖特基二极管是一种低功耗、超高速半导体器件。 The Schottky diode is a low-power, ultra-high speed semiconductor device. 最显著的特点为反向恢复时间极短(可以小到几纳秒),正向导通压降低。 The most notable feature is the reverse recovery time is very short (as small as a few nanoseconds), the forward voltage drop. 其多用作高频、低压、大电流整流二极管、续流二极管、保护二极管,也有用在微波通信等电路中作整流二极管、小信号检波二极管使用。 Which is often used as a high-frequency, low-voltage, high-current rectifier diode, a freewheeling diode, a protective diode, the rectifying diode is also useful for microwave communication circuits, small signal detector diodes used. 在通信、电源、变频器、太阳能接线盒等中比较常见。 In the more common communications, power, inverter, junction box or the like solar energy.

[0004]肖特基势垒二极管是常见的两端器件,它由金属和低掺杂N型硅形成肖特基接触来工作的,常用来形成肖特基接触的金属有钛、镍、铂金、钼及钴等,这些金属和表面洁净的n型硅经快速热退火后会形成金属硅化物。 [0004] Schottky barrier diodes are common across the device, which is formed of a metal and a low-doped N-type silicon Schottky contact to work, the metal used to form a Schottky contact are titanium, nickel, platinum , molybdenum, and cobalt, these metals and n-type silicon clean surface after rapid thermal annealing will form a metal silicide. 近年来,沟槽技术被广泛使用,常用的沟槽型结构是由介质层及导电介质组成的。 Recently, trench technology is widely used, it is a conventional trench structure by a dielectric layer and a conductive medium thereof. 肖特基势垒二极管使用沟槽结构有两个重要原因,其一, 传统平面型结构容易表面击穿,对器件的可靠性带来挑战,而沟槽结构肖特基势垒二极管克服了平面型结构的这一缺点;其二,沟槽型肖特基势垒二极管利用电荷平衡(charge balance)原理可以提高器件的击穿电压。 Using a trench Schottky barrier diode structure has two important reasons, First, the conventional planar structure can be easily surface breakdown, the device reliability challenges, and the channel structure to overcome the Schottky barrier diode plane the disadvantage of the structure; Second, the trench Schottky barrier diode using charge balance (charge balance) principles can increase the breakdown voltage of the device. 传统的沟槽结构是使用氧化层作沟槽结构的,这种结构可以提高器件的击穿电压也可以降低表面电场,不过这种结构的正向性能较差,要达到某个较大电流会浪费很多面积。 Conventional trench structure is used as a trench oxide layer structure, this structure can increase the breakdown voltage of the device may also reduce the surface electric field, but the poor performance of such a forward configuration, a large current will be achieved waste a lot of space.

[0005] 传统沟槽型肖特基势垒二极管器件的正向导通电压较大,无效面积与有效面积的比值较大,浪费较多的面积,不符合器件微型化的发展趋势,因此,本发明提供了一种新型沟槽结构,以在保证器件击穿电压满足要求的同时降低正向导通电压,并且通过调节沟槽间距来降低无效面积与有效面积的比值,从而节约器件面积,使器件性能更优更微型化。 Forward voltage [0005] The conventional trench Schottky barrier diode device is large, the void ratio of the area of ​​the larger effective area, an area of ​​more waste, does not meet the trend of miniaturization of the device, therefore, the present invention provides a novel trench structure, to simultaneously satisfy the requirements of the breakdown voltage of the device to ensure the reduction in forward voltage, and the ratio of the ineffective area is reduced by adjusting the effective area of ​​the groove pitch, thereby saving device area, the device better performance and more miniaturized.

发明内容 SUMMARY

[0006]鉴于以上所述现有技术的缺点,本发明的目的在于提供一种沟槽结构肖特基势垒二极管及其制作方法,用于在保证肖特基势垒二极管反向击穿能力的同时,减小正向导通压降和减小芯片面积。 [0006] In view of the foregoing disadvantages of the prior art, an object of the present invention is to provide a structure of a trench Schottky barrier diode and a manufacturing method for ensuring a Schottky barrier diode reverse breakdown capability at the same time, reducing the forward voltage drop and reduce the chip area.

[0007] 为实现上述目的及其他相关目的,本发明提供一种沟槽结构肖特基势垒二极管的制作方法,包括以下步骤: [0007] To achieve the above objects and other related objects, the present invention provides a method of manufacturing a trench structure of a Schottky barrier diode, comprising the steps of:

[0008] 1)提供一N型重掺杂的硅衬底,于所述硅衬底表面形成N型轻掺杂的硅外延层; [0008] 1) providing a heavily doped N-type silicon substrate, the silicon substrate surface to form an N-type lightly doped epitaxial silicon layer;

[0009] 2)于所述硅外延层形成多个间隔排列的沟槽; ' [0009] 2) a plurality of spaced grooves formed in said silicon epitaxial layer; '

[0010] 3)对各所述沟槽的底部进行刻蚀,形成预设形状的沟槽底部结构,于各所述沟槽底部结构表面形成介质层,并裸露出各所述沟槽侧壁的硅外延层; [0010] 3) of the bottom of each trench etching, the trench formed in a predetermined shape bottom structure, a dielectric layer is formed on each of the bottom surface of the trench structure, the trench sidewalls and each of said exposed the silicon epitaxial layer;

[0011] 4)于所述沟槽底部结构及沟槽内填充P型硅,并去除多余的P型硅直至露出所述硅外延层表面; [0011] 4) P-type silicon is filled in the trench structure and the trench bottom, removing excess until the P-type silicon epitaxial layer to expose said silicon surface;

[0012] 5)于所述硅外延层表面形成肖特基金属,并进行退火使所述硅外延层及肖特基金属间形成金属硅化物; [0012] 5) forming a Schottky metal on the surface of the silicon epitaxial layer, and annealing said silicon epitaxial layer between the Schottky metal and forming a metal silicide;

[0013] 6)于所述金属娃化物表面形成阳电极; [0013] 6) an anode electrode is formed on the surface of the metal compound baby;

[0014] 7)减薄所述硅衬底,并于所述硅衬底背面形成阴电极。 [0014] 7) thinning the silicon substrate, and forming a cathode electrode on the back surface of the silicon substrate.

[0015] 作为本发明沟槽结构肖特基势垒二极管的制作方法的一种优选方案,步骤3)包括以下步骤: [0015] A preferred method for fabricating a trench structure as an embodiment of the present invention, a Schottky barrier diode, step 3) comprises the steps of:

[0016] 3-1)于各所述沟槽的侧壁及底部形成刻蚀阻挡层; [0016] 3-1) etch stop layer is formed on the sidewalls and bottom of each trench;

[0017] 3-2)选择性刻蚀以去除各沟槽底部的刻蚀阻挡层,保留各沟槽侧壁的刻蚀阻挡层; [0017] 3-2) is selectively etched to remove the etch stop layer at the bottom of each trench, the sidewall of each groove to retain the etch stop layer;

[0018] 3-3)刻蚀各沟槽底部以形成预设形状的沟槽底部结构; [0018] 3-3) the bottom of each trench is etched to form a predetermined shape of the groove bottom structure;

[0019] 3-4)于所述沟槽底部结构表面形成介质层; [0019] 3-4) to the bottom surface of the trench structure forming a dielectric layer;

[0020] 3-5)选择性刻蚀去除各沟槽侧壁的刻蚀阻挡层,裸露出各沟槽侧壁的硅外延层。 [0020] 3-5) selectively removing each of the sidewalls of the trench etching the etch stop layer, trench sidewalls of each bare silicon epitaxial layer.

[0021] 作为本发明沟槽结构肖特基势垒二极管的制作方法的一种优选方案,所述沟槽底部结构的截面形状包括多边形、圆球形或椭球形。 [0021] As a preferred embodiment of the method for fabricating a trench structure according to the present invention, a Schottky barrier diode, the cross-sectional shape of the bottom of the trench structure comprises a polygonal, spherical or ellipsoidal.

[0022] 作为本发明沟槽结构肖特基势垒二极管的制作方法的一种优选方案,所述沟槽底部结构的最大径向宽度为大于所述沟槽底部的径向宽度。 [0022] As a preferred embodiment of the method for fabricating a trench structure of a Schottky barrier diode according to the present invention, the bottom of the trench structure to be greater than the maximum radial width of the radial width of the channel bottom.

[0023]作为本发明沟槽结构肖特基势垒二极管的制作方法的一种优选方案,步骤4)所填充的P型硅为完全充满所述沟槽底部结构的填充结构、内部具有空洞的填充结构或于p型硅与介质层之间具有空洞的填充结构。 [0023] As a preferred embodiment of the method for fabricating a trench structure of a Schottky barrier diode of the present invention, the step 4) P-type silicon filled completely filled with the filling structure of the bottom of the trench structure, having a hollow interior filling structure or a structure having a cavity filled between the p-type silicon and the dielectric layer.

[0024]作为本发明沟槽结构肖特基势垒二极管的制作方法的一种优选方案,步骤4)还包括对所述硅外延层表面进行清洗的步骤。 [0024] A preferred method for fabricating a trench structure as an embodiment of the present invention, a Schottky barrier diode, step 4) further comprises the step of cleaning the surface of the epitaxial silicon layer.

[0025] 本发明还提供一种沟槽结构肖特基势垒二极管,包括: [0025] The present invention further provides a trench Schottky barrier diode structure, comprising:

[0026] N型重掺杂的硅衬底; [0026] N-type heavily doped silicon substrate;

[0027] N型轻掺杂的硅外延层,结合于所述硅衬底表面; [0027] N-type lightly doped epitaxial silicon layer, bonded to the silicon substrate surface;

[0028] 多个沟槽,间隔形成于所述硅外延层中; [0028] a plurality of grooves formed in said spacer layer of epitaxial silicon;

[0029] 沟槽底部结构,呈预设形状形成于各所述沟槽的底部; [0029] The bottom of the trench structure, the form of each preset shape formed on the bottom of the trench;

[0030] 介质层,结合于各沟槽底部结构表面; [0030] dielectric layer, bonded to the bottom surface of each trench structure;

[0031] P型硅,填充于各沟槽底部结构及各沟槽中; L」 i牌庇札物,形成于所述硅外延层表面; [0031] P-type silicon, the trench is filled in each of the bottom structure and each trench; L 'i card shelter sheaf was formed on the surface of the epitaxial silicon layer;

[0033]阳电极,形成于所述金属娃化物麵; [0033] The anode electrode is formed on the metal surface Wa thereof;

[0034]阴电极,形成于所述硅衬底背面。 [0034] The cathode electrode is formed on the back surface of the silicon substrate.

[0035]作为本发麵觸结构肖特雜垒二极管的—种讎方案,臟沟槽底部结构的截面形状包括多边形、圆球形或椭球形。 [0035] The contact structure of the present proofed Schottky barrier diode heteroaryl - species Chou embodiment, the sectional shape of the bottom structure comprising a polygonal groove dirty, spherical or ellipsoidal.

[_作为本发麵觸结构肖纏触二贿的-种讎方案,臟捕底部结构的最大径向宽度为大于所述沟槽底部的径向宽度。 [_ Present proofing structure Shore wound contact two contact bribes - species Chou embodiment, the base structure of the catch dirty maximum radial width is greater than the radial width of the channel bottom.

[0037]作为本发明的沟槽结构肖特基势垒二极管的一种优选方案,所述介质层的厚度为O.OOlum〜lOum。 [0037] As a preferred embodiment of the present invention, the trench structure Schottky barrier diode, the thickness of the dielectric layer is O.OOlum~lOum. 、[^038]、、作为^发明的沟槽结构肖特基势垒二极管的一种优选方案,所述p型硅为完全充满所述沟槽底部结构的填充结构、内部具有空洞的填充结构或于P型硅与介质层之间具有空洞的填充结构。 , [^ 038],, as a preferred embodiment of the invention, a trench structure ^ Schottky barrier diode, the p-type silicon to completely fill said trench filling structure floor structure, having a hollow interior filling structure or filling structure having a cavity between the P-type silicon and the dielectric layer.

[0039]作为本发明的沟槽结构肖特基势垒二极管的一种优选方案,所述N型轻掺杂的硅外延层的掺杂浓度为1 X xl〇18/cm3,所述P型硅的掺杂浓度为丨xx 1019/cm3。 [0039] As a preferred embodiment of the present invention, the trench structure Schottky barrier diode, the N-type doping concentration of the lightly doped silicon epitaxial layer is 1 X xl〇18 / cm3, the P-type Shu Si doping concentration is xx 1019 / cm3.

[0040]如上所述,本发明提供一种沟槽结构肖特基势垒二极管及其制作方法,所述制作方法包括以下步骤:1)提供一N型重掺杂的硅衬底,于所述硅衬底表面形成N型轻掺杂的硅外延层;2)于所述桂外延层形成多个间隔排列的沟槽;3)对各所述沟槽的底部进行刻蚀,形成预设形状的沟槽底部结构,于各所述沟槽底部结构表面形成介质层,并裸露出各所述沟槽侧壁的硅外延层;4)于所述沟槽底部结构及沟槽内生长p型硅,并去除多余的p型硅直至露出所述硅外延层表面;5)于所述硅外延层表面形成肖特基金属,并进行退火使所述硅外延层及肖特基金属间形成金属硅化物;6)于所述金属硅化物表面形成阳电极;7)减薄所述硅衬底,并于所述硅衬底背面形成阴电极。 [0040] As described above, the present invention provides a trench Schottky barrier diode structure and fabrication method, the manufacturing method comprising the steps of: a) providing a heavily doped N-type silicon substrate, to the said N-type silicon substrate surface is formed of lightly doped silicon epitaxial layer; 2) in said epitaxial layer forming a plurality of Gui spaced trenches; 3) etching the bottom of each of the trench, forming a predetermined the bottom of the trench-shaped structure, the bottom surface of the trench structure formed on each of said dielectric layer, and the exposed trench sidewalls of each of the silicon epitaxial layer; grown p 4) in said trench bottom and trench structure silicon, removing excess until the p-type silicon epitaxial layer to expose said silicon surface; 5) surface of the silicon epitaxial layer forming a Schottky metal, and annealing the formed silicon epitaxial layer between the Schottky metal and metal silicide; 6) formed on the surface of the metal silicide anode electrode; 7) thinning the silicon substrate, and the backside of the silicon substrate to form a cathode electrode. 与现有技术相比较,本发明利用新型沟槽型结构,能制作出性能更优的肖特基势垒二极管器件,在保证所需反向击穿电压的同时,降低正向导通压降,并且减小器件面积。 Compared with the prior art, the present invention utilizes a novel trench structure, we can produce a better performance of the Schottky barrier diode device, while ensuring a desired reverse breakdown voltage, reducing the forward voltage drop, and to reduce the device area.

附图说明 BRIEF DESCRIPTION

[0041] 图1显示为本发明的沟槽结构肖特基势垒二极管的制作方法中步骤1)所呈现的结构示意图。 [0041] Figure 1 shows a method for fabricating a trench structure of the present invention, the Schottky barrier diode in step 1) presented a schematic view of the structure.

[0042] 图2显示为本发明的沟槽结构肖特基势垒二极管的制作方法中步骤2)所呈现的结构示意图。 [0042] FIG. 2 shows a schematic view of the structure of a trench structure of the present invention method for fabricating a Schottky barrier diode in step 2) is presented. _ _

[0043] 图3〜图6显示为本发明的沟槽结构肖特基势垒二极管的制作方法中步骤3)所呈现的结构不意图。 [0043] FIG 3 ~ FIG. 6 shows a method for fabricating a trench structure of the present invention, the Schottky barrier diode in Step 3) of the presented structure is not intended. ,

[0044] 图7显示为本发明的沟槽结构肖特基势垒二极管的制作方法中步骤4)所呈现的结构示意图。 [0044] FIG. 7 shows a schematic structural diagram of manufacturing method of a trench structure of the present invention, the Schottky barrier diode in step 4) presented. ,

[0045] 图8显示为本发明的沟槽结构肖特基势垒二极管的制作方法中步骤5)所呈现的结构示意图。 [0045] FIG. 8 shows a schematic structural diagram of manufacturing method of a trench structure of the present invention, the Schottky barrier diode in step 5) is presented. ,

[0046] 图9显示为本发明的沟槽结构肖特基势垒二极管的制作方法中步骤6)所呈现的结构示意图。 [0046] Figure 9 shows a method for fabricating a trench structure of the present invention, the Schottky barrier diode in step 6) according to one presented. L〇° J图10业不为本友明的沟槽结构肖特基势垒二极管的制作方法中步骤7)所呈现的结构示意图。 FIG 10 ° J L〇 no industry schematic structural diagram of manufacturing method of the trench structure Friends of the Schottky barrier diode in step 7) presented.

[0048]图11显示为本发明的沟槽结构肖特基势垒二极管与传统沟槽结构的肖特基势垒二极管器件的内部电压-总电流正向特性曲线示意图。 [0048] FIG. 11 shows the internal structure of the present invention, the voltage trench Schottky barrier diode is a Schottky barrier diode device of the conventional trench structure - forward characteristic curve of the total current schematic.

[0049] 元件标号说明 [0049] DESCRIPTION OF REFERENCE NUMERALS element

[0050] 101 硅衬底 [0050] The silicon substrate 101

[0051] 102 硅外延层 [0051] The silicon epitaxial layer 102

[0052] 1〇3 沟槽 [0052] The trench 1〇3

[0053] 104 刻蚀阻挡层 [0053] The etch stop layer 104

[0054] 105 沟槽底部结构 [0054] The bottom of the trench structure 105

[0055] 106 介质层 [0055] The dielectric layer 106

[0056] 1〇7 P型硅 [0056] P-type silicon 1〇7

[0057] 108 金属硅化物 [0057] Metal silicide 108

[0058] 1〇9 阳电极 [0058] The anode electrode 1〇9

[0059] 11〇阴电极 [0059] The cathode electrode 11〇

具体实施方式 detailed description

[0060]以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。 [0060] Hereinafter, an embodiment of the present invention by certain specific examples, those skilled in the art disclosed in this specification may readily understand the content of other advantages and effects of the present invention. 本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。 The present invention may also be implemented or applied through other different specific embodiments, the details of the specification may be carried out in various modified or changed without departing from the spirit of the invention based on various concepts and applications.

[0061]请参阅图1〜图11。 [0061] Referring to FIG. 1 ~ 11. 需要说明的是,本实施例中所提供的图示仅以示意方式说明本发明的基本构想,遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制,其实际实施时各组件的型态、数量及比例可为一种随意的改变,且其组件布局型态也可能更为复杂。 Incidentally, the present embodiment illustrates a schematic manner only examples provided to illustrate the basic idea of ​​the invention, then the drawings shows only related to the present invention, the number of components in the assembly when not in accordance with the actual embodiment, the shape and drawn to scale, its actual implementation of each component type, number and proportion of changes may be as a free, and the layout of the components may also be more complex patterns.

[0062]如图1〜图11所示,本实施例提供一种沟槽结构肖特基势垒二极管的制作方法,包括以下步骤: [0062] As shown in FIG. 1 ~ 11, the present embodiment provides a method for manufacturing a trench Schottky barrier diode structure, comprising the steps of:

[0063] 如图1所示,首先进行步骤1),提供一N型重掺杂的硅衬底101,于所述硅衬底101表面形成N型轻掺杂的硅外延层102。 [0063] As shown in FIG. 1, first step a), providing a heavily doped N-type silicon substrate 101, an N-type lightly doped epitaxial silicon layer 102 on the surface of the silicon substrate 101.

[0064] 作为示例,所述N型重掺杂的硅衬底101的电阻率选择为不大于〇.〇l〇hm • cm,所述N型轻掺杂的硅外延层102的掺杂浓度选择为1 X 1013/cm3〜1 X 1018/cm3之间,厚度选择为2 微米至50微米之间。 [0064] As an example, the N-type heavily doped resistivity of the silicon substrate 101 is selected to be not larger than 〇.〇l〇hm • cm, the doping concentration of the lightly doped N-type silicon epitaxial layer 102 selected to 1 X 1013 / cm3~1 X 1018 / between cm3, a thickness selected between 2 to 50 microns.

[0065]如图2所示,然后进行步骤2),于所述硅外延层102形成多个间隔排列的沟槽103。 [0065] As shown in FIG 2, and then proceeds to step 2), the silicon epitaxial layer 102 to form a plurality of spaced trenches 103 are arranged. [0066]作为示例,采用光刻刻蚀工艺于所述硅外延层102形成多个间隔排列的沟槽103, 所述沟槽103的截面形状可以垂直结构的也可以有一定的倾斜角度,可以是上宽下窄或上窄下宽的梯形,该截面的形状也可以是弧形、多个弧形的组合等形状,所述沟槽103的俯视形状可以为圆形、椭圆形、多边形或圆角多边形等形状,在本实施例中,所述沟槽103的截面形状为矩形,俯视形状为圆形。 [0066] As an example, using a photolithography process to etch the silicon epitaxial layer 102 is arranged a plurality of spaced grooves 103 are formed, the groove 103 may cross-sectional shape may have a certain angle in a vertical configuration, can be is wider at the narrow width or trapezoidal, the sectional shape may be curved, like a combination of a plurality of arcuate shape, the planar shape of the groove 103 may be circular, oval, polygonal or rounded polygonal shape, in the present embodiment, the groove 103 has a rectangular cross-sectional shape, a circular planar shape. 另外,所述沟槽103也可以为密闭的环形沟槽等结构。 Further, the groove 103 may be a structure like a closed annular groove.

[0067] 如图3〜图6所示,然后进行步骤3),对各所述沟槽103的底部进行刻蚀,形成预设形状的沟槽底部结构10f5,于各所述沟槽底部结构105表面形成介质层106,并裸露出各所述沟槽侧壁的硅外延层102。 [0067] As shown in FIG 3 ~ FIG. 6, and then step 3), the bottom of each trench 103 is etched to form a predetermined shape of the bottom of trench structure 10f5, each of said trench bottom structure dielectric layer 105 formed on the surface 106, and the exposed trench sidewalls 102 of each of the silicon epitaxial layer.

[0068] 具体地,包括以下步骤: [0068] Specifically, comprising the steps of:

[0069]步骤3-1),于各所述沟槽的侧壁及底部形成刻蚀阻挡层104,在本实施例中,所述刻蚀阻挡层104为氮化硅层。 [0069] Step 3-1), each formed on the sidewalls and bottom of the trench etch stop layer 104, in this embodiment, the etch stop layer 104 is a silicon nitride layer.

[0070] 步骤3-2),选择性刻蚀以去除各沟槽底部的刻蚀阻挡层1〇4,保留各沟槽侧壁的刻蚀阻挡层104。 [0070] Step 3-2) selectively etching to remove the bottom of each trench etch stop layer 1〇4, retention of each trench sidewall etch stop layer 104.

[0071]步骤3-3),刻蚀各沟槽底部以形成预设形状的沟槽底部结构105,作为示例,所述沟槽底部结构105的截面形状包括多边形、圆球形或椭球形,所述沟槽底部结构105的最大径向宽度为大于所述沟槽底部的径向宽度。 [0071] Step 3-3), the bottom of each trench is etched to form a predetermined shape of the bottom of the trench structure 105, by way of example, a cross-sectional shape of the bottom of the trench structure 105 comprises a polygonal, spherical or ellipsoidal, the the maximum radial width of said bottom of the trench structure 105 is greater than the radial width of the bottom of the trench. 在本实施例中,所述沟槽底部结构105的形状为椭球形,且所述沟槽底部结构105的径向宽度为大于所述沟槽的径向宽度。 In the present embodiment, the shape of the bottom of the trench structure 105 is ellipsoidal, and the radial width of the bottom of the trench structure 105 is greater than the radial width of the trench.

[0072] 步骤3_4),于所述沟槽底部结构1〇5表面形成介质层106,沟槽底部的介质层106可以是二氧化硅,也可以是其他介质层,且二氧化硅的生长方式也有多种,可以是热氧化生长,也可以是PVD、CVD方式生长。 [0072] Step 3_4), the dielectric layer 106 is formed on the bottom surface of the trench structure 1〇5, dielectric layer 106 may be the bottom of the trench silicon dioxide, it may also be another dielectric layer, and a silica growth pattern there are also many, may be thermally grown and may be PVD, CVD growth mode. 作为示例,采用热氧化法于所述沟槽底部结构105表面形成二氧化硅层,作为介质层1〇6,所述二氧化硅层的厚度为O.OOlum〜lOum,优选为0.05um〜 2um,在本实施例中,所述二氧化桂层的厚度为lum。 By way of example, by thermal oxidation silicon dioxide layer is formed on a bottom surface of the trench structure 105, as 1〇6 dielectric layer, said silicon dioxide layer has a thickness O.OOlum~lOum, preferably 0.05um~ 2um in this embodiment, the oxide layer has a thickness of Gui lum.

[OO73] 步骤3_5),选择性刻蚀去除各沟槽侧壁的刻蚀阻挡层104,裸露出各沟槽侧壁的硅外延层102。 [OO73] Step 3_5) is selectively removed by etching sidewalls of each trench etch stop layer 104, the exposed trench sidewalls of each silicon epitaxial layer 102.

[0074] 如图7所示,接着进行步骤4),于所述沟槽底部结构105及沟槽内填充P型娃107,并去除多余的P型硅107直至露出所述硅外延层102表面。 [0074] As shown in FIG 7, followed by step 4), the bottom of the trench structure 105 and the P-type baby filled trench 107, removing excess P-type silicon 107 until the surface of the silicon epitaxial layer 102 is exposed .

[0075]作为示例,所填充的P型硅为完全充满所述沟槽底部结构105的填充结构、内部具有空洞的填充结构或于P型硅与介质层之间具有空洞的填充结构。 [0075] As an example, the P-type silicon is filled completely fill the trench filling structure 105 of the bottom structure, internal structure, or having a cavity having a cavity filled filling structure between the P-type silicon and the dielectric layer. P型硅107掺杂浓度可以根据硅外延层102的掺杂浓度和沟槽间的距离,利用电荷平衡(charge balance)原理而定, 在本实施例中,所述P型硅107的掺杂浓度为1 X l〇12/cm3〜1 X l〇19/CIn3,所述P型硅107填充后,可以改变器件的电场分布。 P-type silicon dopant concentration may be 107 according to the distance between the trench and doping concentration of the silicon epitaxial layer 102, using a charge balance (charge balance) depending on the principle, in the present embodiment, the P-type doped silicon 107 at a concentration of 1 X l〇12 / cm3~1 X l〇19 / CIn3, after the P-type silicon 107 is filled, the device can change the electric field distribution.

[0076]作为示例,采用干法刻蚀、化学腐蚀或机械化学抛光的方法去除硅外延层102表面多余的P型硅107后,对所述硅外延层102表面进行清洗,获得表面光洁的硅外延层1()2表面。 [0076] By way of example, dry etching, chemical etching, or chemical mechanical polishing method for removing excess surface silicon epitaxial layer 102 of the P-type silicon 107, the surface of the silicon epitaxial layer 102 is cleaned to obtain a smooth surface of the silicon () 1 2 surface of the epitaxial layer. [0077] 如图8所示,然后进行步骤5),于所述硅外延层102表面形成肖特基金属,并进行退火使所述娃外延层102及肖特基金属间形成金属桂化物108。 [0077] 8, followed by step 5), the surface of the silicon epitaxial layer 102 forms a Schottky metal, and annealing the epitaxial layer between the baby and the Schottky metal 102 is formed of a metal Gui 108 .

[0078]具体地,采用溅射法于所述硅外延层102表面淀积一定厚度的肖特基金属后,采用快速热退火使所述肖特基金属和所述硅外延层102之间形成金属硅化物1〇8,形成肖特基势垒。 After [0078] Specifically, a certain thickness is deposited by sputtering on the surface of the Schottky metal silicon epitaxial layer 102, rapid thermal anneal is formed between the Schottky metal and the silicon epitaxial layer 102 1〇8 metal silicide, forming a Schottky barrier.

[0079] 作为示例,所述肖特基金属包括钛、镍、铀金或钴等。 [0079] As an example, the Schottky metal comprises titanium, nickel, cobalt, uranium, or gold.

[0080] 如图9所示,接着进行步骤6),于所述金属桂化物108表面形成阳电极109。 [0080] As shown in FIG. 9, followed by a step 6), on the surface 108 of the metal Gui anode electrode 109 is formed.

[0081] 作为示例,所述阳电极109可以为单层或多层金属膜。 [0081] As an example, the anode electrode 109 may be a single layer or multi-layer metal film.

[0082] 如图10所示,最后进行步骤7),减薄所述硅衬底101,并于所述硅衬底1〇1背面形成阴电极110。 [0082] As shown in FIG. 10, the final step 7), thinning the silicon substrate 101, and on the backside of the silicon substrate 1〇1 cathode electrode 110 is formed.

[0083] 作为示例,所述阴电极110为Ti/Ni/Ag等多层金属膜,合金化后形成的阴电极110。 [0083] As an example, the cathode electrode 110 of Ti / Ni / Ag multi-layer metal film, alloy formed after the cathode electrode 110.

[0084] 如图10所示,本实施例还提供一种沟槽结构肖特基势垒二极管,包括: [0084] 10, the present embodiment further provides a trench Schottky barrier diode structure, comprising:

[0085] N型重掺杂的硅衬底ii ; [0085] N-type heavily doped silicon substrate II;

[0086] N型轻掺杂的硅外延层102,结合于所述硅衬底101表面; [0086] N-type lightly doped epitaxial silicon layer 102, 101 bonded to the surface of the silicon substrate;

[0087]多个沟槽,间隔形成于所述硅外延层1〇2中; [0087] a plurality of trenches formed in the silicon epitaxial spacer layer of 1〇2;

[0088] 沟槽底部结构105,呈预设形状形成于各所述沟槽的底部; [0088] the bottom of the trench structure 105, the form of each preset shape formed on the bottom of the trench;

[0089] 介质层1〇6,结合于各沟槽底部结构1 〇5表面; [0089] 1〇6 dielectric layer, bonded to the bottom of each trench structure 1 〇5 surface;

[0090] P型硅107,填充于各沟槽底部结构1〇5及各沟槽中; [0090] P-type silicon 107 is filled in each trench bottom structure 1〇5 and each trench;

[0091]金属硅化物108,形成于所述硅外延层102表面; [0091] The metal silicide 108 is formed on the surface of the epitaxial silicon layer 102;

[0092]阳电极109,形成于所述金属硅化物1〇8表面; [0092] The anode electrode 109 is formed on the surface of the metal silicide 1〇8;

[0093]阴电极110,形成于所述硅衬底i 0 i背面。 [0093] The cathode electrode 110 is formed on the back surface of the silicon substrate i 0 i.

[0094]作为示例,所述沟槽底部结构105的截面形状包括多边形、圆球形或椭球形。 [0094] As an example, a sectional shape of the bottom structure 105 comprises a polygonal, spherical or ellipsoidal said trench.

[0095]作为示例,所述沟槽底部结构105的最大径向宽度为大于所述沟槽底部的径向宽度。 [0095] As an example, the maximum radial width of the bottom of the trench structure 105 is greater than the radial width of the channel bottom.

[0096]作为示例,所述介质层106为二氧化硅层,其厚度为〇• OOlum〜10um。 [0096] As an example, the dielectric layer 106 is a silicon dioxide layer having a thickness of square • OOlum~10um.

[0097] 作为示例,所述P型硅为完全充满所述沟槽底部结构105的填充结构、内部具有空洞的填充结构或于P型硅与介质层之间具有空洞的填充结构。 [0097] As an example, the P-type silicon of the trench is completely filled with the filling structure 105 of the base structure, the internal structure, or having a cavity having a cavity filled filling structure between the P-type silicon and the dielectric layer.

[0098] 作为示例,所述N型轻掺杂的硅外延层102的掺杂浓度为1 X 1013/cra3〜1 X 1〇18/ cm3,所述P型硅107的掺杂浓度为1 X l〇12/cm3〜1 X 1019/cm3。 [0098] As an example, the N-type doping concentration of the lightly doped silicon epitaxial layer 102 is 1 X 1013 / cra3~1 X 1〇18 / cm3, the doping concentration of the P-type silicon 107 is 1 X l〇12 / cm3~1 X 1019 / cm3.

[0099] 图11显示为本发明的沟槽结构肖特基势垒二极管与传统沟槽结构的肖特基势垒二极管器件的内部电压-总电流正向特性曲线示意图。 [0099] FIG. 11 shows the internal structure of the present invention, the voltage trench Schottky barrier diode is a Schottky barrier diode device of the conventional trench structure - forward characteristic curve of the total current schematic. 从正向特性曲线可用看出,本发明的沟槽结构器件的饱和电流大于传统沟槽结构器件,也就是说可以通过降低芯片面积来达到与传统沟槽结构相同的正向电流;在同一个电流下,本发明沟槽结构器件的正向电压小于传统沟槽结构器件。 Forward characteristic curves can be seen from the saturation current of the trench structure of the device according to the present invention is greater than the conventional trench structure of the device, that can be achieved with conventional trench structure same chip area by reducing the forward current; the same a current, a forward voltage of the trench structure of the device of the present invention is less than the conventional trench structure of the device. 另外由器件仿真结果可知,两个器件的击穿电压大致相同,反向漏电相差不大。 Further the device is apparent from the simulation results, the breakdown voltage of the device is substantially the same two, or less reverse leakage.

[0100] 如上所述,本发明提供一种沟槽结构肖特基势垒二极管及其制作方法,所述制作方法包括以下步骤:1)提供一N型重掺杂的硅衬底1〇1,于所述硅衬底10丨表面形成N型轻掺杂的硅外延层102; 2)于所述硅外延层102形成多个间隔排列的沟槽;3)对各所述沟槽的底部进行刻蚀,形成预设形状的沟槽底部结构105,于各所述沟槽底部结构1〇5表面形成介质层1〇6,并裸露出各所述沟槽侧壁的硅外延层1〇2;4)于所述沟槽底部结构1〇5及沟槽内填充P型硅107,并去除多余的P型硅107直至露出所述硅外延层1〇2表面;5)于所述硅外延层102 表面形成肖特基金属,并进行退火使所述硅外延层102及肖特基金属间形成金属硅化物1 〇8; 6)于所述金属硅化物108表面形成阳电极109;7)减薄所述硅衬底1 〇1,并于所述硅衬底101背面形成阴电极110。 [0100] As described above, the present invention provides a trench Schottky barrier diode structure and fabrication method, the manufacturing method comprising the steps of: a) providing a heavily doped N-type silicon substrate 1〇1 forming lightly doped N-type silicon epitaxial layer on a surface of the silicon substrate 10 Shu 102; 2) in said silicon epitaxial layer 102 is formed of a plurality of spaced grooves; 3) of each of the bottom of the trench etching to form a predetermined shape of the bottom of the trench structure 105 is formed on the dielectric layer 1〇6 1〇5 bottom surface of each of said trench structure, and sidewalls of the exposed trenches each of the silicon epitaxial layer 1〇 2; 4) to the bottom of the trench structure and the trench is filled 1〇5 P-type silicon 107, and to remove excess P-type silicon 107 until the exposed surface of the epitaxial silicon layer 1〇2; 5) to the silicon surface of the epitaxial layer 102 forms a Schottky metal, and annealing said silicon epitaxial layer between the Schottky metal 102 and a metal silicide is formed 〇8 1; 6) an anode electrode 109 is formed on the surface of the metal silicide 108; 7 ) 〇1 thinning the silicon substrate 1, and the back surface of the silicon substrate 101 to the cathode electrode 110 is formed. 与现有技术相比较,本发明利用新型沟槽型结构,能制作性能更优的肖特基势垒二极管器件,在保证所需反向击穿电压的同时,降低正向导通压降,并且减小器件面积。 Compared with the prior art, the present invention utilizes a novel trench structure, better performance can be manufactured Schottky barrier diode device, at the same time ensure the required reverse breakdown voltage, reduced forward voltage drop, and reduced device area. 所以,本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。 Therefore, the present invention effectively overcomes the drawbacks of the prior art and with a high degree of value industry.

[0101]上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。 [0101] the above-described embodiments are only to illustrate the principle and efficacy of the present invention, the present invention is not intended to be limiting. 任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。 Any person skilled in this art can be made at without departing from the spirit and scope of the present invention, the above-described embodiments can be modified or changed. 因此,举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。 Thus, one skilled in the art that whenever all having ordinary knowledge in the technical ideas and spirit of the present invention is disclosed without departing from the completed equivalent modified or altered, yet the claims shall be encompassed by the present invention.

Claims (6)

  1. 1.一种沟槽结构肖特基势垒二极管的制作方法,其特征在于,包括以下步骤: 1) 提供一N型重掺杂的硅衬底,于所述硅衬底表面形成N型轻掺杂的硅外延层; 2) 于所述硅外延层形成多个间隔排列的沟槽; 3) 对各所述沟槽的底部进行刻蚀,形成预设形状的沟槽底部结构,于各所述沟槽底部结构表面形成介质层,并裸露出各所述沟槽侧壁的硅外延层; 4) 于所述沟槽底部结构及沟槽内填充P型硅,并去除多余的P型硅直至露出所述硅外延层表面; 5) 于所述娃外延层表面形成肖特基金属,并进行退火使所述桂外延层及肖特基金属间形成金属娃化物; 6) 于所述金属硅化物表面形成阳电极; 7) 减薄所述硅衬底,并于所述硅衬底背面形成阴电极。 1. A method for manufacturing a trench Schottky barrier diode structure, characterized by comprising the steps of: a) providing a heavily doped N-type silicon substrate, an N-type silicon substrate surface to the light doped silicon epitaxial layer; 2) formed in the silicon epitaxial layer a plurality of spaced grooves; 3) of the bottom of each trench is etched to form a predetermined shape of the bottom of the trench structure, the respective the bottom surface of the trench structure forming a dielectric layer, and the exposed trench sidewalls of each of the silicon epitaxial layer; 4) to the bottom of the trench structure and the P-type silicon filled trench, and removing excess P type until the exposed silicon surface of said silicon epitaxial layer; 5) surface of the epitaxial layer forming a Schottky metal doll, and annealing the epitaxial layer and the Schottky Gui between the metal forming the metal compound baby; 6) to the metal silicide anode electrode formed on the surface; 7) thinning the silicon substrate, and the backside of the silicon substrate to form a cathode electrode.
  2. 2.根据权利要求1所述的沟槽结构肖特基势垒二极管的制作方法,其特征在于:步骤3) 包括以下步骤: 3-1)于各所述沟槽的侧壁及底部形成刻蚀阻挡层; 3_2)选择性刻蚀以去除各沟槽底部的刻蚀阻挡层,保留各沟槽侧壁的刻蚀阻挡层; 3_3)刻蚀各沟槽底部以形成预设形状的沟槽底部结构; 3-4)于所述沟槽底部结构表面形成介质层; 3-5)选择性刻蚀去除各沟槽侧壁的刻蚀阻挡层,裸露出各沟槽侧壁的硅外延层。 The method for fabricating a trench structure according to a Schottky barrier diode as claimed in claim, wherein: the step 3) comprises the steps of: 3-1) formed on the sidewalls and bottom of each cut of the trench etch barrier layer; 3_2) is selectively etched to remove the etch stop layer at the bottom of each trench, the sidewall of each groove to retain the etch stop layer; 3_3) etching the bottom of each trench to form a predetermined shape of the groove base structure; 3-4) on the bottom surface of the trench structure forming a dielectric layer; 3-5) selectively removing each of the sidewalls of the trench etching the etch stop layer, trench sidewalls of each bare silicon epitaxial layer .
  3. 3.根据权利要求1所述的沟槽结构肖特基势垒二极管的制作方法,其特征在于:所述沟槽底部结构的截面形状包括多边形、圆球形或椭球形。 The method for fabricating a trench structure according to a Schottky barrier diode as claimed in claim, wherein: said cross-sectional shape of the bottom of the trench structure comprises a polygonal, spherical or ellipsoidal.
  4. 4.根据权利要求1所述的沟槽结构肖特基势垒二极管的制作方法,其特征在于:所述沟槽底部结构的最大径向宽度为大于所述沟槽底部的径向宽度。 The method for fabricating a trench structure according to a Schottky barrier diode as claimed in claim, wherein: the maximum radial width of the bottom of the trench structure is greater than the radial width of the bottom of the trench.
  5. 5.根据权利要求1所述的沟槽结构肖特基势垒二极管的制作方法,其特征在于:步骤4) 所填充的P型硅为完全充满所述沟槽底部结构的填充结构、内部具有空洞的填充结构或于P 型硅与介质层之间具有空洞的填充结构。 The method for fabricating a trench structure according to a Schottky barrier diode as claimed in claim, wherein: step 4) P-type silicon filled completely filled with the filling structure of the trench bottom structure, having an internal or hollow structure having a cavity filled filling structure between the P-type silicon and the dielectric layer.
  6. 6.根据权利要求1所述的沟槽结构肖特基势垒二极管的制作方法,其特征在于:步骤4) 还包括对所述硅外延层表面进行清洗的步骤。 6. A method for fabricating a trench structure according to a Schottky barrier diode as claimed in claim, wherein: the step 4) further comprises the step of washing the surface of the silicon epitaxial layer.
CN 201410333547 2014-07-14 2014-07-14 A trench-structure of a Schottky barrier diode and the manufacturing method CN104124151B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1498425A (en) * 2000-08-31 2004-05-19 通用半导体公司 Trench Schottky rectifier
CN1638151A (en) * 2003-12-25 2005-07-13 三洋电机株式会社 The semiconductor device
CN201629336U (en) * 2010-03-04 2010-11-10 无锡新洁能功率半导体有限公司 Groove schottky barrier rectifier

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JP3860705B2 (en) * 2000-03-31 2006-12-20 新電元工業株式会社 Semiconductor device
WO2009130648A1 (en) * 2008-04-21 2009-10-29 Nxp B.V. Semiconductor devices including a field reducing structure and methods of manufacture thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1498425A (en) * 2000-08-31 2004-05-19 通用半导体公司 Trench Schottky rectifier
CN1638151A (en) * 2003-12-25 2005-07-13 三洋电机株式会社 The semiconductor device
CN201629336U (en) * 2010-03-04 2010-11-10 无锡新洁能功率半导体有限公司 Groove schottky barrier rectifier

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