CN102820225B - There is the manufacture method of the high-voltage high-speed soft-recovery diode of diffusing buffer layer - Google Patents

Abstract

The invention discloses a manufacturing method of a high-voltage fast soft recovery diode with a diffused buffer layer, which belongs to the scope of semiconductor devices. Diffusion buffer layer fast recovery diode adopts two diffusion methods to make buffer layer. Before the PN junction and electrode preparation, first use phosphorus diffusion to form low-concentration and deep junction deep phosphorus diffusion regions on both sides of the silicon wafer, and then in the second During the process of phosphorus diffusion and boron-aluminum diffusion, the junction depth of primary phosphorus diffusion continues to advance, and finally the junction depth of primary phosphorus diffusion is about 20 μm deeper than that of secondary phosphorus diffusion, and the front concentration of primary phosphorus diffusion is less than 1×10 ¹⁵ /cm ^-3 area The depth of the diode is not less than 15 μm; the use of a defect-free zone fused silicon single crystal and a diffused buffer layer can greatly increase the voltage and current levels of the fast soft recovery diode. <!--1-->

Description

Manufacturing method of high voltage fast soft recovery diode with diffusion buffer layer

technical field

The invention belongs to the scope of semiconductor devices, in particular to a manufacturing method of a high voltage (1600V) fast soft recovery diode with a diffusion buffer layer.

Background technique

The basic structure of a diode is a PN junction (as shown in Figures 1 and 2), but in order to lead out the electrodes, high-concentration P+ and N+ layers must be introduced at the contact part between the electrodes and the semiconductor material to ensure ohmic contact and reduce Ohmic contact resistance can be understood from the working principle of diodes:

1) In the forward direction, that is, the anode (P ⁺ ) terminal of the diode is connected to the "+" pole of the external circuit, and the cathode (N ⁺ ) terminal is connected to the " ^- " pole. Under the action of the electric field, the P ⁺ terminal will move toward the N- The base region injects a large number of positively charged minority carriers - holes, and the N ⁺ terminal injects a large number of negatively charged majority carriers - electrons into the N ^- base region. Due to the injection of a large amount of charge in the base region, the resistance of the base region decreases sharply, which is called "conductance modulation effect". Therefore, when the diode is forward, it can pass a large current, but the voltage drop is very small.

2) In the reverse direction, that is, the anode terminal is connected to the "-" pole of the external circuit, and the cathode terminal is connected to the "+" pole. Extreme outflow, negatively charged multi-carrier (majority carriers) electrons flow out to the cathode end, the charge in the base area decreases sharply, and the resistance increases sharply, showing high resistance characteristics. Therefore, when the diode is reversed, it can withstand a high reverse voltage and has only a small leakage current.

3) Reverse recovery characteristics. When a reverse voltage is applied to the conducting diode, since a large number of minority carrier holes are injected into the N ^- base region during forward conduction, these minority carriers need to be completely extracted or neutralized before being turned off. This process Called the "reverse recovery process". At the beginning of the reverse recovery process, a large number of carriers in the base region are extracted under the action of an external reverse voltage. When the number of carriers drops to a certain level, the space charge region of the PN junction begins to establish, and the extraction effect stops. The remaining carriers are blocked in the base region and can only be neutralized by recombination. Figure 3 is a schematic diagram of the current and voltage waveforms during the reverse recovery process. In the figure, t _a is storage or extraction time, t _b is recombination or neutralization time, t _rr is reverse recovery time, t _rr =t _a +t _b , reverse recovery softness is S, S=t _b / t _a requires a soft reverse recovery characteristic, which actually requires a large value of S, that is, requires the extraction time t _a to be as small as possible and the extraction speed to be as fast as possible, while the recombination time t _b should be as long as possible and the recombination speed to be as fast as possible. Maybe slower.

The characteristics of fast recovery diodes are:

1) The reverse recovery time is required to be short, so that the switching speed is fast.

To achieve this goal, proceed from two aspects. One is to shorten the extraction time t _a . The most effective way is to thin the base region, thereby reducing the number of carriers in the base region, but the side effect of thinning the base region is that the reverse voltage of the diode is severely reduced. The second is to increase the recombination speed to reduce the recombination time t _b . Usually, the recombination center is introduced into the base area by techniques such as gold expansion, platinum expansion, electron irradiation, and ion irradiation. The side effects are the forward voltage drop of the diode and Serious increase in power loss. In order to make the increase of forward voltage drop as small as possible, it is also hoped that the base region should be thinned as much as possible to offset the side effects of introducing recombination centers, but it also encounters the problem of a serious drop in the reverse voltage of the diode. This is the fundamental reason why the reverse voltage of the fast recovery diode is difficult to make high and is far lower than that of ordinary diodes.

2) Reverse recovery softness is required to reduce the overvoltage impact in the reverse recovery process.

Reverse recovery softness is critical to the reliability of circuits and devices. Softness and reverse recovery di _r /dt

The greater the softness, the smaller the di _r /dt. The product of di _r /dt and circuit inductance (including stray inductance) constitutes an additional reverse voltage (V _RM - _VR ) peak (see Figure 3). The smaller the softness, the larger the di _r /dt, and the higher the voltage spike, which can even be much larger than the normal reverse voltage V _R . This kind of voltage spike is a large-energy, high-voltage overvoltage shock and harmonic interference to the equipment itself and other equipment connected to the grid, which is very dangerous and destructive. The higher the switching frequency and the shorter the reverse recovery time, the more serious this problem is, so the requirement for reverse recovery softness is also more prominent.

In order to solve the above two key problems of fast recovery diodes, it is proposed to add a low-concentration N thin layer on the leading edge of high-concentration N ⁺ . This thin layer is called a buffer layer. The schematic diagram of its structure and concentration distribution is shown in Figure 4. and Figure 5.

The principle of the buffer layer increasing the voltage and thinning the base region

When the diode is subjected to a reverse voltage, the space charge region expands in the base region and determines the width of the base region. See Figure 6 for the distribution of the electric field E in the space charge region. The graph shows 3 kinds of situations, 3 kinds of situations are all based on the same N ^- base region doping concentration.

In the first case, assuming that the width of the base region is not limited, the space charge region will expand to X _m , and the width of the base region is greater than X _m , and the reverse voltage at this time will reach the avalanche breakdown voltage V corresponding to the doping concentration of the base region _B.

In case 2, the base width is limited to the edge of N ⁺ , no buffer layer. In this case, the space charge region widens to the edge of N ⁺ and enters the N ⁺ barrier layer. Since the concentration of the N ⁺ layer is very high, which is 6 to 7 orders of magnitude higher than that of the N ^- base area, the avalanche breakdown voltage is very low, so Soon after entering, an avalanche breakdown will occur and terminate. Compared with the first case, the reverse voltage has a serious drop, and usually only reaches about 0.7V _B.

In the third case, there is a buffer layer, and the width of the base area is X1. At this time, after the space charge region widens to X1, it will enter the N buffer layer and continue to widen to X2. Since the doping concentration of the N buffer layer is not very high, it is only an order of magnitude higher than the N ^- base region, and has a higher avalanche shock. The breakdown voltage, the reverse voltage can reach about 0.9V _B , which is higher than the second case with the same base thickness. At the same time, the expansion in the buffer layer is relatively narrow, and the width (X2-X1) is usually only about 0.3 of (Xm-X1), which greatly reduces the thickness of the base area, thereby greatly reducing the reverse recovery time and forward on-state voltage drop. .

The principle of buffer layer improving reverse recovery softness

In semiconductors, in addition to the PN junction, there is also a high-low junction, that is, an interface with a sudden change in doping concentration in a semiconductor of the same conductivity type, such as the N ^- N interface and the NN ⁺ interface in Figure 6, both exist high and low knots. The high-low junction is due to the concentration difference on both sides of the interface. The carriers on the high-concentration side will diffuse to the low-concentration side, causing the charges on both sides of the interface to lose balance and generate an electric field. The establishment of the electric field prevents further diffusion of the carriers. until the diffusion force and the electric field force are balanced.

The base area of the diode is introduced into the N buffer layer, so that two high and low junction electric fields of N ^- N and NN ⁺ are generated in the base area. The electric field strength of these two electric fields is very weak, generally below 0.3V. When the diode is forward-conducting and reverse-extracting, the two high-low junctions are flooded by the high-concentration carriers in the base region, which will not affect it. But at the end of the reverse extraction, the carrier concentration in the base area is already very low. At this time, the existence of two high and low junctions will block the reverse extraction, so that there are more carriers in the base area, especially in the buffer layer. Carriers are left to enter the recombination stage, contributing to the prolongation of recombination time. After entering the recombination stage, the existence of the two high and low junctions prevents the outward diffusion of carriers in the buffer layer - recombination, and also delays the recombination speed. The superposition of the two effects makes the buffer layer play a very significant role in prolonging the compounding time and improving the softness of reverse recovery.

Buffer layer width and concentration control

Whether the N buffer layer can really function as a buffer layer depends on the control of its width and concentration. The doping concentration must be controlled within the range of 10 ¹⁴ /cm ³ , and the width is about 20 μm. If the concentration is too low, or the width is too narrow, the space charge region will break through, the voltage will drop severely, and the buffering effect will not be achieved; if the concentration is too high, the recombination will be too fast, and the buffer layer will also not be able to function, and the buffering effect will also be lost. Conductance modulation capability, enabling increased voltage drop. Therefore, the control of doping concentration and width is the key to whether the buffer layer can play a good role.

Contents of the invention

The object of the invention is to propose a kind of manufacturing method of the high-voltage fast soft recovery diode with diffusion buffer layer, it is characterized in that, adopt twice diffusion method to make buffer layer, obtain the diffusion buffer layer fast recovery diode; Before PN junction and electrode preparation , first use primary phosphorus diffusion to form low-concentration and deep-junction phosphorus diffusion regions on both sides of the silicon wafer, then in the process of secondary phosphorus diffusion and boron-aluminum diffusion, the junction depth of primary phosphorus diffusion continues to advance, and finally the primary phosphorus diffusion The junction depth X1 is 15-25 μm deeper than the junction depth X2 of the secondary phosphorus diffusion, and the frontal depth (X1-X) where the primary phosphorus diffusion concentration is lower than 1×10 ¹⁵ cm ^-3 is not less than 15 μm; the specific manufacturing steps are as follows:

(1) The raw materials are defect-free and dislocation-free fused silicon single wafers, the doping concentration is 10 ¹² ~ 10 ¹⁴ cm ^-3 , and the thickness of the silicon wafer is 300 ~ 400 μm;

(2) Deposit phosphorus on both sides of the silicon single wafer at low temperature (950-1050°C) for a short time (5-10 minutes), and then diffuse at high temperature (1240-1260°C) for a long time (60-70 hours), Form an N-type diffusion layer with a low concentration ((2～6)×10 ¹⁶ cm ^-3 ) and a junction depth of 55～60 μm;

(3) On both sides of the silicon single wafer in step (2), use high temperature (1180-1200°C) and long-term (2.5-3.5 hours) to deposit N ⁺ phosphorus thin films with a high concentration of NS>1×10 ²¹ cm ^-3 layer;

(4) Grinding one side of the silicon single wafer in step (3), the grinding depth should be greater than the N-type diffusion layer (typical value: 80-120 μm);

(5) Coat the boron-aluminum diffusion source on the grinding surface of the silicon single wafer in step (4) with a glue homogenizer, then advance at high temperature (1240～1260° C.) and long time (20～30 hours) diffusion; N , N ⁺ diffusion layer advance at the same time, the junction depths are X1 and X2 respectively, and the width (X1-X2) should be ensured to reach 15-25 μm; the frontier junction depth (X1-X) with a concentration of less than 1×10 ¹⁵ cm ^-3 should not be less than 15μm;

(6) Platinum expansion: perform high-temperature platinum expansion on the silicon single wafer in step (5) to control the lifetime of minority carriers. The platinum source is chloroplatinic acid, the diffusion temperature is 800-950°C, the time is 30-60 minutes, and the high-purity nitrogen is protected;

(7) Cutting circle: Cut the silicon single wafer in step (6) into wafers of the required size (typical value: 400A-φ30; 1000A-φ45) with a diamond disc cutting knife;

(8) Anode electrode production: In a high-temperature vacuum sintering furnace, with the help of aluminum foil, the silicon single-crystal wafer and the molybdenum sheet after step (7) are rounded are sintered together to form the anode of the chip;

(9) Cathode electrode production: Evaporate an aluminum film with a thickness of more than 10 μm on the cathode surface of the chip unsintered molybdenum sheet in step (8) by electron beam evaporation, and then place it in a vacuum annealing furnace for annealing at 500-520° C. for 0.5-1 hour , to achieve microalloying and form a cathode electrode;

(10) Carry out grinding angle (25°) molding to the chip of step (9), mesa corrosion and mesa passivation protection with 408 silicon rubber, so far, the manufacturing process of the high voltage fast soft recovery diode chip with diffusion buffer layer is completed.

The advantage of the present invention is that compared with the epitaxial buffer layer diode, the present invention has the following characteristics:

(1) A diffusion buffer layer can be introduced in the base region through the diffusion method to achieve the fast and soft recovery characteristics that only epitaxial diodes can achieve, and the cost is greatly reduced.

(2) The voltage can be made higher than that of the epitaxial diode, because the width of the N ^- base region has no technological limitation. In addition, the diffused diode uses a mesa termination process, which is also conducive to high voltage.

(3) The current can be made very large, because it uses a defect-free and dislocation-free fused silicon single crystal, which can make a large-area chip, and a whole wafer can be used to make a chip, and the current can reach hundreds, Thousands or even tens of thousands of amperes.

(4) Disadvantages: The concentration and depth of the diffused N buffer zone are not easy to be accurately controlled, and the dispersion of device characteristics is greater than that of epitaxial diodes.

Description of drawings

Accompanying drawing 1, the schematic diagram of the basic structure of a common diode.

Accompanying drawing 2, the schematic diagram of doping concentration distribution of common diode.

Accompanying drawing 3, the structural diagram of diode buffer layer.

Accompanying drawing 4, schematic diagram of reverse recovery waveform.

Accompanying drawing 5, the schematic diagram of the diode concentration distribution of the diffusion buffer layer.

Accompanying drawing 6, the schematic diagram of widening space charge region of diffused diode.

Accompanying drawing 7, the manufacturing step of diffusion buffer layer.

detailed description

The invention proposes a manufacturing method of a high-voltage fast soft recovery diode with a diffusion buffer layer. Be described below in conjunction with accompanying drawing.

So far, buffer layers for fast recovery diodes have all been fabricated using a two-step epitaxy method. The main production steps are as follows: the raw material is a silicon single crystal N ⁺ substrate sheet with a thickness of 500-600 μm and a doping concentration > 8×10 ¹⁹ cm ^-3 ; a thin layer with a concentration of 10 ¹⁴ is grown on the N ⁺ substrate sheet by epitaxy. The silicon single crystal thin film in the cm ^-3 range is used as the N buffer layer; and then the N ^- single crystal layer is epitaxially grown on the N buffer layer for the manufacture of the N ^- base region and the P ⁺ layer of the diode.

The existing problems of making fast recovery diodes by epitaxial method are: 1. In view of the current technical level of epitaxial technology, the thickness of epitaxial layer can only be up to 100 μm, and this 100 μm includes three parts: P ⁺ , N ^- and N buffer layer ^. The area width is only about 60 μm, and the voltage of 1200V is already the limit. If the epitaxial thickness is increased, the quality of the epitaxial layer will degrade to an unacceptable level. 2. The current is not large. Unlike defect-free zone fused silicon single crystals, epitaxial silicon single crystals have not yet reached the level of "defect-free", and the thicker the epitaxial layer, the more defects there will be. And one defect often destroys the chip on which it resides. Therefore, it is impossible to make a chip on a wafer by using the epitaxial method. Usually, many chips need to be made on a wafer. The smaller the chip size, the smaller the impact of defects and the higher the yield. At present, the maximum chip size of epitaxial silicon fast recovery diode is 10×15mm, the current can reach 150A, and the maximum voltage is 1200V. The current and voltage levels are much less high than for the diffusion method.

The advantages of making fast recovery diodes by epitaxy are: the concentration ^and width of the three parts of P ⁺ , N ^{- and} N buffer layers can be precisely controlled, ^and the characteristics are easy to optimize; And the concentration of the N buffer layer is evenly distributed, so the reverse recovery time can be made shorter than that of the diffusion method, and the forward voltage drop can be lower.

The present invention uses two diffusion methods to make the buffer layer. Before the preparation of the PN junction and electrodes, the first phosphorus diffusion is used to form low-concentration and deep junction deep phosphorus diffusion regions on both sides of the silicon wafer, and then the second phosphorus diffusion and boron diffusion During the aluminum diffusion process, the junction depth of the primary phosphorus diffusion continues to advance, and finally the junction depth of the primary phosphorus diffusion is about 20 μm deeper than that of the secondary phosphorus diffusion, and the junction depth of the leading edge with a concentration less than 1×10 ¹⁵ cm ^-3 is not less than 15 μm; (Schematic diagram of concentration distribution of diodes in the diffusion buffer layer as shown in accompanying drawing 5 and a schematic diagram of widening of the space charge region of diffusion diodes shown in accompanying drawing 6); by adopting a defect-free region molten silicon single crystal, one wafer can be made into a chip, and the current can reach several Hundreds, thousands or even tens of thousands of amperes, the current and voltage levels are much higher than that of epitaxial diodes. However, the concentration and depth of the diffused N buffer are difficult to control precisely, and the dispersion of device characteristics is greater than that of epitaxial diodes.

The manufacturing steps of the diffusion buffer layer of the diffusion buffer layer fast soft recovery diode shown in accompanying drawing 7 are as follows:

(1) The raw materials are defect-free and dislocation-free fused silicon single wafers, the doping concentration is 10 ¹² ~ 10 ¹⁴ cm ^-3 , and the thickness of the silicon wafer is 300 ~ 400 μm;

(2) Deposit phosphorus on both sides of the silicon single wafer at a low temperature of 1000°C for a short time of 8 minutes, and then diffuse at a high temperature of 1250°C for 65 hours to form a low concentration of (2～6)×10 ¹⁶ cm ^-3 , an N-type diffusion layer with a junction depth of 60 μm;

(3) On both sides of the silicon single wafer in step (2), deposit a high-concentration N ⁺ phosphorus thin layer with NS>1×10 ²¹ cm ^-3 at a high temperature of 1190° C. for 3 hours for a long time;

(4) Grinding the single-sided silicon wafer of step (3), the grinding depth should be greater than the typical value of 100 μm for the N-type diffusion layer;

(5) Coat the boron-aluminum diffusion source on the grinding surface of the silicon single wafer in step (4) with a glue homogenizer, and then diffuse and advance at a high temperature of 1255° C. for 27 hours; N, N ⁺ diffusion layers simultaneously Advance, the junction depths are X1 and X2 respectively, and the width (X1-X2) should be ensured to reach 15-25 μm; the frontier junction depth (X1-X) with a concentration less than 1×10 ¹⁵ cm ^-3 should not be less than 15 μm;

So far, the diffusion type buffer layer is fabricated. The subsequent chip manufacturing process is the same as the manufacturing process of a general diffused fast recovery diode without a buffer layer.

Claims (1)

1. there is a manufacture method for the high-voltage high-speed soft-recovery diode of diffusing buffer layer, it is characterized in that, adopt twice method of diffusion to make resilient coating, obtain diffusing buffer layer fast recovery diode; The concrete making step of diffusing buffer layer is as follows:

(1) raw material adopt nondefective zone silicon crystal disk, and doping content is 10 ¹²~ 10 ¹⁴cm ^-3, silicon wafer thickness is 300 ~ 400 μm;

(2) at above-mentioned silicon single crystal disk two sides low temperature 950 ~ 1050 DEG C, 5 ~ 10 minute short time sedimentary phosphor, then high temperature 1240 ~ 1260 DEG C, diffusion for a long time in 60 ~ 70 hours, requires that square resistance is not less than 200 Ω and forms low concentration (2 ~ 6) × 10 ¹⁶cm ^-3, the dark n type diffused layer of junction depth 55 ~ 60 μm;

(3) in silicon single crystal disk two sides high temperature 1180 ~ 1200 DEG C, 2.5 ~ 3.5 hours long-time deposition high concentration NS > 1 × 10 of step (2) ²¹cm ^-3n ⁺phosphorus thin layer;

(4) by the silicon single crystal disk safe-sided disk of step (3), grinding depth should be greater than n type diffused layer, namely 80 ~ 120 μm;

(5) with sol evenning machine the silicon single crystal disk of step (4) flour milling coating boron-aluminium diffuse source, then high temperature 1240 ~ 1260 DEG C, within 20 ~ 30 hours, spread propelling for a long time; N, N ⁺diffusion layer advances simultaneously, and junction depth is respectively X1, X2, should guarantee that width (X1-X2) reaches 15 ~ 25 μm; Concentration is less than 1 × 10 ¹⁵cm ^-3forward position junction depth (X1-X) be no less than 15 μm, so far, diffused resilient coating completes; Thereafter chip manufacturing program is identical with the manufacture craft of the general diffused fast recovery diode without resilient coating; Comprise:

(6) platinum expansion: carry out high temperature platinum expansion to the silicon single crystal disk of step (5), controls minority carrier lifetime; Platinum source adopts chloroplatinic acid, diffusion temperature 800 ~ 950 DEG C, time 30-60 minute, and high pure nitrogen is protected;

(7) cyclotomy: adopt carborundum disc cyclotomy cutter that the silicon single crystal disk of step (6) is cut into required size: 400A-φ 30mm; The disk of 1000A-φ 45mm;

(8) anode electrode makes: in high-temperature vacuum sintering furnace, by means of aluminium foil, the silicon single crystal disk after step (7) cyclotomy and molybdenum sheet are sintered together, and forms the anode of chip;

(9) cathode electrode makes: deposited by electron beam evaporation is greater than 10 μm of thick aluminium films in the cathode plane evaporation that the chip of step (8) does not sinter molybdenum sheet, then 500 ~ 520 DEG C of annealing 0.5 ~ 1 hour is placed in vacuum annealing furnace, reach microalloying, form cathode electrode;

(10) carry out angle lap 25 ° of moulding, mesa etch and table tops 408 silicon rubber passivation protection to the chip of step (9), so far, the high-voltage high-speed soft recovery diode chip manufacturing process with diffusing buffer layer completes.