CN104681434B - Preparation method of FS-IGBT - Google Patents
Preparation method of FS-IGBT Download PDFInfo
- Publication number
- CN104681434B CN104681434B CN201510037235.2A CN201510037235A CN104681434B CN 104681434 B CN104681434 B CN 104681434B CN 201510037235 A CN201510037235 A CN 201510037235A CN 104681434 B CN104681434 B CN 104681434B
- Authority
- CN
- China
- Prior art keywords
- igbt
- silicon
- silicon chip
- silicon wafer
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a method for preparing an FS-IGBT (Field Stop-Insulated Gate Bipolar Translator) on a silicon wafer, which is used for solving the problems caused by a thin silicon wafer during a preparation process of a medium/low-voltage FS-IGBT that the preparation technology is complicated, the difficulty is large, the thin silicon wafer warps and deforms and is segmented, the size of the thin silicon wafer (a wafer) is limited, the yield is low, the cost is high, and industrialization is difficult to realize and overcoming the huge technical challenge caused by the thin silicon wafer in follow-up scribing of the wafer and encapsulating of a chip. The preparation method comprises the steps of selecting light-doped FZ silicon as a first silicon wafer and heavy-doped CZ silicon or FZ silicon as a second silicon wafer; firstly, making an N-type FS layer and a P-type transparent collecting zone on the back surface of the first silicon wafer; then, bonding the first silicon wafer and the second silicon wafer; making a front-surface structure by thinning the thickness of the first silicon wafer; finally, thinning the second silicon wafer; forming a collector electrode through etching, metal depositing and chemical-mechanical polishing; obtaining the FS-IGBT.
Description
Technical field
The invention belongs to power semiconductor device technology field, is related to insulated gate bipolar transistor (IGBT), specifically relate to
And the preparation method of field cut-off type insulated gate bipolar transistor (FS-IGBT).
Background technology
Insulated gate bipolar transistor (IGBT) is the compound novel electric power electricity of a kind of MOS field-effects and bipolar transistor
Sub- device, its existing MOSFET is easy to drive, and controls simple advantage, has power transistor turns pressure drop low again, on state current
Greatly, little advantage is lost, it has also become one of core electron components and parts in modern power electronic circuit, is widely used in and such as leads to
The every field of the national economy such as letter, the energy, traffic, industry, medical science, household electrical appliance and Aero-Space.The invention of IGBT and should
Particularly important effect is served with the lifting to power electronic system performance, since the nineties in last century, through device junction
The continuous development of structure and preparation technology, the IGBT device and its module of commercial production have covered voltage from 370V to 6500V, electric current
Range of application from 2A to 4000A.
From device drift region structure and preparation method thereof, IGBT experienced (the non-break-through from PT (punch) to NPT
Type) development of FS (field cut-off type) is arrived again.First generation PT type structure cellular is as shown in figure 1, using P+The monocrystalline silicon piece conduct of type CZ
Substrate, by P+Extension N-type buffer layer and N successively on type CZ silicon chip-Drift region, then in N-MOS knots are prepared on drift region
Structure is formed.Device drift region electric field is presented class trapezoidal profile during the structure blocks, in the N of certain device of resistance to pressure-Drift region
Thinner thickness, forward conduction voltage drop is little；But due to as the P of collecting zone+Substrate doping is high, and thickness is big, causes colelctor electrode
Emission effciency is excessive, and the turn-off time is long, and current tail phenomenon substantially, causes turn-off power loss very big, it is difficult to meet high-speed applications
Require.Therefore, usual PT types IGBT need to adopt carrier lifetime control technology to reduce carrier lifetime, so as to reduce shut-off
Time and turn-off power loss, but the forward conduction voltage drop using PT types IGBT device after the method is presented negative temperature coefficient, is unfavorable for
It is used in parallel.For PT type IGBT structures, due to being in thicker P+Extension N-type buffer layer and N on substrate-Drift region, therefore
Thin N can be obtained-Drift region thickness, easily prepares the IGBT device of mesolow.
In order to improve the performance of IGBT device, industry proposes NPT type IGBT structures, cellular on the basis of PT types IGBT
As shown in Figure 2.NPT type structures do not use P+Extension N on type substrate-The technique of layer, but directly use N-The FZ silicon chips of type,
Using N-Type FZ backing material as drift region, in N-Type drift region front prepares MOS structure, and is injected simultaneously by backside particulate
The mode of annealing forms p-type collecting zone.For NPT type IGBT structures, due to by using transparent anode (colelctor electrode) technology, drop
The concentration and thickness of low back side p-type collecting zone, substantially reduces colelctor electrode emission effciency, improves that turn-off power loss is big to ask
Topic, by avoiding using the technologies such as carrier lifetime control, the forward conduction voltage drop of NPT types IGBT is positive temperature coefficient, is made big
Current parallel application is possibly realized.But because during blocking, the Triangle-Profile of NPT type structure electric fields floats in certain resistance to pressure
Move area long, cause conducting resistance and turn-off power loss larger, be still difficult to meet the requirement of high-speed applications.
In order to further improve the performance of IGBT device, with reference to PT types and the advantage of NPT types IGBT, industry proposes FS
(field cut-off) type IGBT structure, cellular is as shown in Figure 3.FS-IGBT directly uses N-Type FZ silicon chip, using N-Type FZ backing material
As drift region, in N-Type drift region front prepares MOS structure, and by adopting diffusion before p-type transparent collecting zone is formed
Or ion implantation technology introduces N-type FS layer, so that drift region electric field is presented class trapezoidal profile in blocking, certain pressure
Under substantially reduce the drift region thickness of device, reduce forward conduction voltage drop；Simultaneously by using transparent anode (colelctor electrode)
Technology, it is ensured that the positive temperature characterisitic of conduction voltage drop.Further, since the p-type collecting zone thickness of FS-IGBT is little, concentration is low, therefore
Emission effciency is low, its tail currents very little, and switching loss becomes high speed low-loss application far below NPT types and PT type structures
Main flow device.However, for the FS-IGBT of mesolow, such as breakdown voltage is the FS-IGBT of 600V, and its chip thickness is generally little
In 70um, and the FS-IGBT of breakdown voltage 400V, its chip thickness only 40um.Either adopt and first do front technique (including just
Face MOS structure and terminal structure), the mode of the thinning back in back note still first does back side work introducing FS layers and p-type collecting zone
Skill (including FS layers and p-type collecting zone), it is then thinning after do the method for front technique, prepare so thin chip, preparation technology
Complicated, difficulty is big, needs very expensive and accurate process equipment, and the too thin deformation for being easily caused silicon chip of silicon chip, warpage
And fragment, the size of silicon chip (wafer) is restricted, yields is low, high cost, it is difficult to which realization is commercially produced, and wafer chi
Very little restriction causes the preparation of device to be difficult to using advanced technologies corresponding with big wafer size.Additionally, thin chip is thick
Degree scribing also for silicon chip and encapsulation etc. of chip bring huge technological challenge, increase process complexity and difficulty, cause with
Wafer prepares similar problem, the i.e. too thin easy cracking of chip, fragment, and yields is low, high cost, it is difficult to which realization is commercially produced
Deng.
For the PT type IGBT devices of mesolow, although P+The resistivity very little of type single crystalline substrate, but in order to further drop
Low thick P+Impact of the type resistance substrate to device property, Jun Zeng propose by back cutting and fill the system of conductive material
Standby mode, obtains structure cell (J.Zeng, Semiconductor Devices Having Reduced as shown in Figure 4
Effective Substrate Resistivity and Associated Methods,US patent#6104062,#
7098108).The structure utilizes the materials such as the metal of high conductivity and thermal conductivity to reduce P+The conducting resistance and heat of type substrate
Resistance, but the structure is still PT type structures, P+The doping content of type substrate is very high, and P+Type substrate is thicker, particularly without the back of the body
The position of portion's cutting filling, it is high for the IGBT device colelctor electrode injection efficiency, it is still necessary to using skills such as carrier lifetime controls
To obtain low switching loss, forward conduction voltage drop is in negative temperature coefficient to art, therefore is not suitable for the preparation of FS-IGBT.
For difficulty prepared by mesolow FS-IGBT, the present invention proposes a kind of preparation method to realize in thicker silicon chip
Upper preparation FS-IGBT.
The content of the invention
It is an object of the invention to a kind of method that FS-IGBT is prepared on thick silicon chip is proposed, to solve mesolow FS-
In IGBT preparation process, complicated process of preparation that thin silicon wafer is brought, difficulty are big, silicon warp, deformation, fragment, silicon chip (wafer)
Size be restricted, yields is low, high cost, it is difficult to realize the problem of industrialization, and the scribing in subsequent wafer and core
Due to huge technological challenge that thin silicon wafer is brought in the encapsulation of piece.
The present invention solves the technical scheme that adopted of above-mentioned technical problem：
A kind of preparation method of FS-IGBT, comprises the following steps：
The first step：Two panels n type single crystal silicon piece is chosen as the first silicon chip and the second silicon chip, wherein the first silicon chip is thickness
300～500 microns of lightly doped FZ silicon, doping content is 1013～1014Individual/cm3, to the drift region for forming FS-IGBT；
Second silicon chip is the heavily doped CZ silicon or FZ silicon of 300～500 microns of thickness, and doping content is 1019～1020Individual/cm3, to
Form the back N+ areas of FS-IGBT；
Second step：Pass through ion implanting N-type impurity and anneal at the back side of the first silicon chip to make the N-type FS layer of FS-IGBT,
The thickness of the FS layers of formation is 2～5 microns, and ion implantation energy is 40keV～500keV, and implantation dosage is 1013～1014Individual/
cm2, annealing temperature is 1150-1200 DEG C, and annealing time is 60～300 minutes；
3rd step：Pass through ion implanting p type impurity again at the back side of the first silicon chip and the p-type of the making FS-IGBT that anneals is saturating
Bright collecting zone, the thickness of the p-type collecting zone of formation is 0.5～2 micron, and ion implantation energy is 30keV～100keV, injectant
Measure as 1013～1014Individual/cm2, annealing temperature is 1150-1200 DEG C, and annealing time is 0～60 minute；
4th step：Using bonding techniques the first silicon chip back side and the second front side of silicon wafer are bonded together to form the 3rd silicon
Piece, bonding temperature be 300～600 DEG C, by bonding techniques formed the 3rd silicon chip the first silicon chip side be front, the second silicon
It is the 3rd front side of silicon wafer that piece side is the back side, i.e. the first front side of silicon wafer, and the second silicon chip back side is the 3rd silicon chip back side；
5th step：Thinning 3rd front side of silicon wafer to positive former first silicon wafer thickness is 30～80 microns, i.e., thinning drift
Area；
6th step：By multiple photoetching, oxidation, ion implanting, annealing, depositing technics through the 3rd thinning silicon chip just
Face makes the Facad structure of FS-IGBT, including cellular MOS structure and terminal structure etc., wherein, PXing Ti areas and terminal field limiting ring
Junction depth be 2～3 microns, ion implantation energy be 40keV～120keV, implantation dosage is 1013～1014Individual/cm2, annealing temperature
Spend for 1100～1150C, annealing time is 30～150 minutes；
7th step：The silicon wafer thickness of original second of thinning 3rd silicon chip back side to the back side is 50～100 microns, i.e., thinning back
N+ areas；
8th step：Using photoetching and etching, in the 3rd silicon chip back side cutting after thinning to p-type transparent collecting zone；
9th step：Deposit metal, it is 2～4 microns to fill groove and cover whole 3rd silicon chip back side to thickness；
Tenth step：Using the metal of chemically mechanical polishing (CMP) planarization back side deposit, colelctor electrode is formed；
It is prepared into FS-IGBT.
Further, in the 5th step, the thinning rear drift region thickness of FS-IGBT device for 400V is 30～40 micro-
Rice, the thinning rear drift region thickness of the FS-IGBT device for 600V is 50～60 microns.
Further, in the 8th step, etching can adopt the methods such as dry etching, orientation wet etching, laser boring,
The shape of the silicon groove for being formed, depth-to-width ratio and the distribution on silicon chip change according to the thickness and lithographic method in back N+ areas
Become.
Further, in the 9th step, before filling collector electrode metal, layer of metal barrier layer is first deposited (such as titanium, nitridation
Titanium, tantalum nitride etc.), can be layer of metal, or multilayer gold to prevent metal from diffusing into the metal in silicon, filled
The combination of category, the metal filled can be tungsten, copper or aluminium etc..
Further, in the 6th step, Facad structure is planar gate structure or trench gate structure.
It should be noted that in order to simplify description, above-mentioned preparation method be by taking n-channel FS-IGBT device as an example illustrating,
But the present disclosure applies equally to the preparation of p-channel FS-IGBT device.And the processing step in the preparation method of above-mentioned FS-IGBT
Additions and deletions and adjustment can be according to actual needs carried out with process conditions；
FS-IGBT structure cells obtained by present invention preparation are as shown in Figure 5.When device forward conduction, the voltage of grid 8 is
High potential, device surface MOS structure raceway groove is opened, back N+The PN junction J2 that area 11 is formed with p-type transparent collecting zone 1 is reverse-biased, and
And the short circuit N of back collector electrode metal 7 of cutting filling+Area 11 and p-type transparent collecting zone 8, therefore back N+Area 11 does not affect FS-
The forward conduction characteristic (including Carrier Profile during forward conduction) of IGBT device, thus the shut-off for also not interfering with device is special
Property.Additionally, electric current can not only pass through back N in forward conduction+The collector electrode metal 7 of cutting filling flows between area 11,
Part electronics can also be spread through p-type transparent collecting zone 1, Jing backs N+Area 11 reaches the collector electrode metal 7 of side and below,
The problem of current convergence is avoided, it is brighter when the phenomenon is relatively thin in FS-IGBT device p-type transparent collecting zone 1 and adulterates relatively low
It is aobvious.When device is blocked, the current potential of grid 8 is electronegative potential, and colelctor electrode 7 is high potential, front PXing Ti areas 4 and N-Drift region 3 is formed
PN junction J1 it is reverse-biased, the pressure of device is born, due to the presence of FS layers, the N in device breakdown-Electric field in drift region 3 is presented
Class trapezoidal profile.Due to back N+The PN junction J2 that area 11 is formed with p-type transparent collecting zone 1 is reverse-biased, and the back of cutting filling
The short circuit N of collector electrode metal 7+Area 11 and p-type transparent collecting zone 8, therefore back N+Area 11 does not affect the blocking of FS-IGBT device special
Property.
Beneficial effects of the present invention show：
The present invention can adopt thick silicon chip to prepare the mesolow FS- with thin drift region in whole chip fabrication process
IGBT, and the FS-IGBT device for finally preparing also has thick silicon wafer thickness.A kind of FS- that the present invention is provided
The preparation method of IGBT can be solved in mesolow FS-IGBT preparation process, and complicated process of preparation that thin silicon wafer is brought, difficulty are big,
Silicon warp, deformation, fragment, the size of silicon chip (wafer) is restricted, is difficult with advanced work corresponding with large scale wafer
Skill technology, yields are low, high cost, it is difficult to realize the problem of industrialization, and in the scribing and the encapsulation of chip of subsequent wafer
In the huge technological challenge that brought due to thin silicon wafer.The IGBT that the present invention is formed is FS types, it is not necessary to adopt lifetime control techniques,
With same with the FS-IGBT that conventional method is obtained such as forward conduction voltage drop it is low, turn-off power loss is little, conduction voltage drop is positive temperature
The advantages of degree coefficient.Therefore, preparation method of the present invention is applicable to the preparation of FS-IGBT device, particularly mesolow FS-
The preparation of IGBT.
Description of the drawings
Fig. 1 is traditional PT types IGBT structure schematic diagram；In Fig. 1：1 is heavily doped P-type backing material, and 2 is N-type cushion
(buffer), 3 is N-Drift region, 4 is p-type body contact zone, and 5 is N-type body contact zone, and 6 is metal emitting, and 7 is metal current collection
Pole, 8 is grid, and 9 is gate medium, and 10 is spacer medium.
Fig. 2 is NPT type IGBT structure schematic diagrames；In Fig. 2：1 is p-type transparent collecting zone, and 3 is N-Drift region, 4 is p-type body
Contact zone, 5 is N-type body contact zone, and 6 is metal emitting, and 7 is metal collector, and 8 is grid, and 9 is gate medium, and 10 are isolation
Medium.
Fig. 3 is FS type IGBT structure schematic diagrames；In Fig. 3：1 is p-type transparent collecting zone, and 2 is N-type field cutoff layer (FS), and 3 are
N-Drift region, 4 is p-type body contact zone, and 5 is N-type body contact zone, and 6 is metal emitting, and 7 is metal collector, and 8 is grid, 9
For gate medium, 10 is spacer medium.
Fig. 4 is the IGBT structure schematic diagram involved by Jun Zeng patents；In Fig. 4：1 be heavily doped P-type backing material, 2
For N-type cushion (buffer), 3 is N-Drift region, 4 is p-type body contact zone, and 5 is N-type body contact zone, and 6 is metal emitting, 7
For metal collector, 8 is grid, and 9 is gate medium, and 10 is spacer medium.
Fig. 5 is FS-IGBT structural representations prepared by the preparation method that the present invention is provided；In Fig. 5：1 is that p-type is transparent
Collecting zone, 2 is N-type field cutoff layer (FS), and 3 is N-Drift region, 4 is p-type body contact zone, and 5 is N-type body contact zone, and 6 send out for metal
Emitter-base bandgap grading, 7 is metal collector, and 8 is grid, and 9 is gate medium, and 10 is spacer medium, and 11 is back side N+Area.
Fig. 6 is the schematic flow sheet of the preparation method that the present invention is provided.
Fig. 7 to Figure 12 is the concrete technology flow process schematic diagram of the preparation method that the present invention is provided.
The FS-IGBT that Figure 13 is obtained for the preparation method that the present invention is provided, traditional FS-IGBT and Jun Zeng patents are related to
IGBT collector current simulation curve comparison diagrams when off.
Specific embodiment
Below in conjunction with accompanying drawing, the principle and characteristic of the present invention are described further, example is served only for explaining this
Invention, is not intended to limit the scope of the present invention.
As shown in fig. 6, the invention provides a kind of prepare the method with thin drift region FS-IGBT, bag on thick silicon chip
Include：
The first step：Two panels n type single crystal silicon piece is chosen as the first silicon chip and the second silicon chip, wherein the first silicon wafer thickness is
300 microns, using lightly doped FZ silicon, doping content is 2.5*1014Individual/cm3, to the drift for forming FS-IGBT described in Fig. 5
Area 3 is moved, the second silicon wafer thickness is 300 microns, and using heavily doped CZ silicon, doping content is 5*1019Individual/cm3, to form figure
The back N+ areas 11 of FS-IGBT described in 5, as Figure 7-8；
Second step：FS-IGBT described in Fig. 5 is prepared by ion implanting N-type impurity and annealing at the back side of the first silicon chip
N-type FS layer 2, the thickness of the FS layers of formation is 2 microns, and typical ion implantation energy is 350keV, and implantation dosage is 1*1013
Individual/cm2, annealing temperature is 1200 DEG C, and annealing time is 60 minutes；
3rd step：Again FS- described in Fig. 5 is prepared by ion implanting p type impurity and annealing at the back side of the first silicon chip
The p-type transparent collecting zone 1 of IGBT, the thickness of the p-type collecting zone of formation is 0.5 micron, and typical ion implantation energy is
40keV, implantation dosage is 1*1013Individual/cm2, annealing temperature is 1200 DEG C, and annealing time is 10 minutes, as shown in Figure 9；
4th step：Using bonding techniques the first silicon chip back side and the second front side of silicon wafer are bonded together to form the 3rd silicon
Piece, bonding temperature be 600 DEG C, by bonding techniques formed the 3rd silicon chip the first silicon chip side be front, the second silicon chip one
Side is the back side, i.e. the first front side of silicon wafer is the 3rd front side of silicon wafer, and the second silicon chip back side is the 3rd silicon chip back side, as shown in Figure 10；
5th step：Thinning 3rd front side of silicon wafer to the 3rd silicon chip gross thickness is 340 microns, i.e., thinning 3rd front side of silicon wafer is extremely
Former first silicon wafer thickness is 40 microns；
6th step：The steps of Jing the 5th the 3rd front side of silicon wafer by multiple photoetching, oxidation, ion implanting, annealing, deposit etc.
Technique prepares the Facad structure of FS-IGBT, including cellular MOS structure and terminal structure etc., typical MOS structure PXing Ti area and
The junction depth of terminal field limiting ring is 2 microns, and typical ion implantation energy is 60keV, and implantation dosage is 1*1014Individual/cm2, annealing
Temperature is 1150 DEG C, and annealing time is 30 minutes；In this step 1150 DEG C of annealing temperatures and 30 minutes annealing times can be obtained
Two beneficial effects：1) defect such as cavity of bonded interface in the 4th step is further reduced by pyroprocess, improves bonding circle
The quality in face；2) due to the presence of concentration gradient, N-type FS layer 2, the silicon chip of p-type transparent collecting zone 1 and the 3rd in pyroprocess
Impurity in Central Plains the second silicon chip side high concentration N-type substrate 11 will be redistributed, due to big concentration gradient the second silicon chip one of original
The middle and high concentration N-type impurity of side N-type substrate 11 is miscellaneous more than p-type in p-type transparent collecting zone 1 to the speed that former first silicon chip side is spread
Diffusion velocity from matter to the side of FS layers 2, while p type impurity is more than to the diffusion velocity of the side of FS layers 2 in p-type transparent collecting zone 1
To the diffusion velocity of drift region 3, by the compensation of impurity, it is 0.3 micron that can obtain with typical thickness to FS layers 2, peak concentration
For 3*1017Individual/cm3P-type transparent collecting zone 1, and obtain typical thickness for 2 microns, peak concentration is 1*1017Individual/cm3FS
Layer, as shown in figure 11；
7th step：Thinning 3rd silicon chip back side to the 3rd silicon chip gross thickness is 140 microns, i.e., it is thinning after back N+ areas 11
Typical thickness be 100 microns；
8th step：Photoetching and etching, in the 3rd silicon chip back side cutting to p-type transparent collecting zone 1；
9th step：Deposit metal, fills groove and covers whole 11 to 3 microns of back N+ areas, and the metal of deposit is saturating with p-type
Bright collecting zone 1 and back N+ areas 11 form respectively Ohmic contact；
Tenth step：Chemically mechanical polishing (CMP) planarizes the metal of backside deposition, forms colelctor electrode 7；
The FS-IGBT of preparation is obtained, as shown in figure 12；
The FS-IGBT that Figure 13 is obtained for the preparation method that the present invention is provided, traditional FS-IGBT (Fig. 4 structures) and Jun
The IGBT (Fig. 5 structures) that Zeng patents are related to collector current simulation curve contrasts when off.Three kinds of structures are using identical
Front MOS structure, identical drift region concentration, thickness and carrier lifetime.It can be seen that preparation of the present invention
The FS-IGBT that method is obtained has most fast turn-off speed, and the turn-off speed of traditional FS-IGBT is slightly slow, and Jun Zeng patents are related to
And IGBT show the delay grown very much and hangover time, turn-off speed is most slow.The IGBT that the present invention is formed is FS types, it is not necessary to
Using lifetime control techniques, can have that the such as forward conduction voltage drop same with the FS-IGBT that conventional method is obtained be low, shut-off is damaged
The advantages of little, conduction voltage drop of consumption is positive temperature coefficient.Therefore, preparation method of the present invention is applicable to FS-IGBT device
Prepare, the particularly preparation of mesolow FS-IGBT.
The present invention can adopt thick silicon chip to prepare the mesolow FS- with thin drift region in whole chip fabrication process
IGBT, and the FS-IGBT device for finally preparing also has thick silicon wafer thickness.A kind of FS- that the present invention is provided
The preparation method of IGBT can be solved in mesolow FS-IGBT preparation process, and complicated process of preparation that thin silicon wafer is brought, difficulty are big,
Silicon warp, deformation, fragment, the size of silicon chip (wafer) is restricted, is difficult with advanced work corresponding with large scale wafer
Skill technology, yields are low, high cost, it is difficult to the problem commercially produced of realization, and the scribing in subsequent wafer and chip
Due to huge technological challenge that thin silicon wafer is brought in encapsulation.
Claims (7)
1. a kind of preparation method of FS-IGBT, comprises the following steps：
The first step：Two panels n type single crystal silicon piece is chosen as the first silicon chip and the second silicon chip, wherein the first silicon chip be thickness 300～
500 microns of lightly doped FZ silicon, doping content is 1013～1014Individual/cm3, to the drift region for forming FS-IGBT；Second silicon
Piece is the heavily doped CZ silicon or FZ silicon of 300～500 microns of thickness, and doping content is 1019～1020Individual/cm3, to form FS-
The back N+ areas of IGBT；
Second step：Pass through ion implanting N-type impurity and anneal at the back side of the first silicon chip to make the N-type FS layer of FS-IGBT, formed
FS layers thickness be 2～5 microns, ion implantation energy be 40keV～500keV, implantation dosage is 1013～1014Individual/cm2,
Annealing temperature is 1150-1200 DEG C, and annealing time is 60～300 minutes；
3rd step：Pass through ion implanting p type impurity again and anneal at the back side of the first silicon chip to make the transparent collection of p-type of FS-IGBT
Electric area, the thickness of the p-type collecting zone of formation is 0.5～2 micron, and ion implantation energy is 30keV～100keV, and implantation dosage is
1013～1014Individual/cm2, annealing temperature is 1150-1200 DEG C, and annealing time is 0～60 minute；
4th step：Using bonding techniques the first silicon chip back side and the second front side of silicon wafer are bonded together to form the 3rd silicon chip, key
Close temperature be 300～600 DEG C, by bonding techniques formed the 3rd silicon chip the first silicon chip side be front, the second silicon chip one
Side is the back side；
5th step：Thinning 3rd front side of silicon wafer to former first silicon wafer thickness is 30～80 microns, i.e. drift region thinned；
6th step：Made through the 3rd thinning front side of silicon wafer by photoetching, oxidation, ion implanting, annealing and depositing technics
The Facad structure of FS-IGBT, including cellular MOS structure and terminal structure, wherein, the junction depth of PXing Ti areas and terminal field limiting ring is 2
～3 microns, ion implantation energy is 40keV～120keV, and implantation dosage is 1013～1014Individual/cm2, annealing temperature be 1100～
1150 DEG C, annealing time is 30～150 minutes；
7th step：Thinning 3rd silicon chip back side to former second silicon wafer thickness is 50～100 microns, i.e., thinning back N+ areas；
8th step：Using photoetching and etching, in the 3rd silicon chip back side cutting after thinning to p-type transparent collecting zone；
9th step：Deposit metal, it is 2～4 microns to fill groove and cover whole 3rd silicon chip back side to thickness；
Tenth step：Using the metal of chemically mechanical polishing planarization back side deposit, colelctor electrode is formed；
It is prepared into FS-IGBT.
2. the preparation method of the FS-IGBT as described in claim 1, it is characterised in that in the 5th step, the FS- for 400V
The thinning rear drift region thickness of IGBT device is 30～40 microns, and the thinning rear drift region thickness of the FS-IGBT device for 600V is
50～60 microns.
3. the preparation method of the FS-IGBT as described in claim 1, it is characterised in that in the 8th step, is etched and is carved using dry method
The method of erosion, orientation wet etching or laser boring, the shape of the silicon groove for being formed, depth-to-width ratio and the distribution root on silicon chip
Determine according to the thickness and lithographic method in back N+ areas.
4. the preparation method of the FS-IGBT as described in claim 1, it is characterised in that in the 9th step, fills collector electrode metal
Before, layer of metal barrier layer is first deposited, to prevent metal from diffusing in silicon.
5. the preparation method of the FS-IGBT as described in claim 4, it is characterised in that the metal material of the metal barrier is
Titanium, titanium nitride or tantalum nitride.
6. the preparation method of the FS-IGBT as described in claim 1, it is characterised in that in the 9th step, the metal filled can
To be the combination of layer of metal, or multiple layer metal, the metal filled is tungsten, copper or aluminium.
7. the preparation method of the FS-IGBT as described in claim 1, it is characterised in that in the 6th step, Facad structure is plane
Grid structure or trench gate structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510037235.2A CN104681434B (en) | 2015-01-26 | 2015-01-26 | Preparation method of FS-IGBT |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510037235.2A CN104681434B (en) | 2015-01-26 | 2015-01-26 | Preparation method of FS-IGBT |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104681434A CN104681434A (en) | 2015-06-03 |
| CN104681434B true CN104681434B (en) | 2017-05-10 |
Family
ID=53316325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510037235.2A Expired - Fee Related CN104681434B (en) | 2015-01-26 | 2015-01-26 | Preparation method of FS-IGBT |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104681434B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106898554A (en) * | 2017-03-17 | 2017-06-27 | 电子科技大学 | A kind of field cut-off type reverse-conducting insulated gate bipolar transistor npn npn preparation method |
| CN109473541A (en) * | 2018-12-25 | 2019-03-15 | 黑龙江大学 | A kind of hetero-junction silicon magnetic sensitive transistor and process for making |
| CN112951905B (en) * | 2021-01-25 | 2024-03-29 | 南瑞联研半导体有限责任公司 | SiC reverse-conduction type insulated gate bipolar transistor device and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5372954A (en) * | 1991-07-24 | 1994-12-13 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating an insulated gate bipolar transistor |
| JP2002261281A (en) * | 2001-03-01 | 2002-09-13 | Hitachi Ltd | Manufacturing method of insulated gate bipolar transistor |
| CN1402356A (en) * | 2001-08-29 | 2003-03-12 | 株式会社东芝 | Semiconductor device of longitudinal structure |
| CN103441074A (en) * | 2013-08-30 | 2013-12-11 | 吴宗宪 | Method for manufacturing IGBT device integrated with diode |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010003960A (en) * | 2008-06-23 | 2010-01-07 | Sanken Electric Co Ltd | Semiconductor device, and manufacturing method thereof |
-
2015
- 2015-01-26 CN CN201510037235.2A patent/CN104681434B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5372954A (en) * | 1991-07-24 | 1994-12-13 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating an insulated gate bipolar transistor |
| JP2002261281A (en) * | 2001-03-01 | 2002-09-13 | Hitachi Ltd | Manufacturing method of insulated gate bipolar transistor |
| CN1402356A (en) * | 2001-08-29 | 2003-03-12 | 株式会社东芝 | Semiconductor device of longitudinal structure |
| CN103441074A (en) * | 2013-08-30 | 2013-12-11 | 吴宗宪 | Method for manufacturing IGBT device integrated with diode |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104681434A (en) | 2015-06-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102569067B (en) | Method for manufacturing planar high-voltage ultrafast soft recovery diode | |
| CN103534811B (en) | Semiconductor device and the manufacture method of semiconductor device | |
| EP2525410A1 (en) | Insulated gate bipolar transistor and manufacturing method thereof | |
| CN104681433B (en) | A kind of FS IGBT preparation method | |
| CN102800591A (en) | Preparation method for FS-IGBT device | |
| CN102903633A (en) | Methods for fabricating anode shorted field stop insulated gate bipolar transistor | |
| CN105590959A (en) | Gate commutated thyristor having dual-p-base-region gate cathode structure and preparation method thereof | |
| CN107170816B (en) | A kind of landscape insulation bar double-pole-type transistor | |
| CN105870180B (en) | Double division trench gate charge storage type RC-IGBT and its manufacturing method | |
| CN106024863A (en) | High-voltage power device terminal structure | |
| CN104681434B (en) | Preparation method of FS-IGBT | |
| CN114823911A (en) | Groove silicon carbide MOSFET integrated with high-speed freewheeling diode and preparation method | |
| CN101931001B (en) | Asymmetrical fast thyristor | |
| CN107078156A (en) | Reverse-conducting lock control bipolar-conduction device and method with reduction warpage risk | |
| CN104616986B (en) | A kind of preparation method of fast recovery diode | |
| CN103219236B (en) | Collecting zone carbon injects internal transparent collector IGBT manufacturing technology | |
| CN110518069A (en) | With partially carbonized silicon/silicon semiconductor material hetero-junctions VDMOS and preparation method thereof | |
| CN103107189B (en) | IGBT back structure and preparation method | |
| CN105489636B (en) | A kind of backside structure of semiconductor power device | |
| CN102931228B (en) | Reverse conducting IGBT (Insulated Gate Bipolar Translator) device and manufacturing method thereof | |
| CN205595336U (en) | Contrary type IGBT back structure of leading | |
| CN114300544A (en) | Fast recovery diode and manufacturing method thereof | |
| CN103268861A (en) | Method for manufacturing FS (field stop) type IGBT (insulated gate bipolar transistor) by multiple epitaxies | |
| CN106158941A (en) | A kind of two-way pressure igbt structure | |
| CN103855204B (en) | Inverse conductivity type IGBT collector structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170510 Termination date: 20200126 |