CN107293480A - A kind of high-voltage diode and preparation method thereof - Google Patents
A kind of high-voltage diode and preparation method thereof Download PDFInfo
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- CN107293480A CN107293480A CN201610202320.4A CN201610202320A CN107293480A CN 107293480 A CN107293480 A CN 107293480A CN 201610202320 A CN201610202320 A CN 201610202320A CN 107293480 A CN107293480 A CN 107293480A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 68
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 68
- 239000010703 silicon Substances 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 63
- 239000012535 impurity Substances 0.000 claims abstract description 40
- 230000005684 electric field Effects 0.000 claims abstract description 17
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 18
- 229910052782 aluminium Inorganic materials 0.000 claims description 15
- 238000009792 diffusion process Methods 0.000 claims description 15
- 239000004411 aluminium Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- 230000008020 evaporation Effects 0.000 claims description 7
- 238000001704 evaporation Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 230000004913 activation Effects 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 230000005611 electricity Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- QQMBHAVGDGCSGY-UHFFFAOYSA-N [Ti].[Ni].[Ag] Chemical compound [Ti].[Ni].[Ag] QQMBHAVGDGCSGY-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000009740 moulding (composite fabrication) Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a kind of high-voltage diode and preparation method thereof, wherein, this method includes：Oxide layer is formed in silicon substrate side, the side of the surface of silicon formation oxide layer is front, and opposite side is the back side；The oxide layer is etched, first is formed and shelters window；Window is sheltered by described first, the adulterated al impurity in the silicon substrate forms the first doped region；Electric field cut-off region is prepared in the periphery of first doped region；The oxide layer on the silicon substrate is removed, and dielectric layer is formed in silicon substrate front；The dielectric layer is etched, electrode contact window is formed, exposes first doped region；First electrode is formed in the positive side of the silicon substrate, and in silicon substrate reverse side formation second electrode.Using this method, existing high-voltage diode manufacture craft production cycle length, the technical problem of low production efficiency can be solved.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of high-voltage diode and preparation method thereof.
Background technology
Diode (Diode), also known as crystal diode, are a kind of two end electronics devices with unilateal conduction characteristic
Part.There is a PN junction inside of diode, and two terminals are drawn from this PN junction.The work of diode is former
Reason is：When additional forward voltage is not more than the threshold voltage of diode, diode is in cut-off state；It is no
Then, diode is in the conduction state；When additional backward voltage is not more than breakdown reverse voltage, at diode
In cut-off state；Otherwise, reverse current can increase suddenly, and diode is in electrical breakdown state.
With the development of science and technology diode is increasingly frequently used in various electronic devices, particularly with
High-voltage diode, because of its good high pressure resistant property, high-voltage diode is got in various electronic devices
To use more.In the prior art, high-voltage diode is generally divided into the deep junction diode of high pressure and high pressure shallow junction
Diode, for the deep junction diode of high pressure, is mainly the method for the pressure voltage by improving single PN junction to carry
The pressure-resistant performance of high whole high-voltage diode.
But, the defect of prior art is, being now mainly used as p type impurity by boron in the art is carried out
Filling, but diffusion coefficient very little of the boron in diode base material silicon, when temperature is 1100 degrees Celsius,
The diffusion coefficient of boron is about 4 × 10-12㎝2/ s, will realize more than 1000V high back voltage, and diffusion time needs
20-40 hours are wanted, the production cycle is long, low production efficiency, is unfavorable for energy-saving and environmental protection.
The content of the invention
In view of this, the embodiment of the present invention provides a kind of high-voltage diode and preparation method thereof, existing to solve
Technology mesohigh diode production cycle length, the technical problem of low production efficiency.
In a first aspect, the embodiments of the invention provide a kind of preparation method of high-voltage diode, including：
Oxide layer is formed in silicon substrate side, the side of the surface of silicon formation oxide layer is front, separately
Side is the back side；
The oxide layer is etched, first is formed and shelters window；
Window is sheltered by described first, the adulterated al impurity in the silicon substrate forms the first doped region；
Electric field cut-off region is prepared in the periphery of first doped region；
The oxide layer on the silicon substrate is removed, and dielectric layer is formed in silicon substrate front；
The dielectric layer is etched, electrode contact window is formed, exposes first doped region；
Form first electrode in the positive side of the silicon substrate, and in silicon substrate reverse side formation the
Two electrodes.
Second aspect, the embodiment of the present invention additionally provides a kind of high-voltage diode, and the high-voltage diode is used
The preparation method of the high-voltage diode of above-mentioned first aspect is made.
High-voltage diode provided in an embodiment of the present invention and preparation method thereof, oxide layer is formed in silicon substrate side,
The oxide layer is etched, first is formed and shelters window, shelter window by first, adulterated al is miscellaneous in silicon substrate
Matter, forms the first doped region, electric field cut-off region is prepared in the periphery of the first doped region, in silicon substrate front one
Side forms first electrode, and in silicon substrate reverse side formation second electrode.Using this method, lead to
Cross in the first doped region adulterated al impurity to improve the diffusion velocity of impurity in a silicon substrate, can solve existing
Fabrication cycle length, the technical problem of low production efficiency in high-voltage diode manufacturing process.
Brief description of the drawings
In order to clearly illustrate the technical scheme of exemplary embodiment of the present, below to description embodiment
In required for the accompanying drawing used do a simple introduction.Obviously, the accompanying drawing introduced is that the present invention to be described
A part of embodiment accompanying drawing, rather than whole accompanying drawing, for those of ordinary skill in the art, not
On the premise of paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of preparation method schematic flow sheet of high-voltage diode provided in an embodiment of the present invention；
Fig. 2 is a kind of diagrammatic cross-section that oxide layer is formed in silicon substrate side provided in an embodiment of the present invention；
Fig. 3 forms the first section signal for sheltering window for a kind of etching oxidation layer provided in an embodiment of the present invention
Figure；
Fig. 4 is a kind of diagrammatic cross-section for forming the first doped region provided in an embodiment of the present invention；
Fig. 5 forms the second section signal for sheltering window for a kind of etching oxidation layer provided in an embodiment of the present invention
Figure；
Fig. 6 is a kind of diagrammatic cross-section for forming the second doped region provided in an embodiment of the present invention；
Fig. 7 is a kind of schematic flow sheet for preparing electric field cut-off region provided in an embodiment of the present invention；
Fig. 8 forms the 3rd section signal for sheltering window for a kind of etching oxidation layer provided in an embodiment of the present invention
Figure；
Fig. 9 is a kind of diagrammatic cross-section for forming electric field cut-off region provided in an embodiment of the present invention；
Figure 10 is a kind of diagrammatic cross-section for forming dielectric layer provided in an embodiment of the present invention；
Figure 11 is a kind of diagrammatic cross-section for forming electrode contact window provided in an embodiment of the present invention；
Figure 12 is a kind of diagrammatic cross-section for forming p type impurity area provided in an embodiment of the present invention；
Figure 13 is a kind of diagrammatic cross-section for forming first electrode provided in an embodiment of the present invention；
Figure 14 is a kind of diagrammatic cross-section for forming second electrode provided in an embodiment of the present invention；
Figure 15 is a kind of top view of high-voltage diode provided in an embodiment of the present invention.
The technical characteristic that reference in figure is referred to respectively is：
101st, silicon substrate；102nd, oxide layer；103rd, first window is sheltered；104th, the first doped region；105、
Second shelters window；106th, the second doped region；107th, the 3rd window is sheltered；108th, electric field cut-off region；109、
Dielectric layer；110th, electrode contact window；111st, p type impurity area；112nd, first electrode；113rd, the second electricity
Pole.
Embodiment
To make the object, technical solutions and advantages of the present invention clearer, below with reference to the embodiment of the present invention
In accompanying drawing, by embodiment, be fully described by technical scheme.Obviously, it is described
Embodiment be the present invention a part of embodiment, rather than whole embodiment, the implementation based on the present invention
Example, the every other implementation that those of ordinary skill in the art obtain on the premise of creative work is not made
Example, each falls within protection scope of the present invention.
Fig. 1 is a kind of schematic flow sheet of the preparation method of high-voltage diode provided in an embodiment of the present invention, please
As shown in fig.1, the preparation method of high-voltage diode provided in an embodiment of the present invention comprises the following steps：
Step S110：Oxide layer 102 is formed in the side of silicon substrate 101, the surface of silicon substrate 101 is formed
The side of oxide layer 102 is front, and opposite side is the back side.
Silicon substrate 101 is provided in this step first, the resistance doping rate of silicon lining 101 can be 35-45
Ω * cm, thickness can be 250 μm -350 μm, and its surface orientation can be<111>.In silicon substrate 101
Upper formation is oxidized to 102, as shown in Fig. 2 oxide layer 102 is preferably silica oxide layer, the oxide layer
Thickness can be 1.5 μm -1.8 μm.Further, the surface of silicon substrate 101 forms the side of oxide layer 102
For front, opposite side is the back side.
Step S120：Etching oxidation layer 102, forms first and shelters window 103.
As shown in figure 3, using the method etching oxidation layer 102 of photoetching and corrosion, forming first and sheltering window
103, expose silicon substrate 101.
Step S130：Window 103 is sheltered by first, the adulterated al impurity in silicon substrate 101 forms the
One doped region 104.
As shown in figure 4, window 103 is sheltered by first, by way of aluminium injection or aluminum evaporation thermal diffusion
The adulterated al impurity in silicon substrate 101, forms the first doped region 104.Optionally, when the side injected by aluminium
Formula is in silicon substrate 101 during adulterated al impurity, and the implantation dosage of the aluminium impurity can be
1*1016/cm2-2*1016/cm2.When by way of aluminum evaporation thermal diffusion in silicon substrate 101 adulterated al impurity
When, aluminum evaporation is first carried out in the range of 150 DEG C -250 DEG C, the aluminium of preset thickness is formed in the front of silicon substrate 101
Piece, the aluminium flake of the preset thickness can be the aluminium flake of 2 μ m thicks.Then formed by the method for thermal diffusion
First doped region 104.It is preferred that, thermal diffusion is carried out in the range of 1050 DEG C -1150 DEG C and forms the first doping
Area 104.When carrying out thermal diffusion in the range of 1050 DEG C -1150 DEG C, the diffusion coefficient of aluminium flake is 1*10-12
cm2/s-1.5*10-12cm2/s.Further, the thickness of the first doped region 104 can be 50 μm -80 μm.
Optionally, in etching oxidation layer 102, when window 103 is sheltered in formation first, it can also include：
Etching oxidation layer 102, forms at least one and second shelters window 105, second, which shelters window 105, surrounds
First shelters window 103, as shown in Figure 5；
Accordingly, window 103 is being sheltered by first, the adulterated al impurity in silicon substrate 101 forms first
When doped region 104, it can also include：
Window 105 second is sheltered by least one, the adulterated al impurity in silicon substrate 101 forms at least one
Individual second doped region 106；Second doped region 106 is located at the periphery of the first doped region 104, as shown in Figure 6.
Step S140：Electric field cut-off region 108 is prepared in the periphery of the first doped region 104.
Refer to shown in Fig. 7, the periphery provided in an embodiment of the present invention in the first doped region prepares electric field cut-off
Area may comprise steps of：
Step S141：Etching oxidation layer 102, forms the 3rd and shelters window 107, the 3rd shelters window 107
Window 103 is sheltered around first.The step is specifically referred to shown in Fig. 8.
Step S142：As shown in figure 9, window 107 is sheltered by the 3rd, the doping N in silicon substrate 101
Type impurity, forms electric field cut-off region 108, and electric field cut-off region 108 surrounds the first doped region 104.
Specifically, the doped resistor rate of N-type impurity can be 3-5 Ω * cm.
Step S150：The oxide layer 102 on silicon substrate 101 is removed, and Jie is formed in the front of silicon substrate 101
Matter layer 109.
Specifically, as shown in Figure 10, removing the oxide layer 102 on silicon substrate 101, in silicon substrate 101 just
Face forms dielectric layer 109, and dielectric layer 109 completely covers silicon substrate 101.Optionally, dielectric layer 109 is preferred
For compound medium layer, formed by way of deposit in the front of silicon substrate 101.Further, dielectric layer
109 can include silica, silicon nitride and mix at least one of oxygen polysilicon.
Step S160：Etch media layer 109, forms electrode contact window 110, exposes the first doped region 104.
Specifically, as shown in figure 11, in position etch media layer 109 corresponding with the first doped region 104,
To form electrode contact window 110 in the top of the first doped region 104, and expose the first doped region 104.
Step S170：First electrode 112 is formed in the positive side of silicon substrate 101, and in silicon substrate 101
Reverse side formation second electrode 113.
Further, before the positive side of silicon substrate 101 forms first electrode 112, in addition to：
P type impurity area 111 is formed away from silicon substrate side in the first doped region 104, and is carried out at annealing activation
Reason.
Specifically, as shown in figure 12, by electrode contact window 110, the implanting p-type in the way of hole is injected
Impurity, to form p type impurity area 111 away from silicon substrate side in the first doped region 104.Optionally, it is described
P type impurity can be boron impurity, and the implantation dosage of the boron impurity can be 3*1016/cm2, p type impurity area
111 thickness can be within 1 μm.Further, in the first doped region 104 away from silicon substrate side shape
Into after p type impurity area 111, annealing activation processing, optionally, annealing are carried out to p type impurity area 111
Temperature can be 800 DEG C, and corresponding annealing time can be 1 hour.
Accordingly, first electrode 112 is formed in the positive side of silicon substrate 101, is specially in p type impurity area
111 positive sides form first electrode 112.
Specifically, forming first electrode 112 in the positive side in p type impurity area 111, it may comprise steps of：
As shown in figure 13, the first electricity is made by way of aluminum evaporation in the positive side in p type impurity area 111
Pole 112；
Further, as shown in figure 14, in the reverse side of silicon substrate 101 formation second electrode 113, second
The material for preparing of electrode 113 can be titanium-nickel-silver alloy.
Present invention also offers a kind of high-voltage diode being made by the above method, concrete structure is participated in
Figure 14.Further, Figure 15 is a kind of top view of high-voltage diode provided in an embodiment of the present invention, from figure
It is recognised that the first doped region 104 is shaped as circle in 15, the second doped region 106 is loop configuration,
And second doped region 106 be located at the periphery of the first doped region 104, electric field cut-off region 108 is similarly annular, electricity
Field cut-off region 108 is located at the second doped region periphery.
The high-voltage diode that the present invention is provided can also be not comprising the second doped region 106, or include multiple rings
The second doped region of shape 106.When comprising multiple annular second doped regions 106, multiple annular second doped regions
106 are arranged at intervals, and multiple the second annular doped regions 106 are located at the first doped region 104 and electric field ends
Between area 108.
It should be noted is that, the shape of the first doped region 104 shown in above-mentioned accompanying drawing is circle,
Here, one kind in the circular simply optional shape of the first doped region 104, the first doped region 104 can also be
Other shapes, such as rectangle.
High-voltage diode provided in an embodiment of the present invention and preparation method thereof, by being adulterated in the first doped region
Aluminium impurity, it is ensured that impurity has a larger diffusion coefficient in a silicon substrate, to realize 1000V with
On it is pressure-resistant, diffusion time only needs to 4 hours, substantially reduces the production cycle, further increases life
Efficiency is produced, and efficiency is relatively low, energy-conserving and environment-protective.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.Those skilled in the art
It will be appreciated that the invention is not restricted to specific embodiment described here, can enter for a person skilled in the art
Row it is various it is obvious change, readjust and substitute without departing from protection scope of the present invention.Therefore, though
So the present invention is described in further detail by above example, but the present invention be not limited only to
Upper embodiment, without departing from the inventive concept, can also include other more equivalent embodiments,
And the scope of the present invention is determined by scope of the appended claims.
Claims (10)
1. a kind of preparation method of high-voltage diode, it is characterised in that comprise the following steps：
Oxide layer is formed in silicon substrate side, the side of the surface of silicon formation oxide layer is front, separately
Side is the back side；
The oxide layer is etched, first is formed and shelters window；
Window is sheltered by described first, the adulterated al impurity in the silicon substrate forms the first doped region；
Electric field cut-off region is prepared in the periphery of first doped region；
The oxide layer on the silicon substrate is removed, and dielectric layer is formed in silicon substrate front；
The dielectric layer is etched, electrode contact window is formed, exposes first doped region；
Form first electrode in the positive side of the silicon substrate, and in silicon substrate reverse side formation the
Two electrodes.
2. the preparation method of high-voltage diode according to claim 1, it is characterised in that in etching institute
Oxide layer is stated, when window is sheltered in formation first, in addition to：
The oxide layer is etched, at least one is formed and second shelters window, described second shelters window around institute
State first and shelter window；
Window is being sheltered by described first, the adulterated al impurity in the silicon substrate forms the first doped region
When, in addition to：
By it is described at least one second shelter window, the adulterated al impurity in the silicon substrate is formed at least
One the second doped region；Second doped region is located between first doped region and the electric field cut-off region.
3. the preparation method of high-voltage diode according to claim 1 or 2, it is characterised in that described
The adulterated al impurity in the silicon substrate, including：
Aluminium injection or aluminum evaporation thermal diffusion by way of in the silicon substrate adulterated al impurity.
4. the preparation method of high-voltage diode according to claim 3, it is characterised in that when passing through aluminium
The mode of injection is in the silicon substrate during adulterated al impurity, and the implantation dosage of the aluminium impurity is
1*1016/cm2-2*1016/cm2。
5. the preparation method of high-voltage diode according to claim 3, it is characterised in that when passing through aluminium
The mode of evaporation thermal diffusion is in the silicon substrate during adulterated al impurity, and wherein the temperature of aluminum evaporation is 150 DEG C
- 250 DEG C, the temperature of thermal diffusion is 1050 DEG C -1150 DEG C.
6. the preparation method of high-voltage diode according to claim 1, it is characterised in that described first
The thickness of doped region is 50 μm -80 μm.
7. the preparation method of high-voltage diode according to claim 1, it is characterised in that described in institute
The periphery for stating the first doped region prepares electric field cut-off region, including：
The oxide layer is etched, the 3rd is formed and shelters window, the described 3rd shelters window covers around described first
Cover window；
Window is sheltered by the described 3rd, the doped N-type impurity in the silicon substrate forms electric field cut-off region,
The electric field cut-off region surrounds first doped region.
8. the preparation method of high-voltage diode according to claim 1, it is characterised in that the medium
Layer includes silica, silicon nitride and mixes at least one of oxygen polysilicon.
9. the preparation method of high-voltage diode according to claim 1, it is characterised in that in the silicon
Substrate face side is formed before first electrode, in addition to：
P type impurity area is formed away from the silicon substrate side in first doped region, and carries out annealing activation
Processing.
10. a kind of high-voltage diode, it is characterised in that the high-voltage diode is appointed using claim 1-9
Method described in one is made.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11126780A (en) * | 1997-10-24 | 1999-05-11 | Tokin Corp | Method of manufacturing semiconductor device |
| CN102820225A (en) * | 2012-08-10 | 2012-12-12 | 清华大学 | Manufacturing method for high-pressure quick soft recovery diode with diffusing buffer layer |
| CN103579367A (en) * | 2013-11-08 | 2014-02-12 | 国家电网公司 | Fast recovery diode chip of low-concentration doped emitter region and manufacturing method thereof |
| CN104701386A (en) * | 2015-02-11 | 2015-06-10 | 株洲南车时代电气股份有限公司 | Matchable fast recovery diode (FRD) of integrated gate commutate thyristor and manufacturing method of matchable fast recovery diode |
-
2016
- 2016-04-01 CN CN201610202320.4A patent/CN107293480A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11126780A (en) * | 1997-10-24 | 1999-05-11 | Tokin Corp | Method of manufacturing semiconductor device |
| CN102820225A (en) * | 2012-08-10 | 2012-12-12 | 清华大学 | Manufacturing method for high-pressure quick soft recovery diode with diffusing buffer layer |
| CN103579367A (en) * | 2013-11-08 | 2014-02-12 | 国家电网公司 | Fast recovery diode chip of low-concentration doped emitter region and manufacturing method thereof |
| CN104701386A (en) * | 2015-02-11 | 2015-06-10 | 株洲南车时代电气股份有限公司 | Matchable fast recovery diode (FRD) of integrated gate commutate thyristor and manufacturing method of matchable fast recovery diode |
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