CN104701386A - Matchable fast recovery diode (FRD) of integrated gate commutate thyristor and manufacturing method of matchable fast recovery diode - Google Patents

Matchable fast recovery diode (FRD) of integrated gate commutate thyristor and manufacturing method of matchable fast recovery diode Download PDF

Info

Publication number
CN104701386A
CN104701386A CN201510072875.7A CN201510072875A CN104701386A CN 104701386 A CN104701386 A CN 104701386A CN 201510072875 A CN201510072875 A CN 201510072875A CN 104701386 A CN104701386 A CN 104701386A
Authority
CN
China
Prior art keywords
silicon chip
diffusion
aluminium
constant temperature
frd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510072875.7A
Other languages
Chinese (zh)
Other versions
CN104701386B (en
Inventor
高建宁
陈芳林
戴小平
蒋谊
郭润庆
张弦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhuzhou CRRC Times Electric Co Ltd
Zhuzhou CRRC Times Semiconductor Co Ltd
Original Assignee
Zhuzhou CSR Times Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhuzhou CSR Times Electric Co Ltd filed Critical Zhuzhou CSR Times Electric Co Ltd
Priority to CN201510072875.7A priority Critical patent/CN104701386B/en
Publication of CN104701386A publication Critical patent/CN104701386A/en
Application granted granted Critical
Publication of CN104701386B publication Critical patent/CN104701386B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Thyristors (AREA)

Abstract

The invention relates to a matchable fast recovery diode (FRD) of an integrated gate commutate thyristor and a manufacturing method of the matchable fast recovery diode. The technical method combining aluminum pre-depositing and boron ion implantation is adopted, so that the shortage that impurities of a quick rectifier tube cannot be uniformly distributed in longitudinal and transverse directions at the P<+> type layer can be overcome, the capacity of the FRD on bearing reverse turn-off current changing rate is greatly improved, and the FRD is able to bear the reverse turn-off current changing rate more than 500A/ microsecond; the technical method combining proton irradiation and electronic irradiation is adopted, thus the reverse recovery time trr of the FRD is less than 7 microseconds, and the soft factors S in the reverse recovery feature are not less than 1.0. The method is novel in technique and simple in process; the unique processes and techniques are adopted to bear relatively large reverse turn-off current changing rate; meanwhile, the soft feature is improved during reverse recovery; the actual application shows that the reliability in use in match with an IGCT is high, and therefore, the quality and yield of the FRD product can be ensured.

Description

The supporting fast recovery diode of integrated gate commutated thyristor and manufacture method thereof
Technical field
The invention belongs to technical field of manufacturing semiconductors, relate to the manufacture method of the supporting fast recovery diode of a kind of integrated gate commutated thyristor.
Background technology
The basic structure of FRD (Fast Recovery Diode, fast recovery diode) is different from general-purpose diode, and it is generally PIN type structure, namely in the middle of P type and N-type silicon materials, adds a base I layer.Because base is thin, QRR is little, not only substantially reduces t rrvalue (reverse recovery time), reduces V fM(forward voltage drop), also can bear higher V rRM(reverse voltage).FRD also has some other structure, as PINN +, P +pINN +, but be all generally deriving in PIN structural.
The more FRD of current domestic application has the supporting FRD of IGBT, its rated voltage is generally at 3300V and following, chip profile is box-shaped, device profile is modular type, its through-current capability and IGBT (InsulatedGate Bipolar Transistor, insulated gate bipolar transistor) coupling, but than general general purpose I GCT (IntegratedGate Commutated Thyristor, integrated gate commutated thyristor) through-current capability little, and IGCT device profile is ceramic flat template, historical facts or anecdotes border cannot supportingly be applied.
Resistance welder super-large current rectification FRD, rated current is very large, and generally between 7000-20000A, but rated voltage generally only requires a few hectovolt, can not mate with the rated voltage of IGCT completely.
Plastic package type FRD, comprises Schottky diode, and general rated voltage, at a few hectovolt and even 1000V, is no more than 2500V, and reverse recovery time is generally nanosecond, can not application supporting with IGCT.
Common fast recovery rectifier pipe, usually adopt heavy metal doping or electron irradiation to reduce the life-span of minority carrier, reverse recovery time is shorter, but softness during Reverse recovery controls not.The softness factor of heavy metal doping is about 0.4-0.7, can not meet the needs of IGCT practical application; Electron irradiation technology accurately can control minority carrier life time, but makes to show as hardware features during rectifying tube Reverse recovery, can not meet the needs of IGCT practical application.
Although a lot, its rated voltage and rated current all can not be mated with IGCT, can not actual supporting application for common fast recovery diode and the supporting FRD kind of IGBT on market.Although common fast recovery rectifier pipe rated voltage and rated current can be mated with IGCT, but it can not bear higher reverse shutoff di/dt (current changing rate), S (the softness factor) simultaneously in reverse recovery characteristic is too little, easily cause high dv/dt (voltage change ratio) and Vrr (reverse spike voltage), when Vrr is greater than the V of common fast recovery rectifier pipe rSMtime, common fast recovery rectifier pipe will lose efficacy by voltage, can damage together by related IGCT device, thus make failure of apparatus when common fast recovery rectifier pipe damages.
Therefore, current Problems existing needs research and development its rated voltage a kind of and rated current can both mate with IGCT, and can bear higher reverse shutoffs di/dt, quick shutoff and reverse recovery time t rrlittle, and there is the FRD supporting with IGCT device application of softer reverse recovery characteristic.
Summary of the invention
Technical problem to be solved by this invention is for the deficiencies in the prior art, provides the manufacture method of the supporting fast recovery diode of a kind of integrated gate commutated thyristor.The method new technology, flow process is simple, uses unique technology to make it to bear higher reverse shutoff di/dt, and simultaneously during Reverse recovery, software feature is very good, and practical application proves with the matching used reliability of IGCT device high.
For this reason, first aspect present invention provides the supporting fast recovery diode of a kind of integrated gate commutated thyristor, and it is P +/ N -/ N +type structure, can bear repetitive peak reverse voltage (being also called reverse BV) V rRMfor 4500-7000V, forward mean current rating I f (AV)for 400-2500A, reverse cut-off current rate of change di/dt is 500-5000A/ μ s, and reverse recovery time, trr was 3-7 μ s, and the softness factor (being also called Reverse recovery softness) S>=1.
Second aspect present invention additionally provides the manufacture method of the supporting fast recovery diode of a kind of integrated gate commutated thyristor, comprising:
Steps A, preliminary treatment: single-sided polishing process is carried out to N-type original silicon chip and obtains preliminary treatment silicon chip;
Step B, P type doping treatment;
Step C, one side mill process: the P-type layer grinding off the non-polished surface of silicon chip, obtains P +/ N -the silicon chip of type structure;
Step D, expands phosphorus process: to P +/ N -the silicon chip of type structure carries out first time cleaning, dries dress boat, then pushes constant temperature diffusion in diffusion furnace and carries out phosphorus impurities pre-deposition; Again second time cleaning carried out to silicon chip, dry dress boat, then push in diffusion furnace, pass into oxygen constant temperature and advance, obtain P +/ N -/ N +the silicon chip of type structure;
Step e, reprocessing: by P +/ N -/ N +the silicon chip of type structure carries out cyclotomy, evaporation of aluminum and alloy and table top moulding and conservation treatment successively and obtains complete chip;
Wherein, in stepb, P type doping treatment comprises carries out aluminium pre-deposition and boron ion implantation to preliminary treatment silicon chip, and then carries out the propelling of boron aluminium, forms P +/ N -the silicon chip of/P type structure.
According to the present invention, described aluminium pre-deposition carries out the two-sided of silicon chip, and described boron ion implantation is carried out at the burnishing surface of silicon chip, and described aluminium pre-deposition and boron ion implantation are carried out according to random order.Preferred described aluminium pre-deposition and boron ion implantation are carried out according to the order of boron ion implantation after first aluminium pre-deposition.
In certain embodiments of the present invention, described aluminium pre-deposition comprises and is carried out cleaning, drying dress boat by silicon chip, then pushes in vacuum aluminum pre-deposition diffusion furnace, and constant temperature spreads, and control surface aluminum concentration is 10 18-10 19/ cm 3.
In the present invention, in above-mentioned aluminium pre-deposition process, the temperature of described constant temperature diffusion is 900-950 DEG C.
In other execution modes of the present invention, described boron ion implantation comprises is undertaken cleaning, drying dress boat by silicon chip, then pushes in oxide-diffused stove, passes into the diffusion of oxygen constant temperature, forms SiO on the two surface of silicon chip 2diaphragm, then injects boron ion at burnishing surface.Injecting deflection angle is 7 °.
In the present invention, in above-mentioned boron ion implantation process, described SiO 2the thickness of diaphragm is 22-52nm; The temperature of described constant temperature diffusion is 800-850 DEG C.
In other execution modes of the present invention, described boron aluminium advances to comprise and is carried out cleaning, drying dress boat by the silicon chip completing aluminium pre-deposition and boron ion implantation, then pushes in oxide-diffused stove, and pass into the diffusion of oxygen constant temperature, control surface boron aluminium total concentration is 10 16-10 17/ cm 3.
In the present invention, in above-mentioned boron aluminium progradation, the temperature of described constant temperature diffusion is 1200-1250 DEG C.
According to the present invention, in step C, the thickness of chip is made to reach 0.7-1.0mm.
According to the present invention, in step D, the temperature of described constant temperature diffusion is 1000-1100 DEG C, and the surperficial phosphorus concentration of constant temperature diffusion controls 10 21-10 22/ cm 3.The temperature that described constant temperature advances is 1000-1100 DEG C, and the surperficial phosphorus concentration that constant temperature advances controls 10 20-10 21/ cm 3.
According to the present invention, described method also comprises step F, and minority carrier life time controls: comprise proton irradiation and electron irradiation.
In the present invention, described proton irradiation carries out on proton irradiation equipment, described electron irradiation carries out on electron irradiation equipment, whether detection chip minority carrier life time reaches predetermined value, if do not reach predetermined value, continue electron irradiation until reach predetermined value, described proton irradiation and electron irradiation carry out according to random order.
In some embodiments of the invention, the predetermined value of described chip minority carrier life time is 2-10 μ s.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the present invention is described.
Fig. 1 is the FRD preparation technology flow chart of embodiment 1.
Fig. 2 is FRD reverse recovery characteristic parameter schematic diagram in the present invention;
In figure, the implication of Reference numeral is as follows: I rrreverse recovery current; t rrreverse recovery time; Reverse shutoff di/dt: reverse current rate of change; t athe memory time of minority carrier; t bthe recombination time of minority carrier; IF forward current; N% gets the percentage of Irr value.
Embodiment
For making the present invention easier to understand, describe the present invention in detail below in conjunction with embodiment and accompanying drawing, these embodiments only play illustrative effect, are not limited to range of application of the present invention.
The supporting fast recovery diode of integrated gate commutated thyristor provided by the present invention, it is P +/ N -/ N +type structure, can bear repetitive peak reverse voltage V rRMfor 4500-7000V, forward mean current rating I f (AV)for 400-2500A, reverse cut-off current rate of change di/dt is 500-5000A/ μ s, and reverse recovery time, trr was 3-7 μ s, and softness factor S>=1.Through inventor test prove practical application prove this fast recovery diode of the present invention and the matching used reliability of IGCT device very high.
In a specific embodiment of the present invention, the manufacture method of the supporting fast recovery diode of integrated gate commutated thyristor provided by the present invention comprises silicon chip preliminary treatment successively, forms P +/ N -the silicon chip of/P type structure, formation P +/ N -the silicon chip of type structure, formation P +/ N -/ N +the silicon chip of type structure and the step of formation complete chip, be specifically described each step below.
Steps A, preliminary treatment:
Choose the N-type silicon single crystal flake of resistivity 200-400 Ω m as original silicon chip, and single-sided polishing process acquisition preliminary treatment silicon chip is carried out to this silicon chip.
Step B, P type doping treatment (formation anode):
In stepb, aluminium pre-deposition and boron ion implantation are carried out to preliminary treatment silicon chip, and then carry out the propelling of boron aluminium, form P +/ N -the silicon chip of/P type structure; Wherein previous P +type layer has aluminium boron two kinds of impurity, and a rear P-type layer only has aluminium impurity.
" aluminium pre-deposition " refers in diffusion in vacuum stove, first aluminium impurity (aluminium atom) is deposited to silicon chip surface, and then advance formation Gaussian Profile by high temperature, remain the feature that aluminium diffusion velocity is fast, be easy to form dark knot, Impurity Distribution is relatively milder simultaneously, can increase in the uniformity of chip genesis analysis.
" boron ion implantation " to refer to boron ion implantation by ion implantation technology in silicon chip, boron ion implantation, to the shallow table of silicon chip, forms controlled diffusion into the surface source, then carries out high temperature and advances diffusion, make boron ion Gaussian Profile again, reach certain junction depth and higher surface concentration.
The high temperature of boron ion advances and adopts Open tdde diffusion: silicon chip is placed in pipe, and is connected with Buchholz protection, and temperature is more than 1000 DEG C.The diffusion uniformity of boron ion implantation surface concentration can be controlled within 5%, by boron ion implantation and spray the comparing of boron diffusion uniformity, the results are shown in Table 1, as can be seen from Table 1, the diffusion uniformity of spray boron is close to 12%, obvious boron ion implantation is higher than the diffusion uniformity of spray boron a lot, and as seen at chip in a lateral direction, the diffusion uniformity of P pole impurity there has also been larger raising.
Diffusion uniformity described in the present invention is weighed by the uneven angle value of sheet resistance.The uneven angle value of described sheet resistance is calculated according to formula (I) by 5 square resistance (sheet resistance) values.
In formula (I):
Max: sheet resistance maximum;
Min: sheet resistance minimum value;
Avg: sheet resistance mean value.
Described interior uniformity is weighed by the uneven angle value of sheet resistance in sheet, the described uneven angle value of interior sheet resistance is calculated according to formula (I) by 5 sheet resistance values (namely measured by the center of single silicon chip sample and 4 points in 4 limit shape distributions) of single silicon chip sample, and in formula (I):
Max is the maximum in 5 sheet resistance values;
Min is the minimum value in 5 sheet resistance values;
The mean value of Avg:5 sheet resistance value.
Between described, uniformity is weighed by the uneven angle value of sheet resistance between sheet, and between described, the uneven angle value of sheet resistance is that in sheet by 5 silicon chip samples, sheet resistance mean value calculates according to formula (I), and in formula (I):
Max be 5 silicon chip samples sheet in maximum in sheet resistance mean value;
Min be 5 silicon chip samples sheet in minimum value in sheet resistance mean value;
Avg be 5 silicon chip samples sheet in the mean value of sheet resistance mean value.
In the sheet of described silicon chip sample, sheet resistance mean value is the mean value of 5 sheet resistance values (namely measured by the center of single silicon chip sample and 4 points in 4 limit shape distributions) of single silicon chip sample.
Between described batch uniformity by batch between the uneven angle value of sheet resistance weigh, between described batch, the uneven angle value of sheet resistance is that between sheet by 5 batches of silicon chip samples, sheet resistance mean value calculates according to formula (I), and in formula (I):
Max be 5 batches of silicon chip samples sheet between maximum in sheet resistance mean value;
Min be 5 batches of silicon chip samples sheet between minimum value in sheet resistance mean value;
Avg be 5 batches of silicon chip samples sheet between the mean value of sheet resistance mean value.
Between the sheet of described silicon chip sample sheet resistance mean value be all silicon chip samples in single batch of silicon chip sample sheet in the mean value of sheet resistance mean value (namely measured by the center of each silicon chip sample and 4 points in 4 limit shapes distributions).
Table 1 boron ion implantation and the contrast of spraying boron diffusion uniformity
Technique Uniformity in sheet Uniformity between sheet Uniformity between batch
Spread after boron ion implantation 1.24％ 3.16％ 3.85％
Spread after chip surface spray boron 8.43％ 10.25％ 11.67％
When applying with IGCT is supporting, it is very high that IGCT opens di/dt, and IGCT opens di/dt and FRD and turns off di/dt, must be restricted for protection FRD, IGCT open di/dt, and the extra external circuit that increases suppresses IGCT to open di/dt.In order to improve the overall performance of device, need to improve the ability to bear that FRD oppositely turns off di/dt (generally at 500A/ more than μ s), namely require that the Impurity Distribution of the P pole in FRD device PIN structural is even, described uniformity comprises both direction: horizontal and vertical.
General fast recovery rectifier pipe adopts and then spreads at chip surface painting boron aluminum impurity source or at chip side placement boron aluminum impurity source, and the uniformity of the P pole impurity obtained is not high.Of the present invention " aluminium pre-deposition " technique and " boron ion implantation " technique to be combined, ensure the uniformity of chip P pole Impurity Distribution longitudinal direction by " aluminium pre-deposition " technique, the uniformity of P pole Impurity Distribution transverse direction can be ensured by the technique that " boron ion implantation " then spreads.The present invention adopts the cooperation process of aluminium pre-deposition+boron ion implantation to ensure that P +type layer, in length and breadth to the high homogeneity of Impurity Distribution, decreases the loss amount of aluminium boron impurity simultaneously, has saved cost, has improve diffuser efficiency.
In one embodiment of the invention, aluminium pre-deposition is carried out to preliminary treatment silicon chip: preliminary treatment silicon chip silicon chip first carried out the general standard RCA clean of semicon industry, dry dress boat, then push in vacuum aluminum pre-deposition diffusion furnace, silicon boat and the diffusion furnace inwall of preformed saturated aluminium doping in diffusion furnace, put into high-purity (purity is 99.9999%) aluminium source, under 900-950 DEG C of condition, carry out constant temperature diffusion, and control surface aluminum concentration is 10 18-10 19/ cm 3.If silicon chip surface aluminum concentration does not reach 10 18-10 19/ cm 3, again can clean, then mend pre-aluminium, until reach pre-provisioning request.
In another embodiment of the present invention, boron ion implantation is carried out to silicon chip: first pre-oxidation forms the very thin SiO of one deck 2protective layer is that boron ion implantation is prepared: silicon chip RCA cleans, dry dress boat, then pushes in oxide-diffused stove, passes into oxygen, and constant temperature diffusion at 800-850 DEG C, forming thickness on the two surface of silicon chip is the SiO of 22-52nm 2diaphragm.Then press technological parameter one side and inject boron ion (B + 11), injection face is burnishing surface, and injecting deflection angle is 7 °.
Inventor according to the present inventor studies discovery, works as SiO 2when protective layer thickness is less than 22nm, boron ion implantation easily causes damage to the silicon chip face under protective layer, works as SiO 2when protective layer thickness is greater than 52nm, the boron ion that major part is injected can rest on SiO 2in protective layer, boron ion implantation technology was lost efficacy.
In another embodiment of the present invention, the propelling of boron aluminium is carried out to silicon chip: after Wafer Cleaning is clean, dry dress boat, then push in oxide-diffused stove, pass into oxygen, and constant temperature diffusion at 1200-1250 DEG C, the surface boron aluminium total concentration of burnishing surface is controlled 10 16-10 17/ cm 3.
In the present invention, described aluminium pre-deposition carries out the two-sided of silicon chip, and described boron ion implantation is carried out at the burnishing surface of silicon chip, and described aluminium pre-deposition and boron ion implantation are carried out according to random order.
In a preferred embodiment, described aluminium pre-deposition and boron ion implantation are carried out according to the order of boron ion implantation after first aluminium pre-deposition.Because if first note boron pre-aluminium (aluminium pre-deposition) again, when pre-aluminium, boron is at high temperature to silicon chip diffusion inside, also can spread in the gas in pre-aluminium diffusion furnace, a boron dividing potential drop can be formed, limit the lifting of aluminum partial pressure in pre-aluminium diffusion furnace gas, thus the content causing aluminium to be diffused in silicon chip is very limited.First pre-aluminium notes boron again would not such problem, because it is allow positively charged boron ion accelerate in the electric field that boron injects, obtains a high speed and then is driven in silicon chip.
Step C, the process of one side mill:
To P +/ N -the silicon chip of/P type structure carries out the process of one side mill, grinds off the P-type layer of the non-polished surface of silicon chip, makes the thickness of chip reach 0.7-1.0mm, obtain P +/ N -the silicon chip of type structure.
Study discovery through the present inventor, the thickness of chip is less than 0.7mm, the V of FRD rRMdo not reach 4500V, chip is thicker, V rRMhigher, but pressure drop V fMwith other key parameters, as QRR Qrr can be deteriorated gradually; The thickness of chip is more than 1mm, FRD pressure drop V fMtoo poor with Qrr characteristic.The THICKNESS CONTROL of chip is at 0.7-1.0mm, and this balances V rRM, V fMand the optimum range after Qrr.
Step D, expands phosphorus process (formation negative electrode):
To P +/ N -the silicon chip of type structure carries out first time RCA and cleans, dries dress boat, then push in diffusion furnace, and at 1000-1100 DEG C, phosphorus impurities pre-deposition is carried out in constant temperature diffusion, adopts liquid source POCl 3diffusion, removes the SiO of silicon chip surface with HF acid soak silicon chip after coming out of the stove 2layer, detects silicon chip negative electrode N +whether the surperficial phosphorus concentration in face controls 10 21-10 22/ cm 3; Then second time RCA cleaning carried out to silicon chip, dry dress boat, then push in diffusion furnace, pass into oxygen, and constant temperature advances at 1150-1200 DEG C, removes the SiO of silicon chip surface after coming out of the stove with HF acid soak silicon chip 2layer, detects silicon chip negative electrode N +whether the surperficial phosphorus concentration in face controls 10 20-10 21/ cm 3, obtain P +/ N -/ N +the silicon chip of type structure, is called for short PIN structural.
Step e, reprocessing (rear operation):
By P +/ N -/ N +the silicon chip of type structure carries out cyclotomy, evaporation of aluminum and alloy and table top moulding and conservation treatment successively and obtains complete chip.
In one embodiment, to P +/ N -/ N +the silicon chip of type structure carries out cyclotomy: the disk with laser cyclotomic machine, silicon chip being cut into required diameter size, such as the disk of diameter 38-96mm.
In another embodiment, to the P through cyclotomy +/ N -/ N +the silicon chip of type structure carries out evaporation of aluminum and alloy treatment: after Wafer Cleaning is clean, put into vacuum evaporator and carry out two-sided evaporation aluminium lamination, then puts in alloying furnace and carry out firmly treatment, at P +/ N -/ N +an aluminium/silicon alloy layer is defined between the silicon chip surface of type structure and the interface of aluminium lamination.
In another embodiment, to the P through evaporation of aluminum and alloy treatment +/ N -/ N +the silicon chip of type structure carries out table top moulding and protection: the silicon chip after evaporation post bake is carried out angle lap moulding, then in etching machine, carries out mesa etch, carry out Coating glue protect afterwards, hot setting, form complete chip.
In another embodiment of the present invention, the manufacture method of the supporting fast recovery diode of integrated gate commutated thyristor provided by the present invention also comprises minority carrier life time rate-determining steps, such as, can carry out proton irradiation and electron irradiation to the complete chip obtained in step e.
In the present invention, described proton irradiation carries out on proton irradiation equipment, described electron irradiation carries out on electron irradiation equipment, whether detection chip minority carrier life time reaches predetermined value, such as 2-10 μ s, if do not reach predetermined value, continue electron irradiation until reach predetermined value, described proton irradiation and electron irradiation carry out according to random order.
Discovery is studied according to the present inventor, when minority carrier life time is less than 2 μ s, V fMbe worth too large; When minority carrier life time is greater than 10 μ s, reverse recovery time, trr value was too large.
IGCT requires it is not only fast but also soft to the reverse recovery characteristic of supporting FRD, " soon " refers to that reverse recovery time trr is short, the length of trr is directly connected to switching loss and the operating frequency of device, and " soft " softness S when referring to Reverse recovery, softness S is greater than 1, otherwise di/dt is high for FRD Reverse recovery, easily causes high dv/dt and peak voltage, causes FRD and IGCT component failure.
Softness S after general heavy metal doping or electron irradiation is below 0.7, and proton irradiation is easily more than 1.0, but due to proton irradiation cost higher, and proton irradiation equipment is rare and correlation experience is less, general FRD many employings Electron irradiation technology.
The defect peak degree of depth of proton irradiation regulates with the change of irradiation energy, and the local minority carrier life time being easy to realize FRD device controls.By proton irradiation, chip minority carrier life time in a longitudinal direction can be made to be certain gradient distribution, instead of to be uniformly distributed, allow the recovery characteristics of device become very soft.
Electron irradiation can reduce easily QRR Qrr, reverse recovery time trr; And proton irradiation can reduce reverse recovery current Irr easily, increase softness factor S value, reach required software feature." proton irradiation " technique combines with " electron irradiation " by the present invention, mutually learns from other's strong points to offset one's weaknesses, and device can be made to obtain best quick soft-recovery characteristic, to meet parameter request during IGCT application.That is the present invention adopts the life control method having gradient to distribute in the cooperation process of proton irradiation+electron irradiation formation silicon chip longitudinal direction, ensures the reverse recovery characteristic that FRD is not only fast but also soft.
Proton irradiation and electron irradiation belong to irradiation technique.Proton irradiation can not penetrate chip, and longitudinally above the minority carrier life time of a certain depth (width of the degree of depth is 5 μm) is very low can only to make chip, thus affecting parameters, different to the influence degree of each parameter of Reverse recovery, major effect Irr, S, to V fM, Qrr, trr also have impact, just mild degree some, also different.And electron irradiation can penetrate chip, thus the minority carrier life time of the longitudinal upper all degree of depth of chip is all reduced and reducing amount is the same, thus affecting parameters, major effect Qrr, trr, to V fM, Irr, S also have impact, just mild degree some, also different.
Therefore, when regulating the proton irradiation degree of depth, proton irradiation dosage and this three state-variables of electron irradiation dosage, it is crucial that ensureing at V fMwhen identical, compare other parameters, as long as other parameters meet the requirements, just can judge that this " proton irradiation+electron irradiation " concrete technology is feasible.
" proton irradiation+electron irradiation " technology, compared with " proton irradiation " technology, works as V fMwhen being worth identical, Qrr, trr value is little.
" proton irradiation+electron irradiation " technology, compared with " electron irradiation " technology, works as V fMwhen being worth identical, Irr value is little, and softness factor S value is large.
That is " proton irradiation+electron irradiation " combination technology overcomes both respective defects dexterously, obtains a reverse recovery parameters Qrr, Irr, trr value is little, and the FRD device that softness factor S value is large, meet the supporting application requirement of IGCT.
In a specific embodiment of the present invention, the manufacture method of the supporting fast recovery diode of integrated gate commutated thyristor provided by the present invention also comprises the step of encapsulation: be assembled in ceramic cartridge by chip, molybdenum sheet, alignment pin, is welded by lower casing on shell with special cold welding packaging machine.
In a specific embodiment of the present invention, the manufacture method of the supporting fast recovery diode of integrated gate commutated thyristor provided by the present invention also comprises the step of test: packaged device, utilizes voltage-current characteristic testing equipment, on-state voltage drop testing equipment, FRD reverse recovery parameters testing equipment to test following voltage-current characteristic, forward voltage drop, the reverse recovery parameters of FRD respectively:
Forward mean current rating I f (AV)400-2500A;
Reverse cut-off current rate of change di/dt 500-5000A/ μ s;
Repetitive peak reverse voltage V rRM4500-7000V;
Non-repetitive peak reverse voltage V rSM4600-7100V;
Forward voltage drop V fM≤ 5.0V;
Peak Repetitive Reverse Current I rRM≤ 50mA;
Maximum junction temperature T vJM125 DEG C;
QRR Qrr≤3200 μ C;
Reverse recovery time trr 3-7 μ s;
Softness factor S >=1.0.
Term of the present invention " heavy metal doping " refers to that the beavy metal impurity of selection deep energy level is diffused into the technology in silicon chip, and this technology can be used for reducing minority carrier life time.Conventional heavy metal has gold, platinum, palladium.
The technology that term of the present invention " proton irradiation " is shot at the target after referring to and being accelerated by hydrogen atom, can control the silicon chip local minority carrier life-span like this.
Term of the present invention " electron irradiation " refers to that silicon chip is placed in irradiation field, is bombarded by electronics, forms complex centre, reaches the object controlling minority carrier life time.
Term of the present invention " forward current " (IF) refers to the FRD current value that forward flows through before oppositely turning off.
In the present invention, n% is the percentage getting Irr value, generally has 10%, 25%, 50%, and this is a set point, its objective is and is convenient to read trr value.Fig. 2 is FRD reverse recovery characteristic parameter schematic diagram in the present invention, and in all character express of the present invention, n% gets 25%.
" cleaning " used in the present invention word, is not having in specially appointed situation, is referring to the standard RCA clean that semicon industry is general.
In the present invention, IGCT is the abbreviation of Integrated Gate Commutated Thyristor, i.e. integrated gate commutated thyristor.
In the present invention, FRD is the abbreviation of Fast Recovery Diode, i.e. fast recovery diode.FRD reverse recovery characteristic parameter comprises Q rr(QRR), I rr(reverse recovery current), t rr(reverse recovery time), S (the softness factor) and oppositely turn off di/dt, wherein, softness factor S calculates according to formula (II), QRR Q rrcalculate according to formula (III).
S＝t b/t a(Ⅱ)
Q rr=∫ trr 0i rrdt (namely within the trr time, the integration of Irr) (III)
According to the inventive method, first choose N-type silicon single crystal disk, single-sided polishing, then two-sided aluminium pre-deposition, then carry out boron ion implantation in the side of burnishing surface, then advance together, form P+/N-/P type (previous P +layer has aluminium boron two kinds of impurity, and a rear P layer only has a kind of impurity of aluminium), then one side grinds off a rear P layer, and continues to be ground to a suitable thickness, namely obtains P +/ N -structure.Then at P +/ N -structural N -face is spread phosphorus impurities to form N +layer (now P +layer surface remains with the SiO of the adequate thickness stayed when boron aluminium advances 2oxide layer, can stop that phosphorus impurities is diffused into P +in layer), form P +/ N -/ N +structure.Last whole silicon chip carries out " proton irradiation+electron irradiation " technique, makes the supporting FRD of IGCT.
The supporting fast recovery diode of integrated gate commutated thyristor adopting the inventive method obtained is P +/ N -/ N +type structure, can bear repetitive peak reverse voltage V rRMbetween 4500-7000V, forward mean current rating I f (AV)between 400-2500A, oppositely turn off di/dt between 500-5000A/ μ s, reverse recovery time is 3-7 μ s, and softness factor S>=1.
The present invention adopts the cooperation process of aluminium pre-deposition and boron ion implantation, overcomes general fast recovery rectifier pipe at P +type layer, in length and breadth to the shortcoming that Impurity Distribution is uneven, significantly improves FRD and bears the ability oppositely turning off di/dt, generally can bear the reverse shutoff di/dt of 500A/ more than μ s.
The cooperation technique of aluminium pre-deposition and boron ion implantation not only overcomes at P +type layer is in length and breadth to the shortcoming that Impurity Distribution is uneven, and when next step boron aluminium advances technique, because there is aluminium and boron ion in silicon chip top layer simultaneously, when High temperature diffusion, aluminium and boron are not only to silicon chip diffusion inside, also spread in diffusion furnace gas, but due to boron dividing potential drop and the mutual containing of aluminum partial pressure, both content is not high, compared with only aluminium pre-deposition or only boron ion implantation just advance and compare, be diffused into aluminium in diffusion furnace or boron impurity content much lower, and then aluminium or Boron contents are high a lot of in silicon chip, impurity loss amount is less and then cost-saving and improve diffuser efficiency.
Adopt the cooperation process of proton irradiation and electron irradiation, make FRD reverse recovery time trr when 7 below μ s, softness S >=1 in reverse recovery characteristic.These 2 features make it the requirement that FRD can meet IGCT application preferably.
The inventive method new technology, the simple and clear smoothness of flow process, unique technology is used to make it to bear higher reverse shutoff di/dt, simultaneously during Reverse recovery, software feature is good, practical application proves with the matching used reliability of IGCT device high, makes the output of FRD product and rate of finished products be obtained for guarantee.
Embodiment
Embodiment 1:
FRD preparation technology flow chart is shown in Fig. 1.
1. preliminary treatment (single-sided polishing):
Choose resistivity be the N-type silicon single crystal flake of 200 Ω .m as original silicon chip, and single-sided polishing process carried out to this silicon chip obtain preliminary treatment silicon chip.
2.P type doping treatment (formation anode):
(1) aluminium pre-deposition:
Silicon chip first carries out the general standard RCA clean of semicon industry, dries dress boat, then push in vacuum aluminum pre-deposition diffusion furnace, be silicon boat and the diffusion furnace inwall of preformed saturated aluminium doping in diffusion furnace, put into purity 99.9999% aluminium source, constant temperature 900 DEG C diffusion, surfaces of aluminum concentration is 10 18/ cm 3.
(2) boron ion implantation:
First silicon chip pre-oxidation is formed one deck SiO 2protective layer is that boron ion implantation is prepared: carry out RCA cleaning to silicon chip, dry dress boat, then push in oxide-diffused stove, pass into oxygen constant temperature 800 DEG C diffusion, and the two surface of silicon chip forms the SiO of thickness 22nm 2diaphragm.Then B is injected from burnishing surface + 11, injecting deflection angle is 7 °.
(3) boron aluminium advances:
After Wafer Cleaning is clean, dry dress boat, then push in oxide-diffused stove, pass into oxygen constant temperature 1200 DEG C diffusion, surface concentration is 10 16/ cm 3.
3. one side mill process
Grind off the P layer of the non-polished surface of silicon chip with wafer lapping machine, after one side mill, chip thickness is 0.7mm, and now silicon chip is P +/ N -structure.
4. expand phosphorus process (formation negative electrode)
After Wafer Cleaning is clean, dries dress boat, then push constant temperature 1000 DEG C diffusion in diffusion furnace, adopt liquid source POCl 3diffusion, with HF acid bubble silicon chip after coming out of the stove, removes the SiO of silicon chip surface 2layer, negative electrode N +surface concentration>=10 21/ cm 3; Then silicon chip RCA cleaning again, drying dress boat, then push in diffusion furnace, pass into oxygen constant temperature 1150 DEG C propelling, with HF acid bubble silicon chip after coming out of the stove, removes the SiO of silicon chip surface 2layer, negative electrode N +surface concentration>=10 20/ cm 3, now silicon chip is P +/ N -/ N +structure, is called for short PIN structural.
5. reprocessing (rear operation)
(1) cyclotomy:
With laser cyclotomic machine, silicon chip is cut into the disk of ￠ 38mm.
(2) evaporation of aluminum and alloy:
After Wafer Cleaning is clean, put into vacuum evaporator and carry out two-sided evaporation aluminium lamination, then put post bake formation alloy-layer in alloying furnace into.
(3) table top moulding and protection:
Silicon chip after evaporation post bake is carried out angle lap moulding, then in etching machine, carries out mesa etch, carry out Coating glue protect afterwards, hot setting, form complete chip.
6. minority carrier life time controls:
(1) proton irradiation:
Proton irradiation equipment carries out proton irradiation.
(2) electron irradiation:
Electron irradiation equipment carries out electron irradiation, and final minority carrier life time controls at 2-10 μ s.
7. encapsulate:
Chip, molybdenum sheet, alignment pin are assembled in ceramic cartridge, with special cold welding packaging machine, lower casing on shell are welded.
8. test:
Packaged device, utilizes voltage-current characteristic testing equipment, on-state voltage drop testing equipment, FRD reverse recovery parameters testing equipment to test voltage-current characteristic, forward voltage drop, reverse recovery parameters respectively.
FRD (ZK 8performance parameter 400-45) is as follows:
Forward mean current rating I f (AV)400A;
Reverse cut-off current rate of change di/dt 500-5000A/ μ s;
Repetitive peak reverse voltage V rRM4500-5000V;
Non-repetitive peak reverse voltage V rSM4600-5100V;
Forward voltage drop V fM≤ 2.5-2.9V;
Peak Repetitive Reverse Current I rRM≤ 50mA;
Maximum junction temperature T vJM125 DEG C;
QRR Qrr≤930 μ C;
Reverse recovery time trr 3-7 μ s;
Softness factor S >=1.0.
Embodiment 2:
The FRD preparation technology flow process of embodiment 2 is identical with embodiment 1.
1. preliminary treatment (single-sided polishing):
Choose resistivity be the N-type silicon single crystal flake of 400 Ω .m as original silicon chip, and single-sided polishing process carried out to this silicon chip obtain preliminary treatment silicon chip.
2.P type doping treatment (formation anode):
(1) aluminium pre-deposition:
Silicon chip first carries out the general standard RCA clean of semicon industry, dries dress boat, then push in vacuum aluminum pre-deposition diffusion furnace, be silicon boat and the diffusion furnace inwall of preformed saturated aluminium doping in diffusion furnace, put into purity 99.9999% aluminium source, constant temperature 950 DEG C diffusion, surface concentration is 10 19/ cm 3.
(2) boron ion implantation:
First silicon chip pre-oxidation is formed one deck SiO 2protective layer is that boron ion implantation is prepared: silicon chip RCA cleans, dry dress boat, then pushes in oxide-diffused stove, passes into oxygen constant temperature 850 DEG C diffusion, and the two surface of silicon chip forms the SiO of thickness 52nm 2diaphragm.Then B is injected from burnishing surface + 11, injecting deflection angle is 7 °.
(3) boron aluminium advances:
After Wafer Cleaning is clean, dry dress boat, then push in oxide-diffused stove, pass into oxygen constant temperature 1250 DEG C diffusion, surface concentration is 10 17/ cm 3.
3. one side mill process:
Grind off the P layer of the non-polished surface of silicon chip with wafer lapping machine, after one side mill, chip thickness is 1.0mm, and now silicon chip is P +/ N -structure.
4. expand phosphorus process (formation negative electrode):
After Wafer Cleaning is clean, dries dress boat, then push constant temperature 1100 DEG C diffusion in diffusion furnace, adopt liquid source POCl 3diffusion, with HF acid bubble silicon chip after coming out of the stove, removes the SiO of silicon chip surface 2layer, negative electrode N +surface concentration>=10 22/ cm 3; Then silicon chip RCA cleaning again, drying dress boat, then push in diffusion furnace, pass into oxygen constant temperature 1200 DEG C propelling, with HF acid bubble silicon chip after coming out of the stove, removes the SiO of silicon chip surface 2layer, negative electrode N +surface concentration>=10 21/ cm 3, now silicon chip is P +/ N -/ N +structure, is called for short PIN structural.
5. reprocessing (rear operation):
(1) cyclotomy:
With laser cyclotomic machine, silicon chip is cut into the disk of ￠ 96mm.
(2) evaporation of aluminum and alloy:
After Wafer Cleaning is clean, put into vacuum evaporator and carry out two-sided evaporation aluminium lamination, then put post bake formation alloy-layer in alloying furnace into.
(3) table top moulding and protection:
Silicon chip after evaporation post bake is carried out angle lap moulding, then in etching machine, carries out mesa etch, carry out Coating glue protect afterwards, hot setting, form complete chip.
6. minority carrier life time controls:
(1) proton irradiation:
Proton irradiation equipment carries out proton irradiation.
(2) electron irradiation:
Electron irradiation equipment carries out electron irradiation, and final minority carrier life time controls at 2-10 μ s
7. encapsulate:
Chip, molybdenum sheet, alignment pin are assembled in ceramic cartridge, with special cold welding packaging machine, lower casing on shell are welded.
8. test:
Packaged device, utilizes voltage-current characteristic testing equipment, on-state voltage drop testing equipment, FRD reverse recovery parameters testing equipment to test voltage-current characteristic, forward voltage drop, reverse recovery parameters respectively.
FRD (ZK cperformance parameter 2500-60) is as follows:
Forward mean current rating I f (AV)2500A;
Reverse cut-off current rate of change di/dt 500-5000A/ μ s;
Repetitive peak reverse voltage V rRM6000-7000V;
Non-repetitive peak reverse voltage V rSM6100-7100V;
Forward voltage drop V fM≤ 4.5-5.0V;
Peak Repetitive Reverse Current I rRM≤ 50mA;
Maximum junction temperature T vJM125 DEG C;
QRR Qrr≤5250 μ C;
Reverse recovery time trr 3-7 μ s;
Softness factor S >=1.0.
Embodiment 3:
The FRD preparation technology flow process of embodiment 3 is identical with embodiment 1.
1. preliminary treatment (single-sided polishing):
Choose resistivity be the N-type silicon single crystal flake of 300 Ω .m as original silicon chip, and single-sided polishing process carried out to this silicon chip obtain preliminary treatment silicon chip.
2.P type doping treatment (formation anode):
(1) aluminium pre-deposition:
Silicon chip first carries out the general standard RCA clean of semicon industry, dries dress boat, then push in vacuum aluminum pre-deposition diffusion furnace, be silicon boat and the diffusion furnace inwall of preformed saturated aluminium doping in diffusion furnace, put into purity 99.9999% aluminium source, constant temperature 930 DEG C diffusion, surface concentration is 5 × 10 18/ cm 3.
(2) boron ion implantation:
First silicon chip pre-oxidation is formed one deck SiO 2protective layer is that boron ion implantation is prepared: silicon chip RCA cleans, dry dress boat, then pushes in oxide-diffused stove, passes into oxygen constant temperature 830 DEG C diffusion, and the two surface of silicon chip forms the SiO of thickness 37nm 2diaphragm.Then B is injected from burnishing surface + 11, injecting deflection angle is 7 °.
(3) boron aluminium advances:
After Wafer Cleaning is clean, dry dress boat, then push in oxide-diffused stove, pass into oxygen constant temperature 1230 DEG C diffusion, surface concentration is 5 × 10 16/ cm 3.
3. one side mill process:
Grind off the P layer of the non-polished surface of silicon chip with wafer lapping machine, after one side mill, chip thickness is 0.8mm, and now silicon chip is P +/ N -structure.
4. expand phosphorus process (formation negative electrode):
After Wafer Cleaning is clean, dries dress boat, then push constant temperature 1050 DEG C diffusion in diffusion furnace, adopt liquid source POCl 3diffusion, with HF acid bubble silicon chip after coming out of the stove, removes the SiO of silicon chip surface 2layer, negative electrode N +surface concentration>=5 × 10 21/ cm 3; Then silicon chip RCA cleaning again, drying dress boat, then push in diffusion furnace, pass into oxygen constant temperature 1180 DEG C propelling, with HF acid bubble silicon chip after coming out of the stove, removes the SiO of silicon chip surface 2layer, negative electrode N +surface concentration>=5 × 10 20/ cm 3, now silicon chip is P +/ N -/ N +structure, is called for short PIN structural.
5. reprocessing (rear operation):
(1) cyclotomy:
With laser cyclotomic machine, silicon chip is cut into the disk of ￠ 73mm.
(2) evaporation of aluminum and alloy:
After Wafer Cleaning is clean, put into vacuum evaporator and carry out two-sided evaporation aluminium lamination, then put post bake formation alloy-layer in alloying furnace into.
(3) table top moulding and protection:
Silicon chip after evaporation post bake is carried out angle lap moulding, then in etching machine, carries out mesa etch, carry out Coating glue protect afterwards, hot setting, form complete chip.
6. minority carrier life time controls:
(1) proton irradiation:
Proton irradiation equipment carries out proton irradiation.
(2) electron irradiation:
Electron irradiation equipment carries out electron irradiation, and final minority carrier life time controls at 2-10 μ s.7. encapsulate:
Chip, molybdenum sheet, alignment pin are assembled in ceramic cartridge, with special cold welding packaging machine, lower casing on shell are welded.
8. test:
Packaged device, utilizes voltage-current characteristic testing equipment, on-state voltage drop testing equipment, FRD reverse recovery parameters testing equipment to test voltage-current characteristic, forward voltage drop, reverse recovery parameters respectively.
FRD (ZK xperformance parameter 1100-45) is as follows:
Forward mean current rating I f (AV)1100A;
Reverse cut-off current rate of change di/dt 500-5000A/ μ s;
Repetitive peak reverse voltage V rRM4500-6000V;
Non-repetitive peak reverse voltage V rSM4600-6100V;
Forward voltage drop V fM≤ 3.5-3.0V;
Peak Repetitive Reverse Current I rRM≤ 50mA;
Maximum junction temperature T vJM125 DEG C;
QRR Qrr≤3200 μ C;
Reverse recovery time trr 3-7 μ s;
Softness factor S >=1.0.
As can be seen from above-described embodiment, the present invention adopts the cooperation process of aluminium pre-deposition+boron ion implantation, ensure that P+ layer in length and breadth to the high uniformity of Impurity Distribution; Decrease the loss amount of aluminium boron impurity simultaneously, saved cost, improve diffuser efficiency.Simultaneously, the present invention adopts the cooperation process of proton irradiation+electron irradiation, the life control method having gradient to distribute on formation silicon chip is longitudinal, overcome the defect that both are respective dexterously, obtain a reverse recovery parameters Qrr, Irr, trr value is little, and the FRD device that softness factor S value is large, ensure to meet the supporting application requirement of IGCT by the reverse recovery characteristic that FRD is not only fast but also soft.In addition, a whole set of the succinct smooth technological process described in this patent.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (14)

1. the supporting fast recovery diode of integrated gate commutated thyristor, it is P +/ N -/ N +type structure, can bear repetitive peak reverse voltage is 4500-7000V, and forward mean current rating is 400-2500A, and reverse cut-off current rate of change is 500-5000A/ μ s, and reverse recovery time is 3-7 μ s, and the softness factor>=1.0.
2. a manufacture method for the supporting fast recovery diode of integrated gate commutated thyristor, comprising:
Steps A, preliminary treatment: single-sided polishing process is carried out to N-type original silicon chip and obtains preliminary treatment silicon chip;
Step B, P type doping treatment;
Step C, one side mill process: the P-type layer grinding off the non-polished surface of silicon chip, obtains P +/ N -the silicon chip of type structure;
Step D, expands phosphorus process: to P +/ N -the silicon chip of type structure carries out first time cleaning, dries dress boat, then pushes constant temperature diffusion in diffusion furnace and carries out phosphorus impurities pre-deposition; Again second time cleaning carried out to silicon chip, dry dress boat, then push in diffusion furnace, pass into oxygen constant temperature and advance, obtain P +/ N -/ N +the silicon chip of type structure;
Step e, reprocessing: by P +/ N -/ N +the silicon chip of type structure carries out cyclotomy, evaporation of aluminum and alloy and table top moulding and conservation treatment successively and obtains complete chip;
Wherein, in stepb, P type doping treatment comprises carries out aluminium pre-deposition and boron ion implantation to preliminary treatment silicon chip, and then carries out the propelling of boron aluminium, forms P +/ N -the silicon chip of/P type structure.
3. method according to claim 2, is characterized in that, described aluminium pre-deposition carries out the two-sided of silicon chip, and described boron ion implantation is carried out at the burnishing surface of silicon chip, and described aluminium pre-deposition and boron ion implantation are carried out according to random order; Preferred described aluminium pre-deposition and boron ion implantation are carried out according to the order of boron ion implantation after first aluminium pre-deposition.
4. method according to claim 3, is characterized in that: described aluminium pre-deposition comprises and carried out cleaning, drying dress boat by silicon chip, then pushes in vacuum aluminum pre-deposition diffusion furnace, and constant temperature spreads, and control surface aluminum concentration is 10 18-10 19/ cm 3.
5. method according to claim 4, is characterized in that: the temperature of described constant temperature diffusion is 900-950 DEG C.
6. method according to claim 3, is characterized in that: described boron ion implantation comprises is undertaken cleaning, drying dress boat by silicon chip, then pushes in oxide-diffused stove, passes into the diffusion of oxygen constant temperature, forms SiO on the two surface of silicon chip 2diaphragm, then injects boron ion at burnishing surface.
7. method according to claim 6, is characterized in that: described SiO 2the thickness of diaphragm is 22-52nm; The temperature of described constant temperature diffusion is 800-850 DEG C.
8. method according to claim 3, it is characterized in that: described boron aluminium advances to comprise and carried out cleaning, drying dress boat by the silicon chip completing aluminium pre-deposition and boron ion implantation, then push in oxide-diffused stove, pass into the diffusion of oxygen constant temperature, control surface boron aluminium total concentration is 10 16-10 17/ cm 3.
9. method according to claim 8, is characterized in that: the temperature of described constant temperature diffusion is 1200-1250 DEG C.
10. method according to claim 2, is characterized in that: in step C, makes the thickness of chip reach 0.7-1.0mm.
11. methods according to claim 2, is characterized in that: in step D, and the temperature of described constant temperature diffusion is 1000-1100 DEG C, and the surperficial phosphorus concentration of constant temperature diffusion controls 10 21-10 22/ cm 3; The temperature that described constant temperature advances is 1150-1200 DEG C, and the surperficial phosphorus concentration that constant temperature advances controls 10 20-10 21/ cm 3.
12., according to the method in claim 2 to 11 described in any one, is characterized in that, described method also comprises step F, and minority carrier life time controls: comprise proton irradiation and electron irradiation.
13. methods according to claim 12, it is characterized in that, described proton irradiation carries out on proton irradiation equipment, described electron irradiation carries out on electron irradiation equipment, whether detection chip minority carrier life time reaches predetermined value, if do not reach predetermined value, continue electron irradiation until reach predetermined value, described proton irradiation and electron irradiation carry out according to random order.
14. methods according to claim 13, is characterized in that, the predetermined value of described chip minority carrier life time is 2-10 μ s.
CN201510072875.7A 2015-02-11 2015-02-11 Integrated gate commutated thyristor, which is matched somebody with somebody, applies mechanically fast recovery diode and its manufacturing method Active CN104701386B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510072875.7A CN104701386B (en) 2015-02-11 2015-02-11 Integrated gate commutated thyristor, which is matched somebody with somebody, applies mechanically fast recovery diode and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510072875.7A CN104701386B (en) 2015-02-11 2015-02-11 Integrated gate commutated thyristor, which is matched somebody with somebody, applies mechanically fast recovery diode and its manufacturing method

Publications (2)

Publication Number Publication Date
CN104701386A true CN104701386A (en) 2015-06-10
CN104701386B CN104701386B (en) 2018-05-29

Family

ID=53348312

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510072875.7A Active CN104701386B (en) 2015-02-11 2015-02-11 Integrated gate commutated thyristor, which is matched somebody with somebody, applies mechanically fast recovery diode and its manufacturing method

Country Status (1)

Country Link
CN (1) CN104701386B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107293480A (en) * 2016-04-01 2017-10-24 无锡华润华晶微电子有限公司 A kind of high-voltage diode and preparation method thereof
CN108493108A (en) * 2018-05-16 2018-09-04 江苏润奥电子制造股份有限公司 A kind of manufacturing method of high-voltage high-speed soft-recovery diode
CN110912380A (en) * 2018-09-17 2020-03-24 国网浙江省电力公司 Method for balancing turn-on and turn-off loss of power semiconductor element
CN112309842A (en) * 2019-07-26 2021-02-02 株洲中车时代半导体有限公司 Manufacturing method of fast recovery diode
CN112309855A (en) * 2019-07-26 2021-02-02 株洲中车时代半导体有限公司 Manufacturing method of fast recovery diode
CN116504824A (en) * 2023-06-27 2023-07-28 清华大学 Power semiconductor device and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1710707A (en) * 2005-05-11 2005-12-21 北京京仪椿树整流器有限责任公司 High-power quick soft-restoring diode and mfg technology thereof
US20110108953A1 (en) * 2009-11-09 2011-05-12 Abb Technology Ag Fast recovery diode
CN102820225A (en) * 2012-08-10 2012-12-12 清华大学 Manufacturing method for high-pressure quick soft recovery diode with diffusing buffer layer
CN104332503A (en) * 2014-10-16 2015-02-04 桑德斯微电子器件（南京）有限公司 High voltage fast recovery diode chip and production process thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1710707A (en) * 2005-05-11 2005-12-21 北京京仪椿树整流器有限责任公司 High-power quick soft-restoring diode and mfg technology thereof
US20110108953A1 (en) * 2009-11-09 2011-05-12 Abb Technology Ag Fast recovery diode
CN102820225A (en) * 2012-08-10 2012-12-12 清华大学 Manufacturing method for high-pressure quick soft recovery diode with diffusing buffer layer
CN104332503A (en) * 2014-10-16 2015-02-04 桑德斯微电子器件（南京）有限公司 High voltage fast recovery diode chip and production process thereof

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107293480A (en) * 2016-04-01 2017-10-24 无锡华润华晶微电子有限公司 A kind of high-voltage diode and preparation method thereof
CN108493108A (en) * 2018-05-16 2018-09-04 江苏润奥电子制造股份有限公司 A kind of manufacturing method of high-voltage high-speed soft-recovery diode
CN108493108B (en) * 2018-05-16 2021-02-09 江苏润奥电子制造股份有限公司 Manufacturing method of high-voltage fast soft recovery diode
CN110912380A (en) * 2018-09-17 2020-03-24 国网浙江省电力公司 Method for balancing turn-on and turn-off loss of power semiconductor element
CN112309842A (en) * 2019-07-26 2021-02-02 株洲中车时代半导体有限公司 Manufacturing method of fast recovery diode
CN112309855A (en) * 2019-07-26 2021-02-02 株洲中车时代半导体有限公司 Manufacturing method of fast recovery diode
CN116504824A (en) * 2023-06-27 2023-07-28 清华大学 Power semiconductor device and manufacturing method thereof
CN116504824B (en) * 2023-06-27 2023-10-31 清华大学 Power semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
CN104701386B (en) 2018-05-29

Similar Documents

Publication Publication Date Title
CN104701386A (en) Matchable fast recovery diode (FRD) of integrated gate commutate thyristor and manufacturing method of matchable fast recovery diode
CN102569067B (en) Method for manufacturing planar high-voltage ultrafast soft recovery diode
CN100459151C (en) Insulation bar dual-pole transistor with the internal transparent collector
CN105552115B (en) Semiconductor devices and the method being used for producing the semiconductor devices
CN102820225B (en) There is the manufacture method of the high-voltage high-speed soft-recovery diode of diffusing buffer layer
CN102074586B (en) Fast recovery diode
CN105977154A (en) Diffusion-technology-based manufacture method for fast recovery diode chip having double buffering layers
CN106298512A (en) A kind of fast recovery diode and preparation method thereof
CN103578978A (en) Method for manufacturing high-voltage fast recovery diodes based on silicon-based bonding materials
CN104409491A (en) High-voltage quick-turn-on thyristor and manufacturing method thereof
CN106601826A (en) Fast recovery diode and manufacturing method thereof
CN108242465A (en) A kind of door pole stream-exchanging thyristor and preparation method thereof
CN106783611A (en) A kind of trench gate IGBT with the embedded diode of grid and preparation method thereof
CN103560086B (en) The preparation method of the super-junction semiconductor device of avalanche capacity can be improved
CN202888149U (en) Full-pressure-welding packaging high-voltage semiconductor device
CN105355552B (en) A kind of preparation method of fast recovery diode
CN102201434A (en) High-frequency thyristor
CN201440416U (en) Fast recovery diode
CN103489927B (en) A kind of quick soft-recovery switch diode and preparation method thereof
CN104362182A (en) Planar double-knot type voltage stabilizing diode chip and producing process thereof
CN206532784U (en) Switching power semiconductor devices
CN107680907B (en) Fast recovery diode manufacturing method and fast recovery diode manufactured by same
CN103296076B (en) Plane IGCT, for manufacturing chip and the manufacture method of plane IGCT
CN205177857U (en) Fast recovery diode
CN206271661U (en) A kind of fast recovery diode

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169

Patentee after: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd.

Address before: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169

Patentee before: ZHUZHOU CSR TIMES ELECTRIC Co.,Ltd.

CP01 Change in the name or title of a patent holder
TR01 Transfer of patent right

Effective date of registration: 20201010

Address after: 412001 Room 309, floor 3, semiconductor third line office building, Tianxin hi tech park, Shifeng District, Zhuzhou City, Hunan Province

Patentee after: Zhuzhou CRRC times Semiconductor Co.,Ltd.

Address before: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169

Patentee before: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd.

TR01 Transfer of patent right