CN206532784U - Switching power semiconductor devices - Google Patents
Switching power semiconductor devices Download PDFInfo
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- CN206532784U CN206532784U CN201720174796.1U CN201720174796U CN206532784U CN 206532784 U CN206532784 U CN 206532784U CN 201720174796 U CN201720174796 U CN 201720174796U CN 206532784 U CN206532784 U CN 206532784U
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- 238000005468 ion implantation Methods 0.000 claims abstract description 57
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 29
- 239000010703 silicon Substances 0.000 claims abstract description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000001413 cellular effect Effects 0.000 abstract description 6
- 238000011982 device technology Methods 0.000 abstract description 2
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
The utility model is related to power semiconductor device technology field, specifically discloses a kind of switching power semiconductor devices.The device includes silicon layer, and the silicon layer has relative first surface and second surface, and it is that the knot terminal region is surrounded that the first surface, which is divided into around active region and knot terminal region, the active region,；The second surface is divided into the first ion implantation region just corresponding with the active region and Doped ions bulk concentration just corresponding with the knot terminal region is less than the second ion implantation region of first ion implantation region, it is that second ion implantation region is surrounded around first ion implantation region, in addition to is incorporated into the metal level of the second surface.The utility model can reduce the free carrier concentration and current density of device junction terminal area, reduce ionization by collision and dynamic avalanche punctures, and edge cellular be reduced because the latch up that current convergence is produced are damaged, so as to improve the general safety workspace of device.
Description
Technical field
The utility model is related to power semiconductor device technology field, more particularly to a kind of switching power semiconductor device
Part.
Background technology
In the knot terminal region of the exemplary power device such as MOSFET, IGBT, FRD, typically all include field limiting ring
Structure, field plate structure, it, which is acted on, is to aid in device and can bear higher reverse pressure-resistant.In device shut-off or reversely restoring process
In, easily occur current convergence phenomenon as shown in Figure 1, be specially because ion implanting covers whole second surface regions
(i.e. 3 positions are same ion concentration injection region in Fig. 1) forms current convergence in knot terminal region.And internal field compared with
High region has the high carrier of comparison (few son) concentration, produces higher ionization by collision and dynamic avalanche, influences (reduction)
The safety operation area (SOA) of device.
To avoid above-mentioned phenomenon, the most frequently used effective way is to reduce the free carrier concentration at knot terminal, so as to subtract
Few ionization by collision and dynamic avalanche puncture.Specific practice is to reduce the ion implantation dosage of second surface, to reduce second surface
The injection efficiency of launch site, so as to reach that reduction flows to the purpose of the concentration of electric charges of first surface active area.But it can so cause
Amount of charge in whole chip body is few, and the ability reduction of transmission electric current, namely the conducting resistance of device increase.
Power semiconductor second surface needs higher doping concentration, back metal is formed well with silicon substrate
Ohmic contact.One layer of higher ion implanting of concentration typically is done in second surface, a furnace anneal is subsequently also carried out,
With the purpose for reaching activation injection ion and repairing implant damage.Due to the limitation of first surface metal level, furnace anneal temperature
Low, the ion-activated rate of injection is low, therefore needs the ion implanting of high dose.But high dose ion injection can be caused to silicon substrate
Damage, causes element leakage big.Also, if furnace anneal temperature is low, the ability of damage is repaired also than relatively low, is largely remained
Damage can also cause the electric leakage of device.
Utility model content
Cause to produce higher collision in knot terminal region formation current convergence for what power semiconductor was present
Element leakage caused by ionization and dynamic avalanche or damage, the problems such as safety operation area is not good, the utility model embodiment is carried
A kind of switching power semiconductor devices is supplied.
In order to reach above-mentioned utility model purpose, the utility model embodiment employs following technical scheme：
A kind of switching power semiconductor devices, including silicon layer, the silicon layer have relative first surface and the second table
Face, the first surface is divided into active region and knot terminal region, in addition to is incorporated into the metal level of the second surface, described
It is that the knot terminal region is surrounded around active region；The second surface is divided into and the active region just corresponding first
Ion implantation region and Doped ions bulk concentration just corresponding with the knot terminal region are less than first ion doped region
It is that second ion implantation region is surrounded around second ion implantation region, first ion implantation region, described
The area of one ion implantation region is less than or equal to the area of the active region.
Preferably, the minimum range at the active area edges to the silicon layer edge is c, first ion doped region
The minimum range at domain edge to the silicon layer edge is d, and the difference of the d and c are not less than 10 μm.
Preferably, the silicon layer is any of silicon dioxide layer, silicon nitride layer, polysilicon layer.
Preferably, the metal level is Ti+Ni+Ag layers, Al+Ti+Ni+Ag layers, any of Ti+Au layers.
Preferably, the thickness of the silicon layer is 50 μm~1000 μm.
Preferably, the thickness of the metal level is 1.4 μm~2.7 μm.
The switching power semiconductor devices that the utility model above-described embodiment is provided, by the ion doped region of second surface
It is divided into the different doped region of plasma levels, wherein the first ion implantation region is the higher doped region of plasma levels,
And defining that the first ion implantation region is faced with active region, the second ion implantation region and knot terminal region are mutually just
Right, the area of the first ion implantation region is less than or equal to the area of active region, it is ensured that metal forms good Europe with silicon layer
Nurse is contacted, and reduces the static parameters such as the conducting resistance of device and static function, the free carrier of reduction device junction terminal area
Concentration and current density, reduce ionization by collision and dynamic avalanche punctures, and reduce what edge cellular was produced due to current convergence
Latch-up is damaged, so as to improve the general safety workspace of device.
Brief description of the drawings
Fig. 1 is ordinary power semiconductor devices termination environment current convergence phenomenon schematic diagram；
The switching power semiconductor device structure front view that Fig. 2 the utility model embodiment is provided；
The switching power semiconductor device structure electric current flowing schematic diagram that Fig. 3 the utility model embodiment is provided；
The switching power semiconductor devices first surface schematic diagram that Fig. 4 the utility model embodiment is provided；
The switching power semiconductor devices second surface schematic diagram that Fig. 5 the utility model embodiment is provided；
The switching power manufacturing method of semiconductor device schematic flow sheet that Fig. 6 the utility model embodiment is provided.
Embodiment
In order that the purpose of this utility model, technical scheme and advantage are more clearly understood, below in conjunction with accompanying drawing and implementation
Example, the utility model is further elaborated.It should be appreciated that specific embodiment described herein is only to explain
The utility model, is not used to limit the utility model.
As shown in Fig. 2,3,4,5, the utility model embodiment provides a kind of switching power semiconductor devices.
The switching power semiconductor devices includes silicon layer 1, and the silicon layer 1 is included with relative first surface and the
Two surfaces, it is the knot that the first surface, which is divided into around active region 11 and knot terminal region 12, the active region 11,
Terminal area 12 is surrounded；The second surface be divided into first ion implantation region 13 just corresponding with the active region 11 and with
The just corresponding plasma levels in the knot terminal region 12 are less than the second ion doped region of first ion implantation region 13
It is that second ion implantation region 14 is surrounded around domain 14, first ion implantation region 13, first ion is mixed
The area in miscellaneous region 13 is less than or equal to the area of the active region 11, and the second surface also incorporates metal level 2.
In the utility model embodiment, first surface is chip front side；Second surface is chip back.
Preferably, the silicon layer 1 is any of silicon dioxide layer, silicon nitride layer, polysilicon layer.
Preferably, the metal level 2 is Ti+Ni+Ag layers, Al+Ti+Ni+Ag layers, any of Ti+Au layers.It is therein
Ti (titanium) and Al (aluminum metal) can form good Ohmic contact with the silicon materials at the device back side, reduce the conducting of device
Resistance；Ni metals are as barrier layer or are transition zone, with good cementability, can prevent again upper and lower in encapsulation process
Carry on the back resistance increase caused by the phase counterdiffusion between layer gold.The metals such as Ag, Au due to its good electric conductivity, thermal conductivity, and
Its good solderability between package substrate, generally serves as the outermost layer of power device back metal.The metal level 2 is combined
In on the second surface.
The thickness of the silicon layer 1 is 50 μm~1000 μm, corresponds respectively to block pressure-resistant as little as 600V and blocks high pressure
Up to 10000V product.
The thickness of the metal level 2 is set as 1.4 μm~2.7 μm.
Specifically, Ti (titanium) and Al (aluminum metal) thickness are usually 0.1 μm~0.2 μm, and Ti can be with the device back side
Silicon materials form good Ohmic contact；Ni metals are as barrier layer, and usual thickness is 0.3 μm~0.5 μm, can prevent envelope
Phase counterdiffusion during dress between upper and lower back of the body layer gold.The metals such as Ag, Au guarantee with package substrate welding well, and control material
Cost, usual thickness is 1 μm~2 μm.
Preferably, the minimum range at the edge of active region 11 to the edge of silicon layer 1 is c, and first ion is mixed
The minimum range at the miscellaneous edge of region 13 to the edge of silicon layer 1 is d.The edge of silicon layer 1 reaches the active region in other words
The distance (width in knot terminal region 12) at edge 11 is c, and the edge of silicon layer 1 reaches first ion implantation region 13
Distance (the second ion implantation region 14) is d.
That is, the ion implantation region 13 of active region 11 and first is just relative, but the area of active region 11 is big
In or equal to the first ion implantation region 13.On the one hand it ensure that the metal level 2 of second surface and silicon layer 1 form good Europe
Nurse is contacted, and reduces the associated static such as conducting resistance of device parameter and quiescent dissipation；On the other hand, the first ion doped region
The area in domain 13 is smaller than active region 11, it is possible to reduce free carrier and current density reduce collision to knot terminal region 12
Ionization and dynamic avalanche puncture, and reduce edge cellular because the latch-up that current convergence is produced is damaged, device is improved on the whole
Safety operation area.
In the bulk concentration of the injection ion contained described above, the product that shaping is referred in the utility model, the
The note possessed on the bulk concentration and the second ion implantation region 14 of the injection ion possessed on one ion implantation region 13
Enter the bulk concentration of ion.
Preferably, the bulk concentration of the ion for the injection that first ion implantation region 13 possesses is 1.0E17cm-3
~1.0E19cm-3, the bulk concentration of the ion for the injection that second ion implantation region 14 possesses is 1.0E15cm-3~
1.0E16cm-3.What the bulk concentration for the injection ion that the first ion implantation region 13 possesses possessed than the second ion implantation region 14
The bulk concentration of injection ion is higher by an order of magnitude, is more than or equal to the first ion doped region with reference to the area of active region 11
The area in domain 13, can effectively reduce free carrier and current density to knot terminal region 12, reduce ionization by collision and dynamic
State avalanche breakdown, reduces edge cellular because the latch-up that current convergence is produced is damaged, the safe work of device is improved on the whole
Make area.
Preferably, the type of the injection ion is N-type or p-type.The N-type ion is in P elements, arsenic element
It is at least one.This dvielement can reach 80%~100% activity ratio so that the ion of injection is most all to turn into effective
Ion, improves the stability of device products parameter, and the defect produced by ion implantation technology can also be obtained well
Repair, reduce element leakage especially hot operation when the possibility leaked electricity.
The p-type ion is from least one of boron element, boron difluoride.This dvielement can reach 80%~
100% activity ratio so that the ion of injection is most all to turn into effective ion, improves the stabilization of device products parameter
Property, and defect produced by ion implantation technology can also be repaired well, reduce element leakage especially high temperature
The possibility leaked electricity during work.
The utility model above-described embodiment, the active region with first surface is divided into by the ion doping of second surface
11st, two different regions of the corresponding Doped ions bulk concentration in knot terminal region 12, wherein the first ion implantation region 13 is
The higher doped region of plasma levels, it is ensured that metal forms good Ohmic contact with silicon layer, reduces the conducting resistance of device
Etc. static parameter and static function, the second ion implantation region is the relatively low doped region of plasma levels, reduces the region
Transmitting injection efficiency, so as to reduce the free carrier concentration and current density of device junction terminal area 12, reduce collision electricity
Puncture from dynamic avalanche, edge cellular is reduced because the latch-up that current convergence is produced is damaged, so as to improve the whole of device
Body safety operation area.
Correspondingly, on the premise of above-described embodiment, the utility model embodiment additionally provides above-mentioned switching power half
The preparation method of conductor device.
As shown in fig. 6, in one embodiment, the preparation method of above-mentioned switching power semiconductor devices is at least including following
Step：
1) semi-finished product that Facad structure is completed according to common process are subjected to reduction processing；
2) ion implantation doping processing is carried out to the second surface；
3) second surface region corresponding with the active region is made annealing treatment using laser annealing technique, passed through
The region of the laser annealing processing forms the first ion implantation region；
4) furnace anneal processing is carried out without the region that the laser annealing is handled to the second surface, made by described
The region of furnace anneal processing forms the second ion implantation region；
5) deposition processes of metal level are carried out in the second surface.
The manufacturing process to above-mentioned switching power semiconductor devices is further described in detail below.
Wherein, as shown in fig. 6, in step 1) in, Facad structure here is exactly first surface mentioned above, that is,
Chip front side, having completed the semi-finished product of Facad structure can voluntarily produce, and can also obtain by other means, and this practicality is new
Type is not limited.
Step 1) in, reduction processing is carried out to the second surface of semi-finished product, including reduction processing first is ground to chip,
Then by the way of acid solution carries out batch immersion or monolithic sprinkling to semi-finished product, by grinding at thinned and acid soak
Reason, removes all dielectric layer materials of second surface, and remove the stress produced during grinding.
In one embodiment, acid solution is the aqueous solution of at least one of sulfuric acid, nitric acid, acetic acid, hydrofluoric acid, is not limited certainly
In above-mentioned cited acid.It is every can remove second surface dielectric layer material be respectively provided with feasibility.Here sour water-soluble
Liquid, concentration is not limited, and can determine sour concentration according to specific needs.
Preferably, step 2) in, ion implantation doping processing, the ionic type of injection is N-type or p-type.
Wherein, N-type ion is from least one of P elements, arsenic element.This dvielement can reach 80%~100%
Activity ratio so that the ion of injection is most all to turn into effective ion, improves the stability of device products parameter, and
Defect produced by ion implantation technology can also be repaired well, reduce element leakage especially hot operation when leak
The possibility of electricity.
P-type ion is from least one of boron element, boron difluoride.This dvielement can reach 80%~100%
Activity ratio so that the ion of injection is most all to turn into effective ion, improves the stability of device products parameter, and from
Defect produced by sub- injection technology can also be repaired well, reduce element leakage especially hot operation when leak electricity
Possibility.
The implantation dosage of above-mentioned ion is 1.0E13cm-2~1.0E14cm-2, belong to high concentration ion injection, and here
Implantation dosage refer to unit area injection population of ions, therefore injection after obtained by laser annealing or furnace anneal
The bulk concentration of injection ion refer to the concentration that implantation dosage divided by volume are obtained.High concentration ion injects, and is on the one hand conducive to
Metal layer on back forms good Ohmic contact with silicon layer, reduces associated static parameter and the quiescent dissipations such as conducting resistance, another
Aspect, the activity ratio that follow-up furnace anneal can be avoided to be brought because temperature is relatively low is too low.
Preferably, step 3) in, the laser light intensity of laser annealing is 0.5Jcm-2~5.0Jcm-2, the laser
Energy density be 1Jcm-2~10Jcm-2, laser beam spot is 0.1 × 1.0mm2~1.0 × 10.0mm2, during laser annealing
A length of 0.1~1.0 μ s.Laser annealing under the conditions of this, can quickly realize the high activation amount of injection ion, so as to form high body
The doped region of concentration；In addition, laser annealing defect repair ability is strong, the damage caused to silicon is small, and element leakage is small.
Laser annealing utilizes the automatically scanning pattern of laser annealing apparatus, and regioselectivity scanning is carried out to second surface and is moved back
Fire, selected region is as shown in Figure 5.
Step 4) in, the temperature of the furnace anneal is 400 DEG C~500 DEG C, a length of 10min~60min during furnace anneal,
And made annealing treatment in nitrogen atmosphere.During conventional furnace anneal, activity ratio is low, therefore first use laser annealing is formed
The higher doped region of heart plasma levels, then using furnace anneal, realize the higher doped region of plasma levels (i.e.
One ion implantation region) the relatively low doped region of plasma levels (i.e. the second ion implantation region) distribution.Second surface
Plasma levels it is relatively low doped region correspondence first surface device junction terminal area, due to low bulk concentration doped region from
Daughter concentration is low, therefore, and it launches injection efficiency lowly, so as to reduce the free carrier concentration and electricity of device junction terminal area
Current density, reduces edge cellular because the latch-up that current convergence is produced is damaged, so as to improve the general safety work of device
Area.
Step 5) in, the deposition processes of metal level are general using conventional multiple layer metal material, such as Ti+Ni+Ag, Al+Ti
Any of+Ni+Ag, Ti+Au.Certainly, this cited several metal material are not limited to.The thickness of the metal level deposited
It is set as 1.4 μm~2.7 μm.Specifically, Ti (titanium) and Al (aluminum metal) thickness are usually 0.1 μm~0.2 μm, and Ti can
Good Ohmic contact is formed with the silicon materials at the device back side；Ni metals are as barrier layer, and usual thickness is 0.3 μm~0.5 μm,
Phase counterdiffusion when can prevent from encapsulating between upper and lower back of the body layer gold.The metals such as Ag, Au guarantee with package substrate welding well,
And control material cost, usual thickness is 1 μm~2 μm.
Electron beam evaporation or magnetron sputtering technique, and suitable alloying technology condition are specifically utilized, metal level is given birth to
It is longer than second surface, it is ensured that the metal level of generation can form good alloy contact with second surface, so as to meet follow-up chip
Bonding, the demand of encapsulation.
The preparation method for the switching power semiconductor devices that the utility model above-described embodiment is provided, with prior art phase
Than, it is not necessary to photoetching treatment (photoetching treatment includes some row technical process such as gluing, exposure, development) is carried out, power is simplified
The back process of semiconductor devices；In addition, the doping concentration injection of common process is needed by adjusting ion implantation dosage come real
Existing, high implantation dosage needs high line ion implantation device, and low implantation dosage needs bottom line ion implantation device, and this reality
With new use double annealing technique, it is only necessary to use disposable implantation dosage, so as to omit injection machine equipment, reduce
The operation cost of equipment investment and equipment.The device of acquisition can effectively solve the problem that knot terminal region is caused due to current convergence
Problem of Failure, improve the conductive capability of device, the conducting resistance of device reduced, suitable for popularization and application.
Switching power semiconductor devices in order to preferably embody the offer of the utility model embodiment and preparation method thereof,
Further illustrated below by embodiment.
Embodiment 1
A kind of preparation method of switching power semiconductor devices, comprises the following steps：
1) the qualified semi-finished product for having completed positive technique are chosen；
2) to semi-finished product carry out second surface carry out reduction processing, including first second surface is ground it is thinned, then
Mass concentration is used to carry out immersion treatment for 98% aqueous sulfuric acid, a length of 10 minutes during immersion, this step acid soak processing
Effect be the white residue that produces and to remove the stress produced during grinding when removing grinding.Cleaning is then taken out, semi-finished product table is removed
The spent acid in face；
3) to step 2) obtained semi-finished product chip carries out P elements ion implanting, and implantation dosage is 1.0E14cm-2；
4) regioselectivity scan process is carried out to second surface using laser annealing apparatus, scans second surface centre bit
Put, the region scanned is suitable with the active region of first surface and correspondingly, particular location is as shown in figure 5, regulation laser intensity
Spend for 4.0Jcm-2, the energy density of laser is 8Jcm-2, laser beam spot is 0.8 × 10.0mm2, and laser annealing duration
For 1.0 μ s, the first ion implantation region is obtained；
5) semi-finished product after laser annealing is handled are placed in boiler tube under the atmosphere of nitrogen, carry out furnace anneal processing,
The temperature of furnace anneal is set as 450 DEG C, anneal duration is 30min, formation is centered around overseas second in the first ion doped region
Ion implantation region (as shown in Figure 5)；
6) after furnace anneal is handled, using conventional magnetron sputtering technique, in one layer of gold of second surface magnetron sputtering
Belong to layer, the metal level is Ti+Au layers, the thickness of Ti metal levels is 0.12 μm, the thickness of Au metal levels is 1.0 μm.
Expanded electric-resistivity method (SRP methods, SpreadingResistance Profiles) detection, what the present embodiment made opens
The bulk concentration of the Doped ions of the first ion implantation region formed after the type power semiconductor laser annealing technique processing of pass
For 1.0E18cm-3；The bulk concentration of the Doped ions of second ion implantation region is 3.0E15cm-3；Pass through the electricity of measurement device
Stream, voltage response, it is 2.2V (correspondence 30A 1700V that can calculate the saturation conduction voltage (conducting resistance) of device
IGBT products).
Embodiment 2
A kind of preparation method of switching power semiconductor devices, comprises the following steps：
1) the qualified semi-finished product for having completed positive technique are chosen；
2) to semi-finished product carry out second surface carry out reduction processing, including first second surface is ground it is thinned, then
The aqueous solution for using mass concentration to be mixed for 90% nitric acid with the hydrofluoric acid that mass concentration is 42% carries out immersion treatment, immersion
Shi Changwei 12 minutes, the white residue that the effect of this step acid soak processing is produced when being removal grinding and answering for being produced when removing grinding
Power.Cleaning is then taken out, the spent acid of surface of semi-finished is removed；
3) to step 2) obtained semi-finished product chip carries out boron element ion implanting, and implantation dosage is 3.0E13cm-2；
4) regioselectivity scan process is carried out to second surface using laser annealing apparatus, scans second surface centre bit
Put, the region scanned is suitable with the active region of first surface and correspondingly, particular location is as shown in figure 5, regulation laser intensity
Spend for 5.0Jcm-2, the energy density of laser is 10Jcm-2, laser beam spot is 1.0 × 10.0mm2, and during laser annealing
A length of 0.8 μ s, obtain the first ion implantation region；
5) semi-finished product after laser annealing is handled are placed in boiler tube under the atmosphere of nitrogen, carry out furnace anneal processing,
The temperature of furnace anneal is set as 500 DEG C, anneal duration is 60min, formation is centered around overseas second in the first ion doped region
Ion implantation region (as shown in Figure 5)；
6) after furnace anneal is handled, using conventional magnetron sputtering technique, in one layer of gold of second surface magnetron sputtering
Belong to layer, the metal level is Al+Ti+Ni+Ag layers, the thickness of Al metal levels is 0.12 μm, the thickness of Ti metal levels is 0.10 μm,
The thickness of Ni metal levels is 0.4 μm, and the thickness of Ag metal levels is 1.0 μm.
Expanded electric-resistivity method (SRP methods, SpreadingResistance Profiles) detection, what the present embodiment made opens
The bulk concentration of the Doped ions of the first ion implantation region formed after the type power semiconductor laser annealing technique processing of pass
For 1.0E19cm-3；The bulk concentration of the Doped ions of second ion implantation region is 3.0E16cm-3；Pass through the electricity of measurement device
Stream, voltage response, it is 2.0V (correspondence 50A 1200V that can calculate the saturation conduction voltage (conducting resistance) of device
IGBT products).
Preferred embodiment of the present utility model is the foregoing is only, it is all at this not to limit the utility model
Any modification, equivalent substitution or improvement made within the spirit and principle of utility model etc., should be included in the utility model
Protection domain within.
Claims (6)
1. a kind of switching power semiconductor devices, including silicon layer, the silicon layer have relative first surface and second surface,
The first surface is divided into active region and knot terminal region, in addition to is incorporated into the metal level of the second surface, its feature
It is：It is that the knot terminal region is surrounded around the active region；The second surface is divided into the active region just
Corresponding first ion implantation region and Doped ions bulk concentration just corresponding with the knot terminal region less than described first from
It is second ion implantation region around second ion implantation region of sub- doped region, first ion implantation region
Surround, the area of first ion implantation region is less than or equal to the area of the active region.
2. switching power semiconductor devices as claimed in claim 1, it is characterised in that：The active area edges are to described
The minimum range at silicon layer edge is c, and the minimum range at the first ion implantation region edge to the silicon layer edge is d, institute
The difference for stating d and c is not less than 10 μm.
3. switching power semiconductor devices as claimed in claim 1, it is characterised in that：The silicon layer be silicon dioxide layer,
Any of silicon nitride layer, polysilicon layer.
4. switching power semiconductor devices as claimed in claim 1, it is characterised in that：The metal level is Ti+Ni+Ag
Layer, Al+Ti+Ni+Ag layers, any of Ti+Au layers.
5. switching power semiconductor devices as claimed in claim 3, it is characterised in that：The thickness of the silicon layer be 50 μm~
1000μm。
6. switching power semiconductor devices as claimed in claim 4, it is characterised in that：The thickness of the metal level is 1.4 μ
M~2.7 μm.
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